Microcontroller

BS66F340

Holtek Semiconductor In...

Enhanced Touch A/D Flash MCU with LED Driver December 15, 2016

Manufacturer: Holtek Semiconductor In...

Document: 256 Pages / 7Mb

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Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350 BS66F360/BS66F370 Revision: V1.40 Date: Deee 1 01Deee 1 01

Features

Operating voltage ♦ fSYS= 8MHz: 2.2V~5.5V ♦ fSYS=12MHz: 2.7V~5.5V ♦ fSYS=16MHz: 3.3V~5.5V
Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
Power down and wake-up functions to reduce power consumption
Oscillator type ♦ External High Speed Crystal – HXT ♦ Internal High Speed RC – HIRC ♦ External 32.768kHz Crystal – LXT ♦ Internal 32kHz RC – LIRC
Fully integrated internal 8/12/16MHz oscillator requires no external components
Multi-mode operation: NORMAL, SLOW, IDLE and SLEEP
All instructions executed in one to three instruction cycles
Table read instructions
115 powerful instructions
Up to 16-level subroutine nesting
Bit manipulation instruction Peripheral Features
Program Memory: Up to 32K×16
Data Memory: Up to 1536×8
True EEPROM Memory: 128×8
Fully integrated touch key functions – require no external components
Watchdog T imer function
Up to 60 bidirectional I/O lines
Two external interrupt lines shared with I/O pins
Multiple T imer Modules for time measure, input capture, compare match output, PWM output function or single pulse output function
Serial Interfaces Module – SIM for SPI or I2C
Fully-duplex Universal Asynchronous Receiver and T ransmitter Interface – UART
Programming I/O source current
Dual T ime-Base functions for generation of fixed time interrupt signals
8-channel 12-bit resolution A/D converter
Temperature Sensor
In Application Programming function – IAP
Low voltage reset function
Low voltage detect function

Flash program memory can be re-programmed up to 100,000 times
Flash program memory data retention > 10 years
True EEPROM data memory can be re-programmed up to 1,000,000 times
True EEPROM data memory data retention > 10 years
Wide range of available package types General Description The series of devices are Flash Memory A/D type 8-bit high performance RISC architecture microcontroller with fully integrated touch key functions. W ith all touch key functions provided internally and with the convenience of Flash Memory multi-programm ing features, each device has all the features to of fer designers a reliable and easy means of implementing T ouch Keyes within their products applications. The t ouch ke y func tions a re ful ly i ntegrated c ompletely e liminating t he ne ed for e xternal components. In addition to the flash program memory , other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non-volatile data such as serial numbers, calibration data, etc. Analog features include a multi-channel 12-bit A/D converter with temperature sensor . Protective features such as an internal W atchdog T imer and Low V oltage Reset functions coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. These devices also include fully integrated low and high speed oscillators which are flexibly used for different applications. The ability to operate and s witch dynamically betw een a range of operating modes using dif ferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the internal UAR T, I2C and SPI inte rfaces, while the inclusion of flexible I/O programming features, Timer modules and many other features further enhance device functionality and flexibility. The touch key devices will find excellent use in a huge range of modern T ouch Key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few.

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Selection Table Most features are common to all devices. The main features distinguishing them are Memory capacity, I/ O c ount, T ouch Modul e a nd ke y m umber, st ack c apacity a nd pa ckage t ypes. T he following table summarises the main features of each device. Part No. Program Memory Data Memory Data EEPROM I/O A/D Temp. Sensor Time Base BSF340 4k×1 1×8 18×8 1-it×8 √ BSF30 8k×1 78×8 18×8 40 1-it×8 √ BSF30 1k×1 104×8 18×8 4 1-it×8 √ BSF370 3K×1 13×8 18×8 0 1-it×8 √ Part No. Timer Module Touch Module Touch Key SIM UART Stacks Package BSF340 10-it CTM× 10-it PTM×1 1-it STM×1 3 1 √ √ 8 8SSOP BSF30 10-it CTM× 10-it PTM×1 1-it STM×1 0 √ √ 8 44/48LQFP BSF30 10-it CTM× 10-it PTM×1 1-it STM×1 7 8 √ √ 1 8SOP 44/48LQFP BSF370 10-it CTM× 10-it PTM×1 1-it STM×1 9 3 √ √ 1 44/48/4LQFP Note: As devices exist in more than one package format, the table reflects the situation for the package with the most pins. Block Diagram 8-it RISC MCU Coe I/O Tie Modules Flash Poga Meoy EEPROM Data Meoy Flash/EEPROM Pogaing Ciuity Tie Base SIM (SPI/IC) Low Voltage Reset Wathdog Tie Low Voltage Detet Inteupt Contolle Reset Ciuit Extenal HXT Osillato 1-it A/D Convete RAM Data Meoy IAP UART Intenal HIRC/LIRC Osillatos Tepeatue Senso Touh Key Modules Extenal LXT Osillato

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pin Assignment PE4/OSC1 PE5/CTP1B/OSC2 PB7/INT1/KEY4/AN7 PB6/PTCK/KEY3/AN6 PB5/STCK/KEY2/AN5 PB4/PTPI/PTPB/KEY1/AN4 PA4/SDO/XT2 VSS VDD PB0/SDI/SDA/VREF/AN0 PB1/SCK/SCL/AN1 PB2/PTPI/TX/PTP/AN2 PA3/SCS/XT1 PB3/RX/AN3 PC0/KEY5 PC1/KEY6 PC3/KEY8 PC2/KEY7 PE0/KEY9 PA7/CTP1 PE3/STPI/STPB/KEY12 PE2/STPI/STP/KEY11 PA0/SDO/ICPDA/OCDSDA PA1/CTP0 PA5/CTP0B PA6/CTCK0/INT0 PE1/KEY10 PA2/CTCK1/SCS/ICPCK/OCDSCK BS66F340/BS66V340

28 SSOP-A

28 SOP-A

PE3/STP0B/STP0I_1/KEY24 PE2/STP0/STP0I_0/KEY23 PD5/KEY18 PD6/KEY19 PD7/KEY20 PB4/PTP0B/PTP0I_1/AN4/KEY1 PB5/STCK0/AN5/KEY2PB6/PTCK0/AN6/KEY3 PA2/SCSB/OCDSCK PA0/SDO/OCDSDA PA4/SDO/XT2 PA3/SCSB/XT1 VSS VDD PE5/CTCK1/OSC2 PE4/OSC1 PA1/CTP0PA5/CTP0B PB3/RX/AN3 PB2/PTP0/PTP0I_0/TX/AN2 PB0/VREF/SDI/SDA/RESB/AN0 PB1/SCK/SCL/AN1PD3/KEY16 PD2/KEY15 PD1/KEY14 PD4/KEY17

44 LQFP-A

34 3 3 37 38 39 40 41 4 43 44 PE/CTCK1/OSC PE4/OSC1 PE7/CTP1B PE/CTP1 PA1/CTP0 PA/CTP0B PA/CTCK0/INT0 PA7 PD3/KEY1 PD/KEY1 PD1/KEY14 PA0/SDO/ICPDA/OCDSDA VSS PA4/SDO/XT PA3/SCS/XT1 VDD PB3/RX/AN3 PB0/SDI/SDA/VREF/AN0 PB1/SCK/SCL/AN1 PB/PTPI/TX/PTP/AN PB7/INT1/KEY4/AN7 PB/PTCK/KEY3/AN PB/STCK/KEY/AN PB4/PTPI/PTPB/KEY1/AN4 PD/KEY18 PD4/KEY17 PD/KEY19 PE1 PE3/STPI/STPB PE/STPI/STP PA/SCS/ICPCK/OCDSCK NC NC NC NC NC PE0 PD7/KEY0 PC7/KEY1 PC/KEY11 PC/KEY10 PC4/KEY9 PC3/KEY8 PC/KEY7 BS66F350/BS66V350

48 LQFP-A

13 14 1 1 17 18 19 0 1 3 4 44 47 48 37 38 39 40 41 4 43 44 PE/CTCK1/OSC PE4/OSC1 PE7/CTP1B PE/CTP1 PA1/CTP0 PA/CTP0B PA/CTCK0/INT0 PA7 PD3/KEY1 PD/KEY1 PD1/KEY14 PD0/KEY13 PA0/SDO/ICPDA/OCDSDA VSS PA4/SDO/XT PA3/SCS/XT1 VDD PB3/RX/AN3 PB0/SDI/SDA/VREF/AN0 PB1/SCK/SCL/AN1 PB/PTPI/TX/PTP/AN PB7/INT1/KEY4/AN7 PB/PTCK/KEY3/AN PB/STCK/KEY/AN PB4/PTPI/PTPB/KEY1/AN4 PD/KEY18 PD4/KEY17 PD/KEY19 PE1 PE3/STPI/STPB PE/STPI/STP PE0 PA/SCS/ICPCK/OCDSCK NC NC NC NC NC NC PD7/KEY0 PC3/KEY8 PC/KEY7 PC1/KEY PC0/KEY PC/KEY10 PC4/KEY9 PC/KEY11 PC7/KEY1

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F360/BS66V360 13 14 1 1 17 18 19 0 1 3 4 44 47 48 37 38 39 40 41 4 43 44 PE/CTCK1/OSC PE4/OSC1 PE7/CTP1B/KEY PE/CTP1/KEY PA1/CTP0 PA/CTP0B PA/CTCK0/INT0 PA7 PD3/KEY1 PD/KEY1 PD1/KEY14 PD0/KEY13 PA0/SDO/ICPDA/OCDSDA VSS PA4/SDO/XT PA3/SCS/XT1 VDD PB3/RX/AN3 PB0/SDI/SDA/VREF/AN0 PB1/SCK/SCL/AN1 PB/PTPI/TX/PTP/AN PB7/INT1/KEY4/AN7 PB/PTCK/KEY3/AN PB/STCK/KEY/AN PB4/PTPI/PTPB/KEY1/AN4 PD/KEY18 PD4/KEY17 PD/KEY19 PE1/KEY PE3/STPI/STPB/KEY4 PE/STPI/STP/KEY3 PE0/KEY1 PA/SCS/ICPCK/OCDSCK PF PF4 PF3 PF PF1/KEY8 PF0/KEY7 PD7/KEY0 PC3/KEY8 PC/KEY7 PC1/KEY PC0/KEY PC/KEY10 PC4/KEY9 PC/KEY11 PC7/KEY1 BS66F360/BS66V360 34 3 3 37 38 39 40 41 4 43 44 PE/CTCK1/OSC PE4/OSC1 PE7/CTP1B/KEY PE/CTP1/KEY PA1/CTP0 PA/CTP0B PA/CTCK0/INT0 PA7 PD3/KEY1 PD/KEY1 PD1/KEY14 PA0/SDO/ICPDA/OCDSDA VSS PA4/SDO/XT PA3/SCS/XT1 VDD PB3/RX/AN3 PB0/SDI/SDA/VREF/AN0 PB1/SCK/SCL/AN1 PB/PTPI/TX/PTP/AN PB7/INT1/KEY4/AN7 PB/PTCK/KEY3/AN PB/STCK/KEY/AN PB4/PTPI/PTPB/KEY1/AN4 PD/KEY18 PD4/KEY17 PD/KEY19 PE1 PE3/STPI/STPB/KEY4 PE/STPI/STP/KEY3 PA/SCS/ICPCK/OCDSCK PF PF3 PF PF1/KEY8 PF0/KEY7 PE0 PD7/KEY0 PC7/KEY1 PC/KEY11 PC/KEY10 PC4/KEY9 PC3/KEY8 PC/KEY7

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F370/BS66V370 13 14 1 1 17 18 19 0 1 3 4 44 47 48 37 38 39 40 414 43 44 PE/CTCK1/OSC PE4/OSC1 PE7/CTP1B/KEY PE/CTP1/KEY PA1/CTP0 PA/CTP0B PA/CTCK0/INT0 PA7 PD3/KEY1 PD/KEY1 PD1/KEY14 PD0/KEY13 PA0/SDO/ICPDA/OCDSDA VSS PA4/SDO/XT PA3/SCS/XT1 VDD PB3/RX/AN3 PB1/SCK/SCL/AN1 PB/PTP/PTPI/TX/AN PB7/INT1/AN7/KEY4 PB/PTCK/AN/KEY3 PB/STCK/AN/KEY PB4/PTPB/PTPI/AN4/KEY1 PD/KEY18 PD4/KEY17 PD/KEY19 PE1/KEY PE3/STPB/STPI/KEY4 PE/STP/STPI/KEY3 PE0/KEY1 PA/SCS/ICPCK/OCDSCK PF PF4 PF3 PF PF1/KEY8 PF0/KEY7 PD7/KEY0 PC3/KEY8 PC/KEY7 PC1/KEY PC0/KEY PC/KEY10 PC4/KEY9 PC/KEY11 PC7/KEY1 PB0/VREF/SDI/SDA/AN0

64 LQFP-A

Note: T he OC DSDA a nd OC DSCK p ins a re t he OC DS d edicated p ins a nd o nly a vailable f or t he B S66V3x0 device which is the OCDS EV chip for the BS66F3x0 device.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pin Descriptions With the exceptio n of the power pins and some relevant transformer control pins, all pins on these devices c an be re ferenced by t heir Por t na me, e .g. P A0, P A1 e tc, whi ch re fer t o t he di gital I/ O function of the pins. However these Port pins are also shared with other function such as the Analog to Digital Converter, T imer Module pins etc. T he function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on smaller package sizes. BS66F340 Pad Name Function OPT I/T O/T Description PA0/SDO/ ICPDA/ OCDSDA PA0 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS0 — CMOS SPI data output ICPDA — ST CMOS ICP Data/Addess pin OCDSDA — ST CMOS OCDS Data/Addess pin fo EV hip only. PA1/CTP0 PA1 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA/CTCK1/ SCS/ ICPCK/ OCDSCK PA PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTCK1 PAS0 ST — CTM1 lok input SCS PAS0 IFS ST CMOS SPI slave selet ICPCK — ST CMOS ICP Clok pin OCDSCK — ST — OCDS Clok pin fo EV hip only. PA3/SCS/ XT1 PA3 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave selet XT1 PAS0 LXT — LXT osillato pin PA4/SDO/ XT PA4 PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS1 — CMOS SPI data output XT PAS1 — LXT LXT osillato pin PA/CTP0B PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inveted output PA/CTCK0/ INT0 PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 lok input INT0 PAS1 INTEG INTC0 ST — Extenal Inteupt 0

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PA7/CTP1 PA7 PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP1 PAS1 — CMOS CTM1 output PB0/SDI/ SDA/VREF/ AN0 PB0 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SDI PBS0 ST — SPI data input SDA PBS0 ST NMOS IC data line VREF PBS0 — AN A/D Convete efeene voltage output AN0 PBS0 AN — A/D Convete analog input PB1/SCK/ SCL/AN1 PB1 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SCK PBS0 ST CMOS SPI seial lok SCL PBS0 ST NMOS IC lok line AN1 PBS0 AN — A/D Convete analog input PB/PTPI/ TX/PTP/AN PB PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS0 IFS ST — PTM aptue input TX PBS0 — CMOS UART TX seial data output PTP PBS0 — CMOS PTM output AN PBS0 AN — A/D Convete analog input PB3/RX/AN3 PB3 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. RX PBS0 ST — UART RX seial data input AN3 PBS0 AN — A/D Convete analog input PB4/PTPI/ PTPB/KEY1/ AN4 PB4 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS1 IFS ST — PTM aptue input PTPB PBS1 — CMOS PTM inveted output KEY1 PBS1 AN — Touh key input AN4 PBS1 AN — A/D Convete analog input PB/STCK/ KEY/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STCK PBS1 ST — STM lok input KEY PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB/PTCK/ KEY3/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTCK PBS1 ST — PTM lok input KEY3 PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB7/INT1/ KEY4/AN7 PB7 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. INT1 PBS1 INTEG INTC0 ST — Extenal Inteupt 1 KEY4 PBS1 AN — Touh key input AN7 PBS1 AN — A/D Convete analog input

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PC0/KEY PC0 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC1/KEY PC1 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC/KEY7 PC PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY7 PCS0 AN — Touh key input PC3/KEY8 PC3 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY8 PCS0 AN — Touh key input PE0/KEY9 PE0 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY9 PES0 AN — Touh key input PE1/KEY10 PE1 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY10 PES0 AN — Touh key input PE/STPI/ STP/KEY11 PE PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STP PES0 — CMOS STM output KEY11 PES0 AN — Touh key input PE3/STPI/ STPB/ KEY1 PE3 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STPB PES0 — CMOS STM inveted output KEY1 PES0 AN — Touh key input PE4/OSC1 PE4 PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. OSC1 PES1 HXT — HXT osillato pin PE/CTP1B/ OSC PE PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1B PES1 — CMOS CTM0 inveted output OSC PES1 — HXT HXT osillato pin VDD VDD — PWR — Positive powe supply VSS VSS — PWR — Negative powe supply g ound. Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt T rigger input; AN: Analog signal; CMOS: CMOS output; NMOS: NMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F350 Pad Name Function OPT I/T O/T Description PA0/SDO/ ICPDA/ OCDSDA PA0 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS0 — CMOS SPI data output ICPDA — ST CMOS ICP Data/Addess pin OCDSDA — ST CMOS OCDS Data/Addess pin fo EV hip only. PA1/CTP0 PA1 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA/SCS/ ICPCK/ OCDSCK PA PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave selet ICPCK — ST CMOS ICP Clok pin OCDSCK — ST — OCDS Clok pin fo EV hip only. PA3/SCS/XT1 PA3 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave selet XT1 PAS0 LXT — LXT osillato pin PA4/SDO/XT PA4 PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS1 — CMOS SPI data output XT PAS1 — LXT LXT osillato pin PA/CTP0B PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inveted output PA/CTCK0/ INT0 PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 lok input INT0 PAS1 INTEG INTC0 ST — Extenal Inteupt 0 PA7 PA7 PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. PB0/SDI/ SDA/VREF/ AN0 PB0 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SDI PBS0 ST — SPI data input SDA PBS0 ST NMOS IC data line VREF PBS0 — AN A/D Convete efeene voltage output AN0 PBS0 AN — A/D Convete analog input

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PB1/SCK/ SCL/AN1 PB1 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SCK PBS0 ST CMOS SPI seial lok SCL PBS0 ST NMOS IC lok line AN1 PBS0 AN — A/D Convete analog input PB/PTPI/TX/ PTP/AN PB PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS0 IFS ST — PTM aptue input TX PBS0 — CMOS UART TX seial data output PTP PBS0 — CMOS PTM output AN PBS0 AN — A/D Convete analog input PB3/RX/AN3 PB3 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. RX PBS0 ST — UART RX seial data input AN3 PBS0 AN — A/D Convete analog input PB4/PTPI/ PTPB/KEY1/ AN4 PB4 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS1 IFS ST — PTM aptue input PTPB PBS1 — CMOS PTM inveted output KEY1 PBS1 AN — Touh key input AN4 PBS1 AN — A/D Convete analog input PB/STCK/ KEY/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STCK PBS1 ST — STM lok input KEY PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB/PTCK/ KEY3/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTCK PBS1 ST — PTM lok input KEY3 PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB7/INT1/ KEY4/AN7 PB7 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. INT1 PBS1 INTEG INTC0 ST — Extenal Inteupt 1 KEY4 PBS1 AN — Touh key input AN7 PBS1 AN — A/D Convete analog input PC0/KEY PC0 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC1/KEY PC1 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC/KEY7 PC PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY7 PCS0 AN — Touh key input

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PC3/KEY8 PC3 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY8 PCS0 AN — Touh key input PC4/KEY9 PC4 PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY9 PCS1 AN — Touh key input PC/KEY10 PC PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY10 PCS1 AN — Touh key input PC/KEY11 PC PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY11 PCS1 AN — Touh key input PC7/KEY1 PC7 PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PCS1 AN — Touh key input PD0/KEY13 PD0 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY13 PDS0 AN — Touh key input PD1/KEY14 PD1 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY14 PDS0 AN — Touh key input PD/KEY1 PD PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PDS0 AN — Touh key input PD3/KEY1 PD3 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PDS0 AN — Touh key input PD4/KEY17 PD4 PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY17 PDS1 AN — Touh key input PD/KEY18 PD PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY18 PDS1 AN — Touh key input PD/KEY19 PD PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY19 PDS1 AN — Touh key input PD7/KEY0 PD7 PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY0 PDS1 AN — Touh key input PE0 PE0 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PE1 PE1 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PE/STPI/ STP PE PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STP PES0 — CMOS STM output PE3/STPI/ STPB PE3 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STPB PES0 — CMOS STM inveted output

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PE4/OSC1 PE4 PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. OSC1 PES1 HXT — HXT osillato pin PE/CTCK1/ OSC PE PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTCK1 PES1 ST — CTM1 lok input OSC PES1 — HXT HXT osillato pin PE/CTP1 PE PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1 PES1 — CMOS CTM1 output PE7/CTP1B PE7 PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1B PES1 — CMOS CTM1 inveted output VDD VDD — PWR — Positive powe supply VSS VSS — PWR — Negative powe supply g ound. Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt T rigger input; AN: Analog signal; CMOS: CMOS output; NMOS: NMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F360 Pad Name Function OPT I/T O/T Description PA0/SDO/ ICPDA/ OCDSDA PA0 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS0 — CMOS SPI data output ICPDA — ST CMOS ICP Data/Addess pin OCDSDA — ST CMOS OCDS Data/Addess pin fo EV hip only. PA1/CTP0 PA1 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA/SCS/ ICPCK/ OCDSCK PA PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave selet ICPCK — ST CMOS ICP Clok pin OCDSCK — ST — OCDS Clok pin fo EV hip only. PA3/SCS/XT1 PA3 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave selet XT1 PAS0 LXT — LXT osillato pin PA4/SDO/ XT PA4 PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS1 — CMOS SPI data output XT PAS1 — LXT LXT osillato pin PA/CTP0B PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inveted output PA/CTCK0/ INT0 PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 lok input INT0 PAS1 INTEG INTC0 ST — Extenal Inteupt 0 PA7 PA7 PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. PB0/SDI/ SDA/VREF/ AN0 PB0 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SDI PBS0 ST — SPI data input SDA PBS0 ST NMOS IC data line VREF PBS0 — AN A/D Convete efeene voltage output AN0 PBS0 AN — A/D Convete analog input

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PB1/SCK/ SCL/AN1 PB1 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SCK PBS0 ST CMOS SPI seial lok SCL PBS0 ST NMOS IC lok line AN1 PBS0 AN — A/D Convete analog input PB/PTPI/TX/ PTP/AN PB PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS0 IFS ST — PTM aptue input TX PBS0 — CMOS UART TX seial data output PTP PBS0 — CMOS PTM output AN PBS0 AN — A/D Convete analog input PB3/RX/AN3 PB3 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. RX PBS0 ST — UART RX seial data input AN3 PBS0 AN — A/D Convete analog input PB4/PTPI/ PTPB/KEY1/ AN4 PB4 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS1 IFS ST — PTM aptue input PTPB PBS1 — CMOS PTM inveted output KEY1 PBS1 AN — Touh key input AN4 PBS1 AN — A/D Convete analog input PB/STCK/ KEY/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STCK PBS1 ST — STM lok input KEY PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB/PTCK/ KEY3/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTCK PBS1 ST — PTM lok input KEY3 PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB7/INT1/ KEY4/AN7 PB7 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. INT1 PBS1 INTEG INTC0 ST — Extenal Inteupt 1 KEY4 PBS1 AN — Touh key input AN7 PBS1 AN — A/D Convete analog input PC0/KEY PC0 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC1/KEY PC1 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC/KEY7 PC PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY7 PCS0 AN — Touh key input PC3/KEY8 PC3 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY8 PCS0 AN — Touh key input

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PC4/KEY9 PC4 PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY9 PCS1 AN — Touh key input PC/KEY10 PC PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY10 PCS1 AN — Touh key input PC/KEY11 PC PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY11 PCS1 AN — Touh key input PC7/KEY1 PC7 PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PCS1 AN — Touh key input PD0/KEY13 PD0 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY13 PDS0 AN — Touh key input PD1/KEY14 PD1 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY14 PDS0 AN — Touh key input PD/KEY1 PD PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PDS0 AN — Touh key input PD3/KEY1 PD3 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PDS0 AN — Touh key input PD4/KEY17 PD4 PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY17 PDS1 AN — Touh key input PD/KEY18 PD PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY18 PDS1 AN — Touh key input PD/KEY19 PD PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY19 PDS1 AN — Touh key input PD7/KEY0 PD7 PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY0 PDS1 AN — Touh key input PE0/KEY1 PE0 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PES0 AN — Touh key input PE1/KEY PE1 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PES0 AN — Touh key input PE/STPI/ STP/KEY3 PE PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STP PES0 — CMOS STM output KEY3 PES0 AN — Touh key input

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PE3/STPI/ STPB/KEY4 PE3 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STPB PES0 — CMOS STM inveted output KEY4 PES0 AN — Touh key input PE4/OSC1 PE4 PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. OSC1 PES1 HXT — HXT osillato pin PE/CTCK1/ OSC PE PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTCK1 PES1 ST — CTM1 lok input OSC PES1 — HXT HXT osillato pin PE/CTP1/ KEY PE PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1 PES1 — CMOS CTM1 output KEY PES1 AN — Touh key input PE7/CTP1B/ KEY PE7 PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1B PES1 — CMOS CTM1 inveted output KEY PES1 AN — Touh key input PF0/KEY7 PF0 PFPU PFS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY7 PFS0 AN — Touh key input PF1/KEY8 PF1 PFPU PFS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY8 PFS0 AN — Touh key input PF~PF PFn PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. VDD VDD — PWR — Positive powe supply VSS VSS — PWR — Negative powe supply g ound. Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt T rigger input; AN: Analog signal; CMOS: CMOS output; NMOS: NMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F370 Pad Name Function OPT I/T O/T Description PA0/SDO/ ICPDA/ OCDSDA PA0 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS0 — CMOS SPI data output ICPDA — ST CMOS ICP Data/Addess pin OCDSDA — ST CMOS OCDS Data/Addess pin fo EV hip only. PA1/CTP0 PA1 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0 PAS0 — CMOS CTM0 output PA/SCS/ ICPCK/ OCDSCK PA PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave selet ICPCK — ST CMOS ICP Clok pin OCDSCK — ST — OCDS Clok pin fo EV hip only. PA3/SCS/XT1 PA3 PAWU PAPU PAS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS PAS0 IFS ST CMOS SPI slave selet XT1 PAS0 LXT — LXT osillato pin PA4/SDO/ XT PA4 PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO PAS1 — CMOS SPI data output XT PAS1 — LXT LXT osillato pin PA/CTP0B PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTP0B PAS1 — CMOS CTM0 inveted output PA/CTCK0/ INT0 PA PAWU PAPU PAS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. CTCK0 PAS1 ST — CTM0 lok input INT0 PAS1 INTEG INTC0 ST — Extenal Inteupt 0 PA7 PA7 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. PB0/VREF/ SDI/SDA/ AN0 PB0 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SDI PBS0 ST — SPI data input SDA PBS0 ST NMOS IC data line VREF PBS0 — AN A/D Convete efeene voltage output AN0 PBS0 AN — A/D Convete analog input PB1/SCK/ SCL/AN1 PB1 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. SCK PBS0 ST CMOS SPI seial lok SCL PBS0 ST NMOS IC lok line AN1 PBS0 AN — A/D Convete analog input

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PB/PTPI/ TX/PTP/AN PB PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS0 IFS ST — PTM aptue input TX PBS0 — CMOS UART TX seial data output PTP PBS0 — CMOS PTM output AN PBS0 AN — A/D Convete analog input PB3/RX/AN3 PB3 PBPU PBS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. RX PBS0 ST — UART RX seial data input AN3 PBS0 AN — A/D Convete analog input PB4/PTPI/ PTPB/KEY1/ AN4 PB4 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTPI PBS1 IFS ST — PTM aptue input PTPB PBS1 — CMOS PTM inveted output KEY1 PBS1 AN — Touh key input AN4 PBS1 AN — A/D Convete analog input PB/STCK/ KEY/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STCK PBS1 ST — STM lok input KEY PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB/PTCK/ KEY3/AN PB PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTCK PBS1 ST — PTM lok input KEY3 PBS1 AN — Touh key input AN PBS1 AN — A/D Convete analog input PB7/INT1/ KEY4/AN7 PB7 PBPU PBS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. INT1 PBS1 INTEG INTC0 ST — Extenal Inteupt 1 KEY4 PBS1 AN — Touh key input AN7 PBS1 AN — A/D Convete analog input PC0/KEY PC0 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC1/KEY PC1 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PCS0 AN — Touh key input PC/KEY7 PC PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY7 PCS0 AN — Touh key input PC3/KEY8 PC3 PCPU PCS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY8 PCS0 AN — Touh key input PC4/KEY9 PC4 PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY9 PCS1 AN — Touh key input

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PC/KEY10 PC PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY10 PCS1 AN — Touh key input PC/KEY11 PC PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY11 PCS1 AN — Touh key input PC7/KEY1 PC7 PCPU PCS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PCS1 AN — Touh key input PD0/KEY13 PD0 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY13 PDS0 AN — Touh key input PD1/KEY14 PD1 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY14 PDS0 AN — Touh key input PD/KEY1 PD PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PDS0 AN — Touh key input PD3/KEY1 PD3 PDPU PDS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PDS0 AN — Touh key input PD4/KEY17 PD4 PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY17 PDS1 AN — Touh key input PD/KEY18 PD PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY18 PDS1 AN — Touh key input PD/KEY19 PD PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY19 PDS1 AN — Touh key input PD7/KEY0 PD7 PDPU PDS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY0 PDS1 AN — Touh key input PE0/KEY1 PE0 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY1 PES0 AN — Touh key input PE1/KEY PE1 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY PES0 AN — Touh key input PE/STPI/ STP/KEY3 PE PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STP PES0 — CMOS STM output KEY3 PES0 AN — Touh key input PE3/STPI/ STPB/KEY4 PE3 PEPU PES0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. STPI PES0 IFS ST — STM aptue input STPB PES0 — CMOS STM inveted output KEY4 PES0 AN — Touh key input

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PE4/OSC1 PE4 PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. OSC1 PES1 HXT — HXT osillato pin PE/CTCK1/ OSC PE PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTCK1 PES1 ST — CTM1 lok input OSC PES1 — HXT HXT osillato pin PE/CTP1/ KEY PE PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1 PES1 — CMOS CTM1 output KEY PES1 AN — Touh key input PE7/CTP1B/ KEY PE7 PEPU PES1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1B PES1 — CMOS CTM1 inveted output KEY PES1 AN — Touh key input PF0/KEY7 PF0 PFPU PFS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY7 PFS0 AN — Touh key input PF1/KEY8 PF1 PFPU PFS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY8 PFS0 AN — Touh key input PF PF PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PF3 PF3 PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PF4 PF4 PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PF PF PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PG0/KEY9 PG0 PGPU PGS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY9 PGS0 AN — Touh key input PG1/KEY30 PG1 PGPU PGS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY30 PGS0 AN — Touh key input PG/KEY31 PG PGPU PGS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY31 PGS0 AN — Touh key input PG3/KEY3 PG3 PGPU PGS0 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY3 PGS0 AN — Touh key input PG4/KEY33 PG4 PGPU PGS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY33 PGS1 AN — Touh key input PG/KEY34 PG PGPU PGS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY34 PGS1 AN — Touh key input PG/KEY3 PG PGPU PGS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY3 PGS1 AN — Touh key input PG7/KEY3 PG7 PGPU PGS1 ST CMOS Geneal pupose I/O. Registe enaled pull-up. KEY3 PGS1 AN — Touh key input PH0 PH0 PHPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PH1 PH1 PHPU ST CMOS Geneal pupose I/O. Registe enaled pull-up.

Rev. 1.40 30 Deee 1 01 Rev. 1.40 31 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pad Name Function OPT I/T O/T Description PH PH PHPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PH3 PH3 PHPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PH4 PH4 PHPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PH PH PHPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. VDD VDD1 VDD — PWR — Positive powe supply VSS VSS1 VSS — PWR — Negative powe supply g ound. Legend: I/T: Input type; O/T: Output type; OPT: Optional by register option; PWR: Power; ST: Schmitt T rigger input; AN: Analog signal; CMOS: CMOS output; NMOS: NMOS output; HXT: High frequency crystal oscillator; LXT: Low frequency crystal oscillator Absolute Maximum Ratings Note: These are stress ratings only . Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VDD Opeating Voltage (HXT) ─ fSYS=8MHz . ─ . V fSYS=1MHz .7 ─ . V fSYS=1MHz 3.3 ─ . V Opeating Voltage (HIRC) ─ fSYS=8MHz . ─ . V fSYS=1MHz .7 ─ . V fSYS=1MHz 3.3 ─ . V

Rev. 1.40 30 Deee 1 01 Rev. 1.40 31 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IDD Opeating Cuent (HXT) 3V fSYS=fH=4MHz No load all peipheals off ─ 00 70 μA V ─ 1.0 1. A 3V fSYS=fH=8MHz No load all peipheals off ─ 1.0 1. A V ─ .0 3.0 A 3V fSYS=fH=1MHz No load all peipheals off ─ 1. .7 A V ─ 3.0 4. A V fSYS=fH=1MHz no load all peipheals off ─ 3. .4 A Opeating Cuent (HIRC) 3V fSYS=fH=8MHz No load all peipheals off ─ 0.8 1. A V ─ 1. .4 A 3V fSYS=fH=1MHz No load all peipheals off ─ 1. 1.8 A V ─ .4 3. A V fSYS=fH=1MHz no load all peipheals off ─ 3. 4.8 A Opeating Cuent (LXT) 3V fSYS=fSUB=fLXT=3.78kHz No load all peipheals off ─ 10 0 μA V ─ 30 0 μA Opeating Cuent (LIRC) 3V fSYS=fSUB=fLIRC=3kHz No load all peipheals off ─ 10 0 μA V ─ 30 0 μA ISTB Standy Cuent (IDLE0 Mode) 3V fSYS off fSUB on No load all peipheals off WDT enaled ─ 1.3 3.0 μA V ─ .4 .0 μA Standy Cuent (IDLE1 Mode) 3V fSYS=1MHz on fSUB on No load all peipheals off WDT enaled ─ 0.9 1.4 A V ─ 1.4 .1 A Standy Cuent (SLEEP Mode) 3V fSYS off fSUB off No load all peipheals off WDT enaled ─ 1. 1.8 μA V ─ 1.8 .7 μA VIL Input Low Voltage fo I/O Pots o Input Pins V ─ 0 ─ 1. V ─ ─ 0 ─ 0.VDD V VIH Input High Voltage fo I/O Pots o Input Pins V ─ 3. ─ .0 V ─ ─ 0.8VDD ─ VDD V IOL Sink Cuent fo I/O Pins 3V VOL=0.1VDD 17 34 ─ A V 34 8 ─ A IOH Soue Cuent fo I/O Pins 3V VOH=0.9VDD -. -11.0 ─ A V -11.0 -.0 ─ A Pogaing Soue Cuent fo I/O Pins * 3V VOH=0.9VDD PxPS[n+1:n]=00 x=A B C G o H n=0 o -1.0 -.0 ─ A V -.0 -4.0 ─ A 3V VOH=0.9VDD PxPS[n+1:n]=01 x=A B C G o H n=0 o -1.7 -3. ─ A V -3. -7.0 ─ A 3V VOH=0.9VDD PxPS[n+1:n]=10 x=A B C G o H n=0 o -. -.0 ─ A V -.0 -10.0 ─ A 3V VOH=0.9VDD PxPS[n+1:n]=11 x=A B C G o H n=0 o -. -11.0 ─ A V -11.0 -.0 ─ A RPH Pull-high Resistane fo I/O Pots 3V ─ 0 0 100 kΩ V ─ 10 30 0 kΩ *Note: 1. The I/O pins with pogaing soue uent ae PA1 PA~PA7 PB4~PB7 PC0~PC3 fo BSF340. . The I/O pins with p ogaing sou e uent ae PA1 PA~PA7 PB4~PB7 PC0~PC7 fo BSF30/ BSF30/BSF370 PG0~PG3 PH0~PH3 fo BSF370.

Rev. 1.40 3 Deee 1 01 Rev. 1.40 33 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A.C. Characteristics Ta=°C Symbol Parameter Test Condition Min. Typ. Max. UnitVDD Condition fSYS Syste Clok (HXT) .~.V fSYS=fHXT=8MHz ─ 8 ─ MHz .7~.V fSYS=fHXT=1MHz ─ 1 ─ MHz 3.3~.V fSYS=fHXT=1MHz ─ 1 ─ MHz Syste Clok (HIRC) .~.V fSYS=fHIRC=8MHz ─ 8 ─ MHz .7~.V fSYS=fHIRC=1MHz ─ 1 ─ MHz 3.3~.V fSYS=fHIRC=1MHz ─ 1 ─ MHz Syste Clok (LXT) .~.V fSYS=fLXT=3.78kHz ─ 3.78 ─ kHz Syste Clok (LIRC) .~.V fSYS=fLIRC=3kHz ─ 3 ─ kHz fHIRC High Speed Intenal RC Osillato (HIRC) (1MHz ti at VDD=3V) 3V Ta=°C -% 1 +% MHz 3V ± 0.1V Ta=0°C~70°C -% 1 +% MHz .7V~.V Ta=0°C~70°C -7% 1 +7% MHz .7V~.V Ta=-40°C~8°C -10% 1 +10% MHz 3V Ta=°C -0% 8 +0% MHz 3V Ta=°C -0% 1 +0% MHz High Speed Intenal RC Osillato (HIRC) (1MHz T i at VDD=V) V Ta=°C -% 1 +% MHz V ± 0.1V Ta=0°C~70°C -% 1 +% MHz .7V~.V Ta=0°C~70°C -7% 1 +7% MHz .7V~.V Ta=-40°C~8°C -10% 1 +10% MHz V Ta=°C -0% 8 +0% MHz V Ta=°C -0% 1 +0% MHz fLIRC Low Speed Intenal RC Osillato (LIRC) V Ta=°C -10% 3 +10% kHz .V~.V Ta=-40°C~8°C -40% 3 +40% kHz tTPI STPI PTPI pin Miniu Input Pulse Width ─ ─ 0.3 ─ ─ μs tTCK CTCKn STCK PTCK pin Miniu Input Pulse Width ─ ─ 0.3 ─ ─ μs tINT Inteupt Pin Miniu Input Pulse Width ─ ─ 10 ─ ─ μs tSST Syste Stat-up Tie Peiod (Wake-up fo Powe Down Mode and fSYS off) ─ fSYS=fH=fHXT~fHXT/4 18 ─ ─ tHXT ─ fSYS=fH=fHIRC~fHIRC/4 1 ─ ─ tHIRC ─ fSYS=fSUB=fLXT 104 ─ ─ tLXT ─ fSYS=fSUB=fLIRC ─ ─ tLIRC Syste Stat-up Tie Peiod (Wake-up fo Powe Down Mode and fSYS on) ─ fSYS=fH~fH/4 fH=fHXT o fHIRC ─ ─ tH ─ fSYS=fSUB=fLXT o fLIRC ─ ─ tSUB Syste Stat-up Tie Peiod (SLOW Mode → NORMAL Mode) (NORMAL Mode → SLOW Mode) ─ fHXT off → on (HXTF=1) 104 ─ ─ tHXT ─ fHIRC off → on (HIRCF=1) 1 ─ ─ tHIRC ─ fLXT off → on (LXTF=1) 104 ─ ─ tLXT Syste Stat-up Tie peiod (WDT Hadwae Reset) ─ ─ 0 ─ ─ tSYS

Rev. 1.40 3 Deee 1 01 Rev. 1.40 33 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Symbol Parameter Test Condition Min. Typ. Max. UnitVDD Condition tRSTD Syste Reset Delay Tie (Powe-on Reset LVR Hadwae eset LVRC/WDTC/RSTC Softwae Reset) ─ ─ 0 100 s Syste Reset Delay Tie (WDT Hadwae Reset) ─ ─ 8.3 1.7 33.3 s tEERD EEPROM Read Tie ─ ─ ─ ─ 4 tSYS tEEWR EEPROM W ite Ti e ─ ─ ─ 4 s Note: tSYS= 1/fSYS A/D Converter Characteristics Operating Temperature: -40°C~85°C, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VDD Opeating Voltage ─ ─ .7 ─ . V VADI Input Voltage ─ ─ 0 ─ VREF V VREF Refeene Voltage ─ ─ ─ VDD V DNL Diffeential Non-lineaity 3V VREF=VDD tADCK=0.5μs or 10μs ─ ─ ±3 LSBV INL Integal Non-lineaity 3V VREF=VDD tADCK=0.5μs or 10μs ─ ─ ±4 LSBV IADC Additional Cuent Consuption fo A/D Convete Enale 3V No load tADCK=0.5μs ─ 1.0 .0 A V ─ 1. 3.0 A tADCK Clok Peiod ─ AN≠Temperature sensor output 0. ─ 10 μs ─ AN=Tepeatue senso output 1 ─ μs tADC Convesion Tie (Inluding A/D Saple and Hold Tie) ─ AN≠Temperature sensor output ─ 1 ─ tADCK ─ AN=Tepeatue senso output ─ ─ tADCK tONST A/D Convete On-to-Stat Tie ─ ─ 4 ─ ─ μs Temperature Sensor Electrical Characteristics Ta=25°C, Operating Temperature: -40°C~85°C, unless otherwise specified. Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VDD Opeating Voltage ─ ─ .7 ─ . V VTSVREF Tepeatue Senso Refeene Voltage 3V Ta=°C T i @VDD=3V K_VPTAT=0 K_REFO=0 -% .01 +% VV CodeTS A/D Convesion Code Range 3V Ta=°C VREF=VTSVREF GXEN=1 AN=Tepeatue senso output 1990 0 00 LSBV 3V Ta=90°C VREF=VTSVREF GXEN=1 AN=Tepeatue senso output 3400 380 40 LSBV 3V Ta=-40°C VREF=VTSVREF GXEN=1 AN=Tepeatue senso output 0 70 99 LSBV tTSS Tepeatue Senso Tun on Stale Tie 3V ─ ─ ─ μsV

Rev. 1.40 34 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LVD/LVR Electrical Characteristics Ta=°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VLVR Low Voltage Reset Voltage ─ LVR Enale voltage selet .1V - % + % VLVR Enale voltage selet .V . LVR Enale voltage selet 3.1V 3.1 LVR Enale voltage selet 3.8V 3.8 VLVD Low Voltage Deteto Voltage ─ LVD Enale voltage selet .0V - % + % V LVD Enale voltage selet .V . LVD Enale voltage selet .4V .4 LVD Enale voltage selet .7V .7 LVD Enale voltage selet 3.0V 3.0 LVD Enale voltage selet 3.3V 3.3 LVD Enale voltage selet 3.V 3. LVD Enale voltage selet 4.0V 4.0 VBG Bandgap Refeene Voltage ─ ─ - % 1.04 + % V IOP LVD/LVR Opeating Cuent V LVD/LVR Enale VBGEN=0 ─ 0 μA V LVD/LVR Enale VBGEN=1 ─ 30 μA tBGS VBG Tun on Stale Tie ─ No load ─ ─ 10 μs tLVDS LVDO Stale Tie ─ Fo LVR enale VBGEN=0 LVD off→on ─ ─ 1 μs ─ Fo LVR disale VBGEN=0 LVD off→on ─ ─ 10 μs tLVR Miniu Low Voltage Width to Reset ─ ─ 10 40 480 μs tLVD Miniu Low Voltage Width to Inteupt ─ ─ 0 10 40 μs

Rev. 1.40 34 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Electrical Characteristics Ta=°C Touch Key RC Oscillator 500kHz Mode Selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only Senso (KEY) Osillato Opeating Cuent 3V *fSENOSC = 00kHz — 30 0 µAV — 0 10 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC = 00kHz MnTSS = 0 — 30 0 µAV — 0 10 3V *fREFOSC = 00kHz MnTSS = 1 — 30 0 µAV — 0 10 CKEYOSC Senso (KEY) Osillato Extenal Capaito 3V *fSENOSC=00kHz 3 10 30 pF V 10 0 pF CREFOSC Refeene Osillato Intenal Capaito 3V *fSENOSC=00kHz 3 10 30 pF V 10 0 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V * CEXT=7 8 9 10 11 1 13 14 1 … 0pF 100 00 1000 kHz V 100 00 1000 kHz fREFOSC Refeene Osillato Opeating Fequeny 3V * CINT=7 8 9 10 11 1 13 14 1 … 0pF 100 00 1000 kHz V 100 00 1000 kHz Note: 1. fSENOSC = 500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 500kHz. 2. fREFOSC = 500kHz: Adjust Reference oscill ator internal capacitor to make sure that the reference oscillator frequency is equal to 500kHz. Touch Key RC Oscillator 1000kHz Mode Selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only Senso (KEY) Osillato Opeating Cuent 3V *fSENOSC = 1000kHz — 40 80 µAV — 80 10 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC = 1000kHz MnTSS = 0 — 40 80 µAV — 80 10 3V *fREFOSC = 1000kHz MnTSS = 1 — 40 80 µAV — 80 10 CKEYOSC Senso (KEY) Osillato Extenal Capaito 3V *fSENOSC=1000kHz 3 10 pF V 10 0 pF CREFOSC Refeene Osillato intenal Capaito 3V *fSENOSC=1000kHz 3 10 pF V 10 0 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V * CEXT=3 4 7 8 9 … 0pF 10 1000 000 kHz V 10 1000 000 kHz fREFOSC Refeene Osillato Opeating Fequeny 3V * CINT=3 4 7 8 9 … 0pF 10 1000 000 kHz V 10 1000 000 kHz Note: 1. fSENOSC = 1000kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 1000kHz. 2. fREFOSC = 1 000kHz: Adj ust R eference o scillator i nternal c apacitor t o m ake sur e t hat t he r eference o scillator frequency is equal to 1000kHz.

Rev. 1.40 3 Deee 1 01 Rev. 1.40 37 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key RC Oscillator 1500kHz Mode Selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only Senso (KEY) Osillato Opeating Cuent 3V *fSENOSC=100kHz — 0 10 µAV — 10 40 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC=100kHz MnTSS=0 — 0 10 µAV — 10 40 3V *fREFOSC=100kHz MnTSS=1 — 0 10 µAV — 10 40 CKEYOSC Senso (KEY) Osillato Extenal Capaito 3V *fSENOSC=100kHz 4 8 0 pF V 10 0 pF CREFOSC Refeene Osillato intenal Capaito 3V *fSENOSC=100kHz 4 8 0 pF V 10 0 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V * CEXT=3 4 7 8 9 … 0pF 10 100 3000 kHz V 10 100 3000 kHz fREFOSC Refeene Osillato Opeating Fequeny 3V * CEXT=3 4 7 8 9 … 0pF 10 100 3000 kHz V 10 100 3000 kHz Note: 1. fSENOSC=1500kHz: A djust K EYn external capacitor to make s ure that the S ensor os cillator frequency is equal to 1500kHz. 2. fREFOSC=1500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 1500kHz. Touch Key RC Oscillator 2000kHz Mode Selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only Senso (KEY) Osillato Opeating Cuent 3V *fSENOSC=000kHz — 80 10 µAV — 10 30 IREFOSC Only Refeene Osillato Opeating Cuent 3V *fREFOSC=000kHz MnTSS=0 — 80 10 µAV — 10 30 3V *fREFOSC=000kHz MnTSS=1 — 80 10 µAV — 10 30 CKEYOSC Senso (KEY) Osillato Extenal Capaito 3V *fSENOSC=000kHz 4 8 0 pF V 10 0 pF CREFOSC Refeene Osillato Intenal Capaito 3V *fSENOSC=000kHz 4 8 0 pF V 10 0 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V * CEXT=3 4 7 8 9 … 0pF 10 000 4000 kHz V 10 000 4000 kHz fREFOSC Refeene Osillato Opeating Fequeny 3V * CEXT=3 4 7 8 9 … 0pF 10 000 4000 kHz V 10 000 4000 kHz Note: 1. fSENOSC=2000kHz: A djust K EYn external capacitor to make s ure that the S ensor os cillator frequency is equal to 2000kHz. 2. fREFOSC=2000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 2000kHz.

Rev. 1.40 3 Deee 1 01 Rev. 1.40 37 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Power-on Reset Characteristics Ta=°C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VPOR VDD Stat Voltage to Ensue Powe-on Reset ─ ─ ─ ─ 100 V RRPOR VDD Raising Rate to Ensue Powe-on Reset ─ ─ 0.03 ─ ─ V/s tPOR Miniu Tie fo VDD Stays at VPOR to Ensue Powe-on Reset ─ ─ 1 ─ ─ s /G54/G69 /G6D/G65 /G56 /G44/G44 /G56 /G50/G4F /G52 /G52/G52 /G50/G4F /G52 /G74 /G50/G4F /G52

Rev. 1.40 38 Deee 1 01 Rev. 1.40 39 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver System Architecture A key factor in the high-performan ce features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantag e of the usual features found within RIS C microcontrollers providing increas ed s peed of operation and enhanced performance. The pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addresse d. The simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional I/ O a nd A/ D c ontrol syst em wi th m aximum re liability a nd fle xibility. T his m akes t hese devices suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The main system clock, derived from either a HXT , LXT , HIRC or LIRC oscillator is subdivided into four internall y generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way , one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive instruction cycles, the pipelining structure of the microcontroller ensures that instructions are ef fectively executed in one instruction cycle. The exce ption to this are instructions where the content s of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle t o first obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. The requirement for this extra cycle should be taken into accou nt by programmers in timing sensitive applications. /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G28 /G50/G43 /G29 /G45/G78 /G65/G63 /G75/G74 /G65 /G20/G49/G6E /G73/G74 /G2E/G20 /G28/G50 /G43/G2D /G31/G29 /G46/G65 /G74/G63 /G68/G20 /G49/G6E /G73/G74 /G2E/G20/G28 /G50/G43 /G2B/G31 /G29 /G45/G78 /G65/G63 /G75/G74 /G65 /G20/G49/G6E /G73/G74 /G2E/G20 /G28/G50 /G43/G29 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73 /G74/G2E/G20 /G28/G50 /G43/G2B /G32/G29 /G45/G78 /G65/G63 /G75/G74 /G65/G20 /G49/G6E /G73/G74 /G2E/G20 /G28/G50 /G43/G2B /G31/G29 /G50/G43 /G50/G43 /G2B/G31 /G50/G43 /G2B/G32 /G4F /G73/G63/G69 /G6C/G6C /G61/G74 /G6F/G72 /G20/G43 /G6C/G6F /G63/G6B /G28/G53 /G79/G73/G74 /G65/G6D /G20/G43 /G6C/G6F /G63/G6B/G29 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G31 /G50/G72 /G6F/G67 /G72/G61 /G6D/G20 /G43 /G6F/G75/G6E /G74/G65 /G72 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G32 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G33 /G50 /G68/G61/G73 /G65/G20 /G43/G6C /G6F /G63/G6B/G20 /G54 /G34 /G50/G69 /G70/G65/G6C /G69/G6E /G69/G6E /G67 System Clocking and Pipelining

Rev. 1.40 38 Deee 1 01 Rev. 1.40 39 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20 /G31/G45 /G78/G65 /G63/G75 /G74/G65 /G20/G49 /G6E/G73 /G74/G2E/G20/G31 /G46/G65 /G74/G63 /G68/G20 /G49/G6E /G73/G74 /G2E/G20/G32 /G46/G6C /G75/G73 /G68/G20 /G50/G69 /G70/G65/G6C /G69/G6E /G65 /G31 /G32 /G33 /G34 /G35 /G36 /G44/G45 /G4C/G41 /G59/G3A /G4D/G4F /G56/G20 /G41/G2C /G5B/G31 /G32/G48 /G5D /G43/G41 /G4C/G4C /G20/G44 /G45/G4C /G41/G59 /G43/G50 /G4C/G20 /G5B /G31/G32/G48 /G5D /G3A /G3A /G4E/G4F /G50 /G45/G78 /G65/G63 /G75/G74 /G65/G20 /G49/G6E /G73/G74 /G2E/G20 /G32 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G33 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G36 /G45/G78 /G65/G63 /G75/G74 /G65/G20 /G49/G6E /G73 /G74/G2E/G20/G36 /G46/G65 /G74/G63 /G68 /G20/G49/G6E /G73/G74 /G2E/G20/G37 Instruction Fetching Program Counter During pro gram e xecution, t he Progr am Co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. It is automatically incremented by one each time an instruction is e xecuted e xcept for i nstructions, suc h a s "JMP" or "CAL L" t hat de mand a j ump t o a non- consecutive Program Memory address. For the device whose memory capacity is greater than 8K words the Program Memory address may be located in a certain program memory bank w hich is selected by the program memory bank pointer bit, PBP0 or PBP1. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When executi ng instructions re quiring jumps to non-consecutive addresses suc h as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the Program Counter . For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter High Byte Low Byte (PCL) BSF340 PC11~PC8 PC7~PC0 BSF30 PC1~PC8 PC7~PC0 BSF30 PBP0 PC1~PC8 PC7~PC0 BSF370 PBP0 PBP1 PC1~PC8 PC7~PC0 Program Counter The lower byte of the Program Counter , known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register . By transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch.

Rev. 1.40 40 Deee 1 01 Rev. 1.40 41 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer , and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allo wing the programmer to use the struct ure more easily . However , when the stack is full, a CALL subroutine instruction can still be execu ted which will result in a stack overflow . Precautions should be taken to avoid such cases which might cause unpredictable program branching. If the stack is overflow, the first Program Counter save in the stack will be lost. Stak Pointe Stak Level Stak Level 1 Stak Level 3 Stak Level N Poga Meoy Poga Counte Botto of Stak Top of Stak Note: N=8 for BS66F340/BS66F350, N=12 for BS66F360 while N=16 for BS66F370 Arithmetic and Logic Unit – ALU The arith metic-logic unit or ALU is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. Connected to the main micro controller data bus, the ALU receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register . As these ALU calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:

Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA
Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA
Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC
Increment and Decrement: INCA, INC, DECA, DEC LINCA, LINC, LDECA, LDEC
Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA

Rev. 1.40 40 Deee 1 01 Rev. 1.40 41 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Flash Program Memory The Progra m Me mory i s t he l ocation whe re t he use r c ode or progra m i s st ored. For t hese de vices series the Program Memory are Flash type, which means it can be programmed and re-programmed a large number of times, allowing the user the convenience of code modification on the same device. By using the appropriate programming tools, these Flash devices of fer users the flexibility to conveniently debug and develop their applications while also offering a means of field programming and updating. Device Capacity Banks BSF340 4K × 1 — BSF30 8K × 1 — BSF30 1K × 1 0~1 BSF370 3K × 1 0~3 Structure The Program Memory has a capacit y of 4K×16 to 32K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. T able data, which c an b e se tup i n a ny l ocation wi thin t he Pr ogram Me mory, i s a ddressed b y a se parate t able pointer registers. 000H Initialisation Veto 004H FFFH 1 its Inteupt Vetos Look-up Tale n00H nFFH BS66F340 Initialisation Veto 1 its Inteupt Vetos Look-up Tale BS66F350 1FFFH Initialisation Veto 1 its Inteupt Vetos Look-up Tale BS66F360 Bank 1 3FFFH 000H 0CH Initialisation Veto 1 its Inteupt Vetos Look-up Tale BS66F370 Bank 1 Bank Bank 3 4000H FFFH 000H 7FFFH Program Memory Structure Special Vectors Within the Program Memory , certai n locations are reserved for the reset and interrupts. The location 000H is reserved for use by these devices reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.

Rev. 1.40 4 Deee 1 01 Rev. 1.40 43 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. T o use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register , TBLP and TBHP . These registers define the total address of the look-up table. After se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he Pr ogram Me mory u sing the "T ABRD [m]" or "T ABRDL [m]" instructions respectively when the memory [m] is located in sector 0. If the memory [m] is locate d in other sectors except sector 0, the data can be retrieved from the program memory using the corresponding extended t able read i nstruction such a s "L TABRD [m]" or "L TABRDL [m]" respectively . When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G20/G54 /G42/G4C /G48 /G55/G73 /G65/G72 /G20/G53 /G65/G6C /G65/G63 /G74/G65 /G64 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G48/G69 /G67/G68 /G20/G42 /G79/G74 /G65/G4C /G6F/G77 /G20/G42 /G79/G74 /G65 /G54/G42 /G4C/G50 /G20/G52 /G65/G67 /G69/G73 /G74/G65 /G72 /G44/G61 /G74/G61 /G41/G64 /G64/G72 /G65/G73 /G73 /G31/G36 /G20/G62 /G69/G74 /G73 /G50/G72 /G6F/G67 /G72/G61 /G6D/G20 /G4D/G65 /G6D/G6F /G72/G79 /G4C/G61/G73 /G74/G20/G70 /G61/G67/G65 /G20/G6F /G72 /G54/G42 /G48/G50 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from t he de vice. T his e xample use s ra w t able da ta l ocated i n t he l ast pa ge whi ch i s st ored t here using the O RG s tatement. The value at this O RG s tatement is " 0F00H" w hich refers to the s tart address of the last page within the 4K Program Memory of the BS66F340 device. The table pointer low byte register is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "0F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page pointed by the TBHP register if the "T ABRD [m]" instruction is being used. The high byte o f t he t able d ata wh ich i n t his c ase i s e qual t o z ero wi ll b e t ransferred t o t he T BLH r egister automatically when the "TABRD [m] instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt S ervice Routine us e table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.

Rev. 1.40 4 Deee 1 01 Rev. 1.40 43 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 mov a ,06h ; initialise low table pointer - note that this address is referenced mov t blp,a ; to the last page or the page that tbhp pointed mov a ,0fh ; initialise high table pointer mov tbhp,a tabrd t empreg1 ; transfers value in table referenced by table pointer data at program ; memory address "0F06H" transferred to tempreg1 and TBLH dec t blp ; reduce value of table pointer by one tabrd t empreg2 ; transfers value in table referenced by table pointer data at program ; memory address "0F05H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 org 0 F00h ; sets initial address of program memory dc 00 Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh In Circuit Programming – ICP The p rovision o f Fl ash t ype Pr ogram Me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. T his enables product m anufacturers to e asily keep thei r manufa ctured products supplied with the latest program releases without removal and re- insertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Pogaing Seial Data/Addess ICPCK PA Pogaing Clok VDD VDD Powe Supply VSS VSS Gound The Program Memory and EEPROM data memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. T wo additional lines are required for the power supply . The technical details regarding the in-cir cuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user must take care of the ICPDA and ICPCK pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins.

Rev. 1.40 44 Deee 1 01 Rev. 1.40 4 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G2A /G2A /G57/G72 /G69/G74 /G65/G72 /G5F/G56 /G44/G44 /G49/G43 /G50/G44 /G41 /G49/G43 /G50/G43 /G4B /G57/G72 /G69/G74 /G65/G72 /G5F/G56 /G53/G53 /G54/G6F /G20/G6F /G74/G68 /G65/G72 /G20/G43 /G69/G72 /G63/G75 /G69/G74 /G50/G41/G30 /G50/G41/G32 /G56/G53 /G53 /G56/G44 /G44 /G57/G72 /G69/G74 /G65/G72 /G20/G43 /G6F/G6E/G6E/G65 /G63/G74 /G6F/G72 /G53/G69 /G67/G6E/G61/G6C /G73 /G4D/G43 /G55/G20 /G50/G72 /G6F/G67 /G72/G61 /G6D/G6D /G69/G6E /G67 /G50/G69 /G6E/G73 Note: * may be resistor or capacitor . The resistance of * must be greate r than 1kΩ or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There is an EV chip named BS66V 3x0 w hich is us ed to emulate the real MCU device named BS66F3x0. The EV chip device also provides the "On-Chip Debug" function to debug the real MCU device during development process. The EV chip and real MCU devices, BS66V3x0 and BS66F3x0, are almost functional compatible except the "On-Chip Debug" function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to t he Ho ltek HT -IDE d evelopment t ools. T he OC DSDA p in i s t he OC DS Da ta/Address i nput/output pin whi le t he OCDSCK pi n i s t he OCDS c lock i nput pi n. W hen use rs use t he E V c hip de vice for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no ef fect in the EV chip. However , the two OCDS pins which are pin-shared with the ICP programming pins are still used as the Flash Memory programming pins for ICP . For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins EV Chip OCDS Pins Pin Description OCDSDA OCDSDA On-Chip Deug Suppot Data/Addess input/output OCDSCK OCDSCK On-Chip Deug Suppot Clok input VDD VDD Powe Supply VSS VSS Gound

Rev. 1.40 44 Deee 1 01 Rev. 1.40 4 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver In Application Programming – IAP These devices of fer IAP function to update data or application program to flash ROM. Users can define any ROM location for IAP , but there are some features which user must notice in using IAP function. Note that the BS66F340 device supports the "Block Erase" function instead of the "Page Erase" function. BS66F340 Configurations BS66F350 Configurations BS66F360/370 Configurations Ease Blok wods / lo k Ease Page 3 wods / page Ease Page 4 wods / page W iting Wo d 4 wods / tie W iting Wo d 3 wods / tie W iting Wo d 4 wods / tie Reading Wod 1 wod / tie Reading Wod 1 wod / tie Reading Wod 1 wod / tie In Application Programming Control Registers The Address register , F ARL and F ARH, the Data registers, FD0L/FD0H, FD1L/FD1H, FD2L/FD2H and FD3L/FD3H, and the Control registers, FC0, FC1 and FC2, are the corresponding Flash access registers located in Data Memory sector 0 for IAP . If using the indirect addressing method to access the FC0, FC1 and FC2 regis ters, all read and w rite operations to the regis ters must be performed using the Indirect Addressing Register , IAR1 or IAR2, and the Memory Pointer pair , MP1L/MP1H or MP 2L/MP2H. Because the FC0, FC1 and FC2 control regis ters are located at the addres s of 50H~52H in Data Memory sector 0, the desired value ranged from 50H to 52H must first be written into the MP1L or MP2L Memory Pointer low byte and the value "00H" must also be written into the MP1H or MP2H Memory Pointer high byte. Register Name Bit 7 6 5 4 3 2 1 0 FC0 CFWEN FMOD FMOD1 FMOD0 FWPEN FWT FRDEN FRD FC1 D7 D D D4 D3 D D1 D0 FC FARL A7 A A A4 A3 A A1 A0 FARH (BSF340) — — — — A11 A10 A9 A8 FARH (BSF30) — — — A1 A11 A10 A9 A8 FARH (BSF30) — — A13 A1 A11 A10 A9 A8 FARH (BSF370) — A14 A13 A1 A11 A10 A9 A8 FD0L D7 D D D4 D3 D D1 D0 FD0H D1 D14 D13 D1 D11 D10 D9 D8 FD1L D7 D D D4 D3 D D1 D0 FD1H D1 D14 D13 D1 D11 D10 D9 D8 FDL D7 D D D4 D3 D D1 D0 FDH D1 D14 D13 D1 D11 D10 D9 D8 FD3L D7 D D D4 D3 D D1 D0 FD3H D1 D14 D13 D1 D11 D10 D9 D8 IAP Registers List

FC0 Register Bit 7 6 5 4 3 2 1 0 Nae CFWEN FMOD FMOD1 FMOD0 FWPEN FWT FRDEN FRD R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 1 1 0 0 0 0 Bit 7 CFWEN: Flash Memory W rite enable control 0: Flash memory write function is disabled 1: Flash memory write function has been successfully enabled When this bit is cleared to 0 by application program, the Flash memory write function is disabled. Note that writing a "1" into this bit results in no action. This bit is used to indicate that the Flash memory write function status. When this bit is set to 1 by hardware, it means that the F lash memory w rite function is enabled s uccessfully. Otherwise, the Flash memory write function is disabled as the bit content is zero. Bit 6~4 FMOD2~FMOD0: Mode selection 000: W rite program memory 001: Block/Page erase program memory 010: Reserved 011: Read program memory 10x: Reserved 110: FWEN mode – Flash memory W rite function Enabled mode 111: Reserved When these bits are set to "001", the "Block erase" mode is selected for BS66F340 while the "Page erase" mode is selected for BS66F350/BS66F360/BS66F370. Bit 3 FWPEN: Flash memory W rite Procedure Enable control 0: Disable 1: Enable When this bit is set to 1 and the FMOD field is set to "1 10", the IAP cont roller will execute the "Flash memory write function enable" procedure. Once the Flash memory write func tion i s suc cessfully e nabled, i t i s not ne cessary t o set t he FW PEN bi t a ny more. Bit 2 FWT: Flash memory W rite Initiate control 0: Do not initiate Flash memory write or Flash memory write process is completed 1: Initiate Flash memory write process This bit is set by software and cleared by hardware when the Flash memory write process is completed. Bit 1 FRDEN: Flash memory Read Enable control 0: Flash memory read disable 1: Flash memory read enable Bit 0 FRD: Flash memory Read Initiate control 0: Do not initiate Flash memory read or Flash memory read process is completed 1: Initiate Flash memory read process This bi t i s se t by soft ware a nd c leared by hardware whe n t he Fl ash m emory rea d process is completed.
FC1 Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: Whole chip reset pattern When use r wri tes a spe cific va lue of "55H" t o t his re gister, i t wi ll ge nerate a re set signal to reset whole chip.

FC2 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Bit 7~1 Unimplemented, read as 0. Bit 0 CLWB: Flash memory W rite Buffer Clear control 0: Do n ot i nitiate W rite B uffer C lear p rocess o r W rite B uffer C lear p rocess i s c ompleted 1: Initiate W rite Buffer Clear process This bi t i s se t by soft ware a nd c leared by ha rdware whe n t he W rite Buf fer Cl ear process is completed.
FARL Register Bit 7 6 5 4 3 2 1 0 Nae A7 A A A4 A3 A A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 Flash Memory Address bit 7 ~ bit 0
FARH Register – BS66F340 Bit 7 6 5 4 3 2 1 0 Nae — — — — A11 A10 A9 A8 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3~0 Flash Memory Address bit 11 ~ bit 8
FARH Register – BS66F350 Bit 7 6 5 4 3 2 1 0 Nae — — — A1 A11 A10 A9 A8 R/W — — — R/W R/W R/W R/W R/W POR — — — 0 0 0 0 0 Bit 7~5 Unimplemented, read as 0. Bit 4~0 Flash Memory Address bit 12 ~ bit 8
FARH Register – BS66F360 Bit 7 6 5 4 3 2 1 0 Nae — — A13 A1 A11 A10 A9 A8 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0. Bit 5~0 Flash Memory Address bit 13 ~ bit 8
FARH Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Nae — A14 A13 A1 A11 A10 A9 A8 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as 0. Bit 6~0 Flash Memory Address bit 14 ~ bit 8

FD0L Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 7 ~ bit 0
FD0H Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The first Flash Memory data bit 15 ~ bit 8
FD1L Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 7 ~ bit 0
FD1H Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The second Flash Memory data bit 15 ~ bit 8
FD2L Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 7 ~ bit 0
FD2H Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The third Flash Memory data bit 15 ~ bit 8
FD3L Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data bit 7 ~ bit 0

FD3H Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 The fourth Flash Memory data bit 15 ~ bit 8 Flash Memory Write Function Enable Procedure In orde r t o a llow use rs t o c hange t he Fl ash m emory da ta t hrough t he IAP c ontrol re gisters, use rs must first enable the Flash memory write operation by the following procedure: 1. W rite "110" into the FMOD2~FMOD0 bits to select the FWEN mode. 2. Set the FWPEN bit to "1". The step 1 and step 2 can be executed simultaneously. 3. The pattern data with a sequence of 00H, 04H, 0DH, 09H, C3H and 40H must be written into the FD1L, FD1H, FD2L, FD2H, FD3L and FD3H registers respectively. 4. A counter with a time-out period of 300μs will be activated to allow users writing the correct pattern data into the FD1L/FD1H~FD3L/FD3H register pairs. The counter clock is derived from LIRC oscillator. 5. If the counter overflows or the pattern data is incorrect, the Flash memory write operation will not be enabled and users must again repeat the above procedure. T hen the FWPEN bit will automatically be cleared to 0 by hardware. 6. If the pattern data is correct before the counter overflows, the Flash memory write operation will be enabled and the FWPEN bit will automatically be cleared to 0 by hardware. The CFWEN bit will also be set to 1 by hardware to indicate that the Flash memory write operation is successfully enabled. 7. Once the Flash memory write operation is enabled, the user can change the Flash ROM data through the Flash control register. 8. T o disable the Flash memory write operation, the user can clear the CFWEN bit to 0. Flash Meoy Wite Funtion Enale Poedue Set FMOD [:0] =110 & FWPEN=1 Selet FWEN ode & Stat Flash wite Hadwae ativate a ounte Wtie the following patten to Flash Data egistes FD1L= 00h FD1H = 04h FDL= 0Dh FDH = 09h FD3L= C3h FD3H = 40h Suess END Yes Failed CFWEN=0CFWEN = 1 No Is ounte oveflow ? No FWPEN=0 Is patten oet ? Yes Flash Memory Write Function Enable Procedure

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Flash Memory Read/Write Procedure After the Flash memory write functi on is successfully enabled through the preceding IAP procedure, users must fi rst erase the corresponding Flash memory bl ock or pa ge and then initiate the Flash memory writ e operat ion. For t he BS66F340 devi ce t he number of t he bloc k erase operat ion i s 256 words per block, the available block erase address is only specified by F ARH register and the content in the F ARL register is not used to specify the block address. For the BS66F350, BS66F360 and BS66F370 devices the number of the page erase operation is 32, 64 and 64 words per page respectively, the available page erase address is specified by F ARH register and the content of F ARL [7:5] and FARL [7:6] bit field respectively. Erase Block FARH [3:0] FARL [7:0] 0 0000 xxxx xxxx 1 0001 xxxx xxxx 0010 xxxx xxxx 3 0011 xxxx xxxx 4 0100 xxxx xxxx 0101 xxxx xxxx 0110 xxxx xxxx 7 0111 xxxx xxxx 8 1000 xxxx xxxx 9 1001 xxxx xxxx 10 1010 xxxx xxxx 11 1011 xxxx xxxx 1 1100 xxxx xxxx 13 1101 xxxx xxxx 14 1110 xxxx xxxx 1 1111 xxxx xxxx "x": don’t ae BS66F340 Erase Block Number and Selection Erase Page FARH FARL [7:5] FARL [4:0] 0 0000 0000 000 x xxxx 1 0000 0000 001 x xxxx 0000 0000 010 x xxxx 3 0000 0000 011 x xxxx 4 0000 0000 100 x xxxx 0000 0000 101 x xxxx 0000 0000 110 x xxxx 7 0000 0000 111 x xxxx 8 0000 0001 000 x xxxx 9 0000 0001 001 x xxxx : : : : 1 0000 1111 110 x xxxx 17 0000 1111 111 x xxxx 18 0001 0000 000 x xxxx 19 0001 0000 001 x xxxx : : : : 4 0001 1111 110 x xxxx 0001 1111 111 x xxxx "x": don’t ae BS66F350 Erase Page Number and Selection

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Erase Page FARH FARL [7:6] FARL [5:0] 0 0000 0000 00 xx xxxx 1 0000 0000 01 xx xxxx 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx 0000 0001 01 xx xxxx : : : : 1 0001 1111 10 xx xxxx 17 0001 1111 11 xx xxxx 18 0010 0000 00 xx xxxx 19 0010 0000 01 xx xxxx : : : : 4 0011 1111 10 xx xxxx 0011 1111 11 xx xxxx "x": don’t ae BS66F360 Erase Page Number and Selection Erase Page FARH FARL [7:6] FARL [5:0] 0 0000 0000 00 xx xxxx 1 0000 0000 01 xx xxxx 0000 0000 10 xx xxxx 3 0000 0000 11 xx xxxx 4 0000 0001 00 xx xxxx 0000 0001 01 xx xxxx 1 0001 1111 10 xx xxxx 17 0001 1111 11 xx xxxx 18 0010 0000 00 xx xxxx 19 0010 0000 01 xx xxxx 4 0011 1111 10 xx xxxx 0011 1111 11 xx xxxx 0100 0000 00 xx xxxx 7 0100 0000 01 xx xxxx 10 0111 1111 10 xx xxxx 11 0111 1111 11 xx xxxx "x": don’t ae BS66F370 Erase Page Number and Selection

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Read Flash Meoy Clea FRDEN it END Read Finish ? Yes No Set FMOD [:0]=011 & FRDEN=1 Set Flash Addess egistes FARH=xxh FARL=xxh FRD=0 ? Yes No Read data value: FD0L=xxh FD0H=xxh Set FRD=1 Read Flash Memory Procedure

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Wite Flash Meoy Flash Memory Write Function Enable Procedure Set FWT=1 FWT=0 ? Yes No Set Blok Ease addess: FARH/FARL Set FMOD [:0]=001 & FWT=1 à Selet “Blok Ease ode” & Initiate wite opeation FWT=0 ? Yes No END Wite Finish ? Yes No Clea CFWEN=0 Set FMOD [:0]=000 à Selet “Wite Flash Mode” Set Wite stating addess: FARH/FARL Wite data to data egiste: FD0L/FD0H FD1L/FD1H FDL/FDH FD3L/FD3H Write Flash Memory Procedure – BS66F340

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Wite Flash Meoy Flash Memory Write Function Enable Procedure Set FWT=1 FWT=0 ? Yes No Set Page Ease addess: FARH/FARL Set FMOD [:0]=001 & FWT=1 à Selet “Page Ease ode” & Initiate wite opeation FWT=0 ? Yes No END Wite Finish ? Yes No Clea CFWEN=0 Set FMOD [:0]=000 à Selet “Wite Flash Mode” Set Wite stating addess: FARH/FARL Wite data to data egiste: FD0L/FD0H Page data Wite finish Yes No Write Flash Memory Procedure – BS66F350/BS66F360/BS66F370 Note: When the FWT or FRD bit is set to 1, the MCU is stopped.

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Data Memory The Dat a Mem ory is an 8-bit wide RAM inte rnal me mory and is the locat ion where te mporary information is stored. Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to directly under program control, however, some remain p rotected f rom u ser m anipulation. T he se cond a rea o f Da ta Me mory i s r eserved f or g eneral purpose use. All locations within this area are read and write accessible under program control. Switching betwee n the dif ferent Data Memory sectors is achieved by properly setting the Memory Pointers to correct value. Structure The Da ta Me mory i s subdi vided i nto se veral se ctors, a ll of wh ich a re i mplemented i n 8-b it wi de Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The address range of the Special Purpose Data Memory for the device is from 00H to 7FH. The General Purpose Data Memory address range is from 80H to FFH except the T ouch Key Module Data Memory . The T ouch Key Modul Data Memory is located in sector 5 and sector 6 respectively with a start address of 00H. Device Special Purpose Data Memory General Purpose Data Memory Touch Key Module Data Memory Located Sectors Capacity Sector : Address Sector : Address BSF340 0 1 1 x 8 0: 80H~FFH 1: 80H~FFH : 80H~FFH 3: 80H~FFH : 00H~17H : 00H~17H BSF30 0 1 78 x 8 0: 80H~FFH 1: 80H~FFH : 80H~FFH : 00H~7H : 00H~7H BSF30 0 1 104 x 8 0: 80H~FFH 1: 80H~FFH 7: 80H~FFH : 00H~37H : 00H~37H BSF370 0 1 13 x 8 0: 80H~FFH 1: 80H~FFH 11: 80H~FFH : 00H~47H : 00H~47H Data Memory Summary

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H 7FH 80H FFH Speial Pupose Data Meoy Geneal Pupose Data Meoy Seto 0 Seto 1 Seto N (Seto 0 ~ Seto 1) (Seto 0 ~ Seto N) Note: N=3 fo BSF340; N= fo BSF30; N=7 fo BSF30; Touh Key Module Data Meoy (Seto ~Seto ) N=11 fo BSF370 Data Memory Structure Data Memory Addressing For these devices that support the extended instructions, there is no Bank Pointer for Data Memory . The Bank Pointer , PBP , is only avai lable for Program Memory . For Data Memory the desired Sector is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access. Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. For the accessed data memory which is located in any data memory s ectors except s ector 0, the extended ins tructions can be us ed to acces s the data memory instead o f u sing t he i ndirect a ddressing a ccess. T he m ain d ifference b etween st andard i nstructions and exten ded instructions is that the data memory address "m" in the extended instructions can be from 10 bits to 1 1 bits depending upon which device is selected, the high byte indicates a sector and the low byte indicates a specific address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . It is this area of RAM memory that is known as General Purpose Data Memory . This area of Data Memory is fully accessible by the user programing for both reading and wr iting o perations. B y u sing t he b it o peration i nstructions i ndividual b its c an b e se t o r r eset under program control giving the user a lar ge range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant Special Function Register section. Note that for locat ions that are unused, any read instruction to these addresses will return the value "00H".

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H IAR0 01H MP0 0H IAR1 03H MP1L 04H 0H ACC 0H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH LVDC 0DH INTEG 0EH 0FH 10H INTC0 11H 19H PAPU 18H PAWU 1BH 1AH 1DH 1CH 1FH PA PAC 13H 14H MFI0 MFI1 17H : Unused ead as 00H MFI WDTC TB0C CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH H BH AH DH CH FH EH H H EEA 40H 41H 43H 44H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH H MFI3 LVRC EED 1EH EEC Seto 0 Seto 0 Seto 1 H H H H H AH BH CH DH EH FH 70H30H 31H 38H 3CH 33H 34H 37H 3BH 39H 3AH 71H 73H 74H 7BH PBC PBPU PB 3DH 3FH 3EH 7FH MP1H IAR MPL MPH PSCR0 TB1C SCC HXTC LXTC RSTC PCC PCPU PC AH BH CH DH EH FH SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FDL FDH FD3L FD3H Seto 1 HIRCC RSTFC INTC1 INTC ADRL ADCR0 ADRH ADCR1 PSCR1 SLEDC PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC TSC3 PE PEC PEPU 77H 78H USR UCR1 UCR TXR_RXR BRG 79H 7AH TKTMR TKC0 TK1DL TK1DH TKC1 TKM01DL TKM01DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C TKM11DL TKM11DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC IFS PAS0 PAS1 PBS0 PBS1 PCS0 PES0 PES1 Special Purpose Data Memory Structure – BS66F340

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H IAR0 01H MP0 0H IAR1 03H MP1L 04H 0H ACC 0H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH LVDC 0DH INTEG 0EH 0FH 10H INTC0 11H 19H PAPU 18H PAWU 1BH 1AH 1DH 1CH 1FH PA PAC 13H 14H MFI0 MFI1 17H : Unused ead as 00H MFI WDTC TB0C CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH H BH AH DH CH FH EH H H EEA 40H 41H 43H 44H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH H MFI3 LVRC EED 1EH EEC Seto 0 Seto 0 Seto 1 H H H H H AH BH CH DH EH FH 70H30H 31H 38H 3CH 33H 34H 37H 3BH 39H 3AH 71H 73H 74H 7BH PBC PBPU PB 3DH 3FH 3EH 7FH MP1H IAR MPL MPH PSCR0 TB1C SCC HXTC LXTC RSTC PCC PCPU PC AH BH CH DH EH FH SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FDL FDH FD3L FD3H Seto 1 HIRCC RSTFC INTC1 INTC PD PDC PDPU ADRL ADCR0 ADRH ADCR1 PSCR1 SLDEC PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC TSC3 PE PEC PEPU 77H 78H USR UCR1 UCR TXR_RXR BRG 79H 7AH TKTMR TKC0 TK1DL TK1DH TKC1 TKM01DL TKM01DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C TKM11DL TKM11DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC TKM31DL TKM31DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 TKM3C IFS PAS0 PAS1 PBS0 PBS1 PCS0 PDS1 PES0 PES1 FC TKM41DL TKM41DH TKM4ROL TKM4ROH TKM4C0 TKM4C1 TKM4C PCS1 PDS0 Special Purpose Data Memory Structure – BS66F350

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H IAR0 01H MP0 0H IAR1 03H MP1L 04H 0H ACC 0H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH LVDC 0DH INTEG 0EH 0FH 10H INTC0 11H 19H PAPU 18H PAWU 1BH 1AH 1DH 1CH 1FH PA PAC 13H 14H MFI0 MFI1 17H : Unused ead as 00H MFI WDTC TB0C CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH H BH AH DH CH FH EH H H EEA 40H 41H 43H 44H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH H MFI3 LVRC EED 1EH EEC Seto 0 Seto 0 Seto 1 H H H H H AH BH CH DH EH FH 70H30H 31H 38H 3CH 33H 34H 37H 3BH 39H 3AH 71H 73H 74H 7BH PBC PBPU PB 3DH 3FH 3EH 7FH MP1H IAR MPL MPH PSCR0 TB1C SCC HXTC LXTC RSTC PCC PCPU PC AH BH CH DH EH FH SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FDL FDH FD3L FD3H Seto 1 HIRCC RSTFC INTC1 INTC PD PDC PDPU ADRL ADCR0 ADRH ADCR1 PSCR1 SLEDC PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC TSC3 PE PEC PEPU 77H 78H USR UCR1 UCR TXR_RXR BRG 79H 7AH TKTMR TKC0 TK1DL TK1DH TKC1 TKM01DL TKM01DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C TKM11DL TKM11DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC TKM31DL TKM31DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 TKM3C IFS PAS0 PAS1 PBS0 PBS1 PCS0 PDS1 PES0 PES1 FC TKM41DL TKM41DH TKM4ROL TKM4ROH TKM4C0 TKM4C1 TKM4C PCS1 PDS0PBP PF PFC PFPU TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC PFS0 Special Purpose Data Memory Structure – BS66F360

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 00H IAR0 01H MP0 0H IAR1 03H MP1L 04H 0H ACC 0H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH LVDC 0DH INTEG 0EH 0FH 10H INTC0 11H 19H PAPU 18H PAWU 1BH 1AH 1DH 1CH 1FH PA PAC 13H 14H MFI0 MFI1 17H : Unused ead as 00H MFI WDTC TB0C CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH H BH AH DH CH FH EH H H EEA 40H 41H 43H 44H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH H MFI3 LVRC EED 1EH EEC Seto 0 Seto 0 Seto 1 H H H H H AH BH CH DH EH FH 70H30H 31H 38H 3CH 33H 34H 37H 3BH 39H 3AH 71H 73H 74H 7BH PBC PBPU PB 3DH 3FH 3EH MP1H IAR MPL MPH PSCR0 TB1C SCC HXTC LXTC RSTC PCC PCPU PC AH BH CH DH EH FH SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC FC0 FC1 FARL FARH FD0L FD0H FD1L FD1H FDL FDH FD3L FD3H Seto 1 HIRCC RSTFC INTC1 INTC PD PDC PDPU ADRL ADCR0 ADRH ADCR1 PSCR1 SLEDC PTMC0 PTMC1 PTMDL PTMDH PTMAL PTMAH PTMRPL PTMRPH STMC0 STMC1 STMDL STMDH STMAL STMAH STMRP CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH TSC0 TSC1 TSC TSC3 PE PEC PEPU 77H 78H USR UCR1 UCR TXR_RXR BRG 79H 7AH TKTMR TKC0 TK1DL TK1DH TKC1 TKM01DL TKM01DH TKM0ROL TKM0ROH TKM0C0 TKM0C1 TKM0C TKM11DL TKM11DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM1C TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC TKM31DL TKM31DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 TKM3C IFS PAS0 PAS1 PBS0 PBS1 PCS0 PDS1 PES0 PES1 FC TKM41DL TKM41DH TKM4ROL TKM4ROH TKM4C0 TKM4C1 TKM4C PCS1 PDS0PBP PF PFC PFPU TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC TKM1DL TKM1DH TKMROL TKMROH TKMC0 TKMC1 TKMC PFS0 SLEDC1 PG PGC PGPU 7CH 7DH 7FH 7EH TKM71DL TKM71DH TKM7ROL TKM7ROH TKM7C0 TKM7C1 TKM7C PGS0 PGS1 PHPU PH PHC TKM81DL TKM81DH TKM8ROL TKM8ROH TKM8C0 TKM8C1 TKM8C Special Purpose Data Memory Structure – BS66F370

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM register space, do not actually physically exist as normal registers. The method of indirect addressing for RAM data manipulation uses these Indirect Addressing Registers and Memory Pointers, in contrast to direct memory addressing, where the actual memory address is specified. Actions on the IAR0, IAR1 and IAR2 registers will result in no actual read or write operation to these registers but ra ther t o t he m emory l ocation spe cified by t heir c orresponding Me mory Poi nters, MP0, MP1L / MP1H or MP2L /MP2H. Ac ting a s a pa ir, IAR0 a nd MP0 c an t ogether a ccess da ta onl y from Se ctor 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector . As the Indirect Addressing Registers are not physically implemented, reading the Indirect Addressing Registers indirectly will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These Memory Pointers are phys ically implemented in the D ata M emory and can be manipulated in the same wa y a s n ormal r egisters p roviding a c onvenient wa y wi th wh ich t o a ddress a nd t rack d ata. When any operati on to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer . MP0, together with Indirect Addressing Register , IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. Indirect Addressing Program Example

Example 1 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue:

Example 2 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ‘code’ org 00h start: mov a,04h ; setup size of block mov block,a mov a,01h ; setup the memory sector mov mp1h,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp1l,a ; setup memory pointer with first RAM address loop: clr IAR1 ; clear the data at address defined by MP1 inc mp1l ; increment memory pointer MP1L sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Direct Addressing Program Example using extended instructions data .section ‘data’ temp db ? code .section at 0 code org 00h start: lmov a ,[m] ; move [m] data to acc lsub a , [m+1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp continue ; no lmov a ,[m] ; yes, exchange [m] and [m+1] data mov temp,a lmov a,[m+1] lmov [m],a mov a,temp lmov [m+1],a continue: Note: Here "m" is a data memory address located in any data memory sectors. For example, m=1F0H, it indicates address 0F0H in Sector 1.

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Program Memory Bank Pointer – PBP For the BS 66F360 and BS 66F370 device the P rogram M emory is divided into s everal banks . Selecting the required Program Memory area is achieved using the Program Memory Bank Pointer , PBP. T he PBP re gister should be prope rly c onfigured be fore t he de vice e xecutes t he "Bra nch" operation using the "JMP" or "CALL" instruction. After that a jump to a non-consecutive Program Memory address which is located in a certain bank selected by the program memory bank pointer bits will occur. PBP Register – BS66F360 Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 PBP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~1 D7~D1: General data bits and can be read or written. Bit 0 PBP0: Program Memory Bank Point bit 0 0: Bank 0 1: Bank 1 PBP Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Nae D D D4 D3 D D1 PBP1 PBP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~2 D6~D1: General data bits and can be read or written. Bit 1~0 PBP1~PBP0: Program Memory Bank Point bit1~bit 0 00: Bank 0 01: Bank 1 10: Bank 2 11: Bank 3 Accumulator – ACC The A ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. W ithout the Accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he Da ta Me mory resulting i n highe r program ming and t iming overheads. Da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he Ac cumulator; for e xample, wh en t ransferring da ta be tween one user defi ned regi ster and anot her, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory . By manipulating this register , direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted.

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Look-up Table Registers – TBLP, TBHP, TBLH These three special function registers are used to cont rol operation of the look-up table which is stored i n t he Progra m Me mory. T BLP a nd T BHP a re t he t able poi nter a nd i ndicates t he l ocation where the table data is located. Their value must be setup before any table read commands are executed. Their value can be changed, for example using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored afte r a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (T O). These arithmetic/ logical o peration a nd sy stem m anagement fla gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. With the exceptio n of the T O and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the T O or PDF flag. In addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. The T O flag can be af fected only by a system power -up, a WDT time-out or by executing the "CLR WDT" or "HAL T" instruction. The PDF flag is af fected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations.

C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also af fected by a rotate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by a system power -up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction.
TO is cle ared by a system power -up or executing the "CLR WDT" or "HAL T" instruction. T O is set by a WDT time-out.
SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the current instruction operation result.
CZ is the operational result of dif ferent flags for dif ferent instuctions. Refer to register definitions for more details. In additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it.

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver STATUS Register Bit 7 6 5 4 3 2 1 0 Nae SC CZ TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W POR x x 0 0 x x x x "x": unknown Bit 7 SC: The result of the "XOR" operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The the operational result of different flags for different instuctions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM ins tructions, the CZ flag is the " AND" operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag willl not be affected. Bit 5 TO: W atchdog T ime-out flag 0: After power up ow executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred Bit 4 PDF: Power down flag 0: After power up ow executing the "CLR WDT" instruction 1: By executing the "HALT" instructin Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in substraction Bit 0 C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The "C" flag is also affected by a rotate through carry instruction.

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver EEPROM Data Memory These d evices c ontain a n a rea o f i nternal E EPROM Da ta Me mory. E EPROM, wh ich st ands f or Electrically E rasable Progra mmable Re ad Onl y Me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. By incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . The avail ability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. Device Capacity Address BSF340 18 x 8 00H ~ 7FH BSF30 BSF30 BSF370 EEPROM Data Memory Structure The EEP ROM Data Memory capacity is 128×8 bits for the series of devices . Unlike the Program Memory and RAM Data Memory , the EEPROM Data Memory is not directly mapped into memory space and is there fore not directly addressable in the same way as the other types of memory . Read and W rite operatio ns to the EEPROM are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory . These are the address register , EEA, the data register , EED and a single control register , EEC. As both the EEA and EED registers are located in sector 0, they can be directly accessed in the same was as any other Special Function Register . The EEC register , however , being located in sector 1, can be read from or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect Addressing Register , IAR1 or IAR2. Because the EEC control register is located at address 40H in se ctor 1, t he Me mory Poi nter l ow byt e re gister, MP1L or MP2L , m ust first be se t t o t he va lue 40H and the Memory Pointer high byte register , MP1H or MP2H, set to the value, 01H, before any operations on the EEC register are executed. Register Name Bit 7 6 5 4 3 2 1 0 EEA — EEA EEA EEA4 EEA3 EEA EEA1 EEA0 EED D7 D D D4 D3 D D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Registers List EEA Register Bit 7 6 5 4 3 2 1 0 Nae — EEA EEA EEA4 EEA3 EEA EEA1 EEA0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as 0. Bit 6~0 EEA6~EEA0: Data EEPROM address bit 6 ~ bit0

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver EED Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: Data EEPROM data bit 7~bit0 EEC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3 WREN: Data EEPROM write enable 0: Disable 1: Enable This is the D ata EEP ROM W rite Enable Bit w hich mus t be s et high before D ata EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM write control 0: W rite cycle has finished 1: Activate a write cycle This i s t he Da ta E EPROM W rite C ontrol B it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no ef fect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM read enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero w ill inhibit D ata EEPROM read operations. Bit 0 RD: EEPROM read control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the applic ation program will activ ate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no ef fect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time. Reading Data from the EEPROM To read data from the EEP ROM, the read enable bit, RDEN , in the EEC register must firs t be set high to enable the read function. The EEPROM address of the data to be read must then be placed in the EEA register . If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle term inates, the RD bit will be automatically cleared to zero, after which the data can be read from the EED register . The data will remain in the EED register until another read or write operation i s e xecuted. T he a pplication pr ogram c an po ll t he R D bi t t o de termine whe n t he da ta i s valid for reading.

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in t he EE A regist er and t he dat a pla ced in t he EE D regist er. Then t he writ e enabl e bit , WREN, in the EEC register must first be set high to enable the write function. After this, the WR bit in the E EC r egister m ust be i mmediately se t hi gh t o i nitiate a wri te c ycle. T hese t wo i nstructions must be executed consecutively . The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt. When the write cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller , informing the user that the data has been written to the EEPROM. The application program can therefore poll the WR bit to determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered on, the W rite Enable bit in the control regis ter w ill be cleared preventing any w rite operations. Also at power -on the Memory Pointer high byte register , MP1H or MP2H, will be reset to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control register is located in sector 1, this adds a further measure of protection against spurious write operations. During normal program operati on, ensuring that the W rite Enable bit in the cont rol re gister is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register . However , as the EEPROM is contained within a Multi-function Interrupt, the associated multi-function interrupt enable bit must als o be set. When an EEPROM w rite cycle ends, the D EF reques t flag and its associated multi-function interrupt request flag will both be set. If the global, EEPROM and Multi- function interrupts are enabled and the stack is not full, a jump to the associated Multi-function Interrupt vector will take place. When the interrupt is serviced only the Multi-function interrupt flag will be automatically reset, the EEPROM interrupt flag must be manually reset by the application program. Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be Periodic by ensuring that the W rite Enable bit is normally cleared to zero when not writing. Also the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1 where the EEPROM control registe r exist. Although certainly not necessary , consideration might be given in the appli cation program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly . The global interrupt bit EMI should also be cleare d before a write cycle is executed and then re-enabled after the write cycle starts. Note that the devic e should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail.

Reading data from the EEPROM – polling method MOV A , EEPROM_ADRES ; user defined address MOV E EA, A MOV A , 040H ; setup memory pointer low byte MP1L MOV M P1L, A ; MP1L points to EEC register MOV A , 01H ; setup Memory Pointer high byte MP1H MOV M P1H, A SET I AR1.1 ; set RDEN bit, enable read operations S E T I A R 1 . 0 ; s t a r t R e a d C y c l e - s e t R D b i t BACK: S Z I A R 1 . 0 ; c h e c k f o r r e a d c y c l e e n d JMP B ACK C L R I A R 1 ; d i s a b l e E E P R O M w r i t e CLR M P1H MOV A , EED ; move read data to register MOV R EAD_DATA, A
Writing Data to the EEPROM – polling method MOV A , EEPROM_ADRES ; user defined address MOV E EA, A MOV A , EEPROM_DATA ; user defined data MOV E ED, A MOV A , 040H ; setup memory pointer low byte MP1L MOV M P1L, A ; MP1L points to EEC register MOV A , 01H ; setup Memory Pointer high byte MP1H MOV M P1H, A CLR E MI SET I AR1.3 ; set WREN bit, enable write operations S E T I A R 1 . 2 ; s t a r t W r i t e C y c l e - s e t W R b i t SET E MI BACK: S Z I A R 1 . 2 ; c h e c k f o r w r i t e c y c l e e n d JMP B ACK C L R I A R 1 ; d i s a b l e E E P R O M w r i t e CLR M P1H

Rev. 1.40 70 Deee 1 01 Rev. 1.40 71 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Oscillators Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of application program and relevant control registers. Oscillator Overview In additio n to being the source of the main system clock the oscillators also provide clock sources for t he W atchdog T imer a nd T ime B ase I nterrupts. E xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. Al l osc illator op tions a re selected through register programming. The higher frequency oscillators provide higher performance but carry with it the disadvantage of higher power requirements, while the opposite is of course true for the lower frequency oscillators. W ith the capability of dynamically switching between fast and slow system clock, the device has the flexibility to optimize the performance/power ratio, a feature especially important in power sensitive portable applications. Type Name Frequency Pins Extenal High Speed Cystal HXT 400 kHz~0 MHz OSC1/OSC Intenal High Speed RC HIRC 8/1/1 MHz — Extenal Low Speed Cystal LXT 3.78 kHz XT1/XT Intenal Low Speed RC LIRC 3 kHz — Oscillator Types System Clock Configurations There are four methods of generating the system clock, two high speed oscillators for all devices and two low speed oscillators. The high speed oscillator is the external crystal/ceramic oscillator , HXT , and the internal 8/12/16 MHz RC oscillator , HIRC. The two low speed oscillators are the internal 32 kHz RC oscillator , LIRC, and the external 32.768 kHz crystal oscillator , LXT . Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the CKS2~CKS0 bits in the SCC register and as the system clock can be dynamically selected. The actual source clock us ed for the low speed os cillators is chosen via the FSS bit in the SCC register while for the high speed oscillator the source clock is selected by the FHS bit in the SCC register. T he fre quency of t he sl ow spe ed or hi gh spe ed syst em c lock i s de termined usi ng t he CKS2~CKS0 bits in the SCC register . Note that two oscillator selectio ns must be made namely one high speed and one low speed system oscillators. It is not possible to choose a no-oscillator selection for either the high or low speed oscillator.

Rev. 1.40 70 Deee 1 01 Rev. 1.40 71 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver HXT Pesale fH LXT High Speed Osillatos Low Speed Osillatos fH/ fH/1 fH/4 fH/8 fH/4 fH/3 CKS~CKS0 fSYS fSUB fSUB HXTEN FSS LIRC LXTEN fLIRC fLIRC HIRCHIRCEN fH FHS System Clock Configurations External Crystal/Ceramic Oscillator – HXT The E xternal C rystal/Ceramic Sy stem Osc illator i s t he h igh f requency o scillator, wh ich i s t he default oscillator clock source after power on. For most crystal oscillator configurations, the simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feedback for oscillation, without requiring extern al capacitors. However , for some crystal types and frequencies, to ensure oscillation, it may be necessary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur . The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer’s specification. For oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. /G4F/G53 /G43/G31 /G4F/G53 /G43/G32 /G52/G66 /G54/G6F /G20/G69 /G6E/G74 /G65/G72 /G6E/G61/G6C /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G49/G6E /G74/G65 /G72/G6E /G61/G6C /G4F /G73/G63/G69 /G6C/G6C/G61 /G74/G6F /G72 /G43/G69 /G72/G63 /G75/G69 /G74 /G43/G31 /G43/G32 /G52/G70 /G4E/G6F /G74/G65 /G3A/G31 /G2E/G20 /G52/G70 /G20/G69 /G73/G20 /G6E/G6F/G72 /G6D/G61 /G6C/G6C/G79 /G20 /G6E/G6F/G74 /G20/G72 /G65/G71/G75/G69 /G72 /G65/G64/G2E /G20/G43 /G31/G20 /G61/G6E/G64/G20 /G43/G32 /G20/G61 /G72/G65 /G20/G72 /G65/G71/G75 /G69/G72 /G65/G64/G2E /G32/G2E /G20/G41 /G6C/G74 /G68/G6F/G75/G67/G68/G20 /G6E/G6F/G74 /G20/G73 /G68/G6F/G77 /G6E/G20 /G4F/G53 /G43/G31 /G2F/G4F /G53/G43 /G32/G20 /G70/G69 /G6E/G73 /G20/G68 /G61/G76 /G65/G20 /G61/G20 /G70/G61 /G72/G61 /G73/G69 /G74/G69 /G63 /G20/G20/G20/G20/G63 /G61/G70/G61/G63 /G69/G74 /G61/G6E /G63/G65 /G20/G6F /G66/G20/G61 /G72 /G6F/G75/G6E/G64/G20 /G37/G70/G46 /G2E Crystal/Resonator Oscillator HXT Oscillator C1 and C2 Values Crystal Frequency C1 C2 1MHz 0 pF 0 pF 8MHz 0 pF 0 pF 4MHz 0 pF 0 pF 1MHz 100 pF 100 pF Note: C1 and C values ae fo guidane only. Crystal Recommended Capacitor Values

Rev. 1.40 7 Deee 1 01 Rev. 1.40 73 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a fixed frequency of 8/12/16 MHz. Device trimming during the manufacturing process and the inclusion of internal frequency compensati on circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised . As a result, at a power supply of 3V or 5V and at a temperature of 25°C degrees, the fixed oscillation frequency of 12MHz will have a tolerance within 2%. Note that if this interna l system clock option is selected, as it requires no external pins for its operation, I/ O pins are free for use as normal I/O pins. External 32.768 kHz Crystal Oscillator – LXT The Exte rnal 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. This clock source has a fixed frequency of 32.768 kHz and requires a 32.768 kH z crys tal to be connected betw een pins X T1 and X T2. The external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide oscillation. For a pplications whe re pre cise fre quencies a re e ssential, t hese c omponents m ay be required to provide frequency compensation due to dif ferent crystal manufacturing tolerances. After the LXT oscillator is enabled by setting the LXTEN bit to 1, there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microcontroller enters the SLEEP or IDLE Mode, the system clock is switched of f to stop microcontroller activity and to conserve power . However , in many microcontroller applications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. T o do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer ’s specification. The external parallel feedback resistor, Rp, is required. The pin-shared software control bits determine if the XT1/XT2 pins are used for the LXT oscillator or as I/O or other pin-shared functional pins.

If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O or other pin-shared functional pins.
If the LXT oscilla tor is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. /G54/G6F /G20/G69 /G6E/G74 /G65/G72 /G6E/G61/G6C /G63/G69 /G72/G63 /G75/G69 /G74/G73 /G49/G6E /G74/G65 /G72/G6E /G61/G6C /G4F /G73/G63/G69 /G6C/G6C /G61/G74 /G6F/G72 /G43/G69 /G72/G63 /G75/G69 /G74 /G43/G31 /G43/G32 /G52/G70 /G4E/G6F /G74/G65 /G3A/G31 /G2E/G20 /G52/G70 /G2C/G20/G43 /G31/G20 /G61/G6E/G64 /G20/G43 /G32/G20 /G61/G72 /G65/G20 /G72/G65 /G71/G75/G69 /G72 /G65/G64/G2E /G32/G2E /G20/G41 /G6C/G74 /G68/G6F/G75/G67/G68/G20 /G6E/G6F/G74 /G20/G73 /G68/G6F/G77 /G6E/G20 /G70/G69 /G6E/G73 /G20/G68 /G61/G76 /G65/G20 /G61 /G20/G20/G20/G20 /G70/G61/G72 /G61/G73 /G69/G74 /G69/G63 /G20/G63 /G61/G70/G61/G63 /G69/G74 /G61/G6E /G63/G65 /G20/G6F /G66/G20 /G61/G72 /G6F/G75/G6E/G64/G20 /G37/G70/G46 /G2E /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G43 /G4F /G73/G63 /G69/G6C/G6C/G61 /G74/G6F /G72 /G33/G32/G2E /G37/G36 /G38 /G6B/G48 /G7A /G58/G54 /G31 /G58/G54 /G32 External LXT Oscillator

Rev. 1.40 7 Deee 1 01 Rev. 1.40 73 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LXT Oscillator Low Power Function The L XT osc illator ca n funct ion i n one of t wo mode s, t he Spe ed-Up Mode and t he L ow-Power Mode. The mode selection is executed using the LXTSP bit in the LXTC register. LXTSP LXT Operating Mode

0 Low-Powe

1 Speed-Up

When the LXTSP bit is set to high, the LXT Quick Start Mode will be enabled. In the Speed-U p Mode the LXT oscillator will power up and stabilise quickly . However , after the LXT oscillator has fully powered up, it can be placed into the Low-Power Mode by clearin g the LXTSP bit to zero and the oscill ator will continue to run but with reduced current consumption. It is important to note that the LXT operating mode switching must be properly controlled before the LXT oscillator clock is selected as the system clock source. Once the LXT oscillator clock is selected as the system clock source using the CKS bit field and FSS bit in the SCC register , the LXT oscillator operating mode can not be changed. It should be note that no matter what condition the LXTSP is set to the LXT oscillator will always function normally . The only dif ference is that it will take more time to start up if in the Low Power Mode. Internal 32kHz Oscillator – LIRC The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is selected via a software control bit, FSS. It is a fully integrated RC oscillator with a typical frequency of 32 kHz at 5V , requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. As a result, at a power supply of 5V and at a temperature of 25˚C degrees, the fixed oscillation frequency of 32 kHz will have a tolerance within 10%.

Rev. 1.40 74 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Operating Modes and System Clocks Present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conflicting requirements that are especially true i n ba ttery powe red port able a pplications. T he fa st c locks re quired for hi gh pe rformance wi ll by t heir na ture i ncrease c urrent c onsumption a nd of c ourse vi ce-versa, l ower spe ed c locks re duce current consumption. As Holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks Each device has dif ferent clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency , fH, or low frequency , fSUB, source, and is selected using the CKS2~CKS0 bits in the SCC register . The high speed system clock is sourced from an HXT or HIRC oscillator , selected via configuring the FHS bit in the SCC register . The low speed system clock source can be sourced from the internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillators, selected via configuring the FSS bit in the SCC register . The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64.

Rev. 1.40 74 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver HXT Pesale fH LXT High Speed Osillatos Low Speed Osillatos fH/ fH/1 fH/4 fH/8 fH/4 fH/3 CKS~CKS0 fSYS fSUB fSUB HXTEN FSS LIRC LXTEN fLIRC fLIRC HIRCHIRCEN fH LVR WDT fLIRC fSYS/4 fPSC0 Tie Base 0 CLKSEL0[1:0] fSUB fSYS Pesale 0 TB0[:0] fSYS/4 CLKSEL1[1:0] fSUB fSYS FHS fPSC1 Tie Base 1Pesale 1 TB1[:0] Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation can be stopped to conserve the power or continue to oscillate to provide the clock source, fH~fH/64, for peripheral circuit to use, which is determined by configuring the corresponding high speed oscillator enable control bit.

Rev. 1.40 7 Deee 1 01 Rev. 1.40 77 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver System Operation Modes There are six dif ferent modes of operation for the microcontroller , each one with its ow n special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. There are two modes all owing normal operati on of the microcontroller, the NORMAL Mode and SLOW Mode. The remaining four modes, the SLEEP , IDLE0, IDLE1 and IDL E2 Mode are used when the microcontroller CPU i s switched off t o conserve power. Operation Mode CPU Register Setting fSYS fH fSUB fLIRC FHIDEN FSIDEN CKS2~CKS0 NORMAL On x x 000~110 fH~fH/4 On On On SLOW On x x 111 fSUB On/Off (1) On On IDLE0 Off 0 1 000~110 Off Off On On111 On IDLE1 Off 1 1 xxx On On On On IDLE Off 1 0 000~110 On On Off On111 Off SLEEP Off 0 0 xxx Off Off Off On Note: 1. The fH clock will be switched on or of f by configuring the corresponding oscillator enable bit in the SLOW mode. 2. The fLIRC clock will be switched on since the WDT function is always enabled. NORMAL Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators. This mode operate s allowing the microcontroller to operate normally with a clock source will come from one of the high speed oscillators, either the HXT or HIRC oscillators. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 bits in the SCC register .Although a high speed oscillator is used, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the LIRC or LXT oscillator. SLEEP Mode The SLEEP Mode is entered when an HAL T instruction is executed and when the FHIDEN and FSIDEN bit are low . In the SLEEP mode the CPU will be stopped. However the fLIRC clock still continues to operate since the WDT function is always enabled. IDLE0 Mode The IDLE0 Mode is entered when an HAL T instruction is executed and when the FHIDEN bit in the S CC regis ter is low and the F SIDEN bit in the S CC regis ter is high. In the ID LE0 M ode the CPU wi ll be swi tched of f but t he l ow spe ed osc illator wi ll be t urned on t o dri ve som e pe ripheral functions.

Rev. 1.40 7 Deee 1 01 Rev. 1.40 77 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver IDLE1 Mode The IDLE1 Mode is entered when an HAL T instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is high. In the IDLE1 Mode the CPU will be switched of f but both the high and low speed oscillators will be turned on to provide a clock source to keep some peripheral functions operational. IDLE2 Mode The IDLE2 Mode is entered when an HAL T instruction is executed and when the FHIDEN bit in the SCC register is high and the FSIDEN bit in the SCC register is low . In the IDLE2 Mode the CPU will be switched of f but the high speed oscillator will be turned on to provide a clock source to keep some peripheral functions operational. Control Registers The registers, SCC, HIRCC, HXTC and LXTC, are used to control the system clock and the corresponding oscillator configurations. Register Name Bit 7 6 5 4 3 2 1 0 SCC CKS CKS1 CKS0 — FHS FSS FHIDEN FSIDEN HIRCC — — — — HIRC1 HIRC0 HIRCF HIRCEN HXTC — — — — — HXTM HXTF HXTEN LXTC — — — — — LXTSP LXTF LXTEN System Operating Mode Control Registers List SCC Register Bit 7 6 5 4 3 2 1 0 Nae CKS CKS1 CKS0 — FHS FSS FHIDEN FSIDEN R/W R/W R/W R/W — R/W R/W R/W R/W POR 0 0 0 — 0 0 0 0 Bit 7~5 CKS2~CKS0: System clock selection 000: fH 001: fH/2 010: fH/4 011: fH/8 100: fH/16 101: fH/32 110: fH/64 111: fSUB These three bits are used to select which clock is used as the system clock source. In addition to the system clock source directly derived from fH or fSUB, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as 0. Bit 3 FHS: High Frequency clock selection 0: HIRC 1: HXT Bit 2 FSS: Low Frequency clock selection 0: LIRC 1: LXT

Rev. 1.40 78 Deee 1 01 Rev. 1.40 79 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1 FHIDEN: High Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing an "HALT" instruction. Bit 0 FSIDEN: Low Frequency oscillator control when CPU is switched off 0: Disable 1: Enable This bi t i s use d t o cont rol whe ther t he l ow spe ed osc illator i s ac tivated or st opped when the CPU is sw itched of f by executing an " HALT" instruction. The LIRC oscillator is controlled by this bit together with the WDT function enable control when the LIRC is selected to be the low speed oscillator clock source or the WDT function is enabled respectively . If this bit is cleared to 0 but the WDT function is enabled, the LIRC oscillator will also be enabled. HIRCC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — HIRC1 HIRC0 HIRCF HIRCEN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 1 Bit 7~4 Unimplemented, read as 0. Bit 3~2 HIRC1~HIRC0: HIRC frequency selection 00: 8 MHz 01: 12 MHz 10: 16 MHz 11: 8 MHz When the HIRC oscillator is enabled or the HIRC frequency selection is changed by application program, the clock frequency w ill automatically be changed after the HIRCF flag is set to 1. Bit 1 HIRCF: HIRC oscillator stable flag 0: HIRC unstable 1: HIRC stable This bit is used to indi cate whe ther the HIRC oscilla tor is stable or not. When the HIRCEN bit is set to 1 to enable the HIRC oscillator or the HIRC frequency selection is c hanged by a pplication progra m, t he HIRCF bi t wi ll first be c leared t o 0 a nd t hen set to 1 after the HIRC oscillator is stable. Bit 0 HIRCEN: HIRC oscillator enable control 0: Disable 1: Enable

Rev. 1.40 78 Deee 1 01 Rev. 1.40 79 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver HXTC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — — HXTM HXTF HXTEN Bit 7~3 Unimplemented, read as 0. Bit 2 HXTM: HXT mode selection 0: HXT frequency ≤ 10 MHz 1: HXT frequency >10 MHz This bit is used to select the HXT oscillator operating mode. Note that this bit must be properly configured before the HXT is enabled. When the HXTEN bit is set to 1 to enable the HXT oscillator, it is invalid to change the value of this bit. Bit 1 HXTF: HXT oscillator stable flag 0: HXT unstable 1: HXT stable This bit is used to indicate whether the HXT oscillator is stable or not. When the HXTEN bit is set to 1 to enable the HXT oscillator , the HXTF bit will first be cleared to 0 and then set to 1 after the HXT oscillator is stable. Bit 0 HXTEN: HXT oscillator enable control 0: Disable 1: Enable LXTC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — — LXTSP LXTF LXTEN Bit 7~3 Unimplemented, read as 0. Bit 2 LXTSP: LXT oscillator speed-up control 0: Disable – Low power 1: Enable – Speed up This bit is used to control whether the LXT oscillator is operating in the low power or quick start mode. When the LXTSP bit is set to 1, the LXT oscillato r will oscillate quickly but consume more power . If the LXTSP bit is cleared to 0, the LXT oscillator will consume less power but take longer time to stablise. It is important to note that this bi t c an not be c hanged a fter t he L XT osc illator i s se lected a s t he syst em c lock source using the CKS2~CKS0 and FSS bits in the SCC register. Bit 1 LXTF: LXT oscillator stable flag 0: LXT unstable 1: LXT stable This bi t i s use d t o i ndicate whe ther t he L XT osc illator i s st able or not . W hen t he LXTEN bit is set to 1 to enable the LXT oscillator , the LXTF bit will first be cleared to 0 and then set to 1 after the LXT oscillator is stable. Bit 0 LXTEN: LXT oscillator enable control 0: Disable 1: Enable

Rev. 1.40 80 Deee 1 01 Rev. 1.40 81 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Operating Mode Switching These devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the pres ent task in hand. In this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the NORMAL Mode and SLOW Mode is executed using the CKS2~CKS0 bits in the SCC register while Mode Switching from the NORMAL/SLOW Modes to t he SL EEP/IDLE Mode s i s e xecuted vi a t he HAL T i nstruction. W hen a n HAL T i nstruction i s executed, whet her t he de vice e nters t he IDLE Mode or t he SLE EP Mode i s de termined by t he condition of the FHIDEN and FSIDEN bits in the SCC register. NORMAL fSYS=fH~fH/4 fH on CPU un fSYS on fSUB on SLOW fSYS=fSUB fSUB on CPU un fSYS on fH on/off IDLE0 HALT instution exeuted CPU stop FHIDEN=0 FSIDEN=1 fH off fSUB on IDLE1 HALT instution exeuted CPU stop FHIDEN=1 FSIDEN=1 fH on fSUB on IDLE2 HALT instution exeuted CPU stop FHIDEN=1 FSIDEN=0 fH on fSUB off SLEEP HALT instution exeuted CPU stop FHIDEN=0 FSIDEN=0 fH off fSUB off

Rev. 1.40 80 Deee 1 01 Rev. 1.40 81 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver NORMAL Mode to SLOW Mode Switching When r unning i n t he NOR MAL Mo de, wh ich u ses t he h igh sp eed sy stem o scillator, a nd t herefore consumes m ore powe r, t he syste m c lock c an swit ch t o run i n t he SL OW Mode by se t t he CKS2~CKS0 bits to "1 11" in the SCC register . This will then use the low speed system oscillator which wi ll c onsume l ess po wer. Use rs m ay de cide t o do t his fo r c ertain op erations whi ch do no t require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator determined by the FSS bit in the SCC register and therefore requires this oscillator to be stable before full mode switching occurs. NORMAL Mode SLOW Mode CKS~CKS0 = 111 SLEEP Mode FHIDEN=0 FSIDEN=0 HALT instution is exeuted IDLE0 Mode FHIDEN=0 FSIDEN=1 HALT instution is exeuted IDLE1 Mode FHIDEN=1 FSIDEN=1 HALT instution is exeuted IDLE2 Mode FHIDEN=1 FSIDEN=0 HALT instution is exeuted

Rev. 1.40 8 Deee 1 01 Rev. 1.40 83 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SLOW Mode to NORMAL Mode Switching In SLOW mode the system clock is derived from fSUB. When system clock is switched back to the NORMAL mode from fSUB, the CKS2~CKS0 bits should be set to "000" ~"1 10" and then the system clock will respectively be switched to fH~ fH/64. However, i f fH i s not use d i n SL OW m ode a nd t hus swi tched of f, i t wi ll t ake som e t ime t o re - oscillate and stabilise when switching to the NORMAL mode from the SLOW Mode. This is monitored using the HXTF bit in the HXTC register or the HIRCF bit in the HIRCC register . The time duration required for the high speed system oscillator stabilization is specified in the A.C. characteristics. NORMAL Mode SLOW Mode CKS~CKS0 = 000~110 SLEEP Mode FHIDEN=0 FSIDEN=0 HALT instution is exeuted IDLE0 Mode FHIDEN=0 FSIDEN=1 HALT instution is exeuted IDLE1 Mode FHIDEN=1 FSIDEN=1 HALT instution is exeuted IDLE2 Mode FHIDEN=1 FSIDEN=0 HALT instution is exeutedEntering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HAL T" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "0". In this mode all the clocks and functions will be switched off except the WDT function. When this instruction is executed under the conditions described above, the following will occur:

The syst em c lock wi ll be st opped a nd t he a pplication progra m wi ll st op a t t he "HAL T" instruction.
The Data Memory contents and registers will maintain their present condition.
The I/O ports will maintain their present conditions.
In t he st atus r egister, t he Po wer Do wn fla g PDF wi ll b e se t, a nd W DT t imeout fla g T O wi ll b e cleared.
The WDT will be cleared and resume counting as the WDT function is always enabled.

Rev. 1.40 8 Deee 1 01 Rev. 1.40 83 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HAL T" instruction in the application program with the FHIDEN bit in the SCC register equal to "0" and the FSIDEN bit in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur:

The fH clock will be stopped and the applic ation program will stop at the "HAL T" instruction, but the fSUB clock will be on.
The Data Memory contents and registers will maintain their present condition.
The I/O ports will maintain their present conditions.
In t he st atus r egister, t he Po wer Do wn fla g PDF wi ll b e se t, a nd W DT t imeout fla g T O wi ll b e cleared.
The WDT will be cleared and resume counting as the WDT function is always enabled. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HAL T" instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to "1". When this instruction is executed under the conditions described above, the following will occur:
The fH and fSUB clocks will be on but the application program will stop at the "HALT" instruction.
The Data Memory contents and registers will maintain their present condition.
The I/O ports will maintain their present conditions.
In t he st atus r egister, t he Po wer Do wn fla g PDF wi ll b e se t, a nd W DT t imeout fla g T O wi ll b e cleared.
The WDT will be cleared and resume counting as the WDT function is always enabled. Entering the IDLE2 Mode There is only one way for the device to enter the IDLE2 Mode and that is to execute the "HAL T" instruction in the application program with the FHIDEN bit in the SCC register equal to "1" and the FSIDEN bit in the SCC register equal to "0". When this instruction is executed under the conditions described above, the following will occur:
The fH clock will be on but the fSUB clock will be of f and the applicatio n program will stop at the "HALT" instruction.
The Data Memory contents and registers will maintain their present condition.
The I/O ports will maintain their present conditions.
In t he st atus r egister, t he Po wer Do wn fla g PDF wi ll b e se t, a nd W DT t imeout fla g T O wi ll b e cleared.
The WDT will be cleared and resume counting as the WDT function is always enabled.

Rev. 1.40 84 Deee 1 01 Rev. 1.40 8 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 and IDLE2 Mode, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special attention must be made to t he I/ O pi ns on t he de vice. Al l hi gh-impedance i nput pi ns m ust be c onnected t o e ither a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumpti on. This also applies to devices which have dif ferent package types, as there may be unbonbed pins. These must eit her be set up as out puts or if setup as inputs must have pul l-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the LIRC oscillator has enabled. In the IDLE1 and IDLE 2 Mode the high speed oscillator is on, if the peripheral function clock source is derived from the high speed oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps. Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched of f. However , when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stablise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:

An external falling edge on Port A
A system interrupt
A WDT overflow When the device executes the "HAL T" instruction, the PDF flag will be set to 1. The PDF flag will be cleare d to 0 if the device experi ences a system power -up or executes the clear W atchdog T imer instruction. If the system is woken up by a WDT overflow , a W atchdog T imer reset will be initiated and the T O flag will be set to 1. The T O flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the P AWU register to permit a negative transition on the pin to wake up the system . When a Port A pin wake-up occurs, the program wil l resume executi on at the instruction following the "HAL T" instruction. If the system is woken up by an interrupt, then two possible situations may occur . The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HAL T" instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but wukk rather be serviced later when the related interrupt is finally enabled o r wh en a st ack l evel b ecomes f ree. T he o ther si tuation i s wh ere t he r elated i nterrupt i s enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set high before entering the SLEEP or IDLE Mode, the wake-up function of the related interrupt will be disabled.

Rev. 1.40 84 Deee 1 01 Rev. 1.40 8 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Watchdog Timer The W atchdog T imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The W atchdog T imer clock source is provided by the internal RC oscillator , fLIRC. The LIRC internal oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary with VDD, tempera ture and process variations . The W atchdog T imer source clock is then subdivided by a ratio of 28 to 218 to give longer timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register , WDTC, controls the required timeout period as well as the enable/disable operation. This register controls the overall operation of the W atchdog T imer. WDTC Register Bit 7 6 5 4 3 2 1 0 Nae WE4 WE3 WE WE1 WE0 WS WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT function enable control 10101 or 01010: Enabled Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the WRF bit in the RSTFC register will be set to 1. Bit 2~0 WS2~WS0: WDT time-out period selection 000: 28/fLIRC 001: 210/fLIRC 010: 212/fLIRC 011: 214/fLIRC 100: 215/fLIRC 101: 216/fLIRC 110: 217/fLIRC 111: 218/fLIRC These t hree b its d etermine t he d ivision r atio o f t he wa tchdog t imer so urce c lock, which in turn determines the time-out period. RSTFC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3 RSTF: Reset control register software reset flag Described elsewhere.

Rev. 1.40 8 Deee 1 01 Rev. 1.40 87 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 LVRF: LVR function reset flag Described elsewhere. Bit 1 LRF: LVR control register software reset flag Described elsewhere. Bit 0 WRF: WDT control register software reset flag 0: Not occurred 1: Occurred This b it i s se t t o 1 b y t he W DT c ontrol r egister so ftware r eset a nd c leared b y t he application program. Note that this bit can only be cleared to 0 by the application program. Watchdog Timer Operation The W atchdog T imer ope rates by provi ding a de vice re set whe n i ts t imer ove rflows. T his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he Watchdog T imer before it overflows to prevent the W atchdog T imer from executing a reset. This is done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instructio n will not be executed in the correct manner, in which case the W atchdog T imer will overflow and reset the device. W ith regard to the W atchdog T imer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to of fer the enable /disable control and reset control of the W atchdog T imer. The WDT function will be enable d when the WE4~WE0 bits are set to a value of 01010B or 10101B. If the WE4~WE0 bits are se t t o a ny o ther v alues o ther t han 0 1010B a nd 1 0101B, i t wi ll r eset t he d evice a fter 2 ~3 fLIRC clock cycles. After power on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B o 01010B Enale Any othe value Reset MCU Watchdog Timer Enable/Disable Control Under normal program operation, a W atchdog T imer time-out will initialise a device reset and set the status bit T O. However, if the system is in the SLEEP or IDLE Mode, when a W atchdog T imer time-out occurs, the T O bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the W atchdog T imer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 field, the second is using the W atchdog T imer software clear instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the W atchdog T imer. That is to use the single "CLR WDT" instruction to clear the WDT contents. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillat or as its source clock, this will give a maximum watchdog period of around 8s for the 218 division ratio and a minimum timeout of 7.8ms for the 28 division ration. “CLR WDT”Instution 8-stage Divide WDT Pesale WE4~WE0 itsWDTC Registe Reset MCU LIRC fLIRC fLIRC/8 8-to-1 MUX CLR WS~WS0 (fLIRC/8 ~ fLIRC/18) WDT Tie-out (8/fLIRC ~ 18/fLIRC) “HALT”Instution Watchdog timer

Rev. 1.40 8 Deee 1 01 Rev. 1.40 87 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller . In this case, internal circuitry will ensure that the mi crocontroller, after a short delay , will be in a well defined state and ready to execute t he fir st p rogram i nstruction. Af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the pow er-on res et, another res et exis ts in the form of a Low V oltage Res et, L VR, where a ful l re set is im plemented in sit uations whe re the power supply vol tage fa lls below a certain t hreshold. Anot her t ype of re set i s whe n t he W atchdog T imer ove rflows a nd re sets t he microcontroller. All types of reset operations result in different register conditions being setup. Reset Functions There are five w ays in w hich a microcontroller res et can occur , through events occurring both internally and externally. Power-on Reset The m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s first a pplied t o the microcontroller . As well as ensuring that the Program Memory begins execution from the first memory address, a pow er-on reset also ensures that certain other registers are preset to know n conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Powe-on Reset SST Tie-out tRSTD Note: tRSTD is power-on delay with typical time=50 ms Power-On Reset Timing Chart Internal Reset Control There is an intern al reset control register , RSTC, which is used to provide a reset when the device operates abnormal ly due to the environmental noise interference. If the content of the RSTC register is set to any value other than 01010101B or 10101010B, it will reset the device after 2~3 fLIRC clock cycles. After power on the register will have a value of 01010101B. RSTC7 ~ RSTC0 Bits Reset Function 01010101B No opeation 10101010B No opeation Any othe value Reset MCU Internal Reset Function Control

RSTC Register Bit 7 6 5 4 3 2 1 0 Nae RSTC7 RSTC RSTC RSTC4 RSTC3 RSTC RSTC1 RSTC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 RSTC7~RSTC0: Reset function control 01010101: No operation 10101010: No operation Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after 2~3 LIRC clock cycles and the RSTF bit in the RSTFC register will be set to 1.
RSTFC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3 RSTF: Reset control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the RSTC control register software reset and cleared by the application pr ogram. Not e t hat t his bi t c an on ly be c leared t o 0 by t he a pplication program. Bit 2 LVRF: LVR function reset flag Described elsewhere. Bit 1 LRF: LVR control register software reset flag Described elsewhere. Bit 0 WRF: WDT control register software reset flag Described elsewhere. Low Voltage Reset – LVR The micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The L VR function is always enabled with a specific L VR voltag e, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery , the L VR will automatically reset the device internally and the L VRF bit in the RSTFC register will also be set to 1. For a valid L VR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~ VLVR must exist for a tim e greater than that specified by tLVR in the L VD/LVR characteristics. If the low supply voltage state does not exceed this value, the L VR will ignore the low supply voltage and will not perform a reset function. The actual VLVR value can be selected by the L VS bits in the L VRC register . If the L VS7~LVS0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the L VR will reset the device after 2~3 fLIRC clock cycles. When this happens, the LRF bit in the RSTFC register will be set to 1. After power on the register will have the value of 01010101B. Note that the L VR function will be automatically disabled when the device enters the power down mode.

Rev. 1.40 88 Deee 1 01 Rev. 1.40 89 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G4C/G56 /G52 /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G65/G73 /G65/G74 /G74 /G52/G53 /G54/G44 /G20/G2B /G20 /G74 /G53/G53/G54 Note: tRSTD is power-on delay with typical time=50ms Low Voltage Reset Timing Chart

LVRC Register Bit 7 6 5 4 3 2 1 0 Nae LVS7 LVS LVS LVS4 LVS3 LVS LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 LVS7~LVS0: LVR voltage select 01010101: 2.1V 00110011: 2.55V 10011001: 3.15V 10101010: 3.8V Other values: Generates a MCU reset – register is reset to POR value When an actual low voltage condit ion occurs, as specified by one of the four defined LVR voltage value above, an MCU reset will generated. The reset operation will be activated after 2~3 fLIRC clock cycles. In this situation the register conte nts will remain the same after such a reset occurs. Any re gister va lue, o ther t han t he fo ur d efined re gister v alues a bove, wi ll a lso re sult i n the generation of an MCU reset. T he reset operation wi ll be activated after 2~3 fLIRC clock cycles. However in this situation the register contents will be reset to the POR value.
RSTFC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — RSTF LVRF LRF WRF R/W — — — — R/W R/W R/W R/W POR — — — — 0 x 0 0 "x": unknown Bit 7~4 Unimplemented, read as "0" Bit 3 RSTF: Reset control register software reset flag Described elsewhere. Bit 2 LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit can only be cleared to 0 by the application program. Bit 1 LRF: LVR control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the L VRC control register contains any undefined L VR voltage register values. This in ef fect acts like a software-reset function. Note that this bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT control register software reset flag Described elsewhere.

Rev. 1.40 90 Deee 1 01 Rev. 1.40 91 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Watchdog Time-out Reset during Normal Operation The W atchdog time-out Reset during normal operation is the same as the hardw are Low V oltage Reset except that the W atchdog time-out flag T O will be set to "1". /G74 /G52/G53 /G54/G44 /G20/G2B /G20 /G74 /G53/G53/G54 /G57/G44 /G54/G20 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G65/G73 /G65/G74 Note: tRSTD is power-on delay with typical time=16.7ms WDT Time-out Reset during NORMAL Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The W atchdog time-out Reset during SLEEP or IDLE Mode is a little dif ferent from other kinds of re set. Mo st of t he c onditions re main unc hanged e xcept t hat t he Pro gram Count er a nd t he St ack Pointer will be cleared to "0" and the T O flag will be set to "1". Refer to the A.C. Characteristics for tSST details. /G74 /G53/G53/G54 /G57/G44 /G54/G20 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 /G49/G6E /G74/G65 /G72 /G6E/G61/G6C /G20/G52 /G65/G73 /G65/G74 WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart Reset Initial Conditions The dif ferent types of reset described af fect the reset flags in dif ferent ways. These flags, known as P DF and T O are located in the s tatus register and are controlled by various microcontroller operations, su ch a s t he SL EEP o r I DLE Mo de f unction o r W atchdog T imer. T he r eset f lags a re shown in the table: TO PDF Reset Function 0 0 Powe-on eset u u LVR eset duing NORMAL o SLOW Mode opeation 1 u WDT tie-out eset duing NORMAL o SLOW Mode opeation 1 1 WDT tie-out eset duing IDLE o SLEEP Mode opeation "u" stands fo unhanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Reset Function Poga Counte Reset to zeo Inteupts All inteupts will e disaled WDT Ti e Base Clea afte eset WDT egins ounting Tie Modules Tie Modules will e tuned off Input/Output Pots I/O pots will e setup as inputs Stak pointe Stak pointe will point to the top of the stak

Rev. 1.40 90 Deee 1 01 Rev. 1.40 91 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver The dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. Register BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* IAR0 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu IAR1 ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP1L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP1H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ACC ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL ● ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 TBLP ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ● ---- xxxx ---- uuuu ---- uuuu ---- uuuu TBHP ● ---x xxxx ---u uuuu ---u uuuu ---u uuuu TBHP ● --xx xxxx --uu uuuu --uu uuuu --uu uuuu TBHP ● -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu STATUS ● ● ● ● xx00 xxxx uuuu uuuu xx1u uuuu uu11 uuuu PBP ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu IAR ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MPL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MPH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu RSTFC ● ● ● ● ---- 0x00 ---- u1uu ---- uuuu ---- uuuu INTC0 ● ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PA ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PAPU ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PAWU ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PB ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC ● ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SCC ● ● ● ● 000- 0000 000- 0000 000- 0000 uuu- uuuu LVDC ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu LVRC ● ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu WDTC ● ● ● ● 0101 0011 0101 0011 0101 0011 uuuu uuuu RSTC ● ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu PC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu

Rev. 1.40 9 Deee 1 01 Rev. 1.40 93 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* PCC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PD ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU ● ● ● 0000 0000 0000 0000 0000 0000 0uuuu uuuu MFI1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MFI ● ● ● ● -000 -000 -000 -000 -000 -000 -uuu -uuu ADRL (ADRFS=0) ● ● ● ● xxxx ---- xxxx ---- xxxx ---- uuuu ---- ADRL (ADRFS=1) ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ADRH (ADRFS=0) ● ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ADRH (ADRFS=1) ● ● ● ● ---- xxxx ---- uuuu ---- uuuu ---- uuuu ADCR0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ADCR1 ● ● ● ● 0-00 -000 0-00 -000 0-00 -000 u-uu -uuu SIMTOC ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 ● ● ● ● 111- 0000 111- 0000 111- 0000 uuu- uuuu SIMC1 ● ● ● ● 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD ● ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/ SIMC ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0AL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu EEA ● ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu EED ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLEDC ● --00 0000 --00 0000 --00 0000 --uu uuuu SLEDC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMDL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTMAL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu

Rev. 1.40 9 Deee 1 01 Rev. 1.40 93 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* PTMRPL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FC0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FARL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FARH ● --00 0000 --00 0000 --00 0000 --uu uuuu FARH ● -000 0000 -000 0000 -000 0000 -uuu uuuu FD0L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD0H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD1H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FDL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FDH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3L ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu FD3H ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMC1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMDH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMAH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu STMRP ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1C0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1C1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1AL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TSC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PE ● --11 1111 --11 1111 --11 1111 --uu uuuu PE ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC ● --11 1111 --11 1111 --11 1111 --uu uuuu PEC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU ● --00 0000 --00 0000 --00 0000 --uu uuuu PEPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PF ● ● --11 1111 --11 1111 --11 1111 --uu uuuu PFC ● ● --11 1111 --11 1111 --11 1111 --uu uuuu PFPU ● ● --00 0000 --00 0000 --00 0000 --uu uuuu USR ● ● ● ● 0000 1011 0000 1011 0000 1011 uuuu uuuu

Rev. 1.40 94 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* UCR1 ● ● ● ● 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TXR_RXR ● ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu BRG ● ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PG ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PGC ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PGPU ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKTMR ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC0 ● ● ● ● 0000 0-00 0000 0-00 0000 0-00 uuuu u-uu TK1DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TK1DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC1 ● ● ● ● 0000 0011 0000 0011 0000 0011 uuuu uuuu TKM01DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM01DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0C0 ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM0C1 ● ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM0C ● ● ● ● 1110 0100 1110 0100 1110 0100 uuuu uuuu TKM11DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM11DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1C0 ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM1C1 ● ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM1C ● ● ● ● 1110 0100 1110 0100 1110 0100 uuuu uuuu TKM1DL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1DH ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMROL ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMC0 ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKMC1 ● ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKMC ● ● ● ● 1110 0100 1110 0100 1110 0100 uuuu uuuu TKM31DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM31DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3C0 ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM3C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM3C ● ● ● 1110 0100 1110 0100 1110 0100 uuuu uuuu TKM41DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM41DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4C0 ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu

Rev. 1.40 94 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* TKM4C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM4C ● ● ● 1110 0100 1110 0100 1110 0100 uuuu uuuu TKM1DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1DH ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMROL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMC0 ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKMC1 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKMC ● ● 1110 0100 1110 0100 1110 0100 uuuu uuuu TKM1DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1DH ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMROL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKMC0 ● ● --00 0000 --00 0000 --00 0000 --uu uuuu TKMC1 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKMC ● ● 1110 0100 1110 0100 1110 0100 uuuu uuuu TKM71DL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM71DH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM7ROL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM7C0 ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM7C1 ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM7C ● 1110 0100 1110 0100 1110 0100 uuuu uuuu IFS ● ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu PAS0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PAS1 ● 00-- 0000 00-- 0000 00-- 0000 uu-- uuuu PBS0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PBS1 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PCS0 ● ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PCS1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PDS0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PDS1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PES0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PES1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PGS0 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PGS1 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PH ● --11 1111 --11 1111 --11 1111 --uu uuuu PHC ● --11 1111 --11 1111 --11 1111 --uu uuuu PHPU ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM81DL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu

Rev. 1.40 9 Deee 1 01 Rev. 1.40 97 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register BS66F340 BS66F350 BS66F360 BS66F370 Reset (Power On) LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE or SLEEP)* TKM81DH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM8ROL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM8C0 ● --00 0000 --00 0000 --00 0000 --uu uuuu TKM8C1 ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM8C ● 1110 0100 1110 0100 1110 0100 uuuu uuuu Note: "u" stands for unchanged "x" stands for "unknown" "-" stands for unimplemented

Rev. 1.40 9 Deee 1 01 Rev. 1.40 97 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Input/Output Ports Holtek m icrocontrollers of fer c onsiderable fle xibility on t heir I/ O port s. W ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. These d evices p rovide b idirectional i nput/output l ines l abeled wi th p ort n ames P A~PH. T hese I /O ports are mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. A ll of thes e I/O ports can be used for input and output operations. For input operation, these ports are non-latch ing, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where m denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 PA PA PA4 PA3 PA PA1 PA0 PAC PAC7 PAC PAC PAC4 PAC3 PAC PAC1 PAC0 PAPU PAPU7 PAPU PAPU PAPU4 PAPU3 PAPU PAPU1 PAPU0 PAWU PAWU7 PAWU PAWU PAWU4 PAWU3 PAWU PAWU1 PAWU0 PB PB7 PB PB PB4 PB3 PB PB1 PB0 PBC PBC7 PBC PBC PBC4 PBC3 PBC PBC1 PBC0 PBPU PBPU7 PBPU PBPU PBPU4 PBPU3 PBPU PBPU1 PBPU0 PC — — — — PC3 PC PC1 PC0 PCC — — — — PCC3 PCC PCC1 PCC0 PCPU — — — — PCPU3 PCPU PCPU1 PCPU0 PE — — PE PE4 PE3 PE PE1 PE0 PEC — — PEC PEC4 PEC3 PEC PEC1 PEC0 PEPU — — PEPU PEPU4 PEPU3 PEPU PEPU1 PEPU0 I/O Registers List – BS66F340 Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 PA PA PA4 PA3 PA PA1 PA0 PAC PAC7 PAC PAC PAC4 PAC3 PAC PAC1 PAC0 PAPU PAPU7 PAPU PAPU PAPU4 PAPU3 PAPU PAPU1 PAPU0 PAWU PAWU7 PAWU PAWU PAWU4 PAWU3 PAWU PAWU1 PAWU0 PB PB7 PB PB PB4 PB3 PB PB1 PB0 PBC PBC7 PBC PBC PBC4 PBC3 PBC PBC1 PBC0 PBPU PBPU7 PBPU PBPU PBPU4 PBPU3 PBPU PBPU1 PBPU0 PC PC7 PC PC PC4 PC3 PC PC1 PC0 PCC PCC7 PCC PCC PCC4 PCC3 PCC PCC1 PCC0 PCPU PCPU7 PCPU PCPU PCPU4 PCPU3 PCPU PCPU1 PCPU0 PD PD7 PD PD PD4 PD3 PD PD1 PD0 PDC PDC7 PDC PDC PDC4 PDC3 PDC PDC1 PDC0 PDPU PDPU7 PDPU PDPU PDPU4 PDPU3 PDPU PDPU1 PDPU0 PE PE7 PE PE PE4 PE3 PE PE1 PE0 PEC PEC7 PEC PEC PEC4 PEC3 PEC PEC1 PEC0 PEPU PEPU7 PEPU PEPU PEPU4 PEPU3 PEPU PEPU1 PEPU0 I/O Registers List – BS66F350

Rev. 1.40 98 Deee 1 01 Rev. 1.40 99 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 PA PA PA4 PA3 PA PA1 PA0 PAC PAC7 PAC PAC PAC4 PAC3 PAC PAC1 PAC0 PAPU PAPU7 PAPU PAPU PAPU4 PAPU3 PAPU PAPU1 PAPU0 PAWU PAWU7 PAWU PAWU PAWU4 PAWU3 PAWU PAWU1 PAWU0 PB PB7 PB PB PB4 PB3 PB PB1 PB0 PBC PBC7 PBC PBC PBC4 PBC3 PBC PBC1 PBC0 PBPU PBPU7 PBPU PBPU PBPU4 PBPU3 PBPU PBPU1 PBPU0 PC PC7 PC PC PC4 PC3 PC PC1 PC0 PCC PCC7 PCC PCC PCC4 PCC3 PCC PCC1 PCC0 PCPU PCPU7 PCPU PCPU PCPU4 PCPU3 PCPU PCPU1 PCPU0 PD PD7 PD PD PD4 PD3 PD PD1 PD0 PDC PDC7 PDC PDC PDC4 PDC3 PDC PDC1 PDC0 PDPU PDPU7 PDPU PDPU PDPU4 PDPU3 PDPU PDPU1 PDPU0 PE PE7 PE PE PE4 PE3 PE PE1 PE0 PEC PEC7 PEC PEC PEC4 PEC3 PEC PEC1 PEC0 PEPU PEPU7 PEPU PEPU PEPU4 PEPU3 PEPU PEPU1 PEPU0 PF — — PF PF4 PF3 PF PF1 PF0 PFC — — PFC PFC4 PFC3 PFC PFC1 PFC0 PFPU — — PFPU PFPU4 PFPU3 PFPU PFPU1 PFPU0 PG PG7 PG PG PG4 PG3 PG PG1 PG0 PGC PGC7 PGC PGC PGC4 PGC3 PGC PGC1 PGC0 PGPU PGPU7 PGPU PGPU PGPU4 PGPU3 PGPU PGPU1 PGPU0 PH — — PH PH4 PH3 PH PH1 PH0 PHC — — PHC PHC4 PHC3 PHC PHC1 PHC0 PHPU — — PHPU PHPU4 PHPU3 PHPU PHPU1 PHPU0 I/O Registers List – BS66F370 Unimplemented, read as "0". PAWUn: Port A Pin wake-up function control 0: Disable 1: Enable PAPUn/PBPUn/PCPUn/PDPUn/PEPUn/PFPUn/PGPUn/PHPUn: I/O Pin pull-high function control 0: Disable 1: Enable PAn/PBn/PCn/PDn/PEn/PFn/PGn/PHn: I/O Port Data bit 0: Data 0 1: Data 1 PACn/PBCn/PCCn/PDCn/PECn/PFCn/PGCn/PHCn: I/O Pin type selection 0: Output 1: Input

Rev. 1.40 100 Deee 1 01 Rev. 1.40 101 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . T o eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor . These pull-high resistors are selected using the relevant pull-high control registers and are implemented using w eak P MOS transis tors. N ote that the pull-high res istor can be controlled by the relevant pull-high control register only when the pin-shared functional pin is selected as an input or NMOS output. Otherwise, the pull-high resistors can not be enabled. Port A Wake-up The HAL T instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. V arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low . This function is especially suitable for applications that can be woken up via extern al switches. Each pin on Port A can be selected individually to have this wake-up feature using the P AWU register . Note that the wake-up function can be controlled by the wake-up control registers only when the pin-shared functional pin is selected as general purpose input/output and the MCU enters the Power down mode. I/O Port Control Registers Each Po rt h as i ts o wn c ontrol r egister, k nown a s P AC~PHC, wh ich c ontrols t he i nput/output configuration. W ith t his c ontrol re gister, e ach I/ O pi n wi th or wi thout pul l-high re sistors c an be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. I/O Port Source Current Control These devices s upport dif ferent s ource current driving capability for each I/O port. W ith the selection register, SLEDC or SLEDC1, specific I/O port can support four levels of the source current driving capability . Users should refer to the D.C. characteristics sectio n to select the desired source current for different applications. Register Name Bit 7 6 5 4 3 2 1 0 SLEDC (BSF340) — — PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 SLEDC (BSF30/BSF30/ BSF370) PCPS3 PCPS PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 SLEDC1 (BSF370) — — — — PHPS1 PHPS0 PGPS1 PGPS0 I/O Port Source Current Control Registers List

Rev. 1.40 100 Deee 1 01 Rev. 1.40 101 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SLEDC Register – BS66F340 Bit 7 6 5 4 3 2 1 0 Nae — — PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0 Bit 5~4 PCPS1~PCPS0: PC3~PC0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 3~2 PBPS1~PBPS0: PB7~PB4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PAPS1~PAPS0: PA7~PA5 and PA1 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) SLEDC Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Nae PCPS3 PCPS PCPS1 PCPS0 PBPS1 PBPS0 PAPS1 PAPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCPS3~PCPS2: PC7~PC4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 5~4 PCPS1~PCPS0: PC3~PC0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 3~2 PBPS1~PBPS0: PB7~PB4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PAPS1~PAPS0: PA7~PA5 and PA1 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.)

Rev. 1.40 10 Deee 1 01 Rev. 1.40 103 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SLEDC1 Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Nae — — — — PHPS1 PHPS0 PGPS1 PGPS0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3~2 PHPS1~PHPS0: PH3~PH0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Bit 1~0 PGPS1~PGPS0: PG3~PG0 source current selection 00: source current = Level 0 (min.) 01: source current = Level 1 10: source current = Level 2 11: source current = Level 3 (max.) Pin-shared Functions The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions , many of these difficulties can be overcome. For these pins, the desired function of the multi-functio n I/O pins is selected by a series of registers via the application program control. Pin-shared Function Selection Registers The limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes. Each device includes Port "x" output function Selection register "n", labeled as PxSn, and Input Function Selection register , labeled as IFS, which can select the desired functions of the multi-function pin-shared pins. When t he pi n-shared i nput funct ion i s se lected t o be use d, t he c orresponding i nput a nd output functions selection should be properly managed. For example, if the I2C SDA line is used, the corresponding output pin-shared function should be configured as the SDI/SDA function by configuring the PxSn regis ter and the SDA signal intput should be properly selected using the IFS re gister. Howe ver, i f t he e xternal i nterrupt func tion i s se lected t o be use d, t he re levant out put pin-shared function should be selected as an I/O function and the interrupt input signal should be selected. The m ost i mportant p oint t o n ote i s t o m ake su re t hat t he d esired p in-shared f unction i s p roperly selected and also deselected. T o select the desired pin-shared function, the pin-shared function should first be correctly selected using the corresponding pin-shared control register . After that the corresponding peripheral functional setting should be configured and then the peripheral function can be enabled. T o correctly deselect the pin-shared function, the peripheral function should first be disabled and then the corresponding pin-shared function control register can be modified to select other pin-shared functions.

Rev. 1.40 10 Deee 1 01 Rev. 1.40 103 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register Name Bit 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS0 PAS0 PAS04 PAS03 PAS0 PAS01 PAS00 PAS1 PAS17 PAS1 — — PAS13 PAS1 PAS11 PAS10 PBS0 PBS07 PBS0 PBS0 PBS04 PBS03 PBS0 PBS01 PBS00 PBS1 PBS17 PBS1 PBS1 PBS14 PBS13 PBS1 PBS11 PBS10 PCS0 PCS07 PCS0 PCS0 PCS04 PCS03 PCS0 PCS01 PCS00 PES0 PES07 PES0 PES0 PES04 PES03 PES0 PES01 PES00 PES1 — — — — PES13 PES1 PES11 PES10 IFS — — IFS IFS4 IFS3 IFS IFS1 IFS0 Pin-shared Function Selection Registers List – BS66F340 Register Name Bit 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS0 PAS0 PAS04 PAS03 PAS0 PAS01 PAS00 PAS1 — — — — PAS13 PAS1 PAS11 PAS10 PBS0 PBS07 PBS0 PBS0 PBS04 PBS03 PBS0 PBS01 PBS00 PBS1 PBS17 PBS1 PBS1 PBS14 PBS13 PBS1 PBS11 PBS10 PCS0 PCS07 PCS0 PCS0 PCS04 PCS03 PCS0 PCS01 PCS00 PCS1 PCS17 PCS1 PCS1 PCS14 PCS13 PCS1 PCS11 PCS10 PDS0 PDS07 PDS0 PDS0 PDS04 PDS03 PDS0 PDS01 PDS00 PDS1 PDS17 PDS1 PDS1 PDS14 PDS13 PDS1 PDS11 PDS10 PES0 PES07 PES0 PES0 PES04 — — — — PES1 PES17 PES1 PES1 PES14 PES13 PES1 PES11 PES10 IFS — — IFS IFS4 IFS3 IFS IFS1 IFS0 Pin-shared Function Selection Registers List – BS66F350 Register Name Bit 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS0 PAS0 PAS04 PAS03 PAS0 PAS01 PAS00 PAS1 — — — — PAS13 PAS1 PAS11 PAS10 PBS0 PBS07 PBS0 PBS0 PBS04 PBS03 PBS0 PBS01 PBS00 PBS1 PBS17 PBS1 PBS1 PBS14 PBS13 PBS1 PBS11 PBS10 PCS0 PCS07 PCS0 PCS0 PCS04 PCS03 PCS0 PCS01 PCS00 PCS1 PCS17 PCS1 PCS1 PCS14 PCS13 PCS1 PCS11 PCS10 PDS0 PDS07 PDS0 PDS0 PDS04 PDS03 PDS0 PDS01 PDS00 PDS1 PDS17 PDS1 PDS1 PDS14 PDS13 PDS1 PDS11 PDS10 PES0 PES07 PES0 PES0 PES04 PES03 PES0 PES01 PES00 PES1 PES17 PES1 PES1 PES14 PES13 PES1 PES11 PES10 PFS0 — — — — PFS03 PFS0 PFS01 PFS00 IFS — — IFS IFS4 IFS3 IFS IFS1 IFS0 Pin-shared Function Selection Registers List – BS66F360

Rev. 1.40 104 Deee 1 01 Rev. 1.40 10 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register Name Bit 7 6 5 4 3 2 1 0 PAS0 PAS07 PAS0 PAS0 PAS04 PAS03 PAS0 PAS01 PAS00 PAS1 — — — — PAS13 PAS1 PAS11 PAS10 PBS0 PBS07 PBS0 PBS0 PBS04 PBS03 PBS0 PBS01 PBS00 PBS1 PBS17 PBS1 PBS1 PBS14 PBS13 PBS1 PBS11 PBS10 PCS0 PCS07 PCS0 PCS0 PCS04 PCS03 PCS0 PCS01 PCS00 PCS1 PCS17 PCS1 PCS1 PCS14 PCS13 PCS1 PCS11 PCS10 PDS0 PDS07 PDS0 PDS0 PDS04 PDS03 PDS0 PDS01 PDS00 PDS1 PDS17 PDS1 PDS1 PDS14 PDS13 PDS1 PDS11 PDS10 PES0 PES07 PES0 PES0 PES04 PES03 PES0 PES01 PES00 PES1 PES17 PES1 PES1 PES14 PES13 PES1 PES11 PES10 PFS0 — — — — PFS03 PFS0 PFS01 PFS00 PGS0 PGS07 PGS0 PGS0 PGS04 PGS03 PGS0 PGS01 PGS00 PGS1 PGS17 PGS1 PGS1 PGS14 PGS13 PGS1 PGS11 PGS10 IFS — — IFS IFS4 IFS3 IFS IFS1 IFS0 Pin-shared Function Selection Registers List – BS66F370

PAS0 Register Bit 7 6 5 4 3 2 1 0 Nae PAS07 PAS0 PAS0 PAS04 PAS03 PAS0 PAS01 PAS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PAS07~PAS06: PA3 pin function selection 00/11: PA3 01: SCS 10: XT1 Bit 5~4 PAS05~PAS04: PA2 pin function selection PAS0[5:4] BS66F340 BS66F350 BS66F360 BS66F370

00 PA/CTCK1 PA PA PA

01 SCS SCS SCS SCS

10 PA/CTCK1 PA PA PA

11 PA/CTCK1 PA PA PA

Bit 3~2 PAS03~PAS02: PA1 pin function selection 00/10/11: PA1 01: CTP0 Bit 1~0 PAS01~PAS00: PA0 pin function selection 00/10/11: PA0 01: SDO

PAS1 Register – BS66F340 Bit 7 6 5 4 3 2 1 0 Nae PAS17 PAS1 — — PAS13 PAS1 PAS11 PAS10 R/W R/W R/W — — R/W R/W R/W R/W POR 0 0 — — 0 0 0 0 Bit 7~6 PAS17~PAS16: PA7 pin function selection 00/10/11: PA7 01: CTP1 Bit 5~4 Unimplemented, read as 0 Bit 3~2 PAS13~PAS12: PA5 pin function selection 00/10/11: PA5 01: CTP0B Bit 1~0 PAS11~PAS10: PA4 pin function selection 00/11: PA4 01: SDO 10: XT2
PAS1 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Nae — — — — PAS13 PAS1 PAS11 PAS10 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0 Bit 3~2 PAS13~PAS12: PA5 pin function selection 00/10/11: PA5 01: CTP0B Bit 1~0 PAS11~PAS10: PA4 pin function selection 00/11: PA4 01: SDO 10: XT2
PBS0 Register Bit 7 6 5 4 3 2 1 0 Nae PBS07 PBS0 PBS0 PBS04 PBS03 PBS0 PBS01 PBS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PBS07~PBS06: PB3 pin function selection 00/10: PB3 01: RX 11: AN3 Bit 5~4 PBS05~PBS04: PB2 pin function selection 00: PB2/PTPI 01: TX 10: PTP 11: AN2 Bit 3~2 PBS03~PBS02: PB1 pin function selection 00/10: PB1 01: SCK/SCL 11: AN1 Bit 1~0 PBS01~PBS00: PB0 pin function selection 00: PB0 01: SDI/SDA 10: VREF 11: AN0

Rev. 1.40 10 Deee 1 01 Rev. 1.40 107 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver

PBS1 Register Bit 7 6 5 4 3 2 1 0 Nae PBS17 PBS1 PBS1 PBS14 PBS13 PBS1 PBS11 PBS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PBS17~PBS16: PB7 pin function selection 00/01: PB7/INT1 10: KEY4 11: AN7 Bit 5~4 PBS15~PBS14: PB6 pin function selection 00/01: PB6/PTCK 10: KEY3 11: AN6 Bit 3~2 PBS13~PBS12: PB5 pin function selection 00/01: PB5/STCK 10: KEY2 11: AN5 Bit 1~0 PBS11~PBS10: PB4 pin function selection 00: PB4/PTPI 01: PTPB 10: KEY1 11: AN4
PCS0 Register Bit 7 6 5 4 3 2 1 0 Nae PCS07 PCS0 PCS0 PCS04 PCS03 PCS0 PCS01 PCS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCS07~PCS06: PC3 pin function selection 00: PC3 01: PC3 10: KEY8 11: PC3 Bit 5~4 PCS05~PCS04: PC2 pin function selection 00: PC2 01: PC2 10: KEY7 11: PC2 Bit 3~2 PCS03~PCS02: PC1 pin function selection 00: PC1 01: PC1 10: KEY6 11: PC1 Bit 1~0 PCS01~PCS00: PC0 pin function selection 00: PC0 01: PC0 10: KEY5 11: PC0

PCS1 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Nae PCS17 PCS1 PCS1 PCS14 PCS13 PCS1 PCS11 PCS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PCS17~PCS16: PC7 pin function selection 00: PC7 01: PC7 10: KEY12 11: PC7 Bit 5~4 PCS15~PCS14: PC6 pin function selection 00: PC6 01: PC6 10: KEY11 11: PC6 Bit 3~2 PCS13~PCS12: PC5 pin function selection 00: PC5 01: PC5 10: KEY10 11: PC5 Bit 1~0 PCS11~PCS10: PC4 pin function selection 00: PC4 01: PC4 10: KEY9 11: PC4
PDS0 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Nae PDS07 PDS0 PDS0 PDS04 PDS03 PDS0 PDS01 PDS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PDS07~PDS06: PD3 pin function selection 00: PD3 01: PD3 10: KEY16 11: PD3 Bit 5~4 PDS05~PDS04: PD2 pin function selection 00: PD2 01: PD2 10: KEY15 11: PD2 Bit 3~2 PDS03~PDS02: PD1 pin function selection 00: PD1 01: PD1 10: KEY14 11: PD1 Bit 1~0 PDS01~PDS00: PD0 pin function selection 00: PD0 01: PD0 10: KEY13 11: PD0

PDS1 Register – BS66F350/BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Nae PDS17 PDS1 PDS1 PDS14 PDS13 PDS1 PDS11 PDS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PDS17~PDS16: PD7 pin function selection 00: PD7 01: PD7 10: KEY20 11: PD7 Bit 5~4 PDS15~PDS14: PD6 pin function selection 00: PD6 01: PD6 10: KEY19 11: PD6 Bit 3~2 PDS13~PDS12: PD5 pin function selection 00: PD5 01: PD5 10: KEY18 11: PD5 Bit 1~0 PDS11~PDS10: PD4 pin function selection 00: PD4 01: PD4 10: KEY17 11: PD4
PES0 Register Bit 7 6 5 4 3 2 1 0 Nae PES07 PES0 PES0 PES04 PES03 PES0 PES01 PES00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PES07~PES06: PE3 pin function selection PES0[7:6] BS66F340 BS66F350 BS66F360 BS66F370

00 PE3/STPI PE3/STPI PE3/STPI PE3/STPI

01 STPB STPB STPB STPB

10 KEY1 PE3/STPI KEY4 KEY4

11 PE3/STPI PE3/STPI PE3/STPI PE3/STPI

Bit 5~4 PES05~PES04: PE2 pin function selection PES0[5:4] BS66F340 BS66F350 BS66F360 BS66F370

00 PE/STPI PE/STPI PE/STPI PE/STPI

01 STP STP STP STP

10 KEY11 PE/STPI KEY3 KEY3

11 PE/STPI PE/STPI PE/STPI PE/STPI

Bit 3~2 PES03~PES02: PE1 pin function selection PES0[3:2] BS66F340 BS66F350 BS66F360 BS66F370

00 PE1 — PE1 PE1

01 PE1 — PE1 PE1

10 KEY10 — KEY KEY

11 PE1 — PE1 PE1

"—": Unimplemented, read as 0 – BS66F350

Rev. 1.40 108 Deee 1 01 Rev. 1.40 109 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1~0 PES01~PES00: PE0 pin function selection PES0[1:0] BS66F340 BS66F350 BS66F360 BS66F370

00 PE0 — PE0 PE0

01 PE0 — PE0 PE0

10 KEY9 — KEY1 KEY1

11 PE0 — PE0 PE0

Unimplemented, read as 0 – BS66F350

PES1 Register Bit 7 6 5 4 3 2 1 0 Nae PES17 PES1 PES1 PES14 PES13 PES1 PES11 PES10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PES17~PES16: PE7 pin function selection PES1[7:6] BS66F340 BS66F350 BS66F360 BS66F370 00 — PE7 PE7 PE7 01 — CTP1B CTP1B CTP1B 10 — PE7 KEY KEY 11 — PE7 PE7 PE7 Unimplemented, read as 0 – BS66F340 Bit 5~4 PES15~PES14: PE6 pin function selection PES1[5:4] BS66F340 BS66F350 BS66F360 BS66F370 00 — PE PE PE 01 — CTP1 CTP1 CTP1 10 — PE KEY KEY 11 — PE PE PE Unimplemented, read as 0 – BS66F340 Bit 3~2 PES13~PES12: PE5 pin function selection PES1[3:2] BS66F340 BS66F350 BS66F360 BS66F370

00 PE PE/CTCK1 PE/CTCK1 PE/CTCK1

01 CTP1B PE/CTCK1 PE/CTCK1 PE/CTCK1

10 OSC OSC OSC OSC

11 PE PE/CTCK1 PE/CTCK1 PE/CTCK1

Bit 1~0 PES11~PES10: PE4 pin function selection 00: PE4 01: PE4 10: OSC1 11: PE4

PFS0 Register – BS66F360/BS66F370 Bit 7 6 5 4 3 2 1 0 Nae — — — — PFS03 PFS0 PFS01 PFS00 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0 Bit 3~2 PFS03~PFS02: PF1 pin function selection 00/01/11: PF1 10: KEY28

Rev. 1.40 110 Deee 1 01 Rev. 1.40 111 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1~0 PFS01~PFS00: PF0 pin function selection 00/01/11: PF1 10: KEY27

PGS0 Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Nae PGS07 PGS0 PGS0 PGS04 PGS03 PGS0 PGS01 PGS00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PGS07~PGS06: PG3 pin function selection 00: PG3 01: PG3 10: KEY32 11: PG3 Bit 5~4 PGS05~PGS04: PG2 pin function selection 00: PG2 01: PG2 10: KEY31 11: PG2 Bit 3~2 PGS03~PGS02: PG1 pin function selection 00: PG1 01: PG1 10: KEY30 11: PG1 Bit 1~0 PGS01~PGS00: PG0 pin function selection 00: PG0 01: PG0 10: KEY29 11: PG0
PGS1 Register – BS66F370 Bit 7 6 5 4 3 2 1 0 Nae PGS17 PGS1 PGS1 PGS14 PGS13 PGS1 PGS11 PGS10 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PGS17~PGS16: PG7 pin function selection 00: PG7 01: PG7 10: KEY36 11: PG7 Bit 5~4 PGS15~PGS14: PG6 pin function selection 00: PG6 01: PG6 10: KEY35 11: PG6 Bit 3~2 PGS13~PGS12: PG5 pin function selection 00: PG5 01: PG5 10: KEY34 11: PG5 Bit 1~0 PGS11~PGS10: PG4 pin function selection 00: PG4 01: PG4 10: KEY33 11: PG4

IFS Register Bit 7 6 5 4 3 2 1 0 Nae — — IFS IFS4 IFS3 IFS IFS1 IFS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0 Bit 5~4 IFS5~IFS4: SCS input source pin selection 00/10: PA2 01/11: PA3 Bit 3~2 IFS3~IFS2: PTPI input source pin selection 00/10: PB2 01/11: PB4 Bit 1~0 IFS1~IFS0: STPI input source pin selection 00/01: PE2 01/11: PE3 I/O Pin Structures The accompanying diagrams illustrate the internal structures of some generic I/O pin types. As the exact logical construction of the I/O pin will dif fer from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. The wide range of pin-shared structures does not permit all types to be shown. /G56 /G44/G44 /G4D /G55 /G58 /G57/G61 /G6B/G65 /G2D/G75 /G70/G20 /G53/G65 /G6C/G65 /G63/G74 /G53 /G79/G73/G74 /G65/G6D /G20/G57 /G61/G6B /G65/G2D /G75/G70 /G52 /G65/G61/G64/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G44 /G51 /G43/G4B /G53 /G44 /G51 /G43/G4B /G53 /G43/G6F /G6E/G74 /G72/G6F /G6C/G20 /G42/G69 /G74 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G57/G72 /G69/G74 /G65/G20 /G43 /G6F/G6E/G74 /G72/G6F /G6C/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G43/G68 /G69/G70 /G20/G52 /G65/G73 /G65/G74 /G52/G65 /G61/G64 /G20/G43 /G6F/G6E /G74/G72 /G6F/G6C /G20/G52 /G65/G67 /G69/G73 /G74/G65 /G72 /G57/G72 /G69/G74 /G65/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G44/G61 /G74/G61 /G20/G42 /G69/G74 /G49/G2F/G4F /G20/G70 /G69/G6E /G51 /G51 /G50/G41 /G20/G6F /G6E/G6C /G79 /G57/G65 /G61/G6B /G50/G75 /G6C/G6C/G2D /G75/G70 /G50/G75 /G6C/G6C /G2D/G48 /G69/G67 /G68 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G53/G65 /G6C/G65 /G63/G74 Generic Input/Output Structure

Rev. 1.40 11 Deee 1 01 Rev. 1.40 113 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G56 /G44/G44 /G4D /G55 /G58 /G52/G65 /G61/G64 /G20/G44 /G61/G74 /G61/G20 /G52 /G65/G67/G69 /G73/G74 /G65/G72 /G43/G6F /G6E/G74 /G72/G6F /G6C/G20 /G42/G69 /G74 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G57/G72 /G69/G74 /G65/G20 /G43 /G6F/G6E/G74 /G72/G6F /G6C/G20 /G52 /G65/G67/G69 /G73/G74 /G65/G72 /G43/G68 /G69/G70 /G20/G52 /G65/G73 /G65/G74 /G52/G65 /G61/G64 /G20/G43 /G6F/G6E /G74/G72 /G6F/G6C /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G57/G72 /G69/G74 /G65/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67 /G69/G73 /G74/G65 /G72 /G44/G61 /G74/G61 /G20/G42 /G69/G74 /G41/G2F /G44/G20 /G49 /G6E/G70/G75 /G74/G20/G50 /G6F/G72 /G74 /G41/G43 /G53/G33 /G7E/G41 /G43/G53 /G30 /G54/G6F /G20/G41 /G2F/G44 /G20/G43 /G6F/G6E/G76 /G65/G72 /G74/G65 /G72 /G57/G65 /G61/G6B /G50/G75 /G6C/G6C /G2D/G75 /G70 /G41/G6E /G61/G6C /G6F/G67 /G49/G6E /G70/G75/G74 /G53/G65 /G6C/G65 /G63/G74 /G6F/G72 /G44 /G51 /G43/G4B /G53 /G51 /G44 /G51 /G43/G4B /G53 /G51 /G50/G75 /G6C/G6C/G2D /G48/G69 /G67/G68 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G53/G65 /G6C/G65 /G63/G74 A/D Input/Output Structure Programming Considerations Within the user program, one of the things firs t to consider is port initialisation. After a res et, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

Rev. 1.40 11 Deee 1 01 Rev. 1.40 113 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. T o implement time related functions the device includes several T imer Modules, generally abbrevia ted to the name TM. The TMs are multi-purpose timi ng units and serve to provide operations such as T imer/Counter, Input Capture, Compare Match Output and Single Pulse Output as we ll a s be ing t he fun ctional uni t for t he ge neration of PW M si gnals. E ach of t he T Ms ha s t wo interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the dif ferent TM types are described here with more detailed information provided in the individual Compact, Standard and Periodic TM sections. Introduction These de vices c ontain four T Ms a nd e ach i ndividual T M c an be c ategorised a s a c ertain t ype, namely C ompact T ype T M, St andard T ype T M o r Pe riodic T ype T M. Al though si milar i n n ature, the dif ferent TM types vary in their feature complexity . The common features to all of the Compact, Standard and Periodic TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and dif ferences between the three types of TMs are summarised in the accompanying table. TM Function CTM STM PTM Tie/Counte √ √ √ Input Captue — √ √ Copae Math Output √ √ √ PWM Channels 1 1 1 Single Pulse Output — 1 1 PWM Alignent Edge Edge Edge PWM Adjustent Peiod & Duty Duty o Peiod Duty o Peiod Duty o Peiod TM Function Summary TM Operation The dif ferent types of TM of fer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. W hen t he f ree r unning c ount-up c ounter h as t he sa me v alue a s t he p re-programmed comparator, known a s a c ompare m atch si tuation, a T M i nterrupt si gnal wi ll be ge nerated whi ch can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin. TM Clock Source The clock source which drives the main counter in each TM can originate from various sources. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control registers, where "x" stands for C, S or P type TM and "n" stands for the specific TM serial number. Fo r ST M a nd PT M t here i s n o se rial n umber "n" i n t he r elevant p in o r c ontrol b its si nce there is only one STM and PTM respectively in the series of devices, The clock source can be a ratio of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting.

Rev. 1.40 114 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TM Interrupts The Compact, Standard or Periodic type TM has two internal interrupt, one for each of the internal comparator A or comparator P , which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the TMs, irrespective of what type, has one or two TM input pins, with the label xTCKn and xTPnI respectivel y. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register. This external TM input pin allows an external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either a rising or falling active edge. The STCK and PTCK pins are also used as the external trigger input pin in single pulse output mode for the STM and PTM respectively. The other xTM input pin, STPI or PTPI, is the capture input whose acti ve edge can be a rising edge, a falling edge or both rising and falling edges and the active edge transition type is selected using the ST IO1~STIO0 o r PT IO1~PTIO0 b its i n t he ST MC1 o r PT MC1 r egister r espectively. T here i s another capture input, PTCK, for PTM capture input mode, which can be used as the external trigger input source except the PTPI pin. The TM s each have tw o output pins , xTP n and xTP nB. The xTP nB is the inverted s ignal of the xTPn output. The TM output pins can be selected using the corresponding pin-shared function selection bits described in the Pin-shared Function section. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a c ompare m atch si tuation oc curs. T he e xternal xT Pn or xT PnB ou tput pi n i s a lso t he pi n where the TM generates the PWM output waveform. As the TM output pins are pin-shared with other functions, the TM output function must first be setup using relevant pin-shared function selection register. Device CTM STM PTM Input Output Input Output Input Output BSF340 BSF30 BSF30 BSF370 CTCK0 CTCK1 CTP0 CTP0B CTP1 CTP1B STCK STPI STP STPB PTCK PTPI PTP PTPB TM External Pins

Rev. 1.40 114 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TM Input/Output Pin Selection Selecting t o ha ve a T M i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using t he r elevant p in-shared f unction se lection r egisters, wi th t he c orresponding se lection b its i n each pin-shared function register corresponding to a TM input/output pin. Configuring the selection bits correctly will setup the corresponding pin as a TM input/output. The details of the pin-shared function selection are described in the pin-shared function section. CTMn CTCKn CTPn CCR output CTPnB CTM Function Pin Control Block Diagram – n = 0 or 1 STM STCK STP STPI CCR aptue input CCR output STPB STM Function Pin Control Block Diagram PTM PTCK PTP PTPI CCR aptue input CCR output PTPB PTM Function Pin Control Block Diagram

Rev. 1.40 11 Deee 1 01 Rev. 1.40 117 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these registe r pairs must be carried out in a specific way . The important point to note is that data transfer to and from the 8-bit buf fer and its related l ow b yte o nly t akes p lace wh en a wr ite o r r ead o peration t o i ts c orresponding h igh b yte i s executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to us e the " MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PT MRPL, usi ng t he fol lowing a ccess proc edures. Ac cessing t he CCRA or CCRB l ow byt e registers without following these access procedures will result in unpredictable values. Data Bus 8-it Buffe xTMnDHxTMnDL xTMnAHxTMnAL xTMn Counte Registe (Read only) xTMn CCRA Registe (Read/Wite) PTMRPHPTMRPL PTM CCRP Registe (Read/Wite) The following steps show the read and write procedures:

Writing Data to CCRA or CCRP ♦ Step 1. W rite data to Low Byte xTMnAL or PTMRPL –note that here data is only written to the 8-bit buffer. ♦ Step 2. W rite data to High Byte xTMnAH or PTMRPH –here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the Low Byte registers.
Reading Data from the Counter Registers and CCRA or CCRP ♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMRPH –here d ata i s r ead d irectly f rom t he Hi gh B yte r egisters a nd si multaneously d ata i s l atched from the Low Byte register into the 8-bit buffer. ♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMRPL –this step reads data from the 8-bit buffer.

Rev. 1.40 11 Deee 1 01 Rev. 1.40 117 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Compact Type TM – CTM Although the simplest form of the TM types, the Compact TM type still contains three operating modes, wh ich a re C ompare Ma tch Ou tput, T imer/Event C ounter a nd PW M Ou tput m odes. T he Compact TM can also be controlled with an external input pin and can drive two external output pin. Device CTM Core CTM Input Pin CTM Output Pin Note BSF340 BSF30 BSF30 BSF370 10-it CTM (CTM0 CTM1) CTCK0 CTCK1 CTP0 CTP0B CTP1 CTP1B n = 0 ~ 1 fSYS fSYS/4 fH/4 fH/1 fSUB CTCKn 000 001 010 011 100 101 110 111 CTnCK~CTnCK0 10-it Count-up Counte 3-it Copaato P CCRP 7~9 0~9 10-it Copaato A CTnON CTnPAU Copaato A Math Copaato P Math Counte Clea 0 Output Contol Polaity Contol Pin Contol CTPn CTnOC CTnM1 CTnM0 CTnIO1 CTnIO0 CTMnAF Inteupt CTMnPF Inteupt CTnPOL PxSn CCRA CTnCCLRfSUB CTPnB Compact Type TM Block Diagram – n = 0 or 1 Compact TM Operation The Compact TM core is a 10-bit count-up counter which is driven by a user selectable internal or external clock source. There are also two internal comparators with the names, Comparator A and Comparator P . These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP is three-bit w ide w hose value is compared w ith the highes t three bits in the counter while the CCRA is ten-bit wide and therefore compares with all counter bits. The onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear t he c ounter by c hanging t he CT nON bi t from l ow t o hi gh. T he c ounter wi ll a lso be c leared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur , a TM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.

Rev. 1.40 118 Deee 1 01 Rev. 1.40 119 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes and as well as the three CCRP bits. Register Name Bit 7 6 5 4 3 2 1 0 CTMnC0 CTnPAU CTnCK CTnCK1 CTnCK0 CTnON CTnRP CTnRP1 CTnRP0 CTMnC1 CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR CTMnDL D7 D D D4 D3 D D1 D0 CTMnAL D7 D D D4 D3 D D1 D0 10-bit Compact TM Registers List – n = 0 or 1 CTMnDL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CTMn Counter Low Byte Register bit 7 ~ bit 0 CTMn 10-bit Counter bit 7 ~ bit 0 CTMnDH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTMn Counter High Byte Register bit 1 ~ bit 0 CTMn 10-bit Counter bit 9 ~ bit 8 CTMnAL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CTMn CCRA Low Byte Register bit 7 ~ bit 0 CTMn 10-bit CCRA bit 7 ~ bit 0 CTMnAH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 CTMn CCRA High Byte Register bit 1 ~ bit 0 CTMn 10-bit CCRA bit 9 ~ bit 8

Rev. 1.40 118 Deee 1 01 Rev. 1.40 119 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver CTMnC0 Register Bit 7 6 5 4 3 2 1 0 Nae CTnPAU CTnCK CTnCK1 CTnCK0 CTnON CTnRP CTnRP1 CTnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CTnPAU: CTMn Counter Pause control 0: Run 1: Pause The c ounter c an be pa used by se tting t his bi t hi gh. Cl earing t he bi t t o z ero re stores normal counter operation. When in a Pause condition the CTMn will remain powered up a nd c ontinue t o c onsume po wer. T he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. Bit 6~4 CTnCK2~CTnCK0: Select CTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: CTCKn rising edge clock 111: CTCKn falling edge clock These t hree bi ts a re use d t o se lect t he c lock sourc e for t he CT Mn. T he e xternal pi n clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3 CTnON: CTMn Counter On/Off control 0: Off 1: On This bi t c ontrols t he ove rall on /off fun ction of t he CT Mn. Se tting t he bi t hi gh e nables the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero will stop the counter from counting and turn of f the CTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. If the CTMn is in the Compare Match Output Mode then the CTMn output pin will be reset to its initial condition, as specified by the CTnOC bit, when the CTnON bit changes from low to high. Bit 2~0 CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn Counter bit 9 ~ bit 7 000: 1024 CTMn clocks 001: 128 CTMn clocks 010: 256 CTMn clocks 011: 384 CTMn clocks 100: 512 CTMn clocks 101: 640 CTMn clocks 110: 768 CTMn clocks 111: 896 CTMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register , which are then compared with the internal counter ’s highest three bits. The result of this comparison can be selected to clear the internal counter if the CTnCCLR bit is set to zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter . As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing a ll t hree bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver CTMnC1 Register Bit 7 6 5 4 3 2 1 0 Nae CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 CTnM1~CTnM0: Select CTMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Mode 11: T imer/Counter Mode These bits s etup the required operating mode for the CTM n. T o ens ure reliable operation the CTMn should be switched of f before any changes are made to the CTnM1 a nd C TnM0 b its. I n t he T imer/Counter Mo de, t he C TMn o utput p in c ontrol will be disabled. Bit 5~4 CTnIO1~CTnIO0: Select CTMn external pin (CTPn) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: T oggle output PWM Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determin e how the CTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTMn is running. In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn o utput p in c hanges st ate wh en a c ompare m atch o ccurs f rom t he C omparator A. The CTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTMn output pi n sho uld be se tup usi ng t he C TnOC bi t i n t he C TMnC1 re gister. Not e t hat the output level requested by the CTnIO1 and CTnIO0 bits must be dif ferent from the initial value setup using the CTnOC bit otherwise no change will occur on the CTMn output pi n when a com pare match occurs. After the CTMn output pi n changes state, it can be reset to its initial level by changing the level of the CTnON bit from low to high. In the PWM Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn output pin changes state when a certain compare match condition occurs. The PWM output function i s m odified b y c hanging t hese t wo b its. I t i s n ecessary t o o nly c hange t he values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched of f. Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed when the CTMn is running.

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 3 CTnOC: CTPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This i s t he ou tput c ontrol bi t fo r t he CT Mn o utput pi n. It s op eration de pends up on whether CT Mn i s be ing used i n t he Com pare Ma tch Output Mode or i n t he PWM Mode. It ha s no e ffect i f t he CT Mn i s i n t he T imer/Counter Mode. In t he Com pare Match Out put Mode i t de termines t he l ogic l evel of t he CT Mn out put pi n be fore a compare match occurs. In the PWM Mode it determines if the PWM signal is active high or active low. Bit 2 CTnPOL: CTPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the pol arity of the CTPn out put pin. When the bit is set high the CTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the TM is in the T imer/Counter Mode. Bit 1 CTnDPX: CTMn PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This b it d etermines wh ich o f t he C CRA a nd C CRP r egisters a re u sed f or p eriod a nd duty control of the PWM waveform. Bit 0 CTnCCLR: CTMn Counter Clear condition selection 0: CTMn Comparator P match 1: CTMn Comparator A match This bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. Re member t hat t he Compact TM contains two comparators, Comparator A and Comparator P , either of which can be selected to clear the internal counter . W ith the CTnCCLR bi t set hi gh, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low , the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTnCCLR bit is not used in the PWM Mode.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Compact Type TM Operation Modes The Compact T ype TM can operate in one of three operating modes, Compare Match Output Mode, PWM Mode or T imer/Counter Mode. The operating mode is selected using the CTnM1 and CTnM0 bits in the CTMnC1 register. Compare Match Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register , should be set to "00" respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow , a compare match from Comparator A and a compare match from C omparator P . W hen t he C TnCCLR b it i s l ow, t here a re t wo wa ys i n wh ich t he c ounter c an be cleared. One is when a compare match occurs from Comparator P , the other is when the CCRP bits are all zero which allows the counter to overflow . Here both CTMnAF and CTMnPF interrupt request flags for the Comparator A and Comparator P respectively, will both be generated. If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare match occurs from Com parator A. However , here onl y the CTMnAF interrupt request flag wil l be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTnCCLR is high no CTM nPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when its reaches its maximum 10-bit, 3FF Hex, value, however here the CTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTMn output pin will change state. The CTMn output pin condition however only changes state when a CTMnAF interrupt request flag is generated after a compare match occurs from Comparat or A. The CTMnPF interrupt request fla g, g enerated f rom a c ompare m atch o ccurs f rom C omparator P , wi ll h ave n o e ffect o n the CTMn output pin. The way in which the CTMn output pin changes state are determined by the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register . The CTMn output pin can be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTMn output pin, which is setup after the CTnON bit changes from low to high, is setup using the CTnOC bit. Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value 0x3FF CCRP CCRA CTnON CTnPAU CTnPOL CCRP Int. flag CTMnPF CCRA Int. flag CTMnAF CTMn O/P Pin Tie CCRP=0 CCRP > 0 Counte oveflow CCRP > 0 Counte leaed y CCRP value Pause Resue Stop Counte Restat CTnCCLR = 0; CTnM [1:0] = 00 Output pin set to initial Level Low if CTnOC=0 Output Toggle with CTMnAF flag Note CTnIO [1:0] = 10 Ative High Output seletHee CTnIO [1:0] = 11 Toggle Output selet Output not affeted y CTMnAF flag. Reains High until eset y CTnON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when CTnPOL is high Compare Match Output Mode – CTnCCLR = 0 Note: 1. W ith CTnCCLR=0, a Comparator P match will clear the counter 2. The CTMn output pin controlled only by CTMnAF flag 3. The output pin is reset to its initial state by CTnON bit rising edge 4. n = 0 or 1

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value 0x3FF CCRP CCRA CTnON CTnPAU CTnPOL CTMn O/P Pin Tie CCRA=0 CCRA = 0 Counte oveflowCCRA > 0 Counte leaed y CCRA value Pause Resue Stop Counte Restat CTnCCLR = 1; CTnM [1:0] = 00 Output pin set to initial Level Low if CTnOC=0 Output Toggle with CTMnAF flag Note CTnIO [1:0] = 10 Ative High Output seletHee CTnIO [1:0] = 11 Toggle Output selet Output not affeted y CTMnAF flag. Reains High until eset y CTnON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when CTnPOL is high CTMnPF not geneated No CTMnAF flag geneated on CCRA oveflow Output does not hange CCRA Int. flag CTMnAF CCRP Int. flag CTMnPF Compare Match Output Mode – CTnCCLR = 1 Note: 1. W ith CTnCCLR=1, a Comparator A match will clear the counter 2. The CTMn output pin is controlled only by CTMnAF flag 3. The CTMn output pin is reset to initial state by CTnON rising edge 4. The CTMnPF flags is not generated when CTnCCLR=1 5. n = 0 or 1

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer/Counter Mode To se lect t his m ode, bi ts CT nM1 and CT nM0 i n t he CTMnC1 regi ster shoul d be se t t o 1 1 respectively. The T imer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the T imer/Counter Mode the CTMn output pin is not used. Therefore the above description and T iming Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 10 respectively. The PWM function within the CTMn is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the CTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely fl exible. In the P WM mode, the CTnCCLR bit has no ef fect on the P WM operation. Bot h of t he CCRA a nd CCRP re gisters a re use d t o ge nerate t he PW M wave form, one register is used to clear the internal counter and thus control the PWM waveform frequency , while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the CTnDPX bit in the CTMnC1 register . The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP , will be generated when a compare match occurs from either Comparator A or Comparator P . The CTnOC bit in the CTMnC1 register is used to select the required polarity of the PWM waveform while the tw o CTnIO1 and CTnIO0 bits are used to enable the PWM output or to force the TM output pin to a fixed high or low level. The CTnPOL bit is used to reverse the polarity of the PWM output waveform.

10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=0 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Peiod 18 384 1 40 78 89 104 Duty CCRA If fSYS=16MHz, CTMn clock source is fSYS/4, CCRP=2 and CCRA=128, The CTMn PWM output frequency=(fSYS/4)/256=fSYS/1024=15.625kHz, duty=128/256=50%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.
10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=1 CCRP 001b 010b 011b 100b 101b 110b 111b 000b Peiod CCRA Duty 18 384 1 40 78 89 104 The PWM output period is determi ned by the CCRA register value together with the CTMn clock while the PWM duty cycle is defined by the CCRP register value.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value CCRP CCRA CTnON CTnPAU CTnPOL CTMn O/P Pin (CTnOC=1) Tie Counte leaed y CCRP Pause Resue Counte Stop if CTnON it low Counte Reset when CTnON etuns high CTnDPX = 0; CTnM [1:0] = 10 PWM Duty Cyle set y CCRA PWM esues opeation Output ontolled y othe pin-shaed funtion Output Invets when CTnPOL = 1 PWM Peiod set y CCRP CTMn O/P Pin (CTnOC=0) CCRA Int. flag CTMnAF CCRP Int. flag CTMnPF PWM Output Mode – CTnDPX = 0 Note: 1. Here CTnDPX=0 – Counter cleared by CCRP 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTnIO [1:0]=00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n = 0 or 1

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value CCRP CCRA CTnON CTnPAU CTnPOL CCRP Int. flag CTMnPF CCRA Int. flag CTMnAF CTMn O/P Pin (CTnOC=1) Tie Counte leaed y CCRA Pause Resue Counte Stop if CTnON it low Counte Reset when CTnON etuns high CTnDPX = 1; CTnM [1:0] = 10 PWM Duty Cyle set y CCRP PWM esues opeation Output ontolled y othe pin-shaed funtion Output Invets when CTnPOL = 1 PWM Peiod set y CCRA CTMn O/P Pin (CTnOC=0) PWM Output Mode – CTnDPX = 1 Note: 1. Here CTnDPX = 1 – Counter cleared by CCRA 2. A counter clear sets PWM Period 3. The internal PWM function continues even when CTnIO [1:0] = 00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n = 0 or 1

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standard Type TM – STM The Standard T ype TM contains five operating modes, which are Compare Match Output, T imer/ Event Counter , Capture Input, Single Pulse Output and PWM Output modes. The Standard TM can also be controlled with two external input pins and can drive two external output pin. Device STM Core STM Input Pin STM Output Pin BSF340 BSF30 BSF30 BSF370 1-it STM STCK STPI STP STPB fSYS fSYS/4 fH/4 fH/1 fSUB STCK 000 001 010 011 100 101 110 111 STCK~STCK0 1-it Count-up Counte 8-it Copaato P CCRP 8~1 0~1 1-it Copaato A STON STPAU Copaato A Math Copaato P Math Counte Clea 0 Output Contol Polaity Contol Pin Contol STP STOC STM1 STM0 STIO1 STIO0 STMAF Inteupt STMPF Inteupt STPOL PxSn CCRA STCCLR Edge Deteto STPI STIO1 STIO0 fSUB STPB Standard Type TM Block Diagram Standard TM Operation The size of Standard TM is 16-bit wide and its core is a 16-bit count-up counter which is driven by a user selectable internal or externa l clock source. There are also two internal comparators with the names, Comparato r A and Comparator P . These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 8-bit wide whose value is compared the with highest 8 bits in the counter while the CCRA is the sixteen bits and therefore compares all counter bits. The onl y way of changing the value of the 16-bit counte r using the appl ication program , is to clear t he c ounter b y c hanging t he ST ON b it f rom l ow t o h igh. T he c ounter wi ll a lso b e c leared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur , a STM interrupt signal will also usually be generated. The Standard Type TM can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standard Type TM Register Description Overall operation of the Standard TM is controlled using a series of registers. A read only register pair e xists t o st ore t he i nternal c ounter 16 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 16-bit CCRA value. The STMRP register is used to store the 8-bit CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 6 5 4 3 2 1 0 STMC0 STPAU STCK STCK1 STCK0 STON — — — STMC1 STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR STMDL D7 D D D4 D3 D D1 D0 STMDH D1 D14 D13 D1 D11 D10 D9 D8 STMAL D7 D D D4 D3 D D1 D0 STMAH D1 D14 D13 D1 D11 D10 D9 D8 STMRP STRP7 STRP STRP STRP4 STRP3 STRP STRP1 STRP0 16-bit Standard TM Registers List STMDL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter Low Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 7 ~ bit 0 STMDH Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 STM Counter High Byte Register bit 7 ~ bit 0 STM 16-bit Counter bit 15 ~ bit 8 STMAL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STM CCRA Low Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 7 ~ bit 0 STMAH Register Bit 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STM CCRA High Byte Register bit 7 ~ bit 0 STM 16-bit CCRA bit 15 ~ bit 8

Rev. 1.40 130 Deee 1 01 Rev. 1.40 131 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver STMC0 Register Bit 7 6 5 4 3 2 1 0 Nae STPAU STCK STCK1 STCK0 STON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 STPAU: STM Counter Pause control 0: Run 1: Pause The c ounter c an be pa used by se tting t his bi t hi gh. Cl earing t he bi t t o z ero re stores normal c ounter ope ration. W hen i n a Pa use c ondition t he ST M wi ll rem ain powe red up a nd c ontinue t o c onsume po wer. T he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. Bit 6~4 STCK2~STCK0: Select STM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: STCK rising edge clock 111: STCK falling edge clock These three bits are used to select the clock source for the STM. The external pin clock source can be chosen to be active on the rising or falling edge. The cloc k source fSYS is the system clock, while fH and fSUB are other internal clocks, the detai ls of which can be found in the oscillator section. Bit 3 STON: STM Counter On/Off control 0: Off 1: On This bit controls the overall on/of f function of the STM. Setting the bit high enables the counter to run while clearing the bit disables the STM. Clearing this bit to zero will stop the counter from counting and turn of f the STM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. If the STM is in the Compare Match Output Mode then the STM output pin will be reset to its initial condition, as specified by the STOC bit, when the STON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" STMC1 Register Bit 7 6 5 4 3 2 1 0 Nae STM1 STM0 STIO1 STIO0 STOC STPOL STDPX STCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 STM1~STM0: Select STM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: T imer/Counter Mode These bits setup the required operating mode for the STM. T o ensure reliable operation the STM should be switched of f before any changes are made to the STM1 and STM0 bits. In the T imer/Counter Mode, the STM output pin control will be disabled.

Rev. 1.40 130 Deee 1 01 Rev. 1.40 131 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 5~4 STIO1~STIO0: Select STM external pin (STP or STPI) function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: T oggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of STPI 01: Input capture at falling edge of STPI 10: Input capture at rising/falling edge of STPI 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the STM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the STM is running. In t he Com pare Mat ch Out put Mode , t he ST IO1 a nd ST IO0 bi ts de termine how t he STM output pin changes state when a compare match occurs from the Comparator A. The TM output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the STM output pin sh ould b e se tup u sing t he ST OC b it i n t he ST MC1 r egister. No te t hat t he o utput level requested by the STIO1 and STIO0 bits must be dif ferent from the initial value setup using the ST OC bit otherwise no change will occur on the STM output pin when a compare match occurs. After the STM output pin changes state, it can be reset to its initial level by changing the level of the STON bit from low to high. In the PWM Mode, the STIO1 and STIO0 bits determine how the STM output pin changes state when a certain compare match condition occurs. The PWM output function i s m odified b y c hanging t hese t wo b its. I t i s n ecessary t o o nly c hange t he values of t he ST IO1 a nd ST IO0 bi ts onl y a fter t he ST M ha s be en swi tched of f. Unpredictable PW M out puts wi ll oc cur i f t he ST IO1 a nd ST IO0 bi ts a re c hanged when the STM is running. Bit 3 STOC: STM STP Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the STM output pin. Its operation depends upon whether ST M i s b eing u sed i n t he C ompare Ma tch Ou tput Mo de o r i n t he PW M Mode/Single Pulse Output Mode. It has no ef fect if the STM is in the T imer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the STM output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low.

Rev. 1.40 13 Deee 1 01 Rev. 1.40 133 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 STPOL: STM STP Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the STP output pin. When the bit is set high the STM output pin will be inverted and not inverted when the bit is zero. It has no ef fect if the STM is in the T imer/Counter Mode. Bit 1 STDPX: STM PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This b it d etermines wh ich o f t he C CRA a nd C CRP r egisters a re u sed f or p eriod a nd duty control of the PWM waveform. Bit 0 STCCLR: STM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. Re member t hat t he Standard TM contains two comparators, Comparator A and Comparator P , either of which can be selected to clear the internal counter . W ith the STCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low , the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The STCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode. STMRP Register Bit 7 6 5 4 3 2 1 0 Nae STRP7 STRP STRP STRP4 STRP3 STRP STRP1 STRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 STRP7~STRP0: STM CCRP 8-bit register, compared with the STM counter bit 15~bit 8 Comparator P match period = 0: 65536 STM clocks 1~255: (1~255) × 256 STM clocks These eight bits are used to setup the value on the internal CCRP 8-bit register , which are then compared with the internal counter ’s highest eight bits. The result of this comparison ca n be se lected to cl ear the int ernal counte r if t he ST CCLR bit is se t t o zero. Se tting the ST CCLR bit to ze ro ensures tha t a compa re ma tch wi th the CCRP values will reset the internal counter . As the CCRP bits are only compared with the highest eight counter bits, the compare values exist in 256 clock cycle multiples. Clearing a ll e ight bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.

Rev. 1.40 13 Deee 1 01 Rev. 1.40 133 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Standard Type TM Operation Modes The Standard T ype TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or T imer/Counter Mode. The operating mode is selected using the STM1 and STM0 bits in the STMC1 register. Compare Match Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register , should be set to 00 respectively . In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow , a compare matc h from Comparator A and a compare match from Comparator P . When the STCCLR bit is low , there are two ways in which the counter can be cleared. One is when a compare match from Comparator P , the other is when the CCRP bits are all zero which allows the counter t o ov erflow. He re bo th ST MAF a nd ST MPF i nterrupt re quest fla gs fo r Co mparator A a nd Comparator P respectively, will both be generated. If the STCCLR bit in the STMC1 register is high then the counter will be cleared when a compare match oc curs from Com parator A. Howe ver, he re onl y t he ST MAF i nterrupt re quest fla g wi ll be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when STCCLR is high no STMPF interru pt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the STM output pin, will change state. The STM output pin condition however only changes state when a STMAF interrupt request flag is generated after a compare match occurs from Comparator A . The S TMPF interrupt reques t flag, g enerated fr om a c ompare m atch o ccurs fr om C omparator P , wi ll h ave n o e ffect o n t he ST M output pin. The way in which the STM output pin changes state are determined by the condition of the STIO1 and STIO0 bits in the STMC1 register . The STM output pin can be selected using the STIO1 and STIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the STM output pin, which is setup after the ST ON bit changes from low to high, is setup using the ST OC bit. Note that if the STIO1 and STIO0 bits are zero then no pin change will take place.

Rev. 1.40 134 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value 0xFFFF CCRP CCRA STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin Tie CCRP=0 CCRP > 0 Counte oveflow CCRP > 0 Counte leaed y CCRP value Pause Resue Stop Counte Restat STCCLR = 0; STM [1:0] = 00 Output pin set to initial Level Low if STOC=0 Output Toggle with STMAF flag Note STIO [1:0] = 10 Ative High Output seletHee STIO [1:0] = 11 Toggle Output selet Output not affeted y STMAF flag. Reains High until eset y STON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when STPOL is high Compare Match Output Mode – STCCLR = 0 Note: 1. W ith STCCLR=0 a Comparator P match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to itsinitial state by a STON bit rising edge

Rev. 1.40 134 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value 0xFFFF CCRP CCRA STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin Tie CCRA=0 CCRA = 0 Counte oveflowCCRA > 0 Counte leaed y CCRA value Pause Resue Stop Counte Restat STCCLR = 1; STM [1:0] = 00 Output pin set to initial Level Low if STOC=0 Output Toggle with STMAF flag Note STIO [1:0] = 10 Ative High Output seletHee STIO [1:0] = 11 Toggle Output selet Output not affeted y STMAF flag. Reains High until eset y STON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when STPOL is high STMPF not geneated No STMAF flag geneated on CCRA oveflow Output does not hange Compare Match Output Mode – STCCLR = 1 Note: 1. W ith STCCLR=1 a Comparator A match will clear the counter 2. The STM output pin is controlled only by the STMAF flag 3. The output pin is reset to its initial state by a STON bit rising edge 4. A STMPF flag is not generated when STCCLR=1

Rev. 1.40 13 Deee 1 01 Rev. 1.40 137 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer/Counter Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 1 1 respectively . The T imer/Counter M ode operates in an identical w ay to the Compare M atch O utput M ode generating the s ame interrupt flags . The exception is that in the T imer/Counter M ode the S TM output pin is not used. Therefore the above description and T iming Diagrams for the Compare Match Out put Mod e c an be use d t o un derstand i ts fu nction. As t he ST M ou tput pi n i s no t use d i n this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and als o the STIO 1 and STIO 0 bits should be set to 10 res pectively. The PWM function w ithin the STM is useful for applications which require functions such as motor control, heating control, illumination control etc. By providing a signal of fixed frequency but of varying duty cycle on the STM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extre mely fl exible. In the PWM mode, the STCCLR bi t ha s no ef fect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency , while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determined using the STDPX bit in the STMC1 register . The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP , will be generated when a compare match occurs from either Comparator A or Comparator P . The ST OC bit in the STMC1 register is used to select the required polarity of the PWM waveform while the two STIO1 and STIO0 bits are used to enable the PWM output or to force the STM output pin to a fixed high or low level. The STPOL bit is used to reverse the polarity of the PWM output waveform.

16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=0 CCRP 1~255 0 Peiod CCRPx 3 Duty CCRA If fSYS=16MHz, STM clock source is fSYS/4, CCRP=2 and CCRA=128, The STM PWM output frequency=(fSYS/4)/(2×256)=fSYS/2048=7.8125kHz, duty=128/(2×256)=25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.
16-bit STM, PWM Mode, Edge-aligned Mode, STDPX=1 CCRP 1~255 0 Peiod CCRA Duty CCRPx 3 The PW M o utput p eriod i s d etermined b y t he C CRA r egister v alue t ogether wi th t he T M c lock while t he PW M d uty c ycle i s d efined b y t he C CRP r egister v alue e xcept wh en t he C CRP v alue i s equal to 0.

Rev. 1.40 13 Deee 1 01 Rev. 1.40 137 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value CCRP CCRA STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin (STOC=1) Tie Counte leaed y CCRP Pause Resue Counte Stop if STON it low Counte Reset when STON etuns high STDPX = 0; STM [1:0] = 10 PWM Duty Cyle set y CCRA PWM esues opeation Output ontolled y othe pin-shaed funtion Output Invets when STPOL = 1 PWM Peiod set y CCRP STM O/P Pin (STOC=0) PWM Output Mode – STDPX = 0 Note: 1. Here STDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation

Rev. 1.40 138 Deee 1 01 Rev. 1.40 139 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value CCRP CCRA STON STPAU STPOL CCRP Int. flag STMPF CCRA Int. flag STMAF STM O/P Pin (STOC=1) Tie Counte leaed y CCRA Pause Resue Counte Stop if STON it low Counte Reset when STON etuns high STDPX = 1; STM [1:0] = 10 PWM Duty Cyle set y CCRP PWM esues opeation Output ontolled y othe pin-shaed funtion Output Invets when STPOL = 1 PWM Peiod set y CCRA STM O/P Pin (STOC=0) PWM Output Mode – STDPX = 1 Note: 1. Here STDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when STIO [1:0] = 00 or 01 4. The STCCLR bit has no influence on PWM operation

Rev. 1.40 138 Deee 1 01 Rev. 1.40 139 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Single Pulse Output Mode To select this mode, bits STM1 and STM0 in the STMC1 register should be set to 10 respectively and also the STIO1 and STIO0 bits should be set to 1 1 respectively . The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the STM output pin. The trigger for the pulse output lead ing edge is a low to high transition of the ST ON bit, which can be i mplemented using t he a pplication progra m. However i n t he Singl e Pulse Mode, t he ST ON bi t can also be made to automatically change from low to high using the external STCK pin, which will in turn initiate the Single Pulse output. When the ST ON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The ST ON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the STON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the ST ON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a STM interrupt. The counter can only be reset back to zero when the ST ON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The STCCLR and STDPX bits are not used in this Mode. STON it 0 à 1 S/W Coand SET“STON” o STCK Pin Tansition STON it 1 à 0 CCRA Tailing Edge S/W Coand CLR“STON” o CCRA Copae Math STP Output Pin Pulse Width = CCRA Value CCRA Leading Edge Single Pulse Generation

Rev. 1.40 140 Deee 1 01 Rev. 1.40 141 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value CCRP CCRA STON STPAU STPOL CCRP Int. Flag STMPF CCRA Int. Flag STMAF STM O/P Pin (STOC=1) Tie Counte stopped y CCRA Pause Resue Counte Stops y softwae Counte Reset when STON etuns high Pulse Width set y CCRA Output Invets when STPOL = 1 No CCRP Inteupts geneated STM O/P Pin (STOC=0) STCK pin Softwae Tigge Cleaed y CCRA ath STCK pin Tigge Auto. set y STCK pin Softwae Tigge Softwae Clea Softwae Tigge Softwae Tigge Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the STCK pin or by setting the STON bit high 4. A STCK pin active edge will automatically set the STON bit high. 5. In the Single Pulse Mode, STIO [1:0] must be set to "11" and can not be changed.

Rev. 1.40 140 Deee 1 01 Rev. 1.40 141 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Capture Input Mode To select this mode bits STM1 and STM0 in the STMC1 register should be set to 01 respectively . This mode enables external s ignals to capture and s tore the pres ent value of the internal counter and c an t herefore be use d fo r a pplications suc h a s pu lse wi dth m easurements. T he e xternal si gnal is suppl ied on t he ST PI pi n, whose a ctive e dge c an be a ri sing e dge, a fa lling e dge or bot h ri sing and falling edges; the active edge transition type is selected using the STIO1 and STIO0 bits in the STMC1 register . The counter is started when the ST ON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the STPI pin the present value in the counter will be latched into the CCRA registers and a STM interrupt generated. Irrespective of what events occur on the STPI pin the counter will continue to free run until the ST ON bit changes from high to low . When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value c an be use d t o c ontrol t he m aximum c ounter va lue. W hen a CCRP c ompare m atch oc curs from Comparat or P , a STM interrupt will also be generated. Counting the number of overfl ow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The STIO1 and STIO0 bits can select the active trigger edge on the STPI pin to be a rising edge, falling edge or both edge types. If the STIO1 and STIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the STPI pin, however it must be noted that the counter will continue to run. The STCCLR and STDPX bits are not used in this Mode.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 143 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value YY CCRP STON STPAU CCRP Int. Flag STMPF CCRA Int. Flag STMAF CCRA Value Tie Counte leaed y CCRP Pause Resue Counte Reset STM [1:0] = 01 STM aptue pin STPI XX Counte Stop STIO [1:0] Value XX YY XX YY Ative edge Ative edge Ative edge 00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disale Captue Capture Input Mode Note: 1. STM [1:0] = 01 and active edge set by the STIO [1:0] bits 2. A STM Capture input pin active edge transfers the counter value to CCRA 3. STCCLR bit not used 4. No output function -- STOC and STPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 143 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Periodic Type TM – PTM The Pe riodic T ype T M c ontains fiv e o perating m odes, wh ich a re C ompare Ma tch Ou tput, T imer/ Event Counter , Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pin. Device PTM Core PTM Input Pin PTM Output Pin BSF340 BSF30 BSF30 BSF370 10-it PTM PTCK PTPI PTP PTPB fSYS fSYS/4 fH/4 fH/1 fSUB PTCK 000 001 010 011 100 101 110 111 PTCK~PTCK0 10-it Count-up Counte 10-it Copaato P CCRP 0~9 0~9 10-it Copaato A PTON PTPAU Copaato A Math Copaato P Math Counte Clea 0 Output Contol Polaity Contol Pin Contol PTP PTOC PTM1 PTM0 PTIO1 PTIO0 PTMAF Inteupt PTMPF Inteupt PTPOL PxSn CCRA PTCCLR Edge Deteto PTPI PTIO1 PTIO0 fSUB

0 Pin

Periodic Type TM Block Diagram Periodic TM Operation The size of Periodic TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or externa l clock source. There are also two internal comparators with the names, Comparato r A and Comparator P . These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is respectively compared with all counter bits. The onl y wa y of c hanging t he va lue of t he 10-bi t c ounter usi ng t he a pplication program i s t o clear t he c ounter b y c hanging t he PT ON b it f rom l ow t o h igh. T he c ounter wi ll a lso b e c leared automatically by a counter overflow or a compare match with one of its associated comparators. When t hese c onditions occ ur, a PT M i nterrupt si gnal wi ll a lso usua lly be ge nerated. T he Pe riodic Type TM can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pins. All operating setup conditions are selected using relevant internal registers.

Rev. 1.40 144 Deee 1 01 Rev. 1.40 14 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 6 5 4 3 2 1 0 PTMC0 PTPAU PTCK PTCK1 PTCK0 PTON — — — PTMC1 PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR PTMDL D7 D D D4 D3 D D1 D0 PTMAL D7 D D D4 D3 D D1 D0 PTMRPL PTRP7 PTRP PTRP PTRP4 PTRP3 PTRP PTRP1 PTRP0 PTMRPH — — — — — — PTRP9 PTRP8 Periodic TM Registers List PTMDL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM Counter Low Byte Register bit 7 ~ bit 0 PTM 10-bit Counter bit 7 ~ bit 0 PTMDH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTM Counter High Byte Register bit 1 ~ bit 0 PTM 10-bit Counter bit 9 ~ bit 8 PTMAL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTM CCRA Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRA bit 7 ~ bit 0

Rev. 1.40 144 Deee 1 01 Rev. 1.40 14 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver PTMAH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTM CCRA High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRA bit 9 ~ bit 8 PTMRPL Register Bit 7 6 5 4 3 2 1 0 Nae PTRP7 PTRP PTRP PTRP4 PTRP3 PTRP PTRP1 PTRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTRP7~PTRP0: PTM CCRP Low Byte Register bit 7 ~ bit 0 PTM 10-bit CCRP bit 7 ~ bit 0 PTMRPH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTRP9~PTRP8: PTM CCRP High Byte Register bit 1 ~ bit 0 PTM 10-bit CCRP bit 9 ~ bit 8 PTMC0 Register Bit 7 6 5 4 3 2 1 0 Nae PTPAU PTCK PTCK1 PTCK0 PTON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PTPAU: PTM Counter Pause control 0: Run 1: Pause The c ounter c an be pa used by se tting t his bi t hi gh. Cl earing t he bi t t o z ero re stores normal c ounter ope ration. W hen i n a Pa use c ondition t he PT M wi ll rem ain powe red up a nd c ontinue t o c onsume po wer. T he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. Bit 6~4 PTCK2~PTCK0: Select PTM Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCK rising edge clock 111: PTCK falling edge clock These three bits are used to select the clock source for the PTM. The external pin clock source can be chosen to be active on the rising or falling edge. The cloc k source fSYS is the system clock, while fH and fSUB are other internal clocks, the detai ls of which can be found in the oscillator section.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 147 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 3 PTON: PTM Counter On/Off control 0: Off 1: On This bit controls the overall on/of f function of the PTM. Setting the bit high enables the counter to run while clearing the bit disables the PTM. Clearing this bit to zero will stop the counter from counting and turn of f the PTM which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. If the PTM is in the Compare Match Output Mode then the PTM output pin will be reset to its initial condition, as specified by the PTOC bit, when the PTON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMC1 Register Bit 7 6 5 4 3 2 1 0 Nae PTM1 PTM0 PTIO1 PTIO0 PTOC PTPOL PTCAPTS PTCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PTM1~PTM0: Select PTM Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Mode or Single Pulse Output Mode 11: T imer/Counter Mode These bits setup the required operating mode for the PTM. T o ensure reliable operation the PTM should be switched of f before any changes are made to the PTM1 and PTM0 bits. In the T imer/Counter Mode, the PTM output pin control will be disabled. Bit 5~4 PTIO1~PTIO0: Select PTM external pin PTP or PTPI function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: T oggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of PTPI or PTCK 01: Input capture at falling edge of PTPI or PTCK 10: Input capture at rising/falling edge of PTPI or PTCK 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTM output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTM is running.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 147 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver In t he Com pare Mat ch Out put Mode , t he PT IO1 a nd PT IO0 bi ts de termine how t he PTM output pin changes state when a compare match occurs from the Comparator A. The PT M out put pi n c an be se tup t o swi tch hi gh, swi tch l ow or t o t oggle i ts pre sent state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTM output pin sh ould b e se tup u sing t he PT OC b it i n t he PT MC1 r egister. No te t hat t he o utput level requested by the PTIO1 and PTIO0 bits must be dif ferent from the initial value setup using the PT OC bit otherwise no change will occur on the PTM output pin when a compare match occurs. After the PTM output pin changes state, it can be reset to its initial level by changing the level of the PTON bit from low to high. In the PWM Mode, the PTIO1 and PTIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PTM output function is modified by changing these two bits. It is necessary to only change the values of the PTIO1 and PTIO0 bits only after the PTM has been switched of f. Unpredictable PWM outputs will occur if the PTIO1 and PTIO0 bits are changed when the PTM is running. Bit 3 PTOC: PTM PTP Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTM output pin. Its operation depends upon whether PT M i s b eing u sed i n t he C ompare Ma tch Ou tput Mo de o r i n t he PW M Mode/Single Pulse Output Mode. It has no ef fect if the PTM is in the T imer/Counter Mode. In the Compare Match Output Mode it determines the logic level of the PTM output pin before a compare match occurs. In the PWM Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2 PTPOL: PTM PTP Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the PTP output pin. When the bit is set high the PTM output pin will be inverted and not inverted when the bit is zero. It has no ef fect if the PTM is in the T imer/Counter Mode. Bit 1 PTCAPTS: PTM Capture T riiger Source selection 0: From PTPI pin 1: From PTCK pin Bit 0 PTCCLR: PTM Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. Re member t hat t he Periodic T M c ontains t wo c omparators, Com parator A a nd Com parator P , e ither of which can be selected to clear the internal counter . W ith the PTCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low , the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode.

Rev. 1.40 148 Deee 1 01 Rev. 1.40 149 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Periodic Type TM Operation Modes The Periodic T ype TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or T imer/Counter Mode. The operating mode is selected using the PTM1 and PTM0 bits in the PTMC1 register. Compare Match Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register , should be set to 00 respectively . In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow , a compare matc h from Comparator A and a compare match from Comparator P . When the PTCCLR bit is low , there are two ways in which the counter can be cleared. One is when a compare match from Comparator P , the other is when the CCRP bits are all zero which allows the counter t o ov erflow. He re bo th PT MAF a nd PT MPF i nterrupt re quest fla gs fo r Co mparator A a nd Comparator P respectively, will both be generated. If the PTCCLR bit in the PTMC1 register is high then the counter will be cleared when a compare match oc curs from Com parator A. Howe ver, he re onl y t he PT MAF i nterrupt re quest fla g wi ll be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTCCLR is high no PTMPF interru pt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As t he na me of t he m ode sugge sts, a fter a c omparison i s m ade, t he PT M out put pi n wi ll c hange state. The PTM output pin condition however only changes state when a PTMAF interrupt request flag is generated after a compare match occurs from Comparator A . The P TMPF interrupt reques t flag, g enerated fr om a c ompare m atch o ccurs fr om C omparator P , wi ll h ave n o e ffect o n t he PT M output pin. The way in which the PTM output pin changes state are determined by the condition of the PTIO1 and PTIO0 bits in the PTMC1 register . The PTM output pin can be selected using the PTIO1 and PTIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the PTM output pin, which is setup after the PT ON bit changes from low to high, is setup using the PT OC bit. Note that if the PTIO1 and PTIO0 bits are zero then no pin change will take place.

Rev. 1.40 148 Deee 1 01 Rev. 1.40 149 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value 0x3FF CCRP CCRA PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin Tie CCRP=0 CCRP > 0 Counte oveflow CCRP > 0 Counte leaed y CCRP value Pause Resue Stop Counte Restat PTCCLR = 0; PTM [1:0] = 00 Output pin set to initial Level Low if PTOC=0 Output Toggle with PTMAF flag Note PTIO [1:0] = 10 Ative High Output seletHee PTIO [1:0] = 11 Toggle Output selet Output not affeted y PTMAF flag. Reains High until eset y PTON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when PTPOL is high Compare Match Output Mode – PTCCLR = 0 Note: 1. W ith PTCCLR=0, a Comparator P match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value 0x3FF CCRP CCRA PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin Tie CCRA=0 CCRA = 0 Counte oveflowCCRA > 0 Counte leaed y CCRA value Pause Resue Stop Counte Restat PTCCLR = 1; PTM [1:0] = 00 Output pin set to initial Level Low if PTOC=0 Output Toggle with PTMAF flag Note PTIO [1:0] = 10 Ative High Output seletHee PTIO [1:0] = 11 Toggle Output selet Output not affeted y PTMAF flag. Reains High until eset y PTON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when PTPOL is high PTMPF not geneated No PTMAF flag geneated on CCRA oveflow Output does not hange Compare Match Output Mode – PTCCLR = 1 Note: 1. W ith PTCCLR=1, a Comparator A match will clear the counter 2. The PTM output pin is controlled only by the PTMAF flag 3. The output pin is reset to its initial state by a PTON bit rising edge 4. A PTMPF flag is not generated when PTCCLR =1

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Timer/Counter Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 1 1 respectively . The T imer/Counter M ode operates in an identical w ay to the Compare M atch O utput M ode generating the s ame interrupt flags . The exception is that in the T imer/Counter M ode the P TM output pin is not used. Therefore the above description and T iming Diagrams for the Compare Match Out put Mod e c an be use d t o un derstand i ts fu nction. As t he PT M ou tput pi n i s no t use d i n this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and als o the PTIO 1 and PTIO 0 bits should be set to 10 res pectively. The PWM function w ithin the PTM is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the PTM output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extre mely fl exible. In the PWM mode, the PTCCLR bi t ha s no ef fect as the PWM period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency , while the other one is used to control the duty cycl e. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP , will be generated when a compare match occurs from either Comparator A or Comparator P . The PT OC bit in the PTMC1 register is used to select the required polarity of the PWM waveform while the two PTIO1 and PTIO0 bits are used to enable the PWM output or to force the PTM output pin to a fixed high or low level. The PTPOL bit is used to reverse the polarity of the PWM output waveform.

10-bit PTM, PWM Mode, CCRP 1~1023 0 Peiod 1~103 104 Duty CCRA If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128, The PTM PWM output frequency = (fSYS/4)/512 = fSYS/2048 = 7.8125kHz, duty=128/512=25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value CCRP CCRA PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin (PTOC=1) Tie Counte leaed y CCRP Pause Resue Counte Stop if PTON it low Counte Reset when PTON etuns high PTM [1:0] = 10 PWM Duty Cyle set y CCRA PWM esues opeation Output ontolled y othe pin-shaed funtion Output Invets When PTPOL = 1 PWM Peiod set y CCRP PTM O/P Pin (PTOC=0) PWM Mode Note: 1. The counter is cleared by CCRP. 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTIO [1:0] = 00 or 01 4. The PTCCLR bit has no influence on PWM operation

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Single Pulse Output Mode To select this mode, bits PTM1 and PTM0 in the PTMC1 register should be set to 10 respectively and also the PTIO1 and PTIO0 bits should be set to 1 1 respectively . The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTM output pin. The trigger for the pulse output lead ing edge is a low to high transition of the PT ON bit, which can be i mplemented using t he a pplication progra m. However i n t he Singl e Pulse Mode, t he PT ON bi t can also be made to automatically change from low to high using the external PTCK pin, which will in turn initiate the Single Pulse output. When the PT ON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PT ON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compare match from Comparator A will also automatically clear the PT ON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTM interrupt. The counter can only be reset back to zero when the PT ON bit changes from low to high when the counter restarts. In the Single Pulse Mode CCRP is not used. The PTCCLR is not used in this Mode. PTON it 0 à 1 S/W Coand SET“PTON” o PTCK Pin Tansition PTON it 1 à 0 CCRA Tailing Edge S/W Coand CLR“PTON” o CCRA Copae Math PTP Output Pin Pulse Width = CCRA Value CCRA Leading Edge Single Pulse Generation

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value CCRP CCRA PTON PTPAU PTPOL CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF PTM O/P Pin (PTOC=1) Tie Counte stopped y CCRA Pause Resue Counte Stops y softwae Counte Reset when PTON etuns high Pulse Width set y CCRA Output Invets when PTPOL = 1 No CCRP Inteupts geneated PTM O/P Pin (PTOC=0) PTCK pin Softwae Tigge Cleaed y CCRA ath PTCK pin Tigge Auto. set y PTCK pin Softwae Tigge Softwae Clea Softwae Tigge Softwae Tigge Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the PTCK pin or by setting the PTON bit high 4. A PTCK pin active edge will automatically set the PTON bit high. 5. In the Single Pulse Mode, PTIO [1:0] must be set to "11" and can not be changed.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Capture Input Mode To select this mode bits PTM1 and PTM0 in the PTMC1 register should be set to 01 respectively . This mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. The external signal is supplied on the PTPI or PTCK pin, selected by the PTCAPTS bit in the PTMC1 register . The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is selected using the PTIO1 and PTIO0 bits in the PTMC1 register . The counter is s tarted w hen the P TON bit changes from low to high w hich is initiated us ing the application program. When the required edge transition appears on the PTPI or PTCK pin the present value in the counter will be latched into the CCRA registers and a PTM interrupt generated. Irrespective of what events occur o n t he PT PI o r PT CK p in t he c ounter wi ll c ontinue t o f ree r un u ntil t he PT ON b it c hanges from high to low . When a CCRP compare match occurs the counter will reset back to zero; in this way t he CCRP val ue c an be use d t o c ontrol t he m aximum c ounter val ue. Whe n a CCRP c ompare match occurs from Comparator P , a PTM interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTIO1 and PTIO0 bits can select the active trigger edge on the PTPI or PTCK pin to be a rising edge, fall ing edge or both edge types. If the PTIO1 and PTIO0 bits are both set high, then no capture operation will take place irrespectiv e of what happens on the PTPI or PTCK pin, however it must be noted that the counter will continue to run. As the PTPI or PTCK pin is pin shared with other functions, care must be taken if the PTM is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTCCLR, PT OC and PTPOL bits are not used in this Mode.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Counte Value YY CCRP PTON PTPAU CCRP Int. Flag PTMPF CCRA Int. Flag PTMAF CCRA Value Tie Counte leaed y CCRP Pause Resue Counte Reset PTM [1:0] = 01 PTM aptue pin PTPI o PTCK XX Counte Stop PTIO [1:0] Value XX YY XX YY Ative edge Ative edge Ative edge 00 – Rising edge 01 – Falling edge 10 – Both edges 11 – Disale Captue Capture Input Mode Note: 1. PTM [1:0] = 01 and active edge set by the PTIO [1:0] bits 2. A PTM Capture input pin active edge transfers the counter value to CCRA 3. PTCCLR bit not used 4. No output function – PTOC and PTPOL bits are not used 5. CCRP determines the counter value and the counter has a maximum count value when CCRP is equal to zero.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However , to properly process these signals by a microcontroller , they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller , the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Converter Overview These devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signals, such as the T emperature semsor output or T emperature sensor reference voltage, into a 12-bit digital value. The external or internal analog signal to be convert ed is determined by the ACS3~ACS 0 bits together with the TSE and BGMEN bits. When the external analog signal is to be converted, the corresponding pin-shared control bits should first be properly configured and then desired external channel input should be selected using the ACS3~ACS0 bits. This A/ D c onverter a lso i ncludes a t emperature se nsor c ircuitry whic h c ontains a t emperature sensor, operationa l amplifiers and an internal reference voltage. The temperature sensor will detect the t emperature a nd out put a vol tage proporti onal t o t he t emperature. T he out put vol tage c an be amplified by the OPA and then converted to an 12-bit digital data using the A/D converter. The accompanying block diagram shows the internal structure of the A/D converter with temperature sensor together with its associated registers and control bits. Device External Input Channels Internal Signal A/D Channel Select Bits BSF340 BSF30 BSF30 BSF370 8: AN0~AN7 : VTSO VTSVREF ACS3~ACS0 TSE BGMEN Pin-shaed Seletion ACS3~ACS0 A/D Convete START ADBZ VSS A/D Clok ÷ N (N=0~7) fSYS ADCK~ADCK0 VDD ADCEN ADRL ADRH AN0 AN1 AN7 A/D Convete Refeene Voltage A/D Data Registes ADRFS VREF Pin-shaed Seletion IDLE_CONV ATM Tep. Senso TSE BGMEN VBGTS VPTAT OPA1 Gain=1.7 o 1 K_VPTAT OP1EN K_REFO OPA OPEN Gain=4 o GXEN VTSO VDD TSE BGMEN VTSVREF VREFP_EXT 1xxxB VTSO VTSVREF VPTAT TSCLK_S1~TSCLK_S0 VREFS VTSVRI BIAS VTSVREF VDD A/D Converter with Temperature Sensor Diagram

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Registers Descriptions Overall operation of the A/D converter with T emperature sensor is controlled using eight registers. A read only register pair exists to store the A/D Converter data 12-bit value. T wo registers, ADCR0 and ADCR1, are the control registers which setup the operating and control function of the A/D converter. The remaining four registers are the temperature sensor control registers which select the t emperature se nsor si gnal t o b e c onverted a nd t he r eference v oltage so urce t ogether wi th t he temperature sensor conversion clock cycles. Register Name Bit 7 6 5 4 3 2 1 0 ADRL (ADRFS=0) D3 D D1 D0 — — — — ADRL (ADRFS=1) D7 D D D4 D3 D D1 D0 ADRH (ADRFS=0) D11 D10 D9 D8 D7 D D D4 ADRH (ADRFS=1) — — — — D11 D10 D9 D8 ADCR0 START ADBZ ADCEN ADRFS ACS3 ACS ACS1 ACS0 ADCR1 ATM — IDLE_ CONV VREFS — ADCK ADCK1 ADCK0 TSC0 BGMEN GXEN K_REFO — — — — — TSC1 TSE OPEN OP1EN — — — — — TSC VREFP_EXT BIAS D D4 D3 D TSCLK_S1 TSCLK_S0 A/D Converter with Temperature Sensor Registers List A/D Converter Data Registers – ADRL, ADRH As these devices contain an internal 12-bit A/D converter , it requires two data registers to store the converted va lue. T hese a re a hi gh byt e register, kn own a s ADR H, a nd a l ow byt e re gister, kno wn as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is utilised, the format in which the data is stored is controlled by the ADRFS bit in the ADCR0 register as shown in the accompany ing table. D0~D1 1 are the A/D conversion result data bits. Any unused bits will be read as zero. Note that the A/D data register conten ts can only be read in the A/ D conversion completion interrupt service subroutine when the Auto-conversion mode is enabled by setting the A TM bit in the ADCR1 register to 1. The A/D data registe rs contents will be cleared to zero if the A/D converter is disabled. ADRFS ADRH ADRL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 D11 D10 D9 D8 D7 D D D4 D3 D D1 D0 0 0 0 0

1 0 0 0 0 D11 D10 D9 D8 D7 D D D4 D3 D D1 D0 A/D Converter Data Registers

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Converter Control Registers – ADCR0, ADCR1 To control the function and operatio n of the A/D converter , two control registers known as ADCR0 and ADCR1 are provided. These 8-bit registers define functions such as the selection of which analog channel is connected to the internal A/D converter , the digitised data format, the A/D clock source as well as controlling the start function and monitoring the A/D converter busy status. As these de vices c ontain on ly on e a ctual a nalog t o di gital c onverter ha rdware c ircuit, e ach of t he external and internal analog signals must be routed to the converter . The ACS3~ACS0 bits in the ADCR0 register and the TSE and BGMEN bits in the TSC1 and TSC0 registers are used to determine that the specific external channel input or relevant internal temperature sensor signal is selected to be converted. If the internal temperature sensor analog signal is selected to be converted, the ACS3~ACS0 bits should be set as "1xxx" toge ther wit h proper configurati ons of TSE and BGMEN bits. TSE BGMEN ACS3~ACS0 Input Signals Description 0 x x000~x111 AN0~AN7 Extenal hannel analog input 1 0 1xxx VTSO Tepeatue Senso output voltage 1 1 1xxx VTSVREF Tepeatue Senso efeene voltage A/D Converter Input Signal Selection The relev ant pin-shared function selection bits determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not to be used as the A/D converter input. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin- shared function will be removed. In addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an A/D converter input.

ADCR0 Register Bit 7 6 5 4 3 2 1 0 Nae START ADBZ ADCEN ADRFS ACS3 ACS ACS1 ACS0 R/W R/W R R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 START: Start the A/D Conversion 0→1→0: Start This bit is used to initiate an A/ D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. Bit 6 ADBZ: A/D Converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is us ed to indicate w hether the A /D convers ion is in progress or not. When the ST ART bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Bit 5 ADCEN: A/D Converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/ D c onverter. If t he bi t i s se t l ow, t hen t he A/ D c onverter wi ll be swi tched of f reducing the device power consumption. When the A/D converter function is disabled, the conte nts of the A/D data register pair known as ADRH and ADRL will be cleared to zero.

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 4 ADRFS: A/D conversion data format select 0: A/D converter data format → ADRH = D [11:4]; ADRL = D [3:0] 1: A/D converter data format → ADRH = D [11:8]; ADRL = D [7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D converter data register section. Bit 3~0 ACS3~ACS0: A/D converter analog input signal select 0000: External AN0 input 0001: External AN1 input 0010: External AN2 input 0011: External AN3 input 0100: External AN4 input 0101: External AN5 input 0110: External AN6 input 0111: External AN7 input 1xxx: Internal signal from temperature sensor – temperature output voltage or reference voltage The "1xxx" selection is only available when the TSE bit is set to 1. T o select the internal temperature sensor signal to be converted, these bits must be set as "1xxx" when the TSE bit is set to 1. Otherwise, these bits are used to select the external ANn channel input without the regard of the ACS3 value if the TSE bit is cleared to 0.

ADCR1 Register Bit 7 6 5 4 3 2 1 0 Nae ATM — IDLE_CONV VREFS — ADCK ADCK1 ADCK0 R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — 0 0 0 Bit 7 ATM: A/D auto-conversion mode enable control 0: Disable 1: Enable When t his bi t i s se t t o 1, t he A/ D c onverter wi ll c ontinuously pe rform t he da ta conversion after the current conversion is complete without configuring the "ST ART" bit by application program. Note that the A/D conversion data can only be read in the A/D c onversion c ompletion i nterrupt se rvice su broutine wh en t he A/ D auto-conversion mode is enabled. Bit 6 Unimplemented, read as "0" Bit 5 IDLE_CONV: CPU idle conversion mode enable control 0: Disable 1: Enable When this bit is set to 1, the A/D conversion with CPU idle mode will be enabled. The CPU will not operate when the A/D converter is operating with the IDLE_CONV bit being set to 1 until the conversion is completed. Bit 4 VREFS: A/D converter reference voltage select 0: Internal A/D converter power 1: VREF pin This bit is used to select the A/D converter reference voltage and only available when the VREFP_EXT bit in the TSC2 register is set to 1. It is recommended to keep the VREFP_EXT bit low when the internal temperature sensor signal is selected to be converted. Bit 3 Unimplemented, read as "0"

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2~0 ADCK2~ADCK0: A/D conversion clock source select 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These bits are used to select the cloc k source for the A/D converter . It is recommended that the A/D conversion clock frequency should be in the range from 500 kHz to 1MHz by properly configuring the ADCK2~ADCK0 bits when the internal temperature sensor signal is selected to be converted as temperature sensor enabled,

TSC0 Register Bit 7 6 5 4 3 2 1 0 Nae BGMEN GXEN K_REFO — — — — — R/W R/W R/W R/W — — — — — Bit 7 BGMEN: T emperature sensor reference voltage output function enable control 0: Disable 1: Enable This bi t c ontrols t he i nternal t emperature se nsor re ference vo ltage ou tput fu nction and is only available when the TSE bit is set to 1. The internal temperature sensor reference voltage can be converted when the TSE and BG MEN bits are set to 1 and the ACS bit field is set to "1xxx". However , the internal temperature sensor output voltage will be converted if the TSE bit is set to 1 and the BGMEN bit is cleared to 0 together with ACS bit field equal to "1xxx". Bit 6 G5XEN: OPA2 gain select 0: Gain=4 1: Gain=5 This bit controls the OP A2 gain selection. This bit should be properly selected for different temperature range applications to avoid the saturated code. Bit 5 K_REFO: OPA1 gain select 0: Gain=1.675 1: Gain=1 This bit is used to select the OP A1 gain to determine the temperature sensor reference voltage output value. Bit 4~0 Unimplemented, read as "0"
TSC1 Register Bit 7 6 5 4 3 2 1 0 Nae TSE OPEN OP1EN — — — — — R/W R/W R/W R/W — — — — — Bit 7 TSE: T emperature sensor circuitry enable control 0: Disable 1: Enable This bit controls the internal temperature sensor circuitry. When the temperature sensor is enable d by setting the TSE bit to 1, a time named as tTSS should be allowed for the temperature sensor circuit to stabilise before implementing relevant temperature sensor operation.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 6 OP2EN: T emperature sensor OPA2 enable control 0: Disable 1: Enable Bit 5 OP1EN: T emperature sensor OPA1 enable control 0: Disable 1: Enable Bit 4~0 Unimplemented, read as "0"

TSC2 Register Bit 7 6 5 4 3 2 1 0 Nae VREFP_EXT BIAS D D4 D3 D TSCLK_S1 TSCLK_S0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 VREFP_EXT: A/D converter positive reference voltage select 0: T emperature reference voltage – VTSVREF 1: Determined by VREFS bit This bit is used to select the A/D converter positive reference voltage. When this bit is set to 1, the A/D converter reference voltage is determines by the VREFS bit in the ADCR1 register . However , this bit should be set low to select the VTSVREF voltage as the A/D converter reference voltage together with proper configurations of the OP A2 input signal and gain. Bit 6 BIAS: OPA2 bias voltage select 0: VTSVREF 1: Internal A/D converter power Bit 5~2 D5~D2: Data bits for internal used These bits should be kept low and can not be changed. Bit 1~0 TSCLK_S1~TSCLK_S0: T emperature sensor clock source tTSCLK select 00: tTSCLK = tADCK/4 01: tTSCLK = tADCK/8 1x: tTSCLK = tADCK/16 The temperature sensor signal conversion time can be obtained using the equation: Temperature sensor signal conversion time = (5×N+1+16) × tADCK In the above equation "N" represents the divided ratio, 4, 8 or 16, which is determined by the TSCLK_S1 and TSCLK_S0 bits.
TSC3Register Bit 7 6 5 4 3 2 1 0 Bit 7~6 Unimplemented, read as "0" Bit 5 K_VPTAT: OPA1 input voltage select 0: VBG 1: VPTAT This bit is used to select the OP A1 input voltage to obtain the internal temperature sensor reference voltage. Bit 4~0 Unimplemented, read as "0"

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Converter Operation The ST ART bit in the ADCR0 register is used to start the AD conversion. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. The ADBZ bit in the ADCR0 register is used to indicate whether the analog to digital conversion process is in progress or not. This bit will be automatically set to 1 by the microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ will be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register , and if the interrupts are enabled, an internal interrupt signal will be generated. This A/D internal interrupt s ignal w ill direct the program fl ow to the as sociated A /D internal interrupt address f or p rocessing. I f t he A/ D i nternal i nterrupt i s d isabled, t he m icrocontroller c an p oll t he ADBZ bit in the ADCR0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter , which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the SACKS2~SACKS0 bits in the SADC1 register . Although the A/D cloc k source is determined by the system clock fSYS and by bi ts ADCK2~ADCK0, there are som e limi tations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μs, care must be taken for system clock frequencies. For example, as the system clock operates at a frequency of 8MHz, the ADCK2~ADCK0 bits should not be set to 000, 001 or 1 11. Doing so will give A/D clock periods that are less than the minimum A/D clock period which m ay re sult i n i naccurate A/ D c onversion va lues. Re fer t o t he fol lowing t able for e xamples, where values marked with an asteri sk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. However, the recommended A/D clock period is from 1μs to 2μs if the input signal to be converted is the temperature sensor output voltage or reference voltage. fSYS A/D Clock Period (tADCK) ADCK[2:0] = 000 (fSYS) ADCK[2:0] = 001 (fSYS/2) ADCK[2:0] = 010 (fSYS/4) ADCK[2:0] = 011 (fSYS/8) ADCK[2:0] = 100 (fSYS/16) ADCK[2:0] = 101 (fSYS/32) ADCK[2:0] = 110 (fSYS/64) ADCK[2:0] = 111 (fSYS/128)

1 MHz 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs * 128μs *

MHz 00ns 1μs 2μs 4μs 8μs 16μs * 32μs * 64μs *

4 MHz 0ns * 00ns 1μs 2μs 4μs 8μs 16μs * 32μs *

8 MHz 1ns * 0ns * 00ns 1μs 2μs 4μs 8μs 16μs *

1 MHz 83ns * 17ns * 333ns * 7ns 1.33μs 2.67μs 5.33μs 10.67μs * 1 MHz .ns * 1ns * 0ns * 00ns 1μs 2μs 4μs 8μs 0 MHz 0ns * 100ns * 00ns * 400ns * 800ns 1.6μs 3.2μs 6.4μs A/D Clock Period Examples for External Analog Inputs However, the recommended A/D clock period is from 1μs to 2μs if the input signal to be converted is the temperature sensor output voltage or reference voltage. Controlling t he powe r on/ off func tion of t he A/ D c onverter c ircuitry i s i mplemented usi ng t he ADCEN bi t i n t he ADCR 0 re gister. T his bi t m ust be se t hi gh t o powe r on t he A/ D c onverter. When the ADCEN bit is set high to power on the A/D converter internal circuitry a certain delay , as indica ted in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be consumed. In power conscious applications it is therefore recommended that the ADCEN is set low to reduce power consumption when the A/D converter function is not being used.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Converter Reference Voltage The reference voltage supply to the A/D Converter can be supplied from the positive power supply pin, VDD, a n e xternal re ference sourc e suppl ied on pi n VR EF or a n i nternal t emperature se nsor reference voltage VTSVREF. The internal temperature sensor reference voltage can be derived from the intenal VBG or VPTAT voltage selected using the K_VPTAT bit in the TSC3 register and then amplified through a p rogrammable g ain a mplifier e xcept t he o ne so urced f rom VDD. T he PGA g ain c an b e equal to 1.675 or 1 selected by the K_REFO bit in the TSC0 register . As the VREF pin is pin-shared with other functio ns, when the VREF pin is selected as the reference voltage supply pin, the VREF pin-shared function control bits should first be properly configured to disable other pin-shared functions. A/D Converter Input Pins All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions. The c orresponding p in-shared f unction se lection b its i n t he Px S0 a nd Px S1 r egisters, d etermine whether the external input pins are setup as A/D converter analog channel inputs or whether they have other functio ns. If the corresponding pin is setup to be an A/D converter analog channel input, the original pin functions will be disabled. In this way , pins can be changed under program control to change their function between A/D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnecte d if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the relevant A/D input function select ion bits enable an A/D input, the status of the port control register will be overridden. The A /D converter has its ow n reference voltage pin, V REF. H owever, the reference voltage can also be supplied from the power supply pin or an internal temperature sensor circuit, a choice which is made through the VREFP_EXT and VREFS bits in the TSC2 and ADCR1 register respectively . Note that the anal og input signal values must not be allowed to exceed the value of the selected A/D reference voltage. Conversion Rate and Timing Diagram A com plete A/D conversi on contains two parts, dat a sampli ng and dat a conversi on. The dat a sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an external input A/D conversion which is defined as tADC are necessary . However , an A/D conversion for an inter nal temperatur e sensor signal will take a total of 56 A/D clock cycles. Maximum single A/D conversion rate = A/D clock period / 16 (External channel input signal) Maximum si ngle A/ D conversion rate = A/ D clock pe riod / 56 (I nternal T emperature se nsor si gnal) The accompanying diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware w ill begin to carry out the conversion, d uring wh ich t ime t he p rogram c an c ontinue wi th o ther f unctions. T he t ime t aken f or t he A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver ADCEN START ADBZ ACS[3:0] off on off on tONST tADS A/D sapling tie tADS A/D sapling tie Stat of A/D onvesion Stat of A/D onvesion Stat of A/D onvesion End of A/D onvesion End of A/D onvesion tADC A/D onvesion tie tADC A/D onvesion tie tADC A/D onvesion tie x011B x010B x000B x001B A/D hannel swith (TSE=0) A/D Conversion Timing – External Channel Input Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process.

Step 1 Select the required A/D conversion clock by properly programming the ADCK2~ADCK0 bits in the ADCR1 register.
Step 2 Enable the A/D converter by setting the ADCEN bit in the ADCR0 register to one.
Step 3 Select which signal is to be connec ted to the internal A/D converter by correctly configuring the ACS3~ACS0 bits If the TSE bit is 0 and ACS3~ACS0 bits are equal to x000~x1 11, then an external channel input is selected. If the TSE bit is 1 and ACS3~ACS0 bits are equal to 1xxx, then the relevant internal temperature sensor signal is selected.
Step 4 Select the reference voltgage source by configuring the K_VPTAT, K_REFO and VREFS bits.
Step 5 Select the A/D converter output data format by configuring the ADRFS bit.
Step 6 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt bontrol bit, EMI, and the A/D conversion interrupt control bit, ADE, must both be set high in advance.
Step 7 The A/D conversion procedure can now be initialized by setting the ST ART bit from low to high and then low again.
Step 8 If A/ D conversi on i s i n progre ss, t he ADBZ fla g wi ll be se t high. Aft er t he A/ D conversi on process is complete, the ADBZ flag will go low and then the output data can be read from ADRH and ADRL registers. Note: When checking for the end of the conversion process, if the met hod of polling the ADBZ bit in the ADCR0 register is used, the interrupt enable step above can be omitted. However , the interrupt method must be used to check for the end of the conversion process and obtain the corresponding digital output data if the auto-conversion mode is enabled.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Programming Considerations During m icrocontroller ope rations where t he A/D c onverter i s not be ing used, t he A/D i nternal circuitry can be switched of f to reduce power consumption, by setting bit ADCEN low in the ADCR register. When this happens, the inte rnal A/D converter circuits will not consume power irrespective of what analog voltage is applied to their input lines. If the A /D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Converter Transfer Function As the devices contain a 12-bit A/D converter , its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the reference voltage, this gives a single bit analog input value of reference voltage value divided by 4096.

1 LSB = VREF ÷ 4096

The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage = A/D output digital value × VREF ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he A/ D conve rter. E xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 LSB below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 LSB below the VREF level. /G46/G46 /G45/G48 /G28 /G20/G20/G20/G20/G20/G20/G20/G20/G20/G29 /G41/G2F /G44/G20 /G43/G6F /G6E/G76 /G65/G72 /G73/G69 /G6F/G6E /G52/G65 /G73/G75 /G6C/G74 /G46/G46/G46/G48 /G46/G46 /G44/G48 /G30/G33 /G48 /G30/G32 /G48 /G30/G31 /G48 /G30/G2E /G35/G20 /G4C/G53 /G42 /G30/G31 /G32/G33 /G34/G30/G39 /G33 /G34/G30/G39 /G34/G34 /G30/G39 /G35/G34 /G30/G39 /G36 /G41/G6E /G61/G6C /G6F/G67/G20 /G49 /G6E/G70/G75 /G74/G20/G56 /G6F/G6C /G74 /G61/G67/G65 /G31/G2E /G35/G20 /G4C/G53 /G42 /G56 /G52/G45 /G46 /G34/G30/G39 /G36 Ideal A/D Transfer Function

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the ADCR register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an ADBZ polling method to detect the end of conversion clr ADE ; disable ADC interrupt set VREFP_EXT ; deselect the temperature sensor reference voltage mov a,03H ; select fSYS/8 as A/D clock and A/D internal power supply mov ADCR1,a ; as reference voltage set ADCEN mov a,03H ; setup PBS0 to configure pin AN0 mov PBS0,a mov a,20H mov ADCR0,a ; enable and connect AN0 channel to A/D converter start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D polling_EOC: sz ADBZ ; poll the ADCR0 register ADBZ bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register jmp start_conversion ; start next A/D conversion

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt set VREFP_EXT ; deselect the temperature sensor reference voltage mov a,03H ; select fSYS/8 as A/D clock and A/D internal power supply mov ADCR1,a ; as reference voltage set ADCEN mov a,03h ; setup PBS0 to configure pin AN0 mov PBS0,a mov a,20H mov ADCR0,a ; enable and connect AN0 channel to A/D converter Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE ; enable ADC interrupt set EMI ; enable global interrupt ADC_ISR: ; ADC interrupt service routine mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory mov a, ADRL ; read low byte conversion result value mov ADRL_buffer,a ; save result to user defined register mov a, ADRH ; read high byte conversion result value mov ADRH_buffer,a ; save result to user defined register EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four -line SPI interface or two-line I2C interface types, to allow an easy method of communication with external peripheral hardware. Ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory , etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM i nterface func tional pi ns m ust fi rst be se lected usi ng t he c orresponding pi n-shared func tion selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 registe r. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull- high control registers when the SIM function is enabled and the corresponding pins are used as SIM input pins. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or E EPROM m emory de vices, e tc. Ori ginally de veloped by Mot orola, t he four l ine SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the devices can be either mas ter or s lave. A lthough the S PI interface s pecification can control multiple s lave devices from a single master , these devices provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. I t i s a f our l ine i nterface wi th p in names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or enabled us ing the S IMEN bit in the S IMC0 regis ter. Communication betw een devices connected to t he SPI i nterface i s c arried out i n a sl ave/master m ode wi th a ll da ta t ransfer i nitiations be ing implemented by the master . The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. The SPI function in this device offers the following features:

Full duplex synchronous data transfer
Both Master and Slave modes
LSB first or MSB first data transmission modes
Transmission complete flag
Rising or falling active clock edge The status of the SPI interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN.

Rev. 1.40 170 Deee 1 01 Rev. 1.40 171 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G53/G50 /G49/G20/G4D /G61/G73/G74 /G65/G72 /G53/G50 /G49/G20/G53 /G6C /G61/G76/G65 /G53/G43 /G4B /G53/G44 /G4F /G53/G44 /G49 /G53/G43 /G53 /G53/G43 /G4B /G53/G44 /G49 /G53/G44 /G4F /G53/G43 /G53 SPI Master/Slave Connection /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G53/G44 /G49/G20/G50 /G69/G6E /G53/G44 /G4F/G20 /G50/G69 /G6E /G53/G49 /G4D/G44 /G54/G78 /G2F/G52 /G78/G20 /G53/G68 /G69/G66 /G74/G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G42/G75 /G73/G79 /G53/G74 /G61/G74 /G75/G73 /G54/G52 /G46/G20 /G46/G6C /G61/G67 /G57/G43 /G4F/G4C /G20/G46 /G6C/G61 /G67 /G43/G6C /G6F/G63 /G6B /G45/G64 /G67/G65 /G2F/G50 /G6F/G6C /G61/G72 /G69/G74 /G79 /G43/G6F /G6E/G74 /G72/G6F /G6C /G43/G6C /G6F/G63 /G6B /G53/G6F /G75/G72 /G63/G65 /G20/G53 /G65/G6C /G65/G63 /G74 /G66 /G53/G59 /G53 /G66 /G53/G55 /G42 /G53/G43 /G4B/G20 /G50/G69 /G6E /G53/G43 /G53/G20 /G50/G69 /G6E /G43/G53 /G45/G4E /G20/G62 /G69/G74 /G43/G4B /G45/G47 /G20/G62 /G69/G74 /G43 /G4B/G50/G4F /G4C/G42 /G20/G62 /G69/G74 /G43/G54 /G4D/G30 /G20/G43 /G43/G52/G50 /G20/G6D /G61/G74 /G63/G68 /G20/G66 /G72/G65 /G71 /G75/G65/G6E /G63/G79/G2F /G32 SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF SIMC D7 D CKPOLB CKEG MLS CSEN WCOL TRF SIMD D7 D D D4 D3 D D1 D0 SPI Registers List

SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register . After the data is received from the SPI bus, the device can read it from the SIMD register . Any transmission or reception of data from the SPI bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown

Rev. 1.40 170 Deee 1 01 Rev. 1.40 171 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI functio n, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmi ssion clock frequency . Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc.

SIMC0 Register Bit 7 6 5 4 3 2 1 0 Nae SIM SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF R/W R/W R/W R/W — R/W R/W R/W R/W POR 1 1 1 — 0 0 0 0 Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operatin g mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slav e selection and the SPI Master clock frequency . The SPI clock is a function of the system clock but can also be chosen to be sourced from CTM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce T ime Selection Described elsewhere. Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bi t is the overa ll on/of f control for the SIM interface. When the SIMEN bi t is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a mini mum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initiali sed by the applic ation program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: SIM SPI slave mode Incomplete T ransfer Flag 0: SIM SPI slave mode incomplete condition not occurred 1: SIM SPI slave mode incomplete condition occured This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operate s in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 togethe r with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However , the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program.

SIMC2 Register Bit 7 6 5 4 3 2 1 0 Nae D7 D CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bits These bits can be read or written by the application program. Bit 5 CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bi t de termines the ba se condition of the clock line, if the bi t is hi gh, then t he SCK l ine wi ll be l ow whe n t he c lock i s i nactive. W hen t he CKPOL B bi t i s low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. T he CKPOL B bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he SCK l ine will be low when the clock is inact ive. When the CKPOLB bit is low , then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit. Bit 3 MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low , then the SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the bit is high, the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SIMD register duting a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0 TRF: SPI T ransmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transfer is completed The TRF bit is the T ransmit/Receive Complete flag and is set to 1 automatically when an SPI data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt.

Rev. 1.40 17 Deee 1 01 Rev. 1.40 173 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SPI Communication After t he SPI i nterface i s e nabled by se tting t he SIME N bi t hi gh, t hen i n t he Ma ster Mode , whe n data is written to the SIMD register , transmission/reception will begin simultaneously . When the data t ransfer i s c omplete, t he T RF fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register . The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function even in the IDLE Mode. /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G2C/G20/G43 /G4B/G45/G47 /G3D/G30 /G29 /G53/G49 /G4D/G45 /G4E/G2C /G20/G43 /G53/G45 /G4E/G3D /G31 /G53/G49 /G4D/G45 /G4E/G3D /G31/G2C /G20/G43 /G53/G45/G4E /G3D/G30 /G20/G28 /G45/G78 /G74/G65 /G72/G6E /G61/G6C /G20/G50 /G75/G6C /G6C/G2D /G48/G69 /G67/G68 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G2C/G20 /G43/G4B /G45/G47 /G3D/G30 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G2C/G20 /G43/G4B /G45/G47 /G3D/G31 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G2C/G20 /G43/G4B /G45/G47 /G3D/G31 /G29 /G53/G44 /G4F/G20 /G28/G43 /G4B/G45/G47 /G3D/G30 /G29 /G53/G44 /G4F/G20 /G28/G43 /G4B/G45/G47 /G3D/G31 /G29 /G53/G43 /G53 /G53/G44 /G49/G20/G44 /G61/G74 /G61/G20 /G43 /G61/G70/G74 /G75/G72 /G65 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G57/G72 /G69/G74 /G65/G20 /G74/G6F /G20/G53 /G49/G4D /G44 SPI Master Mode Timing /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G29 /G53/G44 /G4F /G53/G43 /G53 /G53/G44 /G49/G20 /G44/G61 /G74/G61 /G20/G43 /G61/G70/G74 /G75/G72 /G65 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G57/G72 /G69/G74 /G65/G20 /G74/G6F /G20/G53 /G49/G4D /G44 /G28/G53 /G44/G4F /G20/G64 /G6F/G65 /G73/G20 /G6E/G6F/G74 /G20/G63 /G68/G61/G6E/G67/G65 /G20/G75 /G6E/G74 /G69/G6C /G20/G66 /G69/G72 /G73/G74 /G20/G53 /G43/G4B /G20 /G65/G64/G67/G65/G29 SPI Slave Mode Timing – CKEG = 0

Rev. 1.40 174 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G31 /G29 /G53/G43 /G4B/G20 /G28/G43 /G4B/G50/G4F /G4C/G42 /G3D/G30 /G29 /G53/G44 /G4F /G53/G43 /G53 /G53/G44 /G49/G20/G44 /G61/G74 /G61/G20 /G43 /G61/G70/G74 /G75/G72 /G65 /G44/G37 /G2F/G44 /G30/G44 /G36/G2F /G44/G31 /G44/G35 /G2F/G44 /G32/G44 /G34/G2F /G44/G33 /G44/G33 /G2F/G44 /G34/G44 /G32/G2F /G44/G35 /G44/G31 /G2F/G44 /G36/G44 /G30/G2F /G44/G37 /G57/G72 /G69/G74 /G65/G20 /G74/G6F /G20/G53 /G49/G4D /G44 /G28/G53 /G44/G4F /G20/G63 /G68 /G61/G6E/G67/G65/G73 /G20/G61 /G73/G20 /G73/G6F /G6F/G6E /G20/G61 /G73/G20 /G77/G72 /G69/G74 /G69 /G6E/G67/G20 /G6F /G63/G63/G75 /G72/G73 /G3B/G20 /G53/G44 /G4F/G20 /G69/G73 /G20/G66/G6C /G6F/G61 /G74/G69 /G6E/G67 /G20/G69 /G66/G20 /G53/G43 /G53/G3D /G31/G29 /G4E/G6F /G74/G65 /G3A/G46 /G6F/G72 /G20/G53 /G50/G49 /G20/G73 /G6C/G61 /G76/G65 /G20/G6D /G6F/G64/G65/G2C /G20/G69 /G66/G20 /G53/G49 /G4D /G45/G4E /G3D/G31 /G20/G61 /G6E/G64 /G20/G43 /G53/G45 /G4E/G3D /G30/G2C /G20/G53 /G50/G49 /G20/G69 /G73/G20 /G61/G6C /G77/G61 /G79/G73 /G20/G65 /G6E /G61/G62/G6C /G65/G64 /G61/G6E/G64/G20 /G69/G67 /G6E/G6F/G72 /G65/G73 /G20/G74 /G68/G65 /G20/G53 /G43/G53 /G20/G6C /G65/G76 /G65/G6C /G2E Note: For SPI slave mode, if SIMEN=1 and CSEN=0, the SPI is always enabled and ignores the SCS level. SPI Slave Mode Timing – CKEG = 1 /G53/G49 /G4D/G45 /G4E/G20 /G3D/G31 /G57/G72 /G69/G74 /G65/G20 /G44/G61 /G74/G61 /G69/G6E /G74/G6F /G20/G53 /G49/G4D /G44 /G57/G43 /G4F/G4C /G3D/G31 /G3F /G43/G6C /G65/G61 /G72/G20 /G57/G43 /G4F/G4C /G59 /G54/G72 /G61/G6E /G73/G6D /G69/G73 /G73/G69 /G6F/G6E /G63/G6F /G6D/G70 /G6C/G65 /G74 /G65/G64/G20 /G3F /G28/G54 /G52/G46 /G3D/G31 /G20/G3F /G29/G20 /G4E /G59 /G52 /G65/G61/G64 /G20/G44 /G61/G74 /G61 /G66/G72 /G6F/G6D /G20/G53 /G49/G4D /G44 /G43/G6C /G65/G61 /G72/G20 /G54/G52 /G46 /G54/G72 /G61/G6E /G73/G66 /G65/G72 /G46 /G69/G6E /G69/G73 /G68 /G65/G64/G3F /G4E /G59 /G45/G4E /G44 /G6D/G61 /G73/G74 /G65/G72 /G20/G6F /G72 /G73/G6C /G61/G76 /G65 /G3F /G4D/G61 /G73/G74 /G65/G72 /G53/G6C /G61/G76 /G65 /G41 /G41 /G53/G50/G49 /G20/G74/G72 /G61/G6E /G73/G66 /G65/G72 /G20 /G43 /G6F/G6E/G66 /G69 /G67/G75/G72 /G65/G20 /G43 /G4B/G50/G4F /G4C/G42 /G2C /G43/G4B /G45/G47 /G2C/G20/G43 /G53/G45/G4E /G20/G61 /G6E/G64 /G20/G4D /G4C/G53 /G20 /G53/G49 /G4D/G5B /G32/G3A /G30/G5D /G3D /G30/G30/G30 /G2C /G30/G30/G31/G2C /G30/G31/G30 /G2C/G30 /G31/G31/G20 /G6F/G72 /G20/G31 /G30/G30/G20 /G53/G49 /G4D/G5B /G32/G3A /G30/G5D /G3D /G31/G30/G31 /G4E SPI Transfer Control Flow Chart

Rev. 1.40 174 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors, EEPROM m emory e tc. Or iginally d eveloped b y Ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. /G44/G65 /G76/G69 /G63/G65 /G53/G6C /G61/G76 /G65 /G44/G65 /G76/G69 /G63/G65 /G4D/G61 /G73/G74 /G65/G72 /G44/G65 /G76/G69 /G63/G65 /G53/G6C /G61/G76 /G65 /G56/G44 /G44 /G53/G44 /G41 /G53/G43 /G4C I2C Master Slave Bus Connection I2C interface Operation The I2C serial interface is a two line interf ace, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two device s communicate with each other on the bidirectional I2C bus, one is known as the master de vice a nd one a s t he sl ave de vice. Bot h m aster a nd sl ave c an t ransmit a nd re ceive da ta, however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. /G49 /G32 /G43/G20 /G44/G61 /G74/G61 /G20/G52 /G65/G67/G69 /G73/G74 /G65/G72 /G28/G53 /G49/G4D /G44/G29 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G28/G53 /G49/G4D /G41/G29 /G53/G68 /G69/G66 /G74/G20 /G52/G65 /G67/G69 /G73/G74 /G65/G72 /G44/G69 /G72/G65 /G63/G74 /G69/G6F /G6E/G20 /G43/G6F /G6E/G74 /G72/G6F /G6C /G4D /G55 /G58 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G4D/G61 /G74/G63 /G68/G20 /G48 /G41/G41/G53 /G49 /G32 /G43/G20 /G49/G6E /G74/G65 /G72/G72 /G75/G70 /G74 /G44/G61 /G74/G61 /G20/G69 /G6E/G20 /G44/G61 /G74/G61 /G20/G4F /G75/G74 /G20 /G54/G72 /G61/G6E /G73/G6D /G69/G74 /G2F/G52 /G65/G63 /G65/G69 /G76/G65 /G43/G6F /G6E/G74 /G72/G6F /G6C/G20 /G55/G6E /G69/G74 /G38/G2D /G62/G69 /G74/G20/G44 /G61/G74 /G61/G20 /G43/G6F /G6D/G70 /G6C/G65 /G74/G65 /G44/G65 /G74/G65 /G63 /G74/G20/G53 /G74/G61 /G72/G74 /G20/G6F /G72/G20 /G53/G74 /G6F/G70 /G44/G61 /G74/G61 /G20/G42 /G75/G73 /G41/G64 /G64/G72 /G65/G73 /G73 /G43/G6F /G6D/G70 /G61/G72 /G61/G74 /G6F/G72 /G54/G58 /G41/G4B /G52/G65 /G61/G64 /G2F/G77 /G72/G69 /G74/G65 /G20/G53 /G6C/G61 /G76/G65 /G53/G52 /G57/G20 /G42/G69 /G74 /G48 /G42/G42/G20 /G42/G69 /G74 /G48/G54 /G58/G20 /G42/G69 /G74 /G48/G43 /G46/G20 /G42/G69 /G74 /G44 /G65/G62/G6F/G75/G6E /G63/G65 /G43/G69 /G72/G63 /G75/G69 /G74/G72 /G79 /G53/G43 /G4C/G20 /G50/G69 /G6E /G53/G44 /G41/G20 /G50/G69 /G6E /G66 /G53/G59 /G53 /G53/G49 /G4D/G54 /G4F /G46 /G53/G49 /G4D/G44 /G45/G42 /G31 /G26 /G53/G49 /G4D/G44 /G45/G42 /G30 /G54/G69 /G6D/G65 /G2D/G6F /G75/G74 /G43 /G6F/G6E/G74 /G72/G6F /G6C /G53/G49 /G4D/G54 /G4F /G45/G4E /G66 /G53/G55 /G42 /G53/G49 /G4D/G54 /G4F /G46 /G41 /G64/G64/G72 /G65/G73 /G73/G20 /G4D/G61 /G74/G63 /G68

Rev. 1.40 17 Deee 1 01 Rev. 1.40 177 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G53/G54 /G41/G52 /G54/G20 /G73/G69 /G67/G6E/G61/G6C /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G53/G65 /G6E/G64 /G20/G73 /G6C/G61 /G76/G65 /G20 /G61/G64/G64 /G72/G65 /G73/G73 /G61/G6E/G64/G20 /G52/G2F /G57/G20 /G62/G69 /G74/G20/G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G41 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65 /G66/G72 /G6F/G6D /G20/G73 /G6C/G61 /G76/G65 /G53 /G65/G6E/G64/G20 /G64/G61/G74 /G61/G20 /G62/G79 /G74/G65 /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 /G41 /G63/G6B /G6E/G6F/G77 /G6C /G65/G64/G67 /G65 /G66/G72 /G6F/G6D /G20/G73 /G6C/G61 /G76/G65 /G53/G54 /G4F/G50 /G20/G73 /G69/G67 /G6E/G61 /G6C /G66/G72 /G6F/G6D /G20/G4D /G61/G73 /G74/G65 /G72 The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. T he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. T o achieve the required I2C data trans fer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Devoune fSYS > MHz fSYS > MHz syste lok deoune fSYS > 4 MHz fSYS > 10 MHz 4 syste lok deoune fSYS > 8 MHz fSYS > 0 MHz I2C Minimum fSYS Frequency I2C Registers There are three control registers associated with the I2C bus, SIMC0, SIMC1 and SIMA, and one data register , SIMD. The SIMD register , which is shown in the above SPI section, is used to store the data being transmitted and received on the I2C bus. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interface. Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMA IICA IICA IICA4 IICA3 IICA IICA1 IICA0 D0 SIMD D7 D D D4 D3 D D1 D0 SIMTOC SIMTOEN SIMTOF SIMTOS SIMTOS4 SIMTOS3 SIMTOS SIMTOS1 SIMTOS0 I2C Registers List

SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by bot h t he SPI a nd I2C fun ctions. Be fore t he de vice wri tes da ta t o t he I2C bus, t he a ctual da ta t o be transmitted must be placed in the SIMD register . After the data is received from the I2C bus, the device can read it from the SIMD register . Any transmission or reception of data from the I2C bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown
SIMA Register The SIMA registe r is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not defined. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register , the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 7 6 5 4 3 2 1 0 Nae IICA IICA IICA4 IICA3 IICA IICA1 IICA0 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~1 IICA6~IICA0: I2C slave address IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0 Bit 0 Undefined bit The bit can be read or written by the application program. There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0 is use d t o c ontrol t he e nable/disable func tion a nd t o se t t he da ta t ransmission c lock fre quency.The SIMC1 register contains the relevant flags which are used to indicate the I2C communication status.
SIMC0 Register Bit 7 6 5 4 3 2 1 0 Nae SIM SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF R/W R/W R/W R/W — R/W R/W R/W R/W POR 1 1 1 — 0 0 0 0 Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is CTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operatin g mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slav e selection and the SPI Master clock frequency . The SPI clock is a function of the system clock but can also be chosen to be sourced from TM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device.

Rev. 1.40 178 Deee 1 01 Rev. 1.40 179 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce T ime Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bi t is the overa ll on/of f control for the SIM interface. When the SIMEN bi t is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a mini mum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initiali sed by the applic ation program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: SIM SPI slave mode Incomplete T ransfer Flag Described elsewhere.

SIMC1 Register Bit 7 6 5 4 3 2 1 0 Nae HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R/W R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus data transfer completion flag 0: Not address match 1: Address match The HAAS fla g i s t he a ddress m atch fla g. T his fla g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. T his flag will be "1" when the I2C bus is busy which will occur when a ST ART signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: I2C slave device transmitter/receiver selection 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received.

Rev. 1.40 178 Deee 1 01 Rev. 1.40 179 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 SRW: I2C slave read/write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SR W f lag i s t he I2C Sl ave R ead/Write f lag. T his f lag d etermines wh ether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SR W flag to determine whether it should be in transmit mode or receive mode. If the SR W flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SR W flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match W ake-Up control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to 1 to enabl e the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0 RXAK: I2C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The R XAK f lag i s t he r eceiver a cknowledge f lag. W hen t he R XAK f lag i s "0 ", i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. T he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. I2C Bus Communication Communication on the I2C bus requires four separate steps, a ST ART signal, a slave device address transmission, a data transmission and finally a ST OP signal. When a ST ART signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMT OF bits to determine whether t he i nterrupt sou rce o riginates fr om a n a ddress m atch, 8 -bit d ata t ransfer c ompletion o r I2C bus time-out occurrence. During a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus, the following are steps to achieve this:

Step 1 Set the SIM2~SIM 0 bits to "1 10" and SIMEN bit to "1" in the SIMC0 register to enable the I2C bus.
Step 2 Write the slave address of the device to the I2C bus address register SIMA.
Step 3 Set the SIME and SIM Muti-Function interrupt enable bit of the interrupt control register to enable the SIM interrupt and Multi-function interrupt.

Rev. 1.40 180 Deee 1 01 Rev. 1.40 181 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G53/G74 /G61/G72 /G74 /G20/G20 /G57/G72 /G69/G74 /G65/G20 /G53/G6C /G61/G76 /G65 /G20/G20 /G41/G64 /G64/G72 /G65/G73 /G73/G20 /G74/G6F /G20/G53 /G49/G4D /G41 /G53/G45 /G54/G20 /G53/G49 /G4D/G5B /G32/G3A /G30/G5D /G3D/G31 /G31/G30 /G53/G45 /G54/G20 /G53/G49 /G4D/G45 /G4E /G20/G20/G20/G49 /G32 /G43/G20 /G42/G75 /G73 /G49/G6E /G74/G65 /G72/G72 /G75/G70/G74 /G3D/G3F /G20 /G45/G6E /G61/G62/G6C /G65 /G44/G69 /G73 /G61/G62/G6C /G65 /G53/G45 /G54/G20 /G53/G49 /G4D/G45 /G20/G61 /G6E/G64 /G20/G4D /G46/G6E /G45 /G57/G61 /G69/G74 /G20/G66/G6F /G72/G20 /G49/G6E /G74/G65 /G72/G72/G75 /G70/G74 /G47/G6F /G74/G6F /G20/G4D /G61/G69 /G6E/G20 /G50/G72 /G6F/G67/G72 /G61/G6D /G43/G4C /G52/G20 /G53/G49 /G4D/G45 /G20 /G50/G6F /G6C/G6C/G20 /G53/G49 /G4D/G46 /G20/G74/G6F /G20/G64 /G65/G63 /G69/G64 /G65/G20 /G77/G68 /G65/G6E /G20/G74 /G6F/G20 /G67/G6F /G20/G74 /G6F/G20 /G49 /G32 /G43/G20 /G42/G75 /G73 /G20/G49/G53 /G52/G20 /G47/G6F /G74/G6F /G20/G4D /G61/G69 /G6E/G20 /G50/G72 /G6F/G67/G72 /G61/G6D I2C Bus Initialisation Flow Chart

I2C Bus Start Signal The ST ART signal can only be generated by the master device connected to the I2C bus and not by the slave device. This ST ART signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A ST ART condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high.
I2C Slave Address The t ransmission o f a ST ART si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he I2C b us. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the ST ART signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SR W bit of the SIMC1 register . The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As a n I2C bus i nterrupt c an c ome fro m t hree sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the HAAS and SIMT OF bits should be examined to see whether the interrupt source has come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out occurrence. When a slave address is matched, the devices must be placed in either the transmit mode and then write data to the SIMD register , or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line.

I2C Bus Read/Write Signal The SR W bit in the SIMC1 registe r defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should examine this bit to determine if it is to be a transmitter or a receiver . If the SR W flag is "1" then this indicates that the master device wishes to read data from the I2C bus, therefore the slave device must be setup to send data to the I2C bus as a transmitter . If the SR W flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.
I2C Bus Slave Address Acknowledge Signal After the mas ter has trans mitted a calling addres s, any s lave device on the I2C bus , w hose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a ST OP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SR W flag to determine if it is to be a transmitter or a receiver . If the SR W flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SR W flag is low , then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0".
I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. T he o rder o f se rial b it t ransmission i s t he MSB fir st a nd t he L SB l ast. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the SDA line to allow the master to send a ST OP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter , the slave device must first write the data to be transmitted into the SIMD register . If setup as a receive r, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmi tter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master.

Rev. 1.40 18 Deee 1 01 Rev. 1.40 183 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver /G44/G61 /G74/G61 /G31/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30 /G30 /G31 /G30 /G30/G31/G30/G31/G30 /G31 /G31 /G53/G3D /G53/G74 /G61/G72 /G74/G20/G28 /G31/G20 /G62/G69 /G74/G29 /G53/G41 /G3D/G53 /G6C/G61 /G76/G65 /G20/G41 /G64/G64 /G72/G65 /G73/G73 /G20/G28 /G37/G20 /G62/G69 /G74/G73 /G29 /G53/G52 /G3D/G53 /G52/G57 /G20/G62 /G69/G74 /G20/G28 /G31/G20 /G62/G69 /G74/G29 /G4D/G3D /G53/G6C /G61/G76 /G65/G20 /G64/G65 /G76/G69 /G63/G65 /G20/G73 /G65/G6E/G64/G20 /G61 /G63/G6B/G6E /G6F/G77 /G6C/G65 /G64/G67/G65/G20 /G62/G69 /G74/G20 /G28/G31 /G20/G62 /G69/G74 /G29 /G44/G3D /G44/G61 /G74/G61 /G20/G28 /G38/G20 /G62/G69 /G74/G73 /G29 /G41/G3D /G41/G43 /G4B /G20/G28 /G52/G58 /G41/G4B /G20/G62 /G69/G74 /G20/G66 /G6F/G72 /G20/G74/G72 /G61/G6E /G73/G6D /G69 /G74/G74/G65 /G72/G2C /G20/G54 /G58/G41/G4B /G20/G62 /G69/G74 /G20/G66/G6F /G72/G20 /G72/G65 /G63/G65 /G69/G76 /G65/G72 /G20/G31 /G20/G62 /G69/G74 /G29 /G50/G3D /G53/G74 /G6F/G70 /G20/G28 /G31/G20 /G62/G69 /G74/G29 /G53/G43 /G4C /G53/G74 /G61/G72 /G74 /G53/G44 /G41 /G53/G52 /G57 /G41/G43 /G4B /G41/G43 /G4B /G53/G74 /G6F/G70 /G53/G43 /G4C /G53/G44 /G41 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73 /G53/G53 /G41/G53 /G52 /G4D/G44 /G41/G44 /G41 /G53/G53 /G41/G53 /G52 /G4D/G44 /G41/G44 /G41/G50 Note: * When a slave address is matched, the device must be placed in either the transmit mode and then write data to the SIMD register , or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram /G48/G54 /G58/G3D /G31/G20 /G3F /G53/G52 /G57/G3D /G31/G20 /G3F /G59/G65 /G73 /G4E/G6F /G52/G58 /G41/G4B/G3D /G31 /G3F /G59/G65 /G73 /G4E/G6F /G4E/G6F /G52 /G65/G61/G64 /G20/G66/G72 /G6F/G6D /G53/G49 /G4D/G44 /G20/G74 /G6F/G20 /G72/G65 /G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G6C/G69/G6E /G65 /G52/G45 /G54/G49 /G59/G65 /G73 /G44/G75 /G6D/G6D /G79/G20 /G72 /G65/G61/G64/G20 /G66/G72 /G6F/G6D /G53/G49 /G4D/G44 /G20/G74 /G6F/G20 /G72/G65 /G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G52/G45 /G54/G49 /G52/G45 /G54/G49 /G57/G72 /G69/G74 /G65/G20 /G64/G61 /G74/G61 /G20/G74 /G6F/G20 /G53/G49 /G4D/G44 /G72/G65 /G6C /G65/G61/G73 /G65/G20 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G53/G45 /G54/G20 /G48/G54 /G58 /G57/G72 /G69/G74 /G65/G20 /G64/G61 /G74/G61 /G20/G74 /G6F/G20 /G53/G49 /G4D/G44 /G74/G6F /G20/G72 /G65/G6C /G65/G61 /G73/G65 /G20/G53 /G43/G4C /G20/G4C /G69/G6E /G65 /G52/G45 /G54/G49 /G43/G4C /G52/G20 /G48/G54 /G58 /G43/G4C /G52/G20 /G54 /G58/G41/G4B /G53/G74 /G61/G72 /G74 /G44/G75 /G6D/G6D /G79/G20 /G72 /G65/G61/G64/G20 /G66/G72 /G6F/G6D /G53/G49 /G4D/G44 /G20/G74/G6F /G20/G72 /G65/G6C /G65/G61/G73 /G65 /G53/G43 /G4C/G20 /G4C/G69 /G6E/G65 /G43/G4C /G52/G20 /G48/G54 /G58 /G43/G4C /G52/G20 /G54 /G58/G41/G4B /G52/G45 /G54/G49 /G48/G41 /G41/G53 /G3D/G31 /G3F /G59/G65 /G73 /G4E/G6F /G53/G49 /G4D/G54 /G4F/G46 /G3D/G31 /G20/G3F /G59/G65 /G73 /G4E/G6F /G53/G45 /G54/G20 /G53/G49 /G4D/G54 /G4F/G45 /G4E /G43/G4C /G52/G20 /G53/G49 /G4D/G54 /G4F/G46 /G52/G45 /G54/G49 I2C Bus ISR Flow Chart

Rev. 1.40 18 Deee 1 01 Rev. 1.40 183 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver I2C Time-out Control In order to reduce the I2C lockup problem due to reception of erroneous clock s ources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry and registers will be reset after a certain time-out period. The time-out counter starts to count on an I2C bus "ST ART" & "address match"c ondition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMT OC register , then a time-out condition will occur . The time-out function will stop when an I2C "STOP" condition occurs. /G49/G20 /G43/G20 /G74/G69 /G6D/G65 /G2D /G6F/G75/G74 /G63 /G6F/G75/G6E /G74/G65 /G72/G20 /G73/G74 /G61/G72 /G74 /G49/G20 /G43/G20 /G74/G69 /G6D/G65 /G2D /G6F/G75/G74 /G20/G63 /G6F/G75/G6E /G74/G65 /G72/G20 /G72/G65 /G73/G65 /G74 /G6F/G6E/G20 /G53/G43 /G4C/G20 /G6E/G65/G67/G61/G74 /G69/G76 /G65 /G20/G74/G72 /G61/G6E/G73 /G69/G74 /G69/G6F /G6E /G31/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30/G30 /G31/G20 /G20/G20/G20/G20/G20/G20 /G30 /G30 /G31 /G30 /G30/G31/G30/G31/G30 /G31 /G31 /G53/G43 /G4C /G53/G74 /G61/G72 /G74 /G53/G44 /G41 /G49/G49 /G43/G53 /G52/G57 /G41/G43 /G4B /G53/G74 /G6F/G70 /G53/G43 /G4C /G53/G44 /G41 /G53/G6C /G61/G76 /G65/G20 /G41/G64 /G64/G72 /G65/G73 /G73 /G32 /G32 I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and the SIMT OEN bit will be c leared t o z ero a nd t he SIMT OF bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. The time-out condition will also generate an interrupt which uses the I2C interrrupt vector . When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out SIMD SIMA SIMC0 No hange SIMC1 Reset to POR ondition I2C Register after Time-out The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections which can be selected using the SIMT OS bits in the SIMT OC register . The time-out duration is calculated by the formula: ((1~64) × (32/fSUB)). This gives a time-out period which ranges from about 1ms to 64ms.

SIMTOC Register Bit 7 6 5 4 3 2 1 0 Nae SIMTOEN SIMTOF SIMTOS SIMTOS4 SIMTOS3 SIMTOS SIMTOS1 SIMTOS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SIMTOEN: SIM I2C T ime-out control 0: Disable 1: Enable Bit 6 SIMTOF: SIM I2C T ime-out flag 0: No time-out occurred 1: T ime-out occurred Bit 5~0 SIMTOS5~SIMTOS0: SIM I2C T ime-out period selection I2C T ime-out clock source is fSUB/32 I2C T ime-out period is equal to [ ]( ) SUBf 321 0 : 5SIMTOS × + UART Interface These devices contain an integrated full-duplex asynchronous serial communications UAR T interface t hat e nables c ommunication wi th e xternal de vices t hat c ontain a se rial i nterface. T he UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is overwri tten or i ncorrectly fra med. The UAR T funct ion possesse s it s own i nternal int errupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features:
Full-duplex, asynchronous communication
8 or 9 bits character length
Even, odd or no parity options
One or two stop bits
Baud rate generator with 8-bit prescaler
Parity, framing, noise and overrun error detection
Support for interrupt on address detect (last character bit=1)
Separately enabled transmitter and receiver
2-byte Deep FIFO Receive Data Buffer
RX pin wake-up function
T ransmit and receive interrupts
Interrupts can be initialized by the following conditions: ♦ Transmitter Empty ♦ Transmitter Idle ♦ Receiver Full ♦ Receiver Overrun ♦ Address Mode Detect

Rev. 1.40 184 Deee 1 01 Rev. 1.40 18 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Tansitte Shift Registe (TSR) Reeive Shift Registe (RSR) TX Pin RX Pin Baud Rate Geneato TX Registe (TXR) RX Registe (RXR) Data to e tansitted Data eeived BuffefSYS MCU Data Bus UART Data Transfer Block Diagram UART External Pin To communicate with an external serial interface, the internal UAR T has two external pins known as TX and RX. The TX and RX pins are the UAR T transmitter and receiver pins respectively . The TX and RX pin function should first be selected by the corresponding pin-shared function selection register before the UAR T function is used. Along with the UAR TEN bit, the TXEN and RXEN bits, if set, will automatically setup these I/O or other pin-shared functional pins to their respective TX output a nd RX i nput c onditions a nd di sable a ny pu ll-high re sistor op tion whi ch m ay e xist on t he TX and RX pins. When the TX or RX pin function is disabled by clearing the UAR TEN, TXEN or RXEN b it, t he T X o r R X p in wi ll b e se t t o a flo ating st ate. At t his t ime wh ether t he i nternal p ull- high resistor is connected to the TX or RX pin or not is determined by the corresponding I/O pull- high function control bit. UART Data Transfer Scheme The a bove di agram shows t he ove rall da ta t ransfer st ructure a rrangement for t he UAR T i nterface. The a ctual da ta t o be t ransmitted from t he MCU i s fi rst t ransferred t o t he T XR re gister by t he application program. The data will then be transferred to the T ransmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator . Only the TXR register is mapped onto the MCU Data Memory , the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UAR T is accepted on the external RX pin, from where it is shifted in, LSB fi rst, t o t he Re ceiver Shi ft Re gister a t a ra te c ontrolled by t he Ba ud Ra te Ge nerator. W hen the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buf fered and can be manipulated by the application program. Only the TXR register i s m apped ont o t he MCU Dat a Me mory, t he Re ceiver Shi ft Re gister i s not m apped a nd i s therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory . This shared register known as the TXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UAR T function. The USR, UCR1 and UCR2 registers c ontrol t he o verall f unction o f t he UAR T, wh ile t he B RG r egister c ontrols t he B aud r ate. The actua l data to be transmitted and received on the serial interface is managed through the TXR_ RXR data registers.

Rev. 1.40 18 Deee 1 01 Rev. 1.40 187 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TXR_RXR Register The TXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Bit 7 6 5 4 3 2 1 0 Nae TXRX7 TXRX TXRX TXRX4 TXRX3 TXRX TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 TXRX7~TXRX0: UART Transmit/Receive Data bits USR Register The USR r egister i s t he st atus r egister f or t he UAR T, wh ich c an b e r ead b y t he p rogram t o determine the present status of the UAR T. All flags within the USR register are read only and further explanations are given below. Bit 7 6 5 4 3 2 1 0 Nae PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7 PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the RXR data register. Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF fla g is the noise fla g. Whe n thi s read only fla g is "0", it indi cates no noise condition. When the flag is "1", it indicates that the UAR T has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The N F flag can be cleared by a softw are sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 5 FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error . When the flag is " 1", it indicates that a framing error has been detected for the current character . The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the RXR data register. Bit 4 OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the rece iver buf fer has overflowed. When this read only flag is "0", it indicates that there is no overrun error . When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the RXR receive data register . The flag is cleared by a software sequence, which is a read to the s tatus regis ter U SR follow ed by an acces s to the RX R data register.

Rev. 1.40 18 Deee 1 01 Rev. 1.40 187 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 3 RIDLE: Receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the init ial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. Bit 2 RXIF: Receive RXR data register status 0: RXR data register is empty 1: RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it indicates that the RXR read data register is empty . When the flag is "1", it indicates that t he R XR r ead d ata r egister c ontains n ew d ata. W hen t he c ontents o f t he sh ift register are trans ferred to the RX R register , an interrupt is generated if RIE=1 in the UCR2 register . If one or more errors are detected in the received word, the appropriate receive-related flags NF , FERR, and/or PERR are set within the same clock cycle. The RXIF flag is clear ed when the USR register is read with RXIF set, followed by a read from the RXR register, and if the RXR register has no data available. Bit 1 TIDLE: T ransmission status 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) The TIDLE flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set to "1" when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR register . The flag is not generated when a data character or a break is queued and ready to be sent. Bit 0 TXIF: T ransmit TXR data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (TXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicat es that the character is not transferred to the transmitter shift register . When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR data register . The TXIF flag is cleared by reading the UAR T status register (USR) with TXIF set and then writing to the TXR data register . Note that when t he T XEN b it i s se t, t he T XIF fla g b it wi ll a lso b e se t si nce t he t ransmit d ata register is not yet full.

Rev. 1.40 188 Deee 1 01 Rev. 1.40 189 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver UCR1 Register The UCR1 register together with the UCR2 register are the UAR T control registers that are used to set the various options for the UAR T function such as overall on/of f control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Nae UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 x 0 "x": unknown Bit 7 UARTEN: UART function enable control 0: Disable UART; TX and RX pins are in a floating state. 1: Enable UART; TX and RX pins function as UART pins The UAR TEN bit is the UAR T enable bit. When this bit is equal to "0", the UAR T will be disabled and the RX pin as well as the TX pin will be set in a floating state. When the bit is equal to "1", the UAR T will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UAR T is disabled, it will empty the buf fer so any character remaining in the buf fer will be discarded. In addition, the value of the baud rate counter will be reset. If the UAR T is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF, OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaf fected. If the UAR T is active and the UAR TEN bit is clear ed, all pending transmissions and re ceptions wi ll be terminated a nd t he module will be reset as defined above. When the UART is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Bit 5 PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This bit is the parity function enable bit. When this bit is equal to 1, the parity function will be enabled. If the bit is equal to 0, then the parity function will be disabled. Bit 4 PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will be selected. If the bit is equal to 0, then even parity type will be selected. Bit 3 STOPS: Number of stop bits selection 0: One stop bit format is used 1: T wo stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to "1", two stop bits format are used. If the bit is equal to "0", then only one stop bit format is used. Bit 2 TXBRK: Transmit break character 0: No break character is transmitted 1: Break characters transmit The T XBRK bi t i s t he T ransmit Bre ak Cha racter bi t. W hen t his bi t i s e qual t o "0", there are no break characters and the TX pin operats normally . When the bit is equal to "1", there are transmit break characters and the transmitter will send logic zeros. When this bit is equal to "1", after the buf fered data has been transmitted, the transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset.

Rev. 1.40 188 Deee 1 01 Rev. 1.40 189 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the receive d data known as RX8. The BNO bit is used to determ ine whether data transfes are in 8-bit or 9-bit format. Bit 0 TX8: Transmit data bit 8 for 9-bit data transfer format (write only) This bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfes are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the UAR T control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UAR T T ransmitter and Receiver as well as enabling the various UAR T interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Nae TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN: UART T ransmitter enable control 0: UART T ransmitter is disabled 1: UART T ransmitter is enabled The TXEN bit is the T ransmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buf fers will be reset. In this situation the TX pin will be set in a floating state. I f t he T XEN b it i s e qual t o "1 " a nd t he UAR TEN b it i s a lso e qual t o 1 , t he transmitter will be enabled and the TX pin will be controlled by the UAR T. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter . If this situation occurs, the TX pin will be set in a floating state. Bit 6 RXEN: UART Receiver enable control 0: UART Receiver is disabled 1: UART Receiver is enabled The RXEN bit is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receiver buf fers will be reset. In this situation the RX pin will be set in a floating state. If the RXEN bit is equal to "1" and the UAR TEN bit is also equal to 1, the receiver will be enabled and the RX pin will be controlled by the UAR T. Clea ring the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. If this situation occurs, the RX pin will be set in a floating state. Bit 5 BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator . This bit, together w ith the value placed in the baud rate regis ter, BRG , controls the baud rate of the UART. If the bit is equal to 0, the low speed mode is selected.

Rev. 1.40 190 Deee 1 01 Rev. 1.40 191 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 4 ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detection function enable control bit. When this bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, ha s a va lue of "1 ", t hen t he re ceived word wi ll be i dentified a s a n a ddress, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3 WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up function is disabled 1: RX pin wake-up function is enabled The bit enables or disables the rece iver wake-up function. If this bit is equal to 1 and the device is in IDLE0 or SLEEP mode, a falling edge on the RX pin will wake up the device. If this bit is equal to 0 and the device is in IDLE or SLEEP mode, any edge transitions on the RX pin will not wake up the device. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled The bit enables or disables the rece iver interrupt. If this bit is equal to 1 and when the receiver overrun flag OERR or received data available flag RXIF is set, the UAR T interrupt request flag will be set. If this bit is equal to 0, the UAR T interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1 TIIE: Transmitter Idle interrupt enable control 0: T ransmitter idle interrupt is disabled 1: T ransmitter idle interrupt is enabled The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and when t he t ransmitter i dle fla g T IDLE i s se t, due t o a t ransmitter i dle c ondition, t he UART interrupt request flag will be set. If this bit is equal to 0, the UAR T interrupt request flag will not be influenced by the condition of the TIDLE flag. Bit 0 TEIE: Transmitter Empty interrupt enable control 0: T ransmitter empty interrupt is disabled 1: T ransmitter empty interrupt is enabled The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and when the transmit ter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UAR T interrupt request flag will not be influenced by the condition of the TXIF flag.

Rev. 1.40 190 Deee 1 01 Rev. 1.40 191 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Baud Rate Generator To setup the speed of the serial data communication, the UAR T function contains its own dedicated baud ra te ge nerator. T he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period o f wh ich i s d etermined b y t wo f actors. T he f irst o f t hese i s t he v alue p laced i n t he B RG register and the second is the value of the BRGH bit within the UCR2 control register . The BRGH bit decides, if the baud rate generat or is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register , N, which is used in the following baud rate calculation formula determines the division factor . Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) )]1N (64[ fSYS + )]1N (16[ fSYS By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register , the required baud rate can be setup. Note that because the actual baud rate is determ ined using a discrete value, N, placed in the BRG register , there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Bit 7 6 5 4 3 2 1 0 Nae BRG7 BRG BRG BRG4 BRG3 BRG BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR x x x x x x x x "x": unknown Bit 7~0 BRG7~BRG0: Baud Rate values By programming the BRGH bit in the UCR2 register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup. Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR = )]1N (64[ fSYS Re-arranging this equation gives N = 1)64BR( fSYS −× Giving a value for N = 0208.121)644800( 4000000 = −× To obtain the closest value, a decim al value of 12 should be placed into the BRG register . This gives an actual or calculated baud rate value of BR= 4808)]112(64[ 4000000 =+ Therefore the error is equal to 4800 48004808− = 0.16%

Rev. 1.40 19 Deee 1 01 Rev. 1.40 193 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver UART Setup and Control For data transfer , the UAR T functio n utilizes a non-return-to-zero, more commonly known as NRZ, format. This is compos ed of one s tart bit, eight or nine data bits and one or two s top bits . P arity is supporte d by t he UAR T hardwa re and ca n be se tup t o be eve n, odd or no pari ty. For the m ost common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setti ng, which is the setting at power -on. The number of data bits and stop bits, along with the parity , are setup by programming the corresponding BNO, PR T, PREN and ST OPS bits in the UCR1 register . The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/of f function of the internal UAR T function is controlled using the UAR TEN bit in the UCR1 register . If the UAR TEN, TXEN and RXEN bits are set, then these two UAR T pins will act as n ormal T X o utput p in a nd R X i nput p in r espectively. I f n o d ata i s b eing t ransmitted o n t he T X pin, then it will default to a logic high value. Clearing t he UAR TEN b it wi ll d isable t he T X a nd R X p ins a nd t hese t wo p ins wi ll b e u sed a s a n I/O or other pin-shared functional pin. When the UAR T function is disabled, the buf fer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UART will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF, OE RR, FE RR, PE RR and NF bei ng c leared whi le bi ts T IDLE, T XIF and RIDL E wi ll be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaf fected. If the UAR TEN bit in the UCR1 regi ster is cl eared while the UAR T is act ive, then all pendi ng transmissions and receptions will be immediately suspended and the UAR T will be reset to a condition as defined above. If the UAR T is then subsequently re-enabled, it will restart again in the same configuration. Data, Parity and Stop Bit Selection The f ormat o f t he d ata t o b e t ransferred i s c omposed o f v arious f actors su ch a s d ata b it l ength, parity on/of f, parity type, address bits and the number of stop bits. These factors are determined by the setup of various bits within the UCR1 register . The BNO bit controls the number of data bits which can be set to either 8 or 9. The PR T bit controls the choice if odd or even parity . The PREN bit controls the parity on/of f function. The ST OPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address detect mode control bit identifi es the frame as an address character . The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bit Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format

Rev. 1.40 19 Deee 1 01 Rev. 1.40 193 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. /G53/G74 /G61/G72 /G74/G20 /G42/G69 /G74 /G42/G69 /G74/G20/G30 /G42/G69 /G74/G20 /G31 /G42/G69 /G74/G20/G32 /G42/G69 /G74/G20/G33 /G42/G69 /G74/G20 /G34 /G42/G69 /G74/G20/G35 /G42/G69 /G74/G20/G36 /G42/G69 /G74/G20 /G37 /G53/G74 /G6F/G70/G20 /G42/G69 /G74 /G4E/G65 /G78/G74 /G53/G74 /G61/G72 /G74 /G42/G69 /G74 /G50/G61 /G72/G69 /G74/G79 /G20/G42 /G69/G74 8-Bit Data Format /G53/G74 /G61/G72 /G74/G20 /G42/G69 /G74 /G42/G69 /G74/G20/G30 /G42/G69 /G74/G20/G31 /G42/G69 /G74/G20 /G32 /G42/G69 /G74/G20/G33 /G42/G69 /G74/G20/G34 /G42/G69 /G74/G20 /G35 /G42/G69 /G74/G20/G36 /G42/G69 /G74/G20/G37 /G53/G74 /G6F/G70/G20 /G42/G69 /G74 /G4E/G65 /G78/G74 /G53/G74 /G61/G72 /G74 /G42/G69 /G74 /G42/G69 /G74/G20 /G38 /G50/G61 /G72/G69 /G74/G79 /G20/G42 /G69/G74 9-Bit Data Format UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. W hen B NO b it i s se t, t he wo rd l ength wi ll b e se t t o 9 b its. I n t his c ase t he 9th b it, wh ich is the MSB, needs to be stored in the TX8 bit in the UCR1 register . At the transmitter core lies the Transmitter Shift Register , more commonly known as the TSR, whos e data is obtained from the transmit d ata r egister, wh ich i s k nown a s t he T XR r egister. T he d ata t o b e t ransmitted i s l oaded into this TXR register by the applic ation program. The TSR register is not written to with new data until the stop bit from the previous transmission has been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR register , if it is available. It should be noted that the TSR register , unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXEN bit is set, but the data will not be transmitted until the TXR register has been loaded with data and the baud rate generator ha s de fined a shi ft c lock sourc e. However , t he t ransmission c an a lso be i nitiated by first loading data into the TXR register , after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empty , in which case a transfer to the TXR register will result in an immed iate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will imm ediately cease and the transmitter will be reset. The TX output pin will then return to the I/ O or other pin-shared function. Transmitting Data When the UAR T is transmitting data, the data is shifted on the TX pin from the shift register , with the least significant bit LSB first. In the transmit mode, the TXR register forms a buf fer between the internal bus and the transmitter shift register . It should be noted that if 9-bit data format has been selected, then the MSB will be take n from the TX8 bit in the UCR1 register . The steps to initiate a data transfer can be summarized as follows:

Make the correct selection of the BNO, PR T, PREN and ST OPS bits to define the required word length, parity type and number of stop bits.
Setup the BRG register to select the desired baud rate.
Set the TXE N bit to ensure that the UAR T transmit ter is enabled and the TX pin is used as a UART transmitter pin.
Access the USR register and write the data that is to be transmitted into the TXR register . Note that this step will clear the TXIF bit.

Rev. 1.40 194 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR register . Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR register write execution The read-only TXIF flag is set by the UAR T hardware and if set indic ates that the TXR register is empty and that other data can now be written into the TXR register without overwriting the previous data. If the TEIE bit is set, then the TXIF flag will generate an interrupt. During a data transmission, a write instruction to the TXR register will place the data into the TXR register , which will be copied to the shift register at the end of the present transmission. When there is no data transmission in progress, a write instruction to the TXR register will place the data directly into the shift register , resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. T o clear the TIDLE bit the following software sequence is used: 1. A USR register access 2. A TXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmitting Break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13xN "0" bits, where N=1, 2, etc. If a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. T ransmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept a t a l ogic hi gh l evel, t hen t he t ransmitter c ircuitry wi ll t ransmit c ontinuous bre ak c haracters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized. UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register . When BNO bit is set, the word length will be set to 9 bits. In this c ase t he 9th b it, wh ich i s t he MSB , wi ll b e st ored i n t he R X8 b it i n t he UC R1 r egister. At t he receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is receive d on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receiv e serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sample d three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register , unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations.

Rev. 1.40 194 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Receiving Data When the UAR T receiver is receiv ing data, the data is serially shifted in on the external RX input pin to the shift register , with the lea st significant bit LSB first. The RXR register is a two byte deep FIFO data buf fer, w here tw o bytes can be held in the F IFO w hile the 3rd byte can continue to be received. Note that the application program must ensure that the data is read from RXR before the 3rd byte has been completely shifted in, otherwise the 3rd byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:

Make the correct selection of the BNO, PR T, PREN and ST OPS bits to define the required word length, parity type and number of stop bits.
Setup the BRG register to select the desired baud rate.
Set the RXEN bit to ensure that the UAR T receiver is enabled and the RX pin is used as a UAR T receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur:
The RXIF bit in the USR register will be set then RXR register has data available, at least one more character can be read.
When the content s of the shift register have been transferred to the RXR register and if the RIE bit is set, then an interrupt will be generated.
If during reception, a frame error , noise error , parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. A RXR register read execution Receiving Break Any break character received by the UAR T will be managed as a framing error . The receiver will count and expect a certain number of bit times as specified by the value s programmed into the BNO and ST OPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete a fter t he num ber of bi t t imes spe cified by BNO a nd ST OPS. T he RXIF bi t i s se t, FE RR is set, zeros are loaded into the rece ive data register , interrupts are generated if appropriate and the RIDLE bit is set. If a long break signal has been detected and the receiver has received a start bit, the data bits and the invalid stop bit, which sets the FERR flag, the receiver must wait for a valid stop bit before looking for the next start bit. The receiver will not make the ass umption that the break condition on the line is the next start bit. A break is regarded as a character that contains only zeros with the FERR flag set. The break character will be loaded into the buf fer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UAR T registers will result in the following:
The framing error flag, FERR, will be set.
The receive data register, RXR, will be cleared.
The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set.

Rev. 1.40 19 Deee 1 01 Rev. 1.40 197 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status flag in the USR register , otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The read only receive interrupt flag, RXIF , in the USR register is set by an edge generated by the receiver. An interrupt is generated if RIE=1, when a word is transferred from the Receive Shift Register , RSR, to the Receive Data Register, RXR. An overrun error can also generate an interrupt if RIE=1. Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The RXR register is composed of a two byte deep FIFO data buf fer, where two bytes can be held in the FIFO register , while a 3th byte can continue to be received. Before the 3th byte has been entirely shifted in, the data should be read from the RXR register . If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen:

The OERR flag in the USR register will be set.
The RXR contents will not be lost.
The shift register will be overwritten.
An interrupt will be generated if the RIE bit is set. The O ERR flag can be cleared by an acces s to the U SR regis ter follow ed by a read to the RX R register. Noise Error – NF Over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. I f n oise i s detected within a frame, the following will occur:
The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit.
Data will be transferred from the shift register to the RXR register.
No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note t hat t he NF fla g i s r eset b y a USR r egister r ead o peration f ollowed b y a n R XR r egister r ead operation. Framing Error – FERR The read only framing error flag, FERR, in the USR register , is set if a zero is detected instead of stop bits. If two stop bits are selecte d, both stop bits must be high. Otherwise the FERR flag will be set. The FERR flag is buffered along with the received data and is cleared in any reset. Parity Error – PERR The read only parity error flag, PERR, in the USR register , is set if the parity of the received word is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the parity type, odd or even, is s elected. The read only P ERR fl ag is buf fered along w ith the received data bytes. It is cleared on any reset, it should be noted that the FERR and PERR flags are buf fered along with the corresponding word and should be read before reading the data word.

Rev. 1.40 19 Deee 1 01 Rev. 1.40 197 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver UART Interrupt Structure Several i ndividual UAR T c onditions c an ge nerate a UAR T i nterrupt. W hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . These conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt cont rol is enabled and the stac k is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be serviced before returning to the main program. Four of thes e conditions h ave t he c orresponding USR r egister fla gs wh ich wi ll g enerate a UAR T i nterrupt i f i ts associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address det ect condit ion, whi ch i s al so a UAR T i nterrupt source, does not have an associa ted flag, but will generate a UAR T interrupt when an address detect condition occurs if its function is e nabled by se tting t he ADDE N bi t i n t he UCR2 re gister. An RX pi n wa ke-up, whi ch i s a lso a UART interrupt source, does not have an associated flag, but will generate a UAR T interrupt if the microcontroller i s woke n up from IDLE0 or SL EEP m ode by a fa lling e dge on t he RX pi n, i f t he WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay , commonly known as the System Start-up T ime, for the oscillator to restart and stabilize before the system resumes normal operation. Note t hat t he USR r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. The flags will be cleared automatically whe n c ertain a ctions a re t aken by t he UAR T, t he de tails of whi ch a re gi ven i n t he UART regi ster se ction. The overal l UAR T i nterrupt ca n be disable d or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. USR Registe Tansitte Epty Flag TXIF WAKE Inteupt signal to MCU Tansitte Idle Flag TIDLE Reeive Oveun Flag OERR Reeive Data Availale RXIF RX Pin Wake-up UCR Registe OR ADDEN RIE TIIE TEIE RX7 if BNO=0 RX8 if BNO=1 UCR Registe UART Inteupt Request Flag URF URE EMI UART Interrupt Structure

Rev. 1.40 198 Deee 1 01 Rev. 1.40 199 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Address Detect Mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register , enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Re ceiver Da ta A vailable i nterrupt, whi ch i s re quested by t he RXIF fl ag. If t he ADDE N bi t is equal to 1, then w hen the data is available, an interrupt w ill only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received word wi ll be de fined a s a n a ddress ra ther t han da ta. A Da ta A vailable i nterrupt wi ll be ge nerated every tim e the last bit of the receiv ed word is set. If the ADDEN bit is equal to 0, then a Receive Data A vailable interrupt will be generated each time the RXIF flag is set, irrespective of the data last but status. The address detection and parity functions are mutually exclusive functions. Therefore, if the address detect function is enable d, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. ADDEN Bit 9 if BNO=1 Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 X 1 √ ADDEN Bit Function UART Power Down and Wake-up When the MCU system clock is switched of f, the UAR T will cease to function. If the MCU executes the "HAL T" instruction and switches of f the system clock while a transmission is still in progress, then the transmission will be paused until the UAR T clock source derived from the microcontroller is activated. In a similar way , if the MCU executes the "HAL T" instruction and switches of f the system clock w hile receiving data, then the reception of data w ill likewise be paus ed. When the MCU enters the IDLE or SLEEP Mode, note that the USR, UCR1, UCR2, transmit and receive registers, as well as the BRG register will not be af fected. It is recomm ended to make sure first that the UAR T data transmission or reception has been finished before the microcontroller enters the IDLE or SLEEP mode. The UA RT function contains a receiver RX pin wake-up function, which is enabled or disabled by the W AKE bit in the UCR2 register . If this bit, along with the UAR T enable bit, UAR TEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the IDLE0 or SLEEP Mode, then a fall ing edge on the RX pin will wake up the MCU from the IDLE0 or SL EEP Mo de. No te t hat a s i t t akes c ertain sy stem c lock c ycles a fter a wa ke-up, b efore n ormal microcontroller operation resumes, any data received during this time on the RX pin will be ignored. For a UAR T wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must be set. If the EMI and URE bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed.

Rev. 1.40 198 Deee 1 01 Rev. 1.40 199 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin shared with the I/O pins, with the desired function chosen via the pin-shared selection register bit. Keys are or ganised into several groups, with eac h group known as a module and having a module number , M0 to Mn. Each module is a fully indepe ndent set of four T ouch Keys and each T ouch Key has its own oscillator . Each module contains its own control logic circuits and register set. Examination of the register names will reveal the module number it is referring to. Device Total Key Number Touch Key Module Touch Key BSF370 3 M0 KEY1~KEY4 M1 KEY~KEY8 M KEY9~KEY1 M3 KEY13~KEY1 M4 KEY17~KEY0 M KEY1~KEY4 M KEY~KEY8 M7 KEY9~KEY3 M8 KEY33~KEY3 BSF30 8 M0 KEY1~KEY4 M1 KEY~KEY8 M KEY9~KEY1 M3 KEY13~KEY1 M4 KEY17~KEY0 M KEY1~KEY4 M KEY~KEY8 BSF30 0 M0 KEY1~KEY4 M1 KEY~KEY8 M KEY9~KEY1 M3 KEY13~KEY1 M4 KEY17~KEY0 BSF340 1 M0 KEY1~KEY4 M1 KEY~KEY8 M KEY9~KEY1 Touch Key Structure

Rev. 1.40 00 Deee 1 01 Rev. 1.40 01 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver KEY 1 Key OSC KEY Key OSC KEY 3 Key OSC KEY 4 Key OSC TKRCOV Multi- fequeny MnDFEN TKMn1DH / TKMn1DL ( to Data Meoy Seto ) TKCFOV TK1DL / TK1DH Mux . Module 0 TKTMR Refeene Osillato TKMnROH / TKMnROL ( fo Data Meoy Seto ) Filte Module n 1-it C/F Counte Filte fSYS/4 M U X MnTSS TKMnC 8-it Tie Slot Counte -it unit peiod ounte 8-it Tie Slot Counte Peload RegisteTKTMR Oveflow 1-it Counte TK1OV M U X TK1S1~TK1S0 fSYS/4 fSYS/ fSYS fSYS/8 1-it C/F Counte Value (Seto ) Touh Key Data Meoy Refeene Os. Capaito Value (Seto ) Note: The structure contained in the dash line is identical for each touch key module which contains four touch keys. Touch Key Function Block Diagram Touch Key Register Definition Each t ouch k ey m odule, wh ich c ontains f our t ouch k ey f unctions, h as i ts o wn su ite r egisters. T he following table shows the register set for each touch key module. The Mn within the register name refers to the T ouch Key module number . The series of devices has up to seven T ouch Key Modules dependent upon the selected device. Name Description TKTMR Touh key tie slot 8-it ounte poload egiste TKC0 Touh key funtion Contol egiste 0 TKC1 Touh key funtion Contol egiste 1 TK1DL Touh key funtion 1-it ounte low yte TK1DH Touh key funtion 1-it ounte high yte TKMn1DL Touh key odule n 1-it C/F ounte low yte TKMn1DH Touh key odule n 1-it C/F ounte high yte TKMnROL Touh key odule n efeene osillato apaito selet low yte TKMnROH Touh key odule n efeene osillato apaito selet high yte TKMnC0 Touh key odule n Contol egiste 0 TKMnC1 Touh key odule n Contol egiste 1 TKMnC Touh key odule n Contol egiste Touch Key Module Registers List

Rev. 1.40 00 Deee 1 01 Rev. 1.40 01 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register Name Bit 7 6 5 4 3 2 1 0 TKTMR D7 D D D4 D3 D D1 D0 TKC0 TKRAMC TKRCOV TKST TKCFOV TK1OV — TKMOD TKBUSY TKC1 D7 D D TSCS TK1S1 TK1S0 TKFS1 TKFS0 TK1DL D7 D D D4 D3 D D1 D0 TK1DH D1 D14 D13 D1 D11 D10 D9 D8 TKMn1DL D7 D D D4 D3 D D1 D0 TKMn1DH D1 D14 D13 D1 D11 D10 D9 D8 TKMnROL D7 D D D4 D3 D D1 D0 TKMnC0 — — MnDFEN D4 MnSOFC MnSOF MnSOF1 MnSOF0 TKMnC1 MnTSS — MnROEN MnKOEN MnK4EN MnK3EN MnKEN MnK1EN TKMnC MnSK31 MnSK30 MnSK1 MnSK0 MnSK11 MnSK10 MnSK01 MnSK00 Touch Key Function Registers List TKTMR Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: T ouch key time slot 8-bit counter proload register The touch key time slot counter proload register is used to determine the touch key time slot overflow time. The time slot unit period is obtained by a 5-bit counter and equal t o 32 t ime sl ot c lock c ycles. T herefore, t he t ime sl ot c ounter ove rflow t ime i s equal to the following equation shown. Time slot counter overflow time= (256 - TKTMR[7:0])×32 tTSC, where tTSC is the time slot counter clock. TKC0 Register Bit 7 6 5 4 3 2 1 0 Nae TKRAMC TKRCOV TKST TKCFOV TK1OV — TKMOD TKBUSY R/W R/W R/W R/W R/W R/W — R/W R/W POR 0 0 0 0 0 — 0 0 Bit 7 TKRAMC: T ouch key Data RAM access control 0: Accessed by MCU 1: Accessed by T ouch key module This bit determines that the touch key RAM is used by the MCU or touch key module. However , the touch key module will have the priority to access the touch key RAM when the touch key module operates in the auto scan mode, i.e., the TKST bit state is changed from 0 to 1 when the TKMOD bit is set low . After the touch key auto scan operation is completed, i.e., the TKBUSY bit state is changed from 1 to 0, the touch key RAM access will be controlled by the TKRAMC bit. Therefore, it is recommended to set the TKRAMC bit to 1 when the touch key module operates in the auto scan mode. Otherwise, the contents of the touch key RAM may be modified as this RAM space is configured by the touch key module followed by the MCU access. Bit 6 TKRCOV: T ouch key time slot counter overflow flag 0: No overflow occurs 1: Overflow occurs

Rev. 1.40 0 Deee 1 01 Rev. 1.40 03 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver This bi t c an be a ccessed by a pplication progra ms. W hen t his bi t i s se t by t ouch ke y time slot counter overflow, the corrrespondingn touch key interrupt request flag will be set. However , if this bit is set by application programs, the touch key interrupt request flag will not be affected. In auto scan mode, if the time slot counter overflows but the touch key auto scan operation is not completed, the TKRCOV bit will not be set. At this time, the touch key module n 16-bit C/F counter , touch key function 16-bit counter and 5-bit time slot unit period counter will be automatically cleared but the 8-bit time slot counter will be re loaded from t he 8-bi t t ime sl ot c ounter pre load re gister. W hen t he t ouch key auto scan operation is completed, the TKRCOV bit and the T ouch Key Interrupt request flag, TKMF , will be set and all modules key and reference oscillators will automatically stop. The touch key modules 16-bit C/F counter , touch key function 16-bit counter , 5-bit time slot unit period counter and 8-bit time s lot counter w ill be automatically switched off. In manual scan mode, if the time slot counter overflows , the TKRCO V bit and the Touch Key Interrupt request flag, T KMF, will be set and all modules key and reference oscillators w ill automatically s top. The touch key module 16-bit C/F counter , touch key function 16-bit counter , 5-bit time slot unit period counter and 8-bit time slot counter will be automatically switched off. Bit 5 TKST: T ouch key detection Start control 0: Stopped or no operation 0→1: Start detection In all modules the touch key module 16-bit C/F counter , touch key function 16-bit counter and 5-bit time slot unit period counter will automatically be cle ared when this bit is clea red to zero. However , the 8-bit programmable time slot counter will not be cleared. When this bit is changed from low to high, the touch key module 16-bit C/F counter, t ouch k ey f unction 1 6-bit c ounter, 5 -bit t ime sl ot u nie p eriod c ounter a nd 8 -bit time slot counter will be switched on together with the key and reference oscillators to drive the corresponding counters. Bit 4 TKCFOV: T ouch key module 16-bit C/F counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set by touch key module 16-bit C/F counter overflow and must be cleared to 0 by application programs. Bit 3 TK16OV: T ouch key function 16-bit counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set by touch key function 16-bit counter overflow and must be cleared to 0 by application programs. Bit 2 Unimplemented, read as "0" Bit 1 TKMOD: T ouch key scan mode select 0: Auto scan mode 1: Manual scan mode In manual scan mode the reference oscillator capacitor value should be properly configured before the scan operation begins and the touch key module 16-bit C/F counter value should be read after the scan operation finishes by application program. In auto scan mode the data movement which is described above is implemented by hardware. The individual reference oscillator capacitor value and 16-bit C/F counter content for all scanned keys will be read from and written into a dedicated T ouch Key Data Memory area. In auto scan mode the keys to be scaned can be arranged in a specific sequence which is determined by the MnSK3[1:0] ~ MnSK0[1:0] bits in the TKMnC2 register. The scan operation will not be stopped until all arranged keys are scanned. Bit 0 TKBUSY: T ouch key scan operation busy flag 0: Not busy – no scan operation is executed or scan operation is complete 1: Busy – scan operation is executing This bit indicates whether the touch key scan operation is executing or not. It is set to 1 when the TKST bit is set high to start the scan operation and cleared to 0 when the touch key time slot counter overflows.

Rev. 1.40 0 Deee 1 01 Rev. 1.40 03 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKC1 Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D TSCS TK1S1 TK1S0 TKFS1 TKFS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 1 1 Bit 7~5 D7~D5: Data bits for test only These bits are used for test purpose only and must be kept as "000" for normal operations. Bit 4 TSCS: T ouch key time slot counter select 0: Each touch key module uses its own time slot counter 1: All touch key modules use Module 0 time slot counter Bit 3~2 TK16S1~TK16S0: T ouch key function 16-bit counter clock source select 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 Bit 1~0 TKFS1~TKFS0: T ouch Key oscillator and Reference oscillator frequency select 00: 500 kHz 01: 1000 kHz 10: 1500 kHz 11: 2000 kHz TK16DH/TK16DL – Touch Key Function 16-bit Counter Register Pair Register TK16DH TK16DL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 D7 D D D4 D3 D D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key function 16-bit counter value. This 16-bit counter can be used to calibrate the reference or key oscillator frequency . When the touch key time slot counter overflows in the manual scan mode, this 16-bit counter will be stopped and the counter content will be unchanged. However, this 16-bit counter content will be cleared to zero at the end of the time slot 0, slot 1 and slot 2 but kept unchanged at the end of the time slot 3 in the auto scan mode. This register pair will be cleared to zero when the TKST bit is set low. TKMn16DH/TKMn16DL – Touch Key Module n 16-bit C/F Counter Register Pair Register TKMn16DH TKMn16DL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D1 D11 D10 D9 D8 D7 D D D4 D3 D D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key module n 16-bit C/F counter value. This 16-bit C/ F counter will be stopped and the counter content will be kept unchanged when the touch key time slot c ounter ove rflows i n t he m anual sca n m ode. Howeve r, t his 16-bi t C/ F c ounter c ontent wi ll be cleared to zero at the end of the tim e slot 0, slot 1 and slot 2 but kept unchanged at the end of the time slot 3 when the auto scan mode is selected. This register pair will be cleared to zero when the TKST bit is set low.

Rev. 1.40 04 Deee 1 01 Rev. 1.40 0 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKMnROH/TKMnROL – Touch Key Module n Reference Oscillator Capacitor Select Register Pair Register TKMnROH TKMnROL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Nae — — — — — — D9 D8 D7 D D D4 D3 D D1 D0 R/W — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W POR — — — — — — 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key module n reference oscillator capacitor value. This register pair will be loaded with the corresponding next time slot capac itor value from the dedicated touch key data memory at the end of the current time slot when the auto scan mode is selected. The reference oscillator internal capacitor value = 1024 pF50x] 0 : 9 [TKMn . TKMnC0 Register Bit 7 6 5 4 3 2 1 0 Nae — — MnDFEN D4 MnSOFC MnSOF MnSOF1 MnSOF0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 MnDFEN: T ouch key module n multi-frequency control 0: Disable 1: Enable This bit is used to control the touch key oscillator frequency doubling function. When this bit is set to 1, the key oscillator frequency will be doubled. Bit 4 D4: Data bit for test only The bit is used for test purpose only and must be kept as "0" for normal operations. Bit 3 MnSOFC: T ouch key module n C-to-F oscillator frequency hopping function control select 0: Controlled by the MnSOF2~MnSOF0 1: Controlled by hardware circuit This bit is used to select the touch key oscillator frequency hopping function control method. When this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value. Bit 2~0 MnSOF2~MnSOF0: T ouch key module n Reference and Key oscillators hopping frequency select 000: fHOP0 – Min. hopping frequency 001: fHOP1 010: fHOP2 011: fHOP3 100: fHOP4 – Selected touch key oscillator frequency 101: fHOP5 110: fHOP6 111: fHOP7 – Max. hopping frequency This bit is used to select the touch key oscillator frequency hopping function control method. When this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value.

Rev. 1.40 04 Deee 1 01 Rev. 1.40 0 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKMnC1 Register Bit 7 6 5 4 3 2 1 0 Nae MnTSS — MnROEN MnKOEN MnK4EN MnK3EN MnKEN MnK1EN R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 0 0 0 Bit 7 MnTSS: T ouch key module n time slot counter clock source select 0: T ouch key module n reference oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5 MnROEN: T ouch key module n Reference oscillator enable control 0: Disable 1: Enable This bit is used to enable the touch key module n reference oscillator . In auto scan mode the referenc e oscilla tor will automatica lly be enable d by sett ing the MnROEN bit high w hen the TKS T bit is s et from low to high if the reference os cillator is selected a s t he t ime sl ot c lock so urce. T he c ombination o f t he Mn TSS, T SCS a nd MnK4EN~MnK1EN bits determines w hether the reference os cillator is us ed or not. When the TK BUSY bit is changed from high to low , the M nROEN bit w ill automatically be set low to disable the reference oscillator. In manua l scan mode the reference oscillator should first be enabled before setting the TKST bit from low to high if the reference oscillator is selected to be used and will be disabled when the TKBUSY bit is changed from high to low. Bit 4 MnKOEN: T ouch key module n Key oscillator enable control 0: Disable 1: Enable This bit is used to enable the touch key module n key oscillator . In auto scan mode the key oscillator will automatically be enabled by setting the MnKOEN bit high when the TKST bit is set form low to high. When the TKBUSY bit is changed from high to low , the MnKOEN bit will automatically be set low to disable the key oscillator. In manual scan mode the key oscillator shoule first be enabled before setting the TKST bit from low to high if the relevant key is enabled to be scanned and will be disabled when the TKBUSY bit is changed from high to low. Bit 3 MnK4EN: T ouch key module n Key 4 enable control 0: Disable 1: Enable Bit 2 MnK3EN: T ouch key module n Key 3 enable control 0: Disable 1: Enable Bit 1 MnK2EN: T ouch key module n Key 2 enable control 0: Disable 1: Enable Bit 0 MnK1EN: T ouch key module n Key 1 enable control 0: Disable 1: Enable

Rev. 1.40 0 Deee 1 01 Rev. 1.40 07 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKMnC2 Register Bit 7 6 5 4 3 2 1 0 Nae MnSK31 MnSK30 MnSK1 MnSK0 MnSK11 MnSK10 MnSK01 MnSK00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 0 0 1 0 0 Bit 7~6 MnSK31~MnSK30: T ouch key module n time slot 3 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 3 and only available in the auto scan mode. Bit 5~4 MnSK21~MnSK20: T ouch key module n time slot 2 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 2 and only available in the auto scan mode. Bit 3~2 MnSK11~MnSK10: T ouch key module n time slot 1 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 1 and only available in the auto scan mode. Bit 1~0 MnSK01~MnSK00: T ouch key module n time slot 0 key scan select 00: KEY 1 01: KEY 2 10: KEY 3 11: KEY 4 These bits are used to select the desired scan key in time slot 0 in the auto scan mode or used as the multiplexer for scan key select in the manual mode. Touch Key Operation When a finger t ouches or i s i n proxi mity t o a t ouch pa d, t he c apacitance of t he pa d wi ll i ncrease. By using this capa citance variation to change slightly the frequency of the internal sense oscillator , touch act ions can be sensed by mea suring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined.

Rev. 1.40 0 Deee 1 01 Rev. 1.40 07 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TKST MnKOEN MnROEN KEY OSC CLK Refeene OSC CLK fCFTMCK Enale fCFTMCK (MnDFEN=0) fCFTMCK (MnDFEN=0) TKBUSY TKRCOV Hadwae set to “0” Set Touh Key inteupt equest flag Touch Key Mamual Scan Mode Timing Diagram Each touch key module contains four touch key inputs w hich are shared logical I/O pins, and the desired function is selected using register bits. Each touch key has its own independent sense oscillator. There are therefore four sense oscillators within each touch key module. During this reference clock fixed interval, the number of clock cycles generated by the s ense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a T ouch Key interrupt signal will be generated in the manual scan mode. Using t he T SCS bi t i n t he T KC1 re gister c an se lect t he m odule 0 t ime sl ot c ounter a s t he t ime slot counter for all modules. All modules use the same started signal, TKST , in the TKC0 register . The t ouch key m odule 16-bi t C/ F counte r, 16-bi t counte r, 5-bi t t ime sl ot unit period counte r i n all m odules wi ll be a utomatically c leared whe n t he T KST b it i s c leared t o z ero, b ut t he 8- Bit programmable tim e slot counter will not be cleared. The overflow time is setup by user . When the TKST bit changes from low to high, the 16-bit C/F counter, 16-bit counter, 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be autom atically stopped and the 16- bit C/F counter , 16-bit counter , 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched of f when the time slot counter overflows. The clock source for the time slot counter is sourced from the reference oscillator or fSYS/4 which is selected using the MnTSS bit in the TKMnC1 registe r. The reference oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register. When the time s lot counter in all the touch key modules or in the touch key module 0 overflow s, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. Each touch key module consists of four touch keys, KEY1 ~ KEY4 are contained in module 0, KEY5 ~ KE Y8 a re c ontained i n m odule 1, KE Y9 ~ KE Y12 a re c ontained i n m odule 3, e tc. E ach touch key module has an identical structure.

Rev. 1.40 08 Deee 1 01 Rev. 1.40 09 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Auto Scan Mode There are two scan modes contained for the touch key function. The auto scan mode can minisize the load of the application programs and improve the touch key scan operation performance. The auto scan mode and manual scan mode are selected using the TKMOD bit in the TKC0 register . When the TKMOD bit is set low , the auto scan mode is selcted to scan the keys in each module in a specific sequence determined by the MnSK3[1:0]~MnSK0[1:0] in the TKMnC2 register. TKST Module 0 Tie slot 0 Tie slot 1 Tie slot Tie slot 3 Module 1 Tie slot 0 Tie slot 1 Tie slot Tie slot 3 Module n Tie slot 0 Tie slot 1 Tie slot Tie slot 3 TKBUSY TKRCOV Cleaed y softwae Tie slot 1 Tie slot Tie slot 3 Tie slot 1 Tie slot Tie slot 3 Tie slot 1 Tie slot Tie slot 3 Touh Key Data Meoy Aess : Set Touh Key inteupt equest flag : Read N ytes fo Touh Key Data Meoy to TKMnROH/TKMnROL egistes : Wite N ytes fo TKMn1DH/TKMn1DL egistes to Touh Key Data Meoy N = Touh Key Module Nue; n = Module Seial Nue Key Auto San Cyle Touch Key Auto Scan Mode Timing Diagram

Rev. 1.40 08 Deee 1 01 Rev. 1.40 09 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver In the auto scan mode the key oscillator and reference oscillator will automatically be enabled when the TKST bit is set from low to high and disabled automatically when the TKBUSY bit changes from high to low . When the TK ST bit is s et from low to high in the auto s can mode, the fi rst reference oscillator i nternal c apacitor va lue wi ll be re ad from a spe cific l ocation of t he de dicated t ouch ke y data memory and loaded into the corresponding TKMnROH/TKMnROL registers. Then the 16-bit C/F counter value will be written into the last location of the corresponding touch key module data memory. After this the selected key will be scanned in time slot 0. At the end of the time slot 0 key scan operation, the reference oscilla tor internal capacitor value for the next selected key will be read from the touch key data memory and loaded into the the next TK MnROH/TKMnROL regis ters. Then the 16-bit C/F counter value of the current scanned key will be written into the corresponding touch key data memory . The whole auto scan operation will sequentially be carried out in the above specific way from time slot 0 to time slot 3. After four keys are scanned, the TKRCOV bit will be set high and the TKBUSY bit will be set low . At the end of the auto scan mode, the first reference oscillator internal capacitor value will again be read from the touch key data memory and loaded into t he correspondi ng T KMnROH/TKMnROL regi sters. T hen t he 16-bit C/ F count er val ue wi ll again be written into the relevant touch key data memory. Touch Key Data Memory The device provides two dedicated Data Memory area for the touch key auto scan mode. One area is us ed to s tore the 16-bit C/F counter values of the touch key module 0~n and located in D ata Memory Sector 5. The other area is used to store the reference oscillator internal capacitor values of the touch key module 0~n and located in Data Memory Sector 6. Device Touch Key Data Memory Sector : Address BSF340 : 00H~17H : 00H~17H BSF30 : 00H~7H : 00H~7H BSF30 : 00H~37H : 00H~37H BSF370 : 00H~47H : 00H~47H Touch Key Data Memory Summary

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 10-bit Ref. OSC capacitor TKMnROL / TKMnROH TKM016DL_K1 TKM016DH_K1 TKM016DL_K2 TKM016DH_K2 TKM016DL_K3 TKM016DH_K3 TKM016DL_K4 TKM016DH_K4 TKM116DL_K1 TKM116DH_K1 TKM116DL_K2 TKM116DH_K2 TKM116DL_K3 TKM116DH_K3 TKM116DL_K4 TKM116DH_K4 Module 0 TKM0ROL_K1 TKM0ROH_K1 TKM0ROL_K2 TKM0ROH_K2 TKM0ROL_K4 TKM0ROH_K4 TKM0ROL_K3 TKM0ROH_K3 TKM1ROL_K1 TKM1ROH_K1 TKM1ROL_K2 TKM1ROH_K2 TKM1ROL_K4 TKM1ROH_K4 TKM1ROL_K3 TKM1ROH_K3 TKM216DL_K1 TKM216DH_K1 TKM216DL_K2 TKM216DH_K2 TKM216DL_K3 TKM216DH_K3 TKM216DL_K4 TKM216DH_K4 TKM2ROL_K1 TKM2ROH_K1 TKM2ROL_K2 TKM2ROH_K2 TKM2ROL_K4 TKM2ROH_K4 TKM2ROL_K3 TKM2ROH_K3 Module 1 Module 2 16-bit C/F counter value (Sector 5) Ref. OSC Capacitor value (Sector 6) Module n TKMnROL_K1 TKMnROH_K1 TKMnROL_K2 TKMnROH_K2 TKMnROL_K4 TKMnROH_K4 TKMnROL_K3 TKMnROH_K3 TKMn16DL_K1 TKMn16DH_K1 TKMn16DL_K2 TKMn16DH_K2 TKMn16DL_K3 TKMn16DH_K3 TKMn16DL_K4 TKMn16DH_K4 00H 01H 02H xxH 16-bit C/F counter TKMn16DL / TKMn16DH Touch Key Circuit Step 1 Step 2 Touch Key Data Memory Map

Rev. 1.40 10 Deee 1 01 Rev. 1.40 11 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Scan Operation Flow Chart Stat Wite Ref. OSC Capaito to TKMnROH/TKMnROL Touch Key Manual Scan Operation Start Set Stat it TKST 0 à 1 ð Busy flag TKBUSY=1 All Tie Slot Counte oveflow ? TKRCOV=0 Initiate Tie Slot & 1-it C/F Counte All Tie Slot & 1-it C/F Counte Stat to ount Tie Slot & 1-it C/F Counte Keep ounting TKRCOV=1 Touh key usy flag TKBUSY=0 Geneate Inteupt equest flag Read C/F ounte fo TKMn1DH/TKMn1DL Touh key san end Set TKST it 1 à 0 End Touch Key Manual Scan Mode Flow Chart – TKMOD=1, TSCS=0

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Stat Wite Ref. OSC intenal Capaito value to Data Meoy (Seto ) Touch Key Auto Scan Operation Start Set Stat it TKST 0 à 1 ð Busy flag TKBUSY=1 All Tie Slot Counte oveflow ? No Initiate Tie Slot & 1-it C/F Counte All Tie Slot ounte & 1-it C/F ounte Stat to ount Tie Slot & 1-it C/F Counte Keep ounting Yes TKRCOV = 1 Geneate Inteupt equest flag Read C/F ounte value fo Data Meoy (Seto ) Touh key san end Set TKST it 1 à 0 End Load Ref. OSC intenal Capaito value fo Data Meoy (Seto ) Stoe C/F ounte value to Data Meoy (Seto ) All key san finish ? Yes No Touh key usy flag TKBUSY=0 Change next key Touch Key Auto Scan Mode Flow Chart – TKMOD=0, TSCS=0 Touch Key Interrupt The touch key only has single inter rupt, when the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned he re a re t he ke ys whi ch a re e nabled. T he 16-bi t C/ F c ounter, 16-bi t c ounter, 5-bi t t ime slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared. Progrsmming Considerations After t he rel evant regi sters are se tup, t he t ouch key det ection process i s i nitiated t he cha nging t he TKST Bit from low to high. This will enable and synchronise all releva nt oscillators. The TKRCOV flag which is the time slot counter flag will go high when the counter overflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency.

Rev. 1.40 1 Deee 1 01 Rev. 1.40 13 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Low Voltage Detector – LVD Each device has a Low V oltage Detector function, also known as L VD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low V oltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name L VDC. Three bits in this register , VL VD2~VLVD0, are used to select one of eight fixed voltages below which a l ow vo ltage c ondition wi ll be de termined. A l ow vo ltage c ondition i s i ndicated whe n t he L VDO bit is set. If the L VDO bit is low , this indicates that the VDD voltage is above the preset low voltage value. The L VDEN bit is used to control the overall on/of f function of the low voltage detector . Setting the bit high will enable the low voltage detector . Clearing the bit to zero will switch of f the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Nae — — LVDO LVDEN VBGEN VLVD VLVD1 VLVD0 R/W — — R R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Uunimplemented, read as "0" Bit 5 LVDO: LVD output flag 0: No Low V oltage Detected 1: Low V oltage Detected Bit 4 LVDEN: Low V oltage Detector Enable control 0: Disable 1: Enable Bit 3 VBGEN: Bandgap V oltage Output Enable control 0: Disable 1: Enable Bit 2~0 VLVD2~VLVD0: LVD V oltage selection 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LVD Operation The Low V oltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified volta ge level stored in the L VDC register . This has a range of between 2.0V and 4.0V . When the power supply voltage, VDD, falls below this pre-determined value, the L VDO bit will be set high indicating a low power supply voltage condition. The Low V oltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the L VDEN bit is high. After enabling the Low Voltage Detector , a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly , at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. /G56/G44 /G44 /G56 /G4C/G56 /G44 /G4C/G56 /G44/G45 /G4E /G4C/G56 /G44/G4F /G74 /G4C/G56 /G44/G53 LVD Operation The Low V oltage Detector also has its own interrupt which is contained within one of the Multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the L VDO bit. The interrupt will only be generated after a delay of tLVD after the L VDO bit has been set high by a low voltage condition. When the device is powered down the Low V oltage Detector will rema in active if the L VDEN bit is high. In this case, the L VF interrupt request flag will be set, causing an interru pt to be generated if VDD falls below the preset L VD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low V oltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode.

Rev. 1.40 14 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Interrupts Interrupts are an important part of any microcontroller s ystem. When an external event or an internal function such as a T imer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several external interrupt and internal interrupts functions . The external interrupts are generated by the action of the external INT0 and INT1 pins, while the internal interrupts are generated by various internal functions such as the TMs, T ouch Key , T ime Base, L VD, EEPROM, SIM, UAR T and the A/D converter, etc. Interrupt Registers Overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the Special Purpose Data Memory , as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. T he first i s t he INT C0~INTC2 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the MFI0~MFI3 registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual interrupts as well as i nterrupt fla gs t o i ndicate t he p resence o f a n i nterrupt r equest. T he n aming c onvention o f t hese follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag Notes Gloal EMI — — INTn Pins INTnE INTnF n = 0 ~ 1 Touh Key TKME TKMF — UART URE URF — Multi-funtion MFnE MFnF n = 0 ~ 3 A/D Convete ADE ADF — Tie Base TBnE TBnF n = 0 ~ 1 LVD LVE LVF — EEPROM wite opeation DEE DEF — SIM SIME SIMF — CTM CTMnPE CTMnPF n = 0 ~ 1CTMnAE CTMnAF PTM PTMPE PTMPF —PTMAE PTMAF STM STMPE STMPF —STMAE STMAF Interrupt Register Bit Naming Conventions

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Register Name Bit 7 6 5 4 3 2 1 0 INTEG — — — — INT1S1 INT1S0 INT0S1 INT0S0 INTC0 — TKMF INT1F INT0F TKME INT1E INT0E EMI INTC1 ADF MF1F MF0F URF ADE MF1E MF0E URE INTC MF3F TB1F TB0F MFF MF3E TB1E TB0E MFE MFI0 — — CTM0AF CTM0PF — — CTM0AE CTM0PE MFI1 STMAF STMPF CTM1AF CTM1PF STMAE STMPE CTM1AE CTM1PE MFI — SIMF PTMAF PTMPF — SIME PTMAE PTMPE MFI3 — — DEF LVF — — DEE LVE Interrupt Registers List INTEG Register Bit 7 6 5 4 3 2 1 0 Nae — — — — INT1S1 INT1S0 INT0S1 INT0S0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~2 INT1S1~INT1S0: Interrupt edge control for INT1 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges Bit 1~0 INT0S1~INT0S0: Interrupt edge control for INT0 pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Nae — TKMF INT1F INT0F TKME INT1E INT0E EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TKMF: T ouch key interrupt request flag 0: No request 1: Interrupt request Bit 5 INT1F: INT1 interrupt request flag 0: No request 1: Interrupt request Bit 4 INT0F: INT0 interrupt request flag 0: No request 1: Interrupt request Bit 3 TKME: T ouch key interrupt control 0: Disable 1: Enable Bit 2 INT1E: INT1 interrupt control 0: Disable 1: Enable Bit 1 INT0E: INT0 interrupt control 0: Disable 1: Enable

Rev. 1.40 1 Deee 1 01 Rev. 1.40 17 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 0 EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register Bit 7 6 5 4 3 2 1 0 Nae ADF MF1F MF0F URF ADE MF1E MF0E URE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 6 MF1F: Multi-function 1 interrupt request flag 0: No request 1: Interrupt request Bit 5 MF0F: Multi-function 0 interrupt request flag 0: No request 1: Interrupt request Bit 4 URF: UART transfer interrupt request flag 0: No request 1: Interrupt request Bit 3 ADE: A/D Converter interrupt control 0: Disable 1: Enable Bit 2 MF1E: Multi-function 1 interrupt control 0: Disable 1: Enable Bit 1 MF0E: Multi-function 0 interrupt control 0: Disable 1: Enable Bit 0 URE: UART transfer interrupt control 0: Disable 1: Enable INTC2 Register Bit 7 6 5 4 3 2 1 0 Nae MF3F TB1F TB0F MFF MF3E TB1E TB0E MFE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 MF3F: Multi-function 3 interrupt request flag 0: No request 1: Interrupt request Bit 6 TB1F: T ime Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 5 TB0F: T ime Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 4 MF2F: Multi-function 2 interrupt request flag 0: No request 1: Interrupt request Bit 3 MF3E: Multi-function 3 interrupt control 0: Disable 1: Enable

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 2 TB1E: T ime Base 1 interrupt control 0: Disable 1: Enable Bit 1 TB0E: T ime Base 0 interrupt control 0: Disable 1: Enable Bit 0 MF2E: Multi-function 2 interrupt control 0: Disable 1: Enable MFI0 Register Bit 7 6 5 4 3 2 1 0 Nae — — CTM0AF CTM0PF — — CTM0AE CTM0PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 CTM0AF: CTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 CTM0PF: CTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 CTM0AE: CTM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 CTM0PE: CTM0 Comparator P match Interrupt control 0: Disable 1: Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Nae STMAF STMPF CTM1AF CTM1PF STMAE STMPE CTM1AE CTM1PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 STMAF: STM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6 STMPF: STM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5 CTM1AF: CTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 CTM1PF: CTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 STMAE: STM Comparator A match Interrupt control 0: Disable 1: Enable Bit 2 STMPE: STM Comparator P match Interrupt control 0: Disable 1: Enable

Rev. 1.40 18 Deee 1 01 Rev. 1.40 19 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Bit 1 CTM1AE: CTM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 CTM1PE: CTM1 Comparator P match Interrupt control 0: Disable 1: Enable MFI2 Register Bit 7 6 5 4 3 2 1 0 Nae — SIMF PTMAF PTMPF — SIME PTMAE PTMPE R/W — R/W R/W R/W — R/W R/W R/W POR — 0 0 0 — 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 SIMF: SIM Interrupt request flag 0: No request 1: Interrupt request Bit 5 PTMAF: PTM Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 PTMPF: PTM Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 Unimplemented, read as "0" Bit 2 SIME: SIM Interrupt control 0: Disable 1: Enable Bit 1 PTMAE: PTM Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 PTMPE: PTM Comparator P match Interrupt control 0: Disable 1: Enable MFI3 Register Bit 7 6 5 4 3 2 1 0 Nae — — DEF LVF — — DEE LVE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 7 DEF: Data EEPROM Interrupt request flag 0: No request 1: Interrupt request Bit 4 LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 DEE: Data EEPROM Interrupt control 0: Disable 1: Enable Bit 0 LVE: LVD Interrupt control 0: Disable 1: Enable

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Interrupt Operation When the conditions for an interrupt event occur, such as a TM Comparator P or Comparator A or A/ D conversion completion, etc, the relevant interrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enabl e bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector . The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . The microcontroller will then fetch its next instruction from this interrupt vector . The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allow s the microcontroller to continue w ith normal execution at the point w here the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . Some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . O nce an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically . This will prevent any further interrupt nesting from occurring. However, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. Al l o f t he i nterrupt r equest fla gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n SL EEP o r IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.

Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver INT0 Pin INT1 Pin INT0F INT1F INT0E INT1E EMI 04H EMI 08H M. Funt. 0 MF0F MF0E EMI 0CH EMI 10H EMI 14H Tie Base 0 TB0F TB0E EMI 18H LVD LVF LVE EMI 1CH Inteupt Nae Request Flags Enale Bits Maste Enale Vector EMI auto disaled in ISR Pioity High Low M. Funt. 1 MF1F MF1E CTM0 P CTM0PF CTM0PE CTM0 A CTM0AF CTM0AE Inteupts ontained within Multi-Funtion Inteupts xxE Enale Bits xxF Request Flag auto eset in ISR Legend xxF Request Flag no auto eset in ISR EMI 0H A/D ADF ADE EMI 4H M. Funt. MFF MFE Tie Base 1 TB1F TB1E M. Funt. 3 MF3F MF3E EEPROM DEF DEE SIM SIMF SIME UART URF URE EMI 8H CTM1 P CTM1PF CTM1PE CTM1 A CTM1AF CTM1AE EMI CH Touh Key TKMF TKME STM P STMPF STMPE STM A STMAF STMAE PTM P PTMPF PTMPE PTM A PTMAF PTMAE Interrupt Scheme External Interrupt The external interrupts are controlled by signal transitions on the pins INT0~INT1. An external interrupt request will take place when the external interrupt request flags, INT0F~INT1F , are set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pins . T o allow the program to branch to its res pective interrupt vector addres s, the g lobal i nterrupt e nable b it, E MI, a nd r espective e xternal i nterrupt e nable b it, I NT0E~INT1E, must first be set. Additionally the correct interrupt edge type mus t be selected using the INTEG register to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pins are pin-shared with I/O pins, they can only be configured as external interrupt pins if their external interrupt enable bit in the corresponding interrupt register has been set and the external interrupt pin is selected by the corresponding pin-shared function selection bits. The pin must also be setup as an input by setting the corresponding bit in the port control register . When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. When the interrupt is serviced, the external interrupt request flags, INT0F~INT1F , will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function.

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Touch Key Interrupt For a T ouch Key interrupt to occur, the global interrupt enable bit, EMI, and the T ouch Key interrupt enable TKME must be first set. An actual T ouch Key interrupt will take place when the T ouch Key request flag, TKMF , is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the T ouch Key time slot counter overflow occurs, a subroutine call to the relevant timer interrupt vector , will take place. When the interrupt is serviced, the T ouch Key interrupt request flag, TKMF , will be automatically reset and the EMI Bit will be automatically cleared to disable other interrupts. UART Transfer Interrupt The UAR T T ransfer Interrupt is controlled by several UAR T transfer conditions. When one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller . These conditions are a transmitter data register empty , transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and UAR T Interrupt enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of the conditions described above occurs, a subroutine call to the UAR T Interrupt vector , will take place. When the interrupt is serviced, the UAR T Interrupt flag, URF , will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/ D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF , is set, which occurs when the A/D conversion process finishes. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, a nd A/ D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector , will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF , will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. Multi-function Interrupt Within the device there are up to four Multi-function interrupts. Unlike the other independent interrupts, these interrupts have no independent source, but rather are formed from other existing interrupt sources, namely the TM interrupts, L VD interrupt, EEPROM write operation interrupt and SIM interface interrupts. A Multi-function interrupt request will take place when any of the Multi-function interrupt request flags MFnF are set. The Multi-function interrupt flags will be set when any of their included functions generate an interrupt request flag. T o allow the program to branch to its respective interrupt vector address, when the Multi-func tion interrupt is enabled and the stack is not full, and either one of the interrupts contained within each of Multi-function interrupt occurs, a subroutine call to one of the Multi-function interrupt vectors will take place. When the interrupt is serviced, the related Multi- Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, it must be noted that, although the Multi-function Interrupt request flags will be automatically reset when the interrupt is serviced, the request flags from the original source of the Multi-function interrupts will not be automatically reset and must be manually reset by the application program.

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Time Base Interrupt The function of the T ime Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer . When this happens its interrupt request flag, TBnF , will be set. T o allow the program to branch to its respective interrupt vector addresses, the global interrup t enable bit, EMI and T ime Base enable bit, TBnE, must first be set. When the interrupt is enabl ed, the stack is not full and the T ime Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF , will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the T ime Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC0 or fPSC1, originates from the internal clock source fSYS, fSYS/4 or fSUB and then passes through a divider , the division ratio of which is selected by programming the appropriate bits in the TB0C and TB1C registers to obtain longer interrupt periods whose value ranges. The clock source whi ch i n t urn c ontrols t he T ime Ba se i nterrupt pe riod i s se lected usi ng t he CL KSEL0[1:0] and CLKSEL1[1:0] bits in the PSCR0 and PSCR1 register respectively. M U X fSYS/4 fSYS fSUB Pesale 0 CLKSEL0[1:0] fPSC0 fPSC0/8 ~ fPSC0/1 M U X M U X TB0[:0] TB1[:0] Tie Base 0 Inteupt Tie Base 1 Inteupt TB0ON TB1ON M U X fSYS/4 fSYS fSUB Pesale 1 CLKSEL1[1:0] fPSC1 fPSC1/8 ~ fPSC1/1 Time Base Interrupts PSCR0 Register Bit 7 6 5 4 3 2 1 0 Nae — — — — — — CLKSEL01 CLKSEL00 Bit 7~2 unimplemented, read as "0" Bit 1~0 CLKSEL01~CLKSEL00: Prescaler 0 clock source selection 00: fSYS 01: fSYS/4 1x: fSUB PSCR1 Register Bit 7 6 5 4 3 2 1 0 Nae — — — — — — CLKSEL11 CLKSEL10 Bit 7~2 unimplemented, read as "0" Bit 1~0 CLKSEL11~CLKSEL10: Prescaler 1 clock source selection 00: fSYS 01: fSYS/4 1x: fSUB

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TB0C Register Bit 7 6 5 4 3 2 1 0 Nae TB0ON — — — — TB0 TB01 TB00 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 TB0ON: T ime Base 0 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0 TB02~TB00: T ime Base 0 time-out period selection 000: 28/fPSC0 001: 29/fPSC0 010: 210/fPSC0 011: 211/fPSC0 100: 212/fPSC0 101: 213/fPSC0 110: 214/fPSC0 111: 215/fPSC0 TB1C Register Bit 7 6 5 4 3 2 1 0 Nae TB1ON — — — — TB1 TB11 TB10 R/W R/W — — — — R/W R/W R/W POR 0 — — — — 0 0 0 Bit 7 TB1ON: T ime Base 1 Enable Control 0: Disable 1: Enable Bit 6~3 unimplemented, read as "0" Bit 2~0 TB12~TB10: T ime Base 1 time-out period selection 000: 28/fPSC1 001: 29/fPSC1 010: 210/fPSC1 011: 211/fPSC1 100: 212/fPSC1 101: 213/fPSC1 110: 214/fPSC1 111: 215/fPSC1 Serial Interface Module Interrupt The Serial Interface Module Interrupt, also known as the SIM interrupt, is contained within the Multi-function Interrupt. A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF , is set, which occurs when a byte of data has been received or transmitted by the SIM interface, an I2C slave address match or I2C bus time-out occurrence. T o allow the program to branch t o i ts r espective i nterrupt v ector a ddress, t he g lobal i nterrupt e nable b it, E MI, t he Se rial Interface Interrupt enable bit, SIME, and Muti-function interrupt enable bit must first be set. When the i nterrupt i s e nabled, t he st ack i s n ot f ull a nd a ny o f t he a bove d escribed si tuations o ccurs, a subroutine c all t o t he re spective Mul ti-function In terrupt ve ctor, wi ll t ake pl ace. W hen t he Se rial Interface Interrupt is serviced, the EMI bit will be automatically cleare d to disable other interrupts, however only the Multi-function interrupt request flag will be also automatically cleared. As the SIMF flag will not be automatically cleared, it has to be cleared by the application program.

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LVD Interrupt The L ow V oltage De tector I nterrupt i s c ontained wi thin t he Mu lti-function I nterrupt. An L VD Interrupt reques t w ill take place w hen the L VD Interrupt request flag, L VF, is s et, w hich occurs when the Low V oltage Detector function detects a low power supply voltage. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, Low V oltage Interrupt enable bit, L VE, and associated Multi-function interrupt enable bit, must first be set. When the interrupt is enabled, the stack is not full and a low voltage conditio n occurs, a subroutine call to the Multi-function Interrupt vector , will take place. When the Low V oltage Interrupt is serviced, the EMI bit will be automatically clear ed to disable other interrupts. However , only the Multi-function interrupt request flag will be also automatically cleared. As the L VF flag will not be automatically cleared, it has to be cleared by the application program. EEPROM Interrupt The EEPROM W rite Interrupt is contained within the Multi-function Interrupt. An EEPROM Write Interrupt request will take place when the EEPROM W rite Interrupt request flag, DEF , is set, which occurs when an EEPROM W rite cycle ends. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, EEPROM W rite Interrupt enable bit, DEE, and associated Multi-function interrupt enable bit must first be set. When the interrupt is enabled, the stack is not full and an EEPROM W rite cycle ends, a subroutine call to the respective Multi-function Interrupt vector will take place. When the EEPROM W rite Interrupt is serviced, the EMI bit will be automatically clear ed to disable other interrupts. However , only the Multi-function interrupt request flag will be automatically cleared. As the DEF flag will not be automatically cleared, it has to be cleared by the application program. TM Interrupt The Compact, Standard and Periodic TMs have two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match situation. All of the TM interrupts are contained within the Multi-function Interrupts. For all of the TM types there are two interrupt request fla gs and two enable control bit s. A TM int errupt reque st wi ll ta ke plac e when any of the TM re quest fla gs a re se t, a si tuation whi ch oc curs whe n a T M c omparator P or A m atch si tuation happens. To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, respective TM Interrupt enable bit, and relevant Multi-function Interrupt enable bit, MFnE, must first be set. When the interrupt is enabled, the stack is not full and a TM comparator match situation occurs, a subroutine call to the relevant Multi-function Interrupt vector locations, will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. However , only the related MFnF flag will be automatically cleared. As the TM interrupt request flags will not be automatically cleared, they have to be cleared by the application program.

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Interrupt Wake-up Function Each of the int errupt funct ions has the ca pability of waki ng up the mi crocontroller when in the SLEEP o r I DLE Mo de. A wa ke-up i s g enerated wh en a n i nterrupt r equest fla g c hanges f rom l ow to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their re spective interrupt fl ag to be set hi gh and consequently ge nerate an i nterrupt. C are m ust t herefore b e t aken i f sp urious wa ke-up si tuations a re t o b e a voided. I f a n interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interr upt enable bits have no ef fect on the interrupt wake-up function. Programming Considerations By di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained w ithin a M ulti-function interrupt, then w hen the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately . If only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.

Rev. 1.40 Deee 1 01 Rev. 1.40 7 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Application Circuits A/D RX VDD VSS BS66F3x0 10uF0.1uF VDD RS488 Tanseive TX I/O RS_DIR Analog Signals I/O KEY1 KEYx XT1 XT 378Hz TM PWM / Captue TM Buzze SPI/IC Couniation Devie OSC1 OSC Syste Cystal I/O Contol Devie

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. In the case of Holtek microcontroller , a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator , most instructions would be i mplemented wi thin 0.5 μs a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP , CALL, RET , RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. E xamples of suc h i nstructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Ac cumulator. One of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. W ithin t he Hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified.

Rev. 1.40 8 Deee 1 01 Rev. 1.40 9 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within t he Hol tek m icrocontroller i nstruction se t. As wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he Ac cumulator wh ich m ay i nvolve a dditional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one Bit right or left. Dif ferent rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he Ca rry Bit from where it can be examined and the necessary serial Bit set high or low . Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or t o a su broutine usi ng t he CAL L i nstruction. T hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. This is done by placing a return ins truction " RET" in the s ubroutine w hich w ill cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping of f point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual Bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data Bits. Bit Operations The abili ty to provide single Bit operations on Data Memory is an extremely flexible feature of all Holtek m icrocontrollers. T his fe ature i s e specially use ful for out put port Bi t progra mming whe re individual Bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" i nstructions r espectively. T he f eature r emoves t he n eed f or p rogrammers t o fir st r ead t he 8 -Bit output port, manip ulate the input data to ensure that other Bits are not changed and then output the port with the correct new data. This read-modify-write process is take n care of automatically when these Bit operation instructions are used. Table Read Operations Data st orage i s norm ally i mplemented by usi ng re gisters. However , whe n worki ng wi th l arge amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory . T o overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HAL T" i nstruction f or Po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the W atchdog T imer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections.

Rev. 1.40 30 Deee 1 01 Rev. 1.40 31 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Instruction Set Summary The i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be use d whe n t he desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A[] Add Data Meoy to ACC 1 Z C AC OV SC ADDM A[] Add ACC to Data Meoy 1Note Z C AC OV SC ADD Ax Add iediate data to ACC 1 Z C AC OV SC ADC A[] Add Data Meoy to ACC with Cay 1 Z C AC OV SC ADCM A[] Add ACC to Data eoy with Cay 1Note Z C AC OV SC SUB Ax Sutat iediate data fo the ACC 1 Z C AC OV SC CZ SUB A[] Sutat Data Meoy fo ACC 1 Z C AC OV SC CZ SUBM A[] Sutat Data Meoy fo ACC with esult in Data Meoy 1Note Z C AC OV SC CZ SBC Ax Sutat iediate data fo ACC with Cay 1 Z C AC OV SC CZ SBC A[] Sutat Data Meoy fo ACC with Cay 1 Z C AC OV SC CZ SBCM A[] Sutat Data Meoy fo ACC with Cay esult in Data Me o y 1Note Z C AC OV SC CZ DAA [] Deial adjust ACC fo Addition with esult in Data Meoy 1Note C Logic Operation AND A[] Logial AND Data Meoy to ACC 1 Z OR A[] Logial OR Data Meoy to ACC 1 Z XOR A[] Logial XOR Data Meoy to ACC 1 Z ANDM A[] Logial AND ACC to Data Meoy 1Note Z ORM A[] Logial OR ACC to Data Meoy 1Note Z XORM A[] Logial XOR ACC to Data Meoy 1Note Z AND Ax Logial AND iediate Data to ACC 1 Z OR Ax Logial OR iediate Data to ACC 1 Z XOR Ax Logial XOR iediate Data to ACC 1 Z CPL [] Copleent Data Meoy 1Note Z CPLA [] Copleent Data Meoy with esult in ACC 1 Z Increment & Decrement INCA [] Ineent Data Meoy with esult in ACC 1 Z INC [] Ineent Data Meoy 1Note Z DECA [] Deeent Data Meoy with esult in ACC 1 Z DEC [] Deeent Data Meoy 1Note Z Rotate RRA [] Rotate Data Meoy ight with esult in ACC 1 None RR [] Rotate Data Meoy ight 1Note None RRCA [] Rotate Data Meoy ight though Cay with esult in ACC 1 C RRC [] Rotate Data Meoy ight though Cay 1Note C RLA [] Rotate Data Meoy left with esult in ACC 1 None RL [] Rotate Data Meoy left 1Note None RLCA [] Rotate Data Meoy left though Cay with esult in ACC 1 C RLC [] Rotate Data Meoy left though Cay 1Note C

Rev. 1.40 30 Deee 1 01 Rev. 1.40 31 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Mnemonic Description Cycles Flag Affected Data Move MOV A[] Move Data Meoy to ACC 1 None MOV []A Move ACC to Data Meoy 1Note None MOV Ax Move iediate data to ACC 1 None Bit Operation CLR [].i Clea it of Data Meoy 1Note None SET [].i Set it of Data Meoy 1Note None Branch Operation JMP add Jup unonditionally None SZ [] Skip if Data Meoy is zeo 1Note None SZA [] Skip if Data Meoy is zeo with data oveent to ACC 1Note None SZ [].i Skip if it i of Data Meoy is zeo 1Note None SNZ [] Skip if Data Meoy is not zeo 1Note None SNZ [].i Skip if it i of Data Meoy is not zeo 1Note None SIZ [] Skip if ineent Data Meoy is zeo 1Note None SDZ [] Skip if deeent Data Meoy is zeo 1Note None SIZA [] Skip if ineent Data Meoy is zeo with esult in ACC 1Note None SDZA [] Skip if deeent Data Meoy is zeo with esult in ACC 1Note None CALL add Suoutine all None RET Retun fo suoutine None RET Ax Retun fo suoutine and load iediate data to ACC None RETI Retun fo inteupt None Table Read Operation TABRD [] Read table (specific page) to TBLH and Data Memory Note None TABRDL [] Read tale (last page) to TBLH and Data Meoy Note None ITABRD [] Increment table pointer TBLP first and Read table to TBLH and Data Memory Note None ITABRDL [] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Meoy Note None Miscellaneous NOP No opeation 1 None CLR [] Clea Data Meoy 1Note None SET [] Set Data Meoy 1Note None CLR WDT Clea Wathdog Tie 1 TO PDF SWAP [] Swap niles of Data Meoy 1Note None SWAPA [] Swap niles of Data Meoy with esult in ACC 1 None HALT Ente powe down ode 1 TO PDF Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT" instruction the T O and PDF flags may be af fected by the execution status. The T O and PDF fla gs a re c leared a fter t he "CL R W DT" i nstructions i s e xecuted. Ot herwise t he T O a nd PDF flags remain unchanged.

Rev. 1.40 3 Deee 1 01 Rev. 1.40 33 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Extended Instruction Set The extended instructions are used to support the full range address access for the data memory . When the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Arithmetic LADD A[] Add Data Meoy to ACC Z C AC OV SC LADDM A[] Add ACC to Data Meoy Note Z C AC OV SC LADC A[] Add Data Meoy to ACC with Cay Z C AC OV SC LADCM A[] Add ACC to Data eoy with Cay Note Z C AC OV SC LSUB A[] Sutat Data Meoy fo ACC Z C AC OV SC CZ LSUBM A[] Sutat Data Meoy fo ACC with esult in Data Meoy Note Z C AC OV SC CZ LSBC A[] Sutat Data Meoy fo ACC with Cay Z C AC OV SC CZ LSBCM A[] Sutat Data Meoy fo ACC with Cay esult in Data Me o y Note Z C AC OV SC CZ LDAA [] Deial adjust ACC fo Addition with esult in Data Meoy Note C Logic Operation LAND A[] Logial AND Data Meoy to ACC Z LOR A[] Logial OR Data Meoy to ACC Z LXOR A[] Logial XOR Data Meoy to ACC Z LANDM A[] Logial AND ACC to Data Meoy Note Z LORM A[] Logial OR ACC to Data Meoy Note Z LXORM A[] Logial XOR ACC to Data Meoy Note Z LCPL [] Copleent Data Meoy Note Z LCPLA [] Copleent Data Meoy with esult in ACC Z Increment & Decrement LINCA [] Ineent Data Meoy with esult in ACC Z LINC [] Ineent Data Meoy Note Z LDECA [] Deeent Data Meoy with esult in ACC Z LDEC [] Deeent Data Meoy Note Z Rotate LRRA [] Rotate Data Meoy ight with esult in ACC None LRR [] Rotate Data Meoy ight Note None LRRCA [] Rotate Data Meoy ight though Cay with esult in ACC C LRRC [] Rotate Data Meoy ight though Cay Note C LRLA [] Rotate Data Meoy left with esult in ACC None LRL [] Rotate Data Meoy left Note None LRLCA [] Rotate Data Meoy left though Cay with esult in ACC C LRLC [] Rotate Data Meoy left though Cay Note C Data Move LMOV A[] Move Data Meoy to ACC None LMOV []A Move ACC to Data Meoy Note None Bit Operation LCLR [].i Clea it of Data Meoy Note None LSET [].i Set it of Data Meoy Note None

Rev. 1.40 3 Deee 1 01 Rev. 1.40 33 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Mnemonic Description Cycles Flag Affected Branch LSZ [] Skip if Data Meoy is zeo Note None LSZA [] Skip if Data Meoy is zeo with data oveent to ACC Note None LSNZ [] Skip if Data Meoy is not zeo Note None LSZ [].i Skip if it i of Data Meoy is zeo Note None LSNZ [].i Skip if it i of Data Meoy is not zeo Note None LSIZ [] Skip if ineent Data Meoy is zeo Note None LSDZ [] Skip if deeent Data Meoy is zeo Note None LSIZA [] Skip if ineent Data Meoy is zeo with esult in ACC Note None LSDZA [] Skip if deeent Data Meoy is zeo with esult in ACC Note None Table Read LTABRD [] Read tale to TBLH and Data Meoy 3Note None LTABRDL [] Read tale (last page) to TBLH and Data Meoy 3Note None LITABRD [] Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL [] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Meoy 3Note None Miscellaneous LCLR [] Clea Data Meoy Note None LSET [] Set Data Meoy Note None LSWAP [] Swap niles of Data Meoy Note None LSWAPA [] Swap niles of Data Meoy with esult in ACC None Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution.

Rev. 1.40 34 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Instruction Definition ADC A,[m] Add D ata M emory to A CC w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C ADCM A,[m] Add A CC to D ata M emory w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C ADD A,[m] Add D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C ADD A,x Add im mediate data to A CC Description The c ontents o f t he A ccumulator a nd t he s pecified im mediate data a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + x Affected fl ag(s) OV, Z , A C, C , S C ADDM A,[m] Add A CC to D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C AND A,[m] Logical A ND D ata M emory t o A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ [ m] Affected fl ag(s) Z AND A,x Logical A ND im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b it w ise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ x Affected fl ag(s) Z ANDM A,[m] Logical A ND A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ AND″ [ m] Affected fl ag(s) Z

Rev. 1.40 34 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver CALL addr Subroutine c all Description Unconditionally c alls a s ubroutine a t t he s pecified a ddress. Th e P rogram C ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. T he sp ecified a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. A s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. Operation Stack ← P rogram Counter + 1 Program C ounter ← a ddr Affected fl ag(s) None CLR [m] Clear D ata M emory Description Each b it o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m] ← 00H Affected fl ag(s) None CLR [m].i Clear bi t o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m].i ← 0 Affected fl ag(s) None CLR WDT Clear W atchdog T imer Description The T O, P DF fl ags a nd t he W DT a re al l c leared. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CPL [m] Complement D ata M emory Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Operation [m] ← [m] Affected fl ag(s) Z CPLA [m] Complement D ata M emory w ith r esult i n A CC Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Th e c omplemented r esult i s s tored i n the A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] Affected fl ag(s) Z DAA [m] Decimal-Adjust A CC f or addition w ith r esult i n D ata M emory Description Convert t he c ontents o f t he A ccumulator v alue to a B CD ( Binary C oded D ecimal) v alue resulting f rom t he p revious a ddition o f t wo B CD v ariables. I f t he low n ibble is greater t han 9 or i f A C fl ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. O therwise t he l ow n ibble remains u nchanged. I f t he h igh n ibble i s g reater t han 9 o r i f t he C fl ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. E ssentially, t he decimal c onversion i s p erformed b y a dding 00H, 0 6H, 6 0H o r 6 6H depending o n t he A ccumulator a nd fl ag c onditions. O nly t he C fl ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal B CD s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. Operation [m] ← A CC + 00H or [m] ← A CC + 06 H o r [m] ← A CC + 60H o r [m] ← A CC + 66H Affected fl ag(s) C

Rev. 1.40 3 Deee 1 01 Rev. 1.40 37 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver DEC [m] Decrement D ata M emory Description Data i n t he s pecified D ata M emory i s d ecremented b y 1 . Operation [m] ← [ m] − 1 Affected fl ag(s) Z DECA [m] Decrement D ata M emory wi th r esult i n A CC Description Data in t he sp ecified D ata M emory is d ecremented b y 1 . T he re sult is s tored in t he Accumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] − 1 Affected fl ag(s) Z HALT Enter p ower down m ode Description This i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. Th e c ontents o f the D ata M emory a nd r egisters a re r etained. Th e W DT a nd p rescaler a re c leared. Th e p ower down fl ag P DF i s s et a nd t he W DT t ime-out fl ag T O i s c leared. Operation TO ← 0 PDF ← 1 Affected fl ag(s) TO, P DF INC [m] Increment D ata M emory Description Data in t he sp ecified D ata M emory is incremented b y 1 . Operation [m] ← [ m] + 1 Affected fl ag(s) Z INCA [m] Increment D ata M emory wi th r esult i n A CC Description Data i n t he sp ecified D ata M emory i s i ncremented b y 1 . Th e re sult i s s tored i n t he A ccumulator. The c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] + 1 Affected fl ag(s) Z JMP addr Jump u nconditionally Description The c ontents o f t he P rogram C ounter a re re placed w ith t he sp ecified a ddress. P rogram execution t hen c ontinues f rom t his n ew a ddress. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. Operation Program Counter ← addr Affected fl ag(s) None MOV A,[m] Move D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. Operation ACC ← [ m] Affected fl ag(s) None MOV A,x Move im mediate data to A CC Description The im mediate data s pecified i s l oaded i nto t he A ccumulator. Operation ACC ← x Affected fl ag(s) None MOV [m],A Move A CC to D ata M emory Description The c ontents o f t he A ccumulator a re c opied to t he s pecified D ata M emory. Operation [m] ← A CC Affected fl ag(s) None

Rev. 1.40 3 Deee 1 01 Rev. 1.40 37 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver NOP No o peration Description No o peration i s p erformed. E xecution c ontinues w ith t he n ext i nstruction. Operation No operation Affected fl ag(s) None OR A,[m] Logical O R D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise logical O R op eration. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ [ m] Affected fl ag(s) Z OR A,x Logical OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical O R operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ x Affected fl ag(s) Z ORM A,[m] Logical OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical O R operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ OR″ [ m] Affected fl ag(s) Z RET Return from s ubroutine Description The P rogram C ounter is re stored f rom t he s tack. P rogram e xecution c ontinues a t t he re stored a ddress. Operation Program Counter ← S tack Affected fl ag(s) None RET A,x Return f rom su broutine and l oad im mediate data to A CC Description The P rogram C ounter i s r estored f rom t he s tack a nd t he A ccumulator l oaded w ith t he s pecified immediate data. P rogram e xecution c ontinues a t t he r estored a ddress. Operation Program Counter ← S tack ACC ← x Affected fl ag(s) None RETI Return from i nterrupt Description The P rogram C ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he EMI b it. E MI i s t he m aster i nterrupt g lobal e nable b it. I f a n i nterrupt w as p ending w hen t he RETI instruction is e xecuted, t he p ending In terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. Operation Program Counter ← S tack EMI ← 1 Affected fl ag(s) None RL [m] Rotate D ata M emory l eft Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← [ m].7 Affected fl ag(s) None

Rev. 1.40 38 Deee 1 01 Rev. 1.40 39 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver RLA [m] Rotate D ata M emory left w ith re sult in A CC Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← [ m].7 Affected fl ag(s) None RLC [m] Rotate D ata M emory l eft t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated l eft b y 1 b it. B it 7 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← C C ← [ m].7 Affected fl ag(s) C RLCA [m] Rotate D ata M emory left t hrough C arry w ith re sult in A CC Description Data i n t he s pecified D ata M emory and t he carry fl ag are r otated l eft b y 1 b it. B it 7 r eplaces t he Carry b it a nd t he o riginal c arry fl ag i s r otated i nto t he b it 0 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← C C ← [ m].7 Affected fl ag(s) C RR [m] Rotate D ata M emory r ight Description The contents of t he s pecified D ata M emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← [ m].0 Affected fl ag(s) None RRA [m] Rotate D ata M emory right with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . Th e r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he Data M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← [ m].0 Affected fl ag(s) None RRC [m] Rotate D ata M emory r ight t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← C C ← [ m].0 Affected fl ag(s) C

Rev. 1.40 38 Deee 1 01 Rev. 1.40 39 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver RRCA [m] Rotate D ata M emory right th rough C arry with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 r eplaces the C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← C C ← [ m].0 Affected fl ag(s) C SBC A,[m] Subtract D ata M emory from A CC wi th C arry Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z SBC A, x Subtract im mediate data f rom A CC w ith Carry Description The immediate da ta a nd t he c omplement o f t he c arry fl ag a re s ubtracted f rom t he Accumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is negative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he C fl ag will be se t t o 1 . Operation ACC ← A CC - [ m] - C Affected fl ag(s) OV, Z , AC , C , S C, CZ SBCM A,[m] Subtract D ata M emory from A CC wi th C arry a nd r esult i n D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he D ata M emory. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z SDZ [m] Skip i f decrement D ata M emory i s 0 Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] − 1 Skip if [ m]=0 Affected fl ag(s) None SDZA [m] Skip i f decrement D ata M emory i s z ero w ith r esult i n A CC Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] − 1 Skip if A CC=0 Affected fl ag(s) None

Rev. 1.40 40 Deee 1 01 Rev. 1.40 41 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SET [m] Set D ata M emory Description Each b it o f t he s pecified D ata M emory i s s et t o 1 . Operation [m] ← F FH Affected fl ag(s) None SET [m].i Set b it o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s s et t o 1 . Operation [m].i ← 1 Affected fl ag(s) None SIZ [m] Skip i f i ncrement D ata M emory i s 0 Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] + 1 Skip if [ m]=0 Affected fl ag(s) None SIZA [m] Skip if increment D ata M emory is z ero w ith re sult in A CC Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] + 1 Skip if A CC=0 Affected fl ag(s) None SNZ [m].i Skip i f D ata M emory i s no t 0 Description If t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m].i ≠ 0 Affected fl ag(s) None SNZ [m] Skip i f D ata M emory i s no t 0 Description If t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m]≠ 0 Affected fl ag(s) None SUB A,[m] Subtract D ata M emory from A CC Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z

Rev. 1.40 40 Deee 1 01 Rev. 1.40 41 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver SUBM A,[m] Subtract D ata M emory from A CC wi th r esult i n D ata M emory Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he D ata M emory. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z SUB A,x Subtract im mediate data f rom A CC Description The im mediate data s pecified b y t he c ode i s s ubtracted f rom t he c ontents o f t he A ccumulator. The re sult is s tored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C flag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − x Affected fl ag(s) OV, Z , A C, C , S C, C Z SWAP [m] Swap ni bbles of D ata M emory Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Operation [m].3~[m].0 ↔ [ m].7~[m].4 Affected fl ag(s) None SWAPA [m] Swap ni bbles of D ata M emory w ith r esult i n A CC Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Th e result i s s tored i n t he A ccumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.3~ACC.0 ← [ m].7~[m].4 ACC.7~ACC.4 ← [ m].3~[m].0 Affected fl ag(s) None SZ [m] Skip i f D ata M emory i s 0 Description If t he contents of t he s pecified D ata M emory i s 0, t he following i nstruction i s s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m]=0 Affected fl ag(s) None SZA [m] Skip i f D ata M emory i s 0 w ith data m ovement to A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. I f t he v alue i s z ero, the f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] Skip if [ m]=0 Affected fl ag(s) None SZ [m].i Skip i f b it i of D ata M emory i s 0 Description If b it i o f t he sp ecified D ata M emory is 0 , t he f ollowing instruction is s kipped. A s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m].i=0 Affected fl ag(s) None

Rev. 1.40 4 Deee 1 01 Rev. 1.40 43 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver TABRD [m] Read ta ble ( specific p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( specific p age) a ddressed b y t he t able p ointer p air (TBLP a nd T BHP) i s mo ved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None TABRDL [m] Read t able (last p age) t o T BLH a nd D ata M emory Description The l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (TBLP) i s mo ved to t he s pecified D ata M emory a nd t he h igh b yte m oved to T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None ITABRD [m] Increment ta ble p ointer l ow b yte fir st and r ead ta ble to T BLH and D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he p rogram code addressed b y t he table p ointer ( TBHP and T BLP) i s m oved to t he s pecified D ata M emory and t he hi gh b yte moved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None ITABRDL [m] Increment t able p ointer l ow by te fi rst a nd r ead t able (last p age) t o T BLH a nd D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( TBLP) i s m oved to t he s pecified D ata M emory and the h igh by te mov ed t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None XOR A,[m] Logical X OR D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ [ m] Affected fl ag(s) Z XORM A,[m] Logical X OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ XOR″ [ m] Affected fl ag(s) Z XOR A,x Logical X OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ x Affected fl ag(s) Z

Rev. 1.40 4 Deee 1 01 Rev. 1.40 43 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add D ata M emory to A CC w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C LADCM A,[m] Add A CC to D ata M emory w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C LADD A,[m] Add D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C LADDM A,[m] Add A CC to D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C LAND A,[m] Logical A ND D ata M emory t o A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ [ m] Affected fl ag(s) Z LANDM A,[m] Logical A ND A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ AND″ [ m] Affected fl ag(s) Z LCLR [m] Clear D ata M emory Description Each b it o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m] ← 00H Affected fl ag(s) None LCLR [m].i Clear bi t o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m].i ← 0 Affected fl ag(s) None

Rev. 1.40 44 Deee 1 01 Rev. 1.40 4 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LCPL [m] Complement D ata M emory Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Operation [m] ← [m] Affected fl ag(s) Z LCPLA [m] Complement D ata M emory w ith r esult i n A CC Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Th e c omplemented r esult i s s tored i n the A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] Affected fl ag(s) Z LDAA [m] Decimal-Adjust A CC f or addition w ith r esult i n D ata M emory Description Convert t he c ontents o f t he A ccumulator v alue to a B CD ( Binary C oded D ecimal) v alue resulting f rom t he p revious a ddition o f t wo B CD v ariables. I f t he low n ibble is greater t han 9 or i f A C fl ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. O therwise t he l ow n ibble remains u nchanged. I f t he h igh n ibble i s g reater t han 9 o r i f t he C fl ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. E ssentially, t he decimal c onversion i s p erformed b y a dding 00H, 0 6H, 6 0H o r 6 6H depending o n t he A ccumulator a nd fl ag c onditions. O nly t he C fl ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal B CD s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. Operation [m] ← A CC + 00H or [m] ← A CC + 06 H o r [m] ← A CC + 60H o r [m] ← A CC + 66H Affected fl ag(s) C LDEC [m] Decrement D ata M emory Description Data i n t he s pecified D ata M emory i s d ecremented b y 1 . Operation [m] ← [ m] − 1 Affected fl ag(s) Z LDECA [m] Decrement D ata M emory wi th r esult i n A CC Description Data in t he sp ecified D ata M emory is d ecremented b y 1 . T he re sult is s tored in t he Accumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] − 1 Affected fl ag(s) Z LINC [m] Increment D ata M emory Description Data in t he sp ecified D ata M emory is incremented b y 1 . Operation [m] ← [ m] + 1 Affected fl ag(s) Z LINCA [m] Increment D ata M emory wi th r esult i n A CC Description Data i n t he sp ecified D ata M emory i s i ncremented b y 1 . Th e re sult i s s tored i n t he A ccumulator. The c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] + 1 Affected fl ag(s) Z

Rev. 1.40 44 Deee 1 01 Rev. 1.40 4 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LMOV A,[m] Move D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. Operation ACC ← [ m] Affected fl ag(s) None LMOV [m],A Move A CC to D ata M emory Description The c ontents o f t he A ccumulator a re c opied to t he s pecified D ata M emory. Operation [m] ← A CC Affected fl ag(s) None LOR A,[m] Logical O R D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise logical O R op eration. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ [ m] Affected fl ag(s) Z LORM A,[m] Logical OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical O R operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ OR″ [ m] Affected fl ag(s) Z LRL [m] Rotate D ata M emory l eft Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← [ m].7 Affected fl ag(s) None LRLA [m] Rotate D ata M emory left w ith re sult in A CC Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← [ m].7 Affected fl ag(s) None LRLC [m] Rotate D ata M emory l eft t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated l eft b y 1 b it. B it 7 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← C C ← [ m].7 Affected fl ag(s) C LRLCA [m] Rotate D ata M emory left t hrough C arry w ith re sult in A CC Description Data i n t he s pecified D ata M emory and t he carry fl ag are r otated l eft b y 1 b it. B it 7 r eplaces t he Carry b it a nd t he o riginal c arry fl ag i s r otated i nto t he b it 0 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← C C ← [ m].7 Affected fl ag(s) C

Rev. 1.40 4 Deee 1 01 Rev. 1.40 47 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LRR [m] Rotate D ata M emory r ight Description The contents of t he s pecified D ata M emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← [ m].0 Affected fl ag(s) None LRRA [m] Rotate D ata M emory right with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it w ith b it 0 rotated i nto b it 7 . Th e r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he Data M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← [ m].0 Affected fl ag(s) None LRRC [m] Rotate D ata M emory r ight t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← C C ← [ m].0 Affected fl ag(s) C LRRCA [m] Rotate D ata M emory right th rough C arry with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 r eplaces the C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← C C ← [ m].0 Affected fl ag(s) C LSBC A,[m] Subtract D ata M emory from A CC wi th C arry Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z LSBCM A,[m] Subtract D ata M emory from A CC wi th C arry a nd r esult i n D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he D ata M emory. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z

Rev. 1.40 4 Deee 1 01 Rev. 1.40 47 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LSDZ [m] Skip i f decrement D ata M emory i s 0 Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] − 1 Skip if [ m]=0 Affected fl ag(s) None LSDZA [m] Skip i f decrement D ata M emory i s z ero w ith r esult i n A CC Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] − 1 Skip if A CC=0 Affected fl ag(s) None LSET [m] Set D ata M emory Description Each b it o f t he s pecified D ata M emory i s s et t o 1 . Operation [m] ← F FH Affected fl ag(s) None LSET [m].i Set b it o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s s et t o 1 . Operation [m].i ← 1 Affected fl ag(s) None LSIZ [m] Skip i f i ncrement D ata M emory i s 0 Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] + 1 Skip if [ m]=0 Affected fl ag(s) None LSIZA [m] Skip if increment D ata M emory is z ero w ith re sult in A CC Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] + 1 Skip if A CC=0 Affected fl ag(s) None LSNZ [m].i Skip i f D ata M emory i s no t 0 Description If t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m].i ≠ 0 Affected fl ag(s) None

Rev. 1.40 48 Deee 1 01 Rev. 1.40 49 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LSNZ [m] Skip i f D ata M emory i s no t 0 Description If t he c ontent o f t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m] ≠ 0 Affected fl ag(s) None LSUB A,[m] Subtract D ata M emory from A CC Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z LSUBM A,[m] Subtract D ata M emory from A CC wi th r esult i n D ata M emory Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he D ata M emory. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z LSWAP [m] Swap ni bbles of D ata M emory Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Operation [m].3~[m].0 ↔ [ m].7~[m].4 Affected fl ag(s) None LSWAPA [m] Swap ni bbles of D ata M emory w ith r esult i n A CC Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Th e result i s s tored i n t he A ccumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.3~ACC.0 ← [ m].7~[m].4 ACC.7~ACC.4 ← [ m].3~[m].0 Affected fl ag(s) None LSZ [m] Skip i f D ata M emory i s 0 Description If t he contents of t he s pecified D ata M emory i s 0, t he following i nstruction i s s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m]=0 Affected fl ag(s) None LSZA [m] Skip i f D ata M emory i s 0 w ith data m ovement to A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. I f t he v alue i s z ero, the f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] Skip if [ m]=0 Affected fl ag(s) None

Rev. 1.40 48 Deee 1 01 Rev. 1.40 49 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver LSZ [m].i Skip if b it i of D ata M emory i s 0 Description If b it i o f t he sp ecified D ata M emory is 0 , t he f ollowing instruction is s kipped. A s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m].i=0 Affected fl ag(s) None LTABRD [m] Read ta ble ( current p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( TBLP) is moved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LTABRDL [m] Read t able (last p age) t o T BLH a nd D ata M emory Description The l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (TBLP) i s mo ved to t he s pecified D ata M emory a nd t he h igh b yte m oved to T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LITABRD [m] Increment ta ble p ointer l ow b yte fir st and r ead ta ble to T BLH and D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he p rogram code addressed b y t he table p ointer ( TBHP and T BLP) i s m oved to t he s pecified D ata M emory and t he hi gh b yte moved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LITABRDL [m] Increment t able p ointer l ow by te fi rst a nd r ead t able (last p age) t o T BLH a nd D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( TBLP) i s m oved to t he s pecified D ata M emory and the h igh by te mov ed t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LXOR A,[m] Logical X OR D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ [ m] Affected fl ag(s) Z LXORM A,[m] Logical X OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ XOR″ [ m] Affected fl ag(s) Z

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Rev. 1.40 0 Deee 1 01 Rev. 1.40 1 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 28-pin SOP (300mil) Outline Dimensions /G32/G38 /G31 /G31/G35 /G31/G34 /G41 /G42 /G43 /G44 /G46 /G43/G27 /G47 /G48 /G61 /G45 Symbol Dimensions in inch Min. Nom. Max. A — 0.40 BSC — B — 0.9 BSC — C 0.01 — 0.00 C’ — 0.70 BSC — D — — 0.104 E — 0.00 BSC — F 0.004 — 0.01 G 0.01 — 0.00 H 0.008 — 0.013 α 0° ― 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.300 BSC — B — 7.00 BSC — C 0.31 — 0.1 C’ — 17.900 BSC — D — — . E — 1.70 BSC — F 0.10 — 0.30 G 0.40 — 1.7 H 0.0 — 0.33 α 0° ― 8°

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 28-pin SSOP (150mil) Outline Dimensions /G32/G38 /G31 /G31/G35 /G31/G34 /G41 /G42 /G43 /G44 /G46 /G43/G27 /G47 /G48 /G61 /G45 Symbol Dimensions in inch Min. Nom. Max. A — 0.3 BSC — B — 0.14 BSC — C 0.008 — 0.01 C’ — 0.390 BSC — D — — 0.09 E — 0.0 BSC — F 0.004 — 0.0098 G 0.01 — 0.00 H 0.004 — 0.010 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — .0 BSC — B — 3.9 BSC — C 0.0 — 0.30 C’ — 9.9 BSC — D — — 1.7 E — 0.3 BSC — F 0.10 — 0. G 0.41 — 1.7 H 0.10 — 0. α 0° — 8°

Rev. 1.40 Deee 1 01 Rev. 1.40 3 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions /G33/G34 /G31/G31 /G31 /G34/G34 /G41 /G42 /G32/G32 /G31/G32 /G45 /G46 /G47 /G48 /G49 /G4A /G4B /G61 /G33/G33 /G32/G33 /G43 /G44 Symbol Dimensions in inch Min. Nom. Max. A — 0.47 BSC — B — 0.394 BSC — C — 0.47 BSC — D — 0.394 BSC — E — 0.03 BSC — F 0.01 0.01 0.018 G 0.03 0.0 0.07 H — — 0.03 I 0.00 — 0.00 J 0.018 0.04 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Dimensions in mm Min. Nom. Max. A — 1.00 BSC — B — 10.00 BSC — C — 1.00 BSC — D — 10.00 BSC — E — 0.80 BSC — F 0.30 0.37 0.4 G 1.3 1.40 1.4 H — — 1.0 I 0.0 — 0.1 J 0.4 0.0 0.7 K 0.09 — 0.0 α 0° — 7°

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 48-pin LQFP (7mm×7mm) Outline Dimensions /G33/G36 /G32/G35 /G33/G37 /G32/G34 /G31/G33 /G31/G32 /G31 /G34/G38 /G41 /G42 /G43 /G44 /G45 /G46 /G47 /G48 /G49 /G4A /G4B /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.34 BSC — B — 0.7 BSC — C — 0.34 BSC — D — 0.7 BSC — E — 0.00 BSC — F 0.007 0.009 0.011 G 0.03 0.0 0.07 H — — 0.03 I 0.00 — 0.00 J 0.018 0.04 0.030 K 0.004 ― 0.008 α 0° ― 7° Symbol Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.0 BSC — F 0.17 0. 0.7 G 1.3 1.40 1.4 H — — 1.0 I 0.0 — 0.1 J 0.4 0.0 0.7 K 0.09 — 0.0 α 0° ― 7°

Rev. 1.40 4 Deee 1 01 Rev. 1.40 Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver 64-pin LQFP (7mm×7mm) Outline Dimensions /G34/G38 /G34/G39 /G33/G33 /G33/G32 /G36/G34 /G31 /G31/G36 /G31/G37 /G41 /G42 /G43 /G44 /G45 /G46 /G47 /G48 /G49 /G4A /G4B /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.34 BSC — B — 0.7 BSC — C — 0.34 BSC — D — 0.7 BSC — E — 0.01 BSC — F 0.00 0.007 0.009 G 0.03 0.0 0.07 H — — 0.03 I 0.00 — 0.00 J 0.018 0.04 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Dimensions in mm Min. Nom. Max. A — 9.00 BSC — B — 7.00 BSC — C — 9.00 BSC — D — 7.00 BSC — E — 0.40 BSC — F 0.13 0.18 0.3 G 1.3 1.40 1.4 H — — 1.0 I 0.0 — 0.1 J 0.4 0.0 0.7 K 0.09 — 0.0 α 0° — 7°

Rev. 1.40 Deee 1 01 Rev. 1.40 PB Deee 1 01 BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver BS66F340/BS66F350/BS66F360/BS66F370 Enhanced Touch A/D Flash MCU with LED Driver Copyight© 01 y HOLTEK SEMICONDUCTOR INC. The infoation appeaing in this Data Sheet is elieved to e auate at the tie of puliation. Howeve Holtek assues no esponsi ility a ising f o the use of the specifications described. The applications mentioned herein are used solely fo the pupose of illustation and Holtek akes no waanty o epesentation that suh appliations will e suita le without fu the odifi ation no e o ends the use of its poduts fo appliation that ay pesent a isk to huan life due to alfuntion o othewise. Holtek's poduts ae not authoized fo use as itial oponents in life suppot devies o systes. Holtek eseves the ight to alte its products without prior notification. For the most up-to-date information, please visit ou we site at http://www.holtek.o.tw.

Product Information

BS66F340 specifications and overview.

Summary

Enhanced Touch A/D Flash MCU with LED Driver December 15, 2016

Description

Enhanced Touch A/D Flash MCU with LED Driver December 15, 2016

Source title BS66F340 Datasheet(PDF) - Holtek Semiconductor Inc

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