Microcontroller

BS87B12A-3

Holtek Semiconductor In...

Touch A/D Flash MCU with OCVP December 05, 2016

Manufacturer: Holtek Semiconductor In...

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Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Revision: V1.20 Date: Deee 0 201Deee 0 201

Rev. 1.20 2 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Table of Contents

Rev. 1.20 2 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

Rev. 1.20 4 Deee 0 201 Rev. 1.20 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

Rev. 1.20 Deee 0 201 Rev. 1.20 7 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

Features

Operating V oltage: ♦ fSYS=8MHz: 2.7V~5.5V ♦ fSYS=12MHz: 2.7V~5.5V ♦ fSYS=16MHz: 4.5V~5.5V
Up to 0.25μs instruction cycle with 16MHz system clock at VDD=5V
Power down and wake-up functions to reduce power consumption
Oscillator T ype: ♦ Internal High Speed RC – HIRC ♦ Internal 32kHz RC – LIRC ♦ External 32.768kHz Crystal – LXT for BS87C16A-3 & BS87D20A-3 only
Fully integrated internal 8/12/16 MHz oscillator requires no external components
Multi-mode operation: FAST, SLOW, IDLE and SLEEP
All instructions executed in one to three instruction cycles
Table read instructions
115 powerful instructions
Up to 8-level subroutine nesting
Bit manipulation instruction Peripheral Features
Program Memory: Up to 8K × 16
Data Memory: Up to 768 × 8
True EEPROM Memory: 64 × 8
Up to 20 touch key functions – fully integrated without requiring external components
Watchdog T imer function
Up to 42 bidirectional I/O lines
Programming I/O source current
Up to 4SCOM & 36SSEG lines Software controlled LCD driver with 1/3 bias
One external interrupt lines shared with I/O pins
Multiple T imer Modules for time measure, input capture, compare match output, PWM output function or single pulse output function
Dual T ime-Base functions for generation of fixed time interrupt signals
Multi-channel 12-bit resolution A/D converter
Over Current/Voltage Protection – OCVP
Serial Interfaces Module – SIM for SPI or I2C
Fully-duplex Universal Asynchronous Receiver and T ransmitter Interface – UART
Low voltage reset function
Low voltage detect function
Wide range of package types

Rev. 1.20 8 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP General Description The serie s of device s is the Fl ash Mem ory type 8-bit high performance RISC archit ecture microcontroller with fully integrated touch key functions. W ith all touch key functions provided internally and with the conve nience of Flash Memory multi-programm ing fea tures, this seri es of devices h as a ll t he f eatures t o o ffer d esigners a r eliable a nd e asy m eans o f i mplementing t ouch switches within their product applications. The touch key functions are fully integrated thus completely eliminating the need for external components. In addition to the Flash Program Memory, ot her memory includes an area of RAM Data Memory as well as an area of true EEPROM Memory for storage of non-volatile data such as serial numbers, calibration data etc. Analog features include a multi-channel 12-bit A/D converter and a Over Current/V oltage Protection module. Protective features such as an internal W atchdog T imer, Low V oltage Reset and Low V oltage Detector functions coupled with excellent noise immunity and ESD protection ensure that reliable operation is maintained in hostile electrical environments. A full choice of internal, external high and low speed oscillators are provided including fully integrated system oscillators which require no external components for its implementation. The ability t o opera te a nd swi tch dyna mically be tween a ra nge of opera ting m odes usi ng di fferent clock sources gives users the ability to optimise microcontroller operation and minimise power consumption. Easy communication with the outside world is provided using the fully integrated SPI or I2C interface functions, while the incl usion of flexible I/O programm ing features, T imer Modules and many other features further enhance device functionality and flexibility. A UAR T module is contained within this series of devices. This interf ace can support applications such as data communication netw orks betw een microcontrollers, low -cost data links betw een PCs and peripheral devices, portable and battery operated device communication, etc. The touch key devices will find excellent use in a huge range of modern T ouch Key product applications such as instrumentation, household appliances, electronically controlled tools to name but a few. Selection Table Most features are common to all devices. The main features distinguishing them are Memory capacity, I/O count, T ime Module number , SSEG lines and touch key number . The following table summarises the main features of each device. Part No. Program Memory Data Memory Data EEPROM I/O External Interrupt A/D Timer Module BS87B12A-3 3k × 1 384 × 8 4 × 8 22 1 12-it × 8 10-it CTM × 1 10-it PTM × 1 BS87C1A-3 4k × 1 12 × 8 4 × 8 30 1 12-it × 8 10-it CTM × 1 10-it PTM × 2 BS87D20A-3 8k × 1 78 × 8 4 × 8 42 1 12-it × 8 10-it CTM × 2 10-it PTM × 2 Part No. Time Base SCOM/ SSEG Touch Key UART SIM Stacks Package BS87B12A-3 2 4/1 12 1 √ 20NSOP 24SOP BS87C1A-3 2 4/20 1 1 √ 24/28SOP 44LQFP BS87D20A-3 2 4/3 20 1 √ 8 28SOP 44LQFP Note: As devices exist in more than one package format, the table reflects the situation for the package with the most pins.

Rev. 1.20 8 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Block Diagram 8-it RISC MCU Coe I/O Tie Modules Flash Poga Meoy EEPROM Data Meoy Flash/EEPROM Pogaing Ciuity (ICP/OCDS) Tie Base SIM (SPI/I2C) Low Voltage Reset Low Voltage Detet Inteupt Contolle * Extenal LXT Os. 12-it A/D Convete RAM Data Meoy UART Intenal HIRC/LIRC Osillatos SCOM/S SEG Wathdog Tie Reset Ciuit Touh Keys OCVP (Copaato+OPA) *: The LXT oscillator is only available for the BS87C16A-3 and BS87D20A-3 devices. Pin Assignment PB0/SSEG0/KEY1 PB1/SSEG1/KEY2 PB2/SSEG2/KEY3 PB3/SSEG3/KEY4 PB4/SSEG4/KEY PB/SSEG/KEY PC0/SSEG8/KEY9/AN0/VREF PC1/SSEG9/KEY10/AN1 PC2/[CTP0B]/SSEG10/KEY11/AN2/[OCVPAI1] PC3/[CTP0]/SSEG11/KEY12/AN3/[OCVPAI2] PA3/SDI/SDA/RX PA0/SDO/PTCK0/SCOM2/ICPDA/OCDSDA PA2/SCS/PTP0I/SCOM3/ICPCK/OCDSCK PA7/SCK/SCL/TX/OCVPVR VDD VSS PA1/SCOM0/OCVPCOUT PA4/INT/CTCK0/SCOM1/OCVPAO PC/PTP0/SSEG13/AN/OCVPAI0 PC4/PTP0B/SSEG12/AN4/OCVPCI BS87B12A-3/BS87BV12A

20 NSOP-A

PC2/[CTP0B]/SSEG10/KEY11/AN2/[OCVPAI1] PC3/[CTP0]/SSEG11/KEY12/AN3/[OCVPAI2] PA3/SDI/SDA/RX PA0/SDO/PTCK0/SCOM2/ICPDA/OCDSDA PA2/SCS/PTP0I/SCOM3/ICPCK/OCDSCK PA7/SCK/SCL/TX/OCVPVR VDD VSS PA1/SCOM0/OCVPCOUT PA4/INT/CTCK0/SCOM1/OCVPAO PC7/CTP0/SSEG1/AN7/OCVPAI2 PC/CTP0B/SSEG14/AN/OCVPAI1 PC/PTP0/SSEG13/AN/OCVPAI0 PC4/PTP0B/SSEG12/AN4/OCVPCI BS87B12A-3/BS87BV12A

24 SOP-A

Rev. 1.20 10 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PB0/SSEG0/KEY1 PB1/SSEG1/KEY2 PB2/SSEG2/KEY3 PB3/SSEG3/KEY4 PB4/SSEG4/KEY PB/PTCK1/SSEG/KEY PB/PTP1/SSEG/KEY7 PB7/PTP1I/SSEG7/KEY8 PC0/SSEG8/KEY9/AN0/VREF PC1/SSEG9/KEY10/AN1 PC2/SSEG10/KEY11/AN2 PC3/SSEG11/KEY12/AN3 PA3/SDI/SDA/RX PA0/SDO/PTCK0/SCOM2/ICPDA/OCDSDA PA2/SCS/PTP0I/SCOM3/ICPCK/OCDSCK PA7/SCK/SCL/TX/OCVPVR VDD VSS PA1/SCOM0/OCVPCOUT PA4/INT/CTCK0/SCOM1/OCVPAO PC7/CTP0/SSEG1/KEY1/AN7/OCVPAI2 PC/CTP0B/SSEG14/KEY1/AN/OCVPAI1 PC/PTP0/SSEG13/KEY14/AN/OCVPAI0 PC4/PTP0B/SSEG12/KEY13/AN4/OCVPCI BS87C16A-3/BS87CV16A PA0/SDO/PTCK0/SCOM2/ICPDA/OCDSDA PA2/SCS/PTP0I/SCOM3/ICPCK/OCDSCK PA7/SCK/SCL/TX/OCVPVR VDD PD1/SSEG17/XT2 PD0/SSEG1/XT1 VSS PA1/SCOM0/OCVPCOUT PA4/INT/CTCK0/SCOM1/OCVPAO PC7/CTP0/SSEG1/KEY1/AN7/OCVPAI2 PC/CTP0B/SSEG14/KEY1/AN/OCVPAI1 PC/PTP0/SSEG13/KEY14/AN/OCVPAI0 PC4/PTP0B/SSEG12/KEY13/AN4/OCVPCI BS87C16A-3/BS87CV16A

28 SOP-A

Rev. 1.20 10 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PC1/SSEG9/KEY10/AN1 NC NC PC2/SSEG10/KEY11/AN2 PC3/SSEG11/KEY12/AN3 NC PC4/PTP0B/SSEG12/KEY13/AN4/OCVPCI PC/PTP0/SSEG13/KEY14/AN/OCVPAI0 NC NC PC/CTP0B/SSEG14/KEY1/AN/OCVPAI1 PB2/SSEG2/KEY3 NC NC PB1/SSEG1/KEY2 PB0/SSEG0/KEY1 NC PA3/SDI/SDA/RX PA0/SDO/PTCK0/SCOM2/ICPDA/OCDSDA NC NC PA2/SCS/PTP0I/SCOM3/ICPCK/OCDSCK PA7/SCK/SCL/TX/OCVPVR VDD PD1/SSEG17/XT2 PD0/SSEG1/XT1 VSS NC PD7 PD PA1/SCOM0/OCVPCOUT PA4/INT/CTCK0/SCOM1/OCVPAO PC7/CTP0/SSEG1/KEY1/AN7/OCVPAI2 PB3/SSEG3/KEY4 PB4/SSEG4/KEY PB/PTCK1/SSEG/KEY PB/PTP1/SSEG/KEY7 PB7/PTP1I/SSEG7/KEY8 NC PD PD4 PD3/PTP1B/SSEG19 PD2/SSEG18 PC0/SSEG8/KEY9/AN0/VREF BS87C16A-3/BS87CV16A

44 LQFP-A

12 13 14 1 1 17 18 19 20 21 22 3433373839 40 41 42 4344 PB0/SSEG0/KEY1 PB1/SSEG1/KEY2 PB2/SSEG2/KEY3 PB3/SSEG3/KEY4 PB4/SSEG4/KEY PB/PTCK1/SSEG/KEY PB/PTP1/SSEG/KEY7 PB7/PTP1I/SSEG7/KEY8 PD3/PTP1B/SSEG19/KEY9 PD2/SSEG18/KEY10 PC0/SSEG8/KEY11/AN0/VREF PC1/SSEG9/KEY12/AN1 PC2/SSEG10/KEY13/AN2 PC3/SSEG11/KEY14/AN3 PA3/SDI/SDA/RX PA0/SDO/PTCK0/SCOM2/ICPDA/OCDSDA PA2/SCS/PTP0I/SCOM3/ICPCK/OCDSCK PA7/SCK/SCL/TX/OCVPVR VDD PD1/SSEG17/XT2 PD0/SSEG1/XT1 VSS PA1/SCOM0/KEY20/OCVPCOUT PA4/INT/CTCK0/SCOM1/KEY19/OCVPAO PC7/CTP0/SSEG1/KEY18/AN7/OCVPAI2 PC/CTP0B/SSEG14/KEY17/AN/OCVPAI1 PC/PTP0/SSEG13/KEY1/AN/OCVPAI0 PC4/PTP0B/SSEG12/KEY1/AN4/OCVPCI BS87D20A-3/BS87DV20A

Rev. 1.20 12 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PC1/SSEG9/KEY12/AN1 PE4/SSEG28 PE/SSEG29 PC2/SSEG10/KEY13/AN2 PC3/SSEG11/KEY14/AN3 PF2/CTP1B/SSEG34 PC4/PTP0B/SSEG12/KEY1/AN4/OCVPCI PC/PTP0/SSEG13/KEY1/AN/OCVPAI0 PE/SSEG30 PE7/SSEG31 PC/CTP0B/SSEG14/KEY17/AN/OCVPAI1 PA7/SCK/SCL/TX/OCVPVR VDD PD1/SSEG17/XT2 PD0/SSEG1/XT1 VSS PF3/SSEG3 PD7/SSEG23 PD/SSEG22 PA1/SCOM0/KEY20/OCVPCOUT PA4/INT/CTCK0/SCOM1/KEY19/OCVPAO PC7/CTP0/SSEG1/KEY18/AN7/OCVPAI2 PB2/SSEG2/KEY3 PE3/SSEG27 PE2/SSEG2 PB1/SSEG1/KEY2 PB0/SSEG0/KEY1 PF0/CTCK1/SSEG32 PA3/SDI/SDA/RX PA0/SDO/PTCK0/SCOM2/ICPDA/OCDSDA PE1/SSEG2 PE0/SSEG24 PA2/SCS/PTP0I/SCOM3/ICPCK/OCDSCK PB3/SSEG3/KEY4 PB4/SSEG4/KEY PB/PTCK1/SSEG/KEY PB/PTP1/SSEG/KEY7 PB7/PTP1I/SSEG7/KEY8 PF1/CTP1/SSEG33 PD/SSEG21 PD4/SSEG20 PD3/PTP1B/SSEG19/KEY9 PD2/SSEG18/KEY10 PC0/SSEG8/KEY11/AN0/VREF BS87D20A-3/BS87DV20A 12 13 14 1 1 17 18 19 20 21 22 34 3 3373839404142 43 44 Note: 1. If the pin-shared pin functi ons have multiple outputs simultaneously , its pin name at the right side of the "/" sign can be used for higher priority. 2. The OCDSDA and OCDSCK pins are the OCDS dedicated pins and only available for the BS87BV12A/ BS87CV16A/BS87DV20A device which is the OCDS EV chip for the BS87B12A-3/BS87C16A-3/ BS87D20A-3 device.

Rev. 1.20 12 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pin Descriptions With the exception of the power pins, all pins on these devices can be referenced by their Port name, e.g. P A0, P A1 etc, which refer to the digital I/O function of the pins. However these Port pins are also sha red wi th ot her func tion suc h a s t he Ana log t o Di gital Conve rter, T imer Modul e pi ns, e tc. The function of each pin is listed in the following table, however the details behind how each pin is configured is contained in other sections of the datasheet. As the Pin Description table shows the situation for the package with the most pins, not all pins in the table will be available on small package sizes. BS87B12A-3 Pad Name Function OPT I/T O/T Description PA0/SDO/PTCK0/ SCOM2/ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO SIMC0 — CMOS SPI data output PTCK0 PTM0C0 ST — PTM0 lok input SCOM2 SLCDC0 — SCOM Softwae LCD COM output ICPDA — ST CMOS ICP Data/Addess pin OCDSDA — ST CMOS OCDS Data/Addess pin fo EV hip only. PA1/SCOM0/ OCVPCOUT PA1 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM0 SLCDC0 — SCOM Softwae LCD COM output OCVPCOUT OCVPC3 — CMOS OCVP opaato output PA2/SCS/PTP0I/ SCOM3/ICPCK/ OCDSCK PA2 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS SIMC0 ST CMOS SPI slave selet PTP0I PTM0C0 PTM0C1 ST — PTM0 aptue input SCOM3 SLCDC0 — SCOM Softwae LCD COM output ICPCK — ST CMOS ICP Clok pin OCDSCK — ST — OCDS Clok pin fo EV hip only. PA3/SDI/SDA/RX PA3 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDI SIMC0 ST — SPI data input SDA SIMC0 ST NMOS I2C data line RX UCR1 ST — UART RX seial data input PA4/INT/CTCK0/ SCOM1/ OCVPAO PA4 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. INT INTEG INTC0 ST — Extenal Inteupt CTCK0 CTM0C0 ST — CTM0 lok input SCOM1 SLCDC0 — SCOM Softwae LCD COM output OCVPAO OCVPC3 — AN OCVP OPA output PA7/SCK/SCL/TX/ OCVPVR PA7 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCK SIMC0 ST CMOS SPI seial lok SCL SIMC0 ST NMOS I2C lok line TX UCR1 — CMOS UART TX seial data output OCVPVR OCVPC1 AN — OCVP DAC efeene voltage input

Rev. 1.20 14 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pad Name Function OPT I/T O/T Description PB0/SSEG0/KEY1 PB0 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG0 SLCDC1 — CMOS Softwae LCD SEG output KEY1 TKM0C1 NSI — Touh key input PB1/SSEG1/KEY2 PB1 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC1 — CMOS Softwae LCD SEG output KEY2 TKM0C1 NSI — Touh key input PB2/SSEG2/KEY3 PB2 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG2 SLCDC1 — CMOS Softwae LCD SEG output KEY3 TKM0C1 NSI — Touh key input PB3/SSEG3/KEY4 PB3 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG3 SLCDC1 — CMOS Softwae LCD SEG output KEY4 TKM0C1 NSI — Touh key input PB4/SSEG4/KEY PB4 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG4 SLCDC1 — CMOS Softwae LCD SEG output KEY TKM1C1 NSI — Touh key input PB/SSEG/KEY PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS Softwae LCD SEG output KEY TKM1C1 NSI — Touh key input PB/SSEG/KEY7 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG SLCDC1 — CMOS Softwae LCD SEG output KEY7 TKM1C1 NSI — Touh key input PB7/SSEG7/KEY8 PB7 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG7 SLCDC1 — CMOS Softwae LCD SEG output KEY8 TKM1C1 NSI — Touh key input PC0/SSEG8/KEY9/ AN0/VREF PC0 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG8 SLCDC2 — CMOS Softwae LCD SEG output KEY9 TKM2C1 NSI — Touh key input AN0 ACERL AN — A/D Convete analog input VREF TMPC0 AN — A/D Convete efeene voltage input PC1/SSEG9/KEY10/ AN1 PC1 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG9 SLCDC2 — CMOS Softwae LCD SEG output KEY10 TKM2C1 NSI — Touh key input AN1 ACERL AN — A/D Convete analog input PC2/[CTP0B]/ SSEG10/KEY11/ AN2/[OCVPAI1] PC2 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. [CTP0B] TMPC0 IFS — CMOS CTM0 inveted output SSEG10 SLCDC2 — CMOS Softwae LCD SEG output KEY11 TKM2C1 NSI — Touh key input AN2 ACERL AN — A/D Convete analog input [OCVPAI1] OCVPC3 IFS AN — OCVP OCP input signal 1 PC3/[CTP0]/SSEG11/ KEY12/AN3/ [OCVPAI2] PC3 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. [CTP0] TMPC0 IFS — CMOS CTM0 non-inveted output SSEG11 SLCDC2 — CMOS Softwae LCD SEG output KEY12 TKM2C1 NSI — Touh key input AN3 ACERL AN — A/D Convete analog input [OCVPAI2] OCVPC3 IFS AN — OCVP OCP input signal 2

Rev. 1.20 1 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87C16A-3 Pad Name Function OPT I/T O/T Description PA0/SDO/PTCK0/ SCOM2/ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO SIMC0 — CMOS SPI data output PTCK0 PTM0C0 ST — PTM0 lok input SCOM2 SLCDC0 — SCOM Softwae LCD COM output ICPDA — ST CMOS ICP Data/Addess pin OCDSDA — ST CMOS OCDS Data/Addess pin fo EV hip only. PA1/SCOM0/ OCVPCOUT PA1 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM0 SLCDC0 — SCOM Softwae LCD COM output OCVPCOUT OCVPC3 — CMOS OCVP opaato output PA2/SCS/PTP0I/ SCOM3/ICPCK/ OCDSCK PA2 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS SIMC0 ST CMOS SPI slave selet PTP0I PTM0C0 PTM0C1 ST — PTM0 aptue input SCOM3 SLCDC0 — SCOM Softwae LCD COM output ICPCK — ST CMOS ICP Clok pin OCDSCK — ST — OCDS Clok pin fo EV hip only. PA3/SDI/SDA/RX PA3 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDI SIMC0 ST — SPI data input SDA SIMC0 ST NMOS I2C data line RX UCR1 ST — UART RX seial data input PA4/INT/CTCK0/ SCOM1/OCVPAO PA4 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. INT INTEG INTC0 ST — Extenal Inteupt CTCK0 CTM0C0 ST — CTM0 lok input SCOM1 SLCDC0 — SCOM Softwae LCD COM output OCVPAO OCVPC3 — AN OCVP OPA output PA7/SCK/SCL/TX/ OCVPVR PA7 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCK SIMC0 ST CMOS SPI seial lok SCL SIMC0 ST NMOS I2C lok line TX UCR1 — CMOS UART TX seial data output OCVPVR OCVPC1 AN — OCVP DAC efeene voltage input PB0/SSEG0/KEY1 PB0 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG0 SLCDC1 — CMOS Softwae LCD SEG output KEY1 TKM0C1 NSI — Touh key input PB1/SSEG1/KEY2 PB1 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC1 — CMOS Softwae LCD SEG output KEY2 TKM0C1 NSI — Touh key input PB2/SSEG2/KEY3 PB2 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG2 SLCDC1 — CMOS Softwae LCD SEG output KEY3 TKM0C1 NSI — Touh key input PB3/SSEG3/KEY4 PB3 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG3 SLCDC1 — CMOS Softwae LCD SEG output KEY4 TKM0C1 NSI — Touh key input

Rev. 1.20 1 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pad Name Function OPT I/T O/T Description PB4/SSEG4/KEY PB4 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG4 SLCDC1 — CMOS Softwae LCD SEG output KEY TKM1C1 NSI — Touh key input PB/PTCK1/SSEG/ KEY PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTCK1 PTM1C0 ST — PTM1 lok input SSEG SLCDC1 — CMOS Softwae LCD SEG output KEY TKM1C1 NSI — Touh key input PB/PTP1/SSEG/ KEY7 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP1 TMPC0 — CMOS PTM1 non-inveted output SSEG SLCDC1 — CMOS Softwae LCD SEG output KEY7 TKM1C1 NSI — Touh key input PB7/PTP1I/SSEG7/ KEY8 PB7 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP1I PTM1C0 PTM1C1 ST — PTM1 aptue input SSEG7 SLCDC1 — CMOS Softwae LCD SEG output KEY8 TKM1C1 NSI — Touh key input PC0/SSEG8/KEY9/ AN0/VREF PC0 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG8 SLCDC2 — CMOS Softwae LCD SEG output KEY9 TKM2C1 NSI — Touh key input AN0 ACERL AN — A/D Convete analog input VREF TMPC0 AN — A/D Convete efeene voltage input PC1/SSEG9/KEY10/ AN1 PC1 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG9 SLCDC2 — CMOS Softwae LCD SEG output KEY10 TKM2C1 NSI — Touh key input AN1 ACERL AN — A/D Convete analog input PC2/SSEG10/KEY11/ AN2 PC2 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG10 SLCDC2 — CMOS Softwae LCD SEG output KEY11 TKM2C1 NSI — Touh key input AN2 ACERL AN — A/D Convete analog input PC3/SSEG11/KEY12/ AN3 PC3 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG11 SLCDC2 — CMOS Softwae LCD SEG output KEY12 TKM2C1 NSI — Touh key input AN3 ACERL AN — A/D Convete analog input PC4/PTP0B/SSEG12/ KEY13/AN4/OCVPCI PC4 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP0B TMPC0 — CMOS PTM0 inveted output SSEG12 SLCDC2 — CMOS Softwae LCD SEG output KEY13 TKM3C1 NSI — Touh key input AN4 ACERL AN — A/D Convete analog input OCVPCI OCVPC3 AN — OCVP OCP input signal / Copaato non- inveting input signal PC/PTP0/SSEG13/ KEY14/AN/OCVPAI0 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP0 TMPC0 — CMOS PTM0 non-inveted output SSEG13 SLCDC2 — CMOS Softwae LCD SEG output KEY14 TKM3C1 NSI — Touh key input AN ACERL AN — A/D Convete analog input OCVPAI0 OCVPC3 AN — OCVP OCP input signal 0

Rev. 1.20 18 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pad Name Function OPT I/T O/T Description PC/CTP0B/SSEG14/ KEY1/AN/OCVPAI1 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP0B TMPC0 — CMOS CTM0 inveted output SSEG14 SLCDC2 — CMOS Softwae LCD SEG output KEY1 TKM3C1 NSI — Touh key input AN ACERL AN — A/D Convete analog input OCVPAI1 OCVPC3 AN — OCVP OCP input signal 1 PC7/CTP0/SSEG1/ KEY1/AN7/OCVPAI2 PC7 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP0 TMPC0 — CMOS CTM0 non-inveted output SSEG1 SLCDC2 — CMOS Softwae LCD SEG output KEY1 TKM3C1 NSI — Touh key input AN7 ACERL AN — A/D Convete analog input OCVPAI2 OCVPC3 AN — OCVP OCP input signal 2 PD0/SEG1/XT1 PD0 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC3 — CMOS Softwae LCD SEG output XT1 CO LXT — LXT pin PD1/SEG17/XT2 PD1 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG17 SLCDC3 — CMOS Softwae LCD SEG output XT2 CO — LXT LXT pin PD2/SEG18 PD2 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG18 SLCDC3 — CMOS Softwae LCD SEG output PD3/PTP1B/SEG19 PD3 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP1B TMPC0 — CMOS PTM1 inveted output SSEG19 SLCDC3 — CMOS Softwae LCD SEG output PD4~PD7 PD4~PD7 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. VDD VDD — PWR — Positive powe supply VSS VSS — PWR — Negative powe supply g ound. Legend: I/T: Input type; O/T: Output type; OPT: Optional by configuration option (CO) or register selection; CMOS: CMOS output; NMOS: NMOS output; SCOM: SCOM output; ST: Schmitt T rigger input; AN: Analog signal; NSI: Non-standard input; PWR: Power; LXT: Low frequency crystal oscillator

Rev. 1.20 18 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87D20A-3 Pad Name Function OPT I/T O/T Description PA0/SDO/PTCK0/ SCOM2/ICPDA/ OCDSDA PA0 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDO SIMC0 — CMOS SPI data output PTCK0 PTM0C0 ST — PTM0 lok input SCOM2 SLCDC0 — SCOM Softwae LCD COM output ICPDA — ST CMOS ICP Data/Addess pin OCDSDA — ST CMOS OCDS Data/Addess pin fo EV hip only. PA1/SCOM0/KEY20/ OCVPCOUT PA1 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCOM0 SLCDC0 — SCOM Softwae LCD COM output KEY20 TKM4C1 NSI — Touh key input OCVPCOUT OCVPC3 — CMOS OCVP opaato output PA2/SCS/PTP0I/ SCOM3/ICPCK/ OCDSCK PA2 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCS SIMC0 ST CMOS SPI slave selet PTP0I PTM0C0 PTM0C1 ST — PTM0 aptue input SCOM3 SLCDC0 — SCOM Softwae LCD COM output ICPCK — ST CMOS ICP Clok pin OCDSCK — ST — OCDS Clok pin fo EV hip only. PA3/SDI/SDA/RX PA3 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SDI SIMC0 ST — SPI data input SDA SIMC0 ST NMOS I2C data line RX UCR1 ST — UART RX seial data input PA4/INT/CTCK0/ SCOM1/KEY19 OCVPAO PA4 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. INT INTEG INTC0 ST — Extenal Inteupt CTCK0 CTM0C0 ST — CTM0 lok input SCOM1 SLCDC0 — SCOM Softwae LCD COM output KEY19 TKM4C1 NSI — Touh key input OCVPAO OCVPC3 — AN OCVP OPA output PA7/SCK/SCL/TX/ OCVPVR PA7 PAWU PAPU ST CMOS Geneal pupose I/O. Registe enaled pull-up and wake-up. SCK SIMC0 ST CMOS SPI seial lok SCL SIMC0 ST NMOS I2C lok line TX UCR1 — CMOS UART TX seial data output OCVPVR OCVPC1 AN — OCVP DAC efeene voltage input PB0/SSEG0/KEY1 PB0 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG0 SLCDC1 — CMOS Softwae LCD SEG output KEY1 TKM0C1 NSI — Touh key input PB1/SSEG1/KEY2 PB1 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC1 — CMOS Softwae LCD SEG output KEY2 TKM0C1 NSI — Touh key input PB2/SSEG2/KEY3 PB2 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG2 SLCDC1 — CMOS Softwae LCD SEG output KEY3 TKM0C1 NSI — Touh key input

Rev. 1.20 20 Deee 0 201 Rev. 1.20 21 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pad Name Function OPT I/T O/T Description PB3/SSEG3/KEY4 PB3 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG3 SLCDC1 — CMOS Softwae LCD SEG output KEY4 TKM0C1 NSI — Touh key input PB4/SSEG4/KEY PB4 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG4 SLCDC1 — CMOS Softwae LCD SEG output KEY TKM1C1 NSI — Touh key input PB/PTCK1/SSEG/ KEY PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTCK1 PTM1C0 ST — PTM1 lok input SSEG SLCDC1 — CMOS Softwae LCD SEG output KEY TKM1C1 NSI — Touh key input PB/PTP1/SSEG/ KEY7 PB PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP1 TMPC — CMOS PTM1 non-inveted output SSEG SLCDC1 — CMOS Softwae LCD SEG output KEY7 TKM1C1 NSI — Touh key input PB7/PTP1I/SSEG7/ KEY8 PB7 PBPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP1I PTM1C0 PTM1C1 ST — PTM1 aptue input SSEG7 SLCDC1 — CMOS Softwae LCD SEG output KEY8 TKM1C1 NSI — Touh key input PC0/SSEG8/KEY11/ AN0/VREF PC0 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG8 SLCDC2 — CMOS Softwae LCD SEG output KEY11 TKM2C1 NSI — Touh key input AN0 ACERL AN — A/D Convete analog input VREF TMPC AN — A/D Convete efeene voltage input PC1/SSEG9/KEY12/ AN1 PC1 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG9 SLCDC2 — CMOS Softwae LCD SEG output KEY12 TKM2C1 NSI — Touh key input AN1 ACERL AN — A/D Convete analog input PC2/SSEG10/ KEY13/AN2 PC2 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG10 SLCDC2 — CMOS Softwae LCD SEG output KEY13 TKM3C1 NSI — Touh key input AN2 ACERL AN — A/D Convete analog input PC3/SSEG11/KEY14/ AN3 PC3 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG11 SLCDC2 — CMOS Softwae LCD SEG output KEY14 TKM3C1 NSI — Touh key input AN3 ACERL AN — A/D Convete analog input PC4/PTP0B/ SSEG12/KEY1/ AN4/OCVPCI PC4 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP0B TMPC — CMOS PTM0 inveted output SSEG12 SLCDC2 — CMOS Softwae LCD SEG output KEY1 TKM3C1 NSI — Touh key input AN4 ACERL AN — A/D Convete analog input OCVPCI OCVPC3 AN — OCVP OCP input signal / Copaato non- inveting input signal PC/PTP0/SSEG13/ KEY1/AN/ OCVPAI0 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP0 TMPC — CMOS PTM0 non-inveted output SSEG13 SLCDC2 — CMOS Softwae LCD SEG output KEY1 TKM3C1 NSI — Touh key input AN ACERL AN — A/D Convete analog input OCVPAI0 OCVPC3 AN — OCVP OCP input signal 0

Rev. 1.20 20 Deee 0 201 Rev. 1.20 21 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pad Name Function OPT I/T O/T Description PC/CTP0B/ SSEG14/KEY17/ AN/OCVPAI1 PC PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP0B TMPC — CMOS CTM0 inveted output SSEG14 SLCDC2 — CMOS Softwae LCD SEG output KEY17 TKM4C1 NSI — Touh key input AN ACERL AN — A/D Convete analog input OCVPAI1 OCVPC3 AN — OCVP OCP input signal 1 PC7/CTP0/SSEG1/ KEY18/AN7/ OCVPAI2 PC7 PCPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP0 TMPC — CMOS CTM0 non-inveted output SSEG1 SLCDC2 — CMOS Softwae LCD SEG output KEY18 TKM4C1 NSI — Touh key input AN7 ACERL AN — A/D Convete analog input OCVPAI2 OCVPC3 AN — OCVP OCP input signal 2 PD0/SEG1/XT1 PD0 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG1 SLCDC3 — CMOS Softwae LCD SEG output XT1 CO LXT — LXT pin PD1/SEG17/XT2 PD1 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG17 SLCDC3 — CMOS Softwae LCD SEG output XT2 CO — LXT LXT pin PD2/SEG18/KEY10 PD2 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG18 SLCDC3 — CMOS Softwae LCD SEG output KEY10 TKM2C1 NSI — Touh key input PD3/PTP1B/SEG19/ KEY9 PD1 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. PTP1B TMPC — CMOS PTM1 inveted output SSEG19 SLCDC3 — CMOS Softwae LCD SEG output KEY9 TKM2C1 NSI — Touh key input PD4/SSEG20 PD4 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG20 SLCDC3 — CMOS Softwae LCD SEG output PD/SSEG21 PD PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG21 SLCDC3 — CMOS Softwae LCD SEG output PD/SSEG22 PD PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG22 SLCDC3 — CMOS Softwae LCD SEG output PD7/SSEG23 PD7 PDPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG23 SLCDC3 — CMOS Softwae LCD SEG output PE0/SSEG24 PE0 PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG24 SLCDC4 — CMOS Softwae LCD SEG output PE1/SSEG2 PE1 PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG2 SLCDC4 — CMOS Softwae LCD SEG output PE2/SSEG2 PE2 PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG2 SLCDC4 — CMOS Softwae LCD SEG output PE3/SSEG27 PE3 PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG27 SLCDC4 — CMOS Softwae LCD SEG output PE4/SSEG28 PE4 PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG28 SLCDC4 — CMOS Softwae LCD SEG output PE/SSEG29 PE PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG29 SLCDC4 — CMOS Softwae LCD SEG output PE/SSEG30 PE PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG30 SLCDC4 — CMOS Softwae LCD SEG output

Rev. 1.20 22 Deee 0 201 Rev. 1.20 23 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pad Name Function OPT I/T O/T Description PE7/SSEG31 PE7 PEPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG31 SLCDC4 — CMOS Softwae LCD SEG output PF0/CTCK1/SSEG32 PF0 PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTCK1 CTM1C0 ST — CTM1 lok input SSEG32 SLCDC — CMOS Softwae LCD SEG output PF1/CTP1/SSEG33 PF1 PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1 TMPC1 ST — CTM1 non-inveted output SSEG33 SLCDC — CMOS Softwae LCD SEG output PF2/CTP1B/SSEG34 PF2 PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. CTP1B TMPC1 ST — CTM1 inveted output SSEG34 SLCDC — CMOS Softwae LCD SEG output PF3/SSEG3 PF3 PFPU ST CMOS Geneal pupose I/O. Registe enaled pull-up. SSEG3 SLCDC — CMOS Softwae LCD SEG output VDD VDD — PWR — Positive powe supply VSS VSS — PWR — Negative powe supply g ound. Legend: I/T: Input type; O/T: Output type; OPT: Optional by configuration option (CO) or register selection; CMOS: CMOS output; NMOS: NMOS output; SCOM: SCOM output; ST: Schmitt T rigger input; AN: Analog signal; NSI: Non-standard input; PWR: Power; LXT: Low frequency crystal oscillator Absolute Maximum Ratings Note: These are stress ratings only . Stresses exceeding the range specified under "Absolute Maximum Ra tings" m ay c ause subst antial da mage t o t hese de vices. Funct ional ope ration of these devices at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect devices reliability.

Rev. 1.20 22 Deee 0 201 Rev. 1.20 23 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP D.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency, pin load conditions, temperature and program instruction type, etc., can all exert an influence on the measured values. Operating Voltage Characteristics Ta= -40°C to 8°C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Opeating Voltage – HIRC fSYS=8MHz 2.7 — . VfSYS=12MHz 2.7 — . fSYS=1MHz 4. — . Opeating Voltage – LXT fSYS=3278Hz 2.7 — . V Opeating Voltage – LIRC fSYS=32kHz 2.7 — . V Standby Current Characteristics Ta=2°C Symbol Standby Mode Test Conditions Min. Typ. Max. Unit VDD Conditions ISTB SLEEP Mode 3V WDT on — 1.3 3.0 μAV — 2.4 .0 IDLE0 Mode – LIRC 3V fSUB=fLIRC=on — 1.3 3.0 μAV — 2.4 .0 IDLE0 Mode – LXT * 3V fSUB=fLXT=on LXTLP=1 — 2. .0 μAV — 10 3V fSUB=fLXT=on LXTLP=0 — 10 μAV — 18 30 IDLE1 Mode – HIRC 3V fSUB on fSYS=8MHz — 0.8 1.2 AV — 1.0 2.0 3V fSUB on fSYS=12MHz — 0.9 1.4 AV — 1.4 2.1 V fSUB on fSYS=1MHz — 2.0 4.0 A Notes: When using the characteristic table data, the following notes should be taken into consideration:

Any digital inputs are setup in a non-floating condition.
All measurements are taken under conditions of no load and with all peripherals in an off state.
There are no DC current paths.
All Standby Current values are taken after a HALT instruction execution thus stopping all instruction execution.
The LXT oscillator is only available for BS87C16A-3 and BS87D20A-3.

Rev. 1.20 24 Deee 0 201 Rev. 1.20 2 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Operating Current Characteristics Ta=2°C Symbol Operating Mode Test Conditions Min. Typ. Max. UnitVDD Conditions IDD SLOW Mode – LIRC 3V fSYS=32kHz — 2 0 μAV — 3 72 SLOW Mode – LXT * 3V fSYS=3278Hz LXTLP=1 — 2 0 μAV — 3 72 3V fSYS=3278Hz LXTLP=0 — 30 0 μAV — 48 9 FAST Mode – HIRC 3V fSYS=8MHz — 1.2 1.8 AV — 2.2 3.3 3V fSYS=12MHz — 1. 2.4 AV — 3.3 .0 V fSYS=1MHz — 4.0 .0 A Notes: When using the characteristic table data, the following notes should be taken into consideration:

Any digital inputs are setup in a non floating condition.
All measurements are taken under conditions of no load and with all peripherals in an off state.
There are no DC current paths.
All Operating Current values are measured using a continuous NOP instruction program loop.
The LXT oscillator is only available for BS87C16A-3 and BS87D20A-3.

Rev. 1.20 24 Deee 0 201 Rev. 1.20 2 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP A.C. Characteristics For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency and temperature etc., can all exert an influence on the measured values. High Speed Internal Oscillator – HIRC – Frequency Accuracy During the program writing operation the writer will trim the HIRC oscillator at a user selected HIRC frequency and user selected voltage of either 3V or 5V. 8/12/16 MHz Symbol Parameter Test Conditions Min Typ Max UnitVDD Temp. fHIRC

8 MHz W ite T i ed

3V/V 2°C -1% 8 +1%

12 MHz W ite T i ed

1 MHz W ite T i ed

V 2°C -1% 1 +1% Notes: 1 . T he 3 V/5V v alues f or VDD a re p rovided a s t hese a re t he t wo se lectable fix ed v oltages a t wh ich t he HIRC frequency is trimmed by the writer. 2. The row below the 3V/5V trim voltage row is provided to show the values for the full VDD range operating voltage. It is recommende d that the trim voltage is fixed at 3V for application voltage ranges 3. The minimum and maximum tole rance values provided in the table are only for the frequency at which the wri ter t rims t he HIRC osc illator. Aft er t rimming a t t his c hosen spe cific freque ncy any cha nge i n HIRC oscillator frequency using the oscillator register control bits by the application program will give a frequency tolerance to within ±20%. Low Speed Oscillators Characteristics – LIRC & LXT * Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Temp. fLIRC LIRC Osillato Fequeny V 2°C -10% 32 +10% kHz fLXT LXT Osillato Fequeny — — — 32.78 — kHz *: The LXT oscillator is only available for BS87C16A-3 and BS87D20A-3.

Rev. 1.20 2 Deee 0 201 Rev. 1.20 27 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Operating Frequency Characteristic Curves System Operating Frequency Operating Voltage 8MHz 12MHz 16MHz 2.7V 4.5V 5.5V System Start Up Time Characteristics Ta= -40°C ~ 8°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions tSST Syste Stat-up Tie Wake-up fo Condition whee fSYS is off — fSYS=fH ~ fH/4 fH=fHIRC — 1 — tHIRC — fSYS=fSUB=fLIRC — 2 — tLIRC — fSYS=fSUB=*fLXT — 128 — tLXT Syste Stat-up Tie Wake-up fo Condition whee fSYS is on — fSYS=fH ~ fH/4 fH=fHIRC — 2 — tH — fSYS=fSUB=fLIRC o *fLXT — 2 — tSUB Syste Speed Swith Tie FAST to Slow Mode o SLOW to FAST Mode — fHIRC switches from off → on — 1 — tHIRC — *fLXT switches from off → on — 128 — tLXT tRSTD Syste Reset Delay Tie Reset Soue fo Powe-on Reset o LVR Hadwae Reset — RRPOR=V/s 2 0 100 sSyste Reset Delay Tie LVRC/WDTC Softwae Reset — — Syste Reset Delay Tie Reset Source from WDT Overflow — — 8.3 1.7 33.3 tSRESET Miniu Softwae Reset Width to Reset — — 4 90 120 μs Notes: 1. For the System Start-up time values, whether fSYS is on or of f depends upon the mode type and the chosen fSYS system oscillator. Details are provided in the System Operating Modes section. 2. The time units, shown by the symbols tHIRC etc. are the inverse of the corresponding frequency values as provided in the frequency tables. For example tHIRC=1/fHIRC, tSYS=1/fSYS etc. 3. If the LIRC is used as the system clock and if it is of f when in the SLEEP Mode, then an additional LIRC start up tim e, tSTART, as provided in the LIRC frequency table, must be added to the tSST time in the table above. 4. T he Sy stem Sp eed Swi tch T ime i s e ffectively t he t ime t aken fo r t he n ewly a ctivated o scillator t o st art u p. 5. The LXT oscillator is only available for BS87C16A-3 and BS87D20A-3.

Rev. 1.20 2 Deee 0 201 Rev. 1.20 27 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Input/Output Characteristics Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VIL Input Low Voltage fo I/O Pots o Input Pins VIH Input High Voltage fo I/O Pots o Input Pins V — 3. — .0 V— — 0.8VDD — VDD IOL Sink Cuent fo I/O Pins 3V VOL=0.1VDD 1 32 — AV 32 4 — IOH Soue Cuent fo I/O Pins 3V VOH=0.9VDD PxPS=00 x=A B C D E o F -1.0 -2.0 — A V -2.0 -4.0 — 3V VOH=0.9VDD PxPS=01 x=A B C D E o F -1.7 -3. — V -3. -7.0 — 3V VOH=0.9VDD PxPS=10 x=A B C D E o F -2. -.0 — V -.0 -10.0 — 3V VOH=0.9VDD PxPS=11 x=A B C D E o F -. -11.0 — V -11.0 -22.0 — RPH Pull-high Resistane fo I/O Pots(Note) 3V — 20 0 100 kΩV — 10 30 0 ILEAK Input leakage uent V VIN=VDD o VIN=VSS — — ±1 μA tTPI TM Captue Input Miniu Pulse Width — — 0.3 — — μs tTCK TM Clok Input Miniu Pulse Width — — 0.3 — — μs tINT Inteupt Input Pin Miniu Pulse Width — — 10 — — μs Note: The RPH inte rnal pull high resistance value is calculated by connecting to ground and enabling the input pin with a pull-high resistor and then measuring the input sink current at the specified supply voltage level. Dividing the voltage by this measured current provides the RPH value. Memory Characteristics Ta= -40°C~8°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VRW VDD fo Read / W ite — — VDDin — VDDax V Program Flash / Data EEPROM Memory tDEW Ease / W ite y le ti e — — — 4 s IDDPGM Pogaing / Ease uent on VDD — — — — .0 A EP Cell Enduane — — 100K — — E/W tRETD ROM Data Retention tie — Ta=2°C — 40 — Yea RAM Data Memory VDR RAM Data Retention voltage — Devie in SLEEP Mode 1.0 — — V

Rev. 1.20 28 Deee 0 201 Rev. 1.20 29 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LVD/LVR Electrical Characteristics Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VLVR Low Voltage Reset Voltage — LVR enaled voltage sele t 2. V -% 2. +% V VLVD Low Voltage Detet Voltage — LVD enaled voltage selet 2.7V 2.7 +% V LVD enaled voltage selet 3.0V 3.0 LVD enaled voltage selet 3.3V 3.3 LVD enaled voltage selet 3.V 3. LVD enaled voltage selet 4.0V 4.0 tLVDS LVDO Stale Tie — Fo LVR enale VBGEN=0 LVD off → on — — 1 μs tLVR Miniu Low Voltage Width to Reset — — 120 240 480 μs tLVD Miniu Low Voltage Width to Inteupt — — 0 120 240 μs A/D Converter Characteristics Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VDD Opeating Voltage — — 2.7 — . V VADI Input Voltage — — 0 — VREF V VREF Refeene Voltage — — 2 — VDD V DNL Diffeential Non-lineaity 3V VREF=VDD tADCK=0.μs o 10μs — — ±3 LSBV INL Integal Non-lineaity 3V VREF=VDD tADCK=0.μs o 10μs — — ±4 LSBV IADC Additional Cuent Consuption fo A/D Convete Enale 3V No load tADCK =0.μs — 1 2 AV — 1. 3 tADCK Clok Peiod — — 0. — 10 μs tON2ST A/D Convete On-to-Stat Tie — — 4 — — μs tADS Sapling Tie — — — 4 — tADCK tADC Convesion Tie (Inluding A/D Saple and Hold Tie) — — — 1 — tADCK Reference Voltage Characteristics Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VBG Bandgap Refeene Voltage — — - 3% 1.09 + 3% V IBG Additional Cuent Consuption fo Bandgap Refeene Voltage Enale — — — 200 300 μA tBG VBG Tun-on Stale Tie — — — — 200 μs Note: The VBG voltage is used as the A/D converter internal signal input.

Rev. 1.20 28 Deee 0 201 Rev. 1.20 29 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Touch Key Electrical Characteristics Ta=2°C Touch Key RC Oscillator 500kHz mode selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only senso (KEY) Osillato Opeating Cuent 3V *fSENOSC=00kHz — 30 0 μAV — 0 120 IREFOSC Only efeene Osillato Opeating Cuent 3V *fREFOSC=00kHz MnTSS=0 — 30 0 μAV — 0 120 3V *fREFOSC=00kHz MnTSS=1 — 30 0 μAV — 0 120 CKEYOSC Senso (KEY) Osillato Extenal Capaito V *fSENOSC=00kHz 10 20 pF CREFOSC Refeene Osillato Intenal Capaito V *fREFOSC=00kHz 10 20 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny V *CEXT=7 8 9 10 11 12 13 14 1 … 0pF 100 00 1000 kHz fREFOSC Refeene Osillato Opeating Fequeny V * CINT=7 8 9 10 11 12 13 14 1 … 0pF 100 00 1000 kHz Note: 1. fSENOSC=500kHz: Adjust KEYn external capacitor to make sure that the Sensor oscillator frequency is equal to 500kHz. 2. fREFOSC=500kHz: Adjust Reference oscilla tor internal capacitor to make sure that the reference oscillator frequency is equal to 500kHz. Touch Key RC Oscillator 1000kHz mode selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only senso (KEY) Osillato Opeating Cuent 3V *fSENOSC=1000kHz — 40 80 μAV — 80 10 IREFOSC Only efeene Osillato Opeating Cuent 3V *fREFOSC=1000kHz MnTSS=0 — 40 80 μAV — 80 10 3V *fREFOSC=1000kHz MnTSS=1 — 40 80 μAV — 80 10 CKEYOSC Senso (KEY) Osillato Extenal Capaito V *fSENOSC=1000kHz 10 20 pF CREFOSC Refeene Osillato Intenal Capaito V *fREFOSC=1000kHz 10 20 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny V *CEXT=1 2 3 4 7 8 9 … 0pF 10 1000 2000 kHz fREFOSC Refeene Osillato Opeating Fequeny V * CINT=1 2 3 4 7 8 9 … 0pF 10 1000 2000 kHz Note: 1. fSENOSC=1000kHz: A djust K EYn external capacitor to make s ure that the S ensor os cillator frequency is equal to 1000kHz. 2. fREFOSC=1000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 1000kHz.

Rev. 1.20 30 Deee 0 201 Rev. 1.20 31 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Touch Key RC Oscillator 1500kHz mode selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only senso (KEY) Osillato Opeating Cuent 3V *fSENOSC=100kHz — 0 120 μAV — 120 240 IREFOSC Only efeene Osillato Opeating Cuent 3V *fREFOSC=100kHz MnTSS=0 — 0 120 μAV — 120 240 3V *fREFOSC=100kHz MnTSS=1 — 0 120 μAV — 120 240 CKEYOSC Senso (KEY) Osillato Extenal Capaito 3V *fSENOSC=100kHz 4 8 1 pF V 10 20 pF CREFOSC Refeene Osillato Intenal Capaito 3V *fREFOSC=100kHz 4 8 1 pF V 10 20 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V *CEXT=1 2 3 4 7 8 9 … 0pF 10 100 3000 kHz V 10 100 3000 kHz fREFOSC Refeene Osillato Opeating Fequeny 3V * CINT=1 2 3 4 7 8 9 … 0pF 10 100 3000 kHz V 10 100 3000 kHz Note: 1. fSENOSC=1500kHz: A djust K EYn external capacitor to make s ure that the S ensor os cillator frequency is equal to 1500kHz. 2. fREFOSC=1500kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 1500kHz. Touch Key RC Oscillator 2000kHz mode selected Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IKEYOSC Only senso (KEY) Osillato Opeating Cuent 3V *fSENOSC=2000kHz — 80 10 μAV — 10 320 IREFOSC Only efeene Osillato Opeating Cuent 3V *fREFOSC=2000kHz MnTSS=0 — 80 10 μAV — 10 320 3V *fREFOSC=2000kHz MnTSS=1 — 80 10 μAV — 10 320 CKEYOSC Senso (KEY) Osillato Extenal Capaito 3V *fSENOSC=2000kHz 4 8 1 pF V 10 20 pF CREFOSC Refeene Osillato Intenal Capaito 3V *fREFOSC=2000kHz 4 8 1 pF V 10 20 pF fKEYOSC Senso (KEY) Osillato Opeating Fequeny 3V *CEXT=1 2 3 4 7 8 9 … 0pF 10 2000 4000 kHz V 10 2000 4000 kHz fREFOSC Refeene Osillato Opeating Fequeny 3V * CINT=1 2 3 4 7 8 9 … 0pF 10 2000 4000 kHz V 10 2000 4000 kHz Note: 1. fSENOSC=2000kHz: A djust K EYn external capacitor to make s ure that the S ensor os cillator frequency is equal to 2000kHz. 2. fREFOSC=2000kHz: Adjust Reference oscillator internal capacitor to make sure that the reference oscillator frequency is equal to 2000kHz.

Rev. 1.20 30 Deee 0 201 Rev. 1.20 31 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IOCVP Additional Cuent Consuption fo OCVP Enale 3V DAC VREF=2.V — — 1.2 AV — 0.73 1.2 VOS_CMP Copaato Input Offset Voltage 3V/V Without aliation OCVPCOF[4:0]=10000 -1 — 1 V 3V/V With aliation -4 — 4 VCM_CMP Copaato Coon Mode Voltage Range 3V/V — VSS — VDD-1.4 V VOS_OPA OPA Input Offset Voltage 3V/V Without aliation OCVPOOF[:0]=100000 -1 — 1 V 3V/V With aliation -4 — 4 VCM_OPA OPA Coon Mode Voltage Range 3V/V — VSS — VDD-1.4 V VHYS Hysteesis 3V/V — 20 40 0 V VOR OPA Maxiu Output Voltage Range 3V/V — VSS+0.1 — VDD-0.1 V Ga PGA Gain Auay (Note) 3V/V — - — % VREF DAC Refeene Voltage 3V/V OCVPVRS=1 2 — VDD V DNL Diffeential Non-lineaity 3V DAC VREF=VDD INL Integal Non-lineaity 3V DAC VREF=VDD Note: The PGA gain accuracy is guaranteed only when the PGA output voltage meets the VOR specification. Software Controlled LCD Electrical Characteristics Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions IBIAS LCD ias uent V μAISEL[1:0]=01 11.7 1.7 21.7 ISEL[1:0]=10 3 0 ISEL[1:0]=11 70 100 130 VSCOM LCD COM 1/3 Bias Level Output — No load 0.317VDD 0.333VDD 0.3VDD VLCD COM 2/3 Bias Level Output 0.34VDD 0.VDD 0.7VDD VSSEG LCD SEG 1/3 Bias Level Output — No load 0.317VDD 0.333VDD 0.3VDD VLCD SEG 2/3 Bias Level Output 0.34VDD 0.VDD 0.7VDD

Rev. 1.20 32 Deee 0 201 Rev. 1.20 33 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP I2C Characteristics Ta=2°C Symbol Parameter Test Condition Min. Typ. Max. UnitVDD Condition fI2C Syste Fequeny fo I2C Standad Mode (100kHz) — No lok deoune 2 — — MHz2 syste loks deoune 4 — — 4 syste loks deoune 8 — — Syste Fequeny fo I2C Fast Mode (400kHz) — No lok deoune — — MHz2 syste loks deoune 10 — — 4 syste loks deoune 20 — — Power-on Reset Characteristics Ta=2°C Symbol Parameter Test Conditions Min. Typ. Max. UnitVDD Conditions VPOR VDD Stat Voltage to Ensue Powe-on Reset — — — — 100 V RRPOR VDD Rising Rate to Ensue Powe-on Reset — — 0.03 — — V/s tPOR Miniu Tie fo VDD Stays at VPOR to Ensue Powe-on Reset — — 1 — — s VDD Tie VPOR tPOR RRPOR

Rev. 1.20 32 Deee 0 201 Rev. 1.20 33 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP System Architecture A key factor in the high-performan ce features of the Holtek range of microcontrollers is attributed to their internal system architecture. The range of devices take advantag e of the usual features found within RIS C microcontrollers providing increas ed s peed of operation and enhanced performance. The pi pelining sc heme i s i mplemented i n suc h a wa y t hat i nstruction fe tching a nd i nstruction execution a re ove rlapped, he nce i nstructions a re e ffectively e xecuted i n one c ycle, wi th t he exception of branch or call instructions. An 8-bit wide ALU is used in practically all instruction set operations, which carries out arithm etic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumulator and the ALU. Certain internal registers are implemented in the Data Memory and can be directly or indirectly addresse d. The simple addressi ng met hods of these registers along with additi onal architectural features ensure that a minimum of external components is required to provide a functional I/ O a nd A/ D c ontrol syst em wi th m aximum re liability a nd fle xibility. T his m akes t hese devices suitable for low-cost, high-volume production for controller applications. Clocking and Pipelining The m ain syst em c lock, de rived from e ither a HIRC, L XT or L IRC osc illator i s subdi vided i nto four internally generated non-overlapping clocks, T1~T4. Note that the LXT oscillator is only available for the BS 87C16A-3 and BS 87D20A-3 devices . The P rogram Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way , one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructio ns takes place in consecutive instruction c ycles, t he pi pelining st ructure of t he m icrocontroller e nsures t hat i nstructions a re effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. For instructions involving branches, such as jump or call instructions, two machine cycles are required to complete instruction execution. An extra cycle is required as the program takes one cycle t o first obt ain t he a ctual j ump or c all a ddress a nd t hen a nother c ycle t o a ctually e xecute t he branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications. Feth Inst. (PC) (Syste Clok) fSYS Phase Clok T1 Phase Clok T2 Phase Clok T3 Phase Clok T4 Poga Counte PC PC+1 PC+2 Pipelining Exeute Inst. (PC-1) Feth Inst. (PC+1) Exeute Inst. (PC) Feth Inst. (PC+2) Exeute Inst. (PC+1) System Clocking and Pipelining

Rev. 1.20 34 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Feth Inst. 1 1 MOV A[12H]

2 CALL DELAY

3 CPL [12H]

4 : DELAY: NOP Exeute Inst. 1 Feth Inst. 2 Exeute Inst. 2 Feth Inst. 3 Flush Pipeline Feth Inst. Exeute Inst. Feth Inst. 7 Instruction Fetching Program Counter During pro gram e xecution, t he Progr am Co unter i s use d t o ke ep t rack of t he a ddress of t he next instruction to be executed. It is automatically incremented by one each time an instruction is e xecuted e xcept for i nstructions, suc h a s "JMP" or "CAL L" t hat de mand a j ump t o a non- consecutive Program Memory address. Only the lower 8 bits, known as the Program Counter Low Register, are directly addressable by the application program. When execut ing instructi ons re quiring jumps to non-consecutive addresses such as a jump instruction, a subrout ine c all, i nterrupt or re set, e tc., t he m icrocontroller m anages progra m c ontrol by loading the required address into the Program Counter . For conditional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execut ion, is discarded and a dummy cycle takes its place while the correct instruction is obtained. Device Program Counter High Byte Low Byte (PCL) BS87B12A-3 PC11~PC8 PC7~PC0 BS87C1A-3 PC11~PC8 PC7~PC0 BS87D20A-3 PC12~PC8 PC7~PC0 Program Counter The lower byte of the Program Counter , known as the Program Counter Low register or PCL, is available for program control and is a readable and writeable register . By transferring data directly into t his r egister, a sh ort p rogram j ump c an b e e xecuted d irectly; h owever, a s o nly t his l ow b yte is available for manipulation, the jumps are limited to the present page of memory that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. Manipulating the PCL register may cause program branching, so an extra cycle is needed to pre-fetch. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack has multiple levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the Stack Pointer , and is neither readable nor writeable. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt routine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the acknowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow allo wing the programmer to use the struct ure more easily . However , when the stack is full, a CALL subroutine instruction can still be execu ted which will result in a stack overflow . Precautions should be taken to avoid such cases which might cause unpredictable program branching.

Rev. 1.20 34 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP If the stack is overflow, the first Program Counter save in the stack will be lost. Stak Pointe Stak Level 2 Stak Level 1 Stak Level 3 Stak Level N Poga Meoy Poga Counte Botto of Stak Top of Stak Note: N=6 for BS87B12A-3 & BS87C16A-3 while N=8 for BS87D20A-3. Arithmetic and Logic Unit – ALU The arith metic-logic unit or ALU is a critical area of the microcontrol ler that carries out arithmetic and logic operations of the instructi on set. Connected to the main micro controller data bus, the ALU receives related ins truction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register . As these ALU calculation or operations may result in carry , borrow or other status changes, the status register will be correspondingly updated to reflect these changes. The ALU supports the following functions:

Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA LADD, LADDM, LADC, LADCM, LSUB, LSUBM, LSBC, LSBCM, LDAA
Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA LAND, LOR, LXOR, LANDM, LORM, LXORM, LCPL, LCPLA
Rotation: RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC LRRA, LRR, LRRCA, LRRC, LRLA, LRL, LRLCA, LRLC
Increment and Decrement: INCA, INC, DECA, DEC LINCA, LINC, LDECA, LDEC
Branch decision: JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI LSZ, LSZA, LSNZ, LSIZ, LSDZ, LSIZA, LSDZA

Rev. 1.20 3 Deee 0 201 Rev. 1.20 37 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Flash Program Memory The Program Memory is the location where the user code or program is stored. For these devices series the Program Memory are Flash type, which means it can be programmed and re-programmed a l arge num ber of t imes, a llowing t he use r t he c onvenience of c ode m odification on t he sa me device. By using the appropriate programming tools, these Flash device s of fer users the flexibility to conveniently debug and develop their applications while also of fering a means of field programming and updating. Device Capacity BS87B12A-3 3K × 1 BS87C1A-3 4K × 1 BS87D20A-3 8K × 1 Structure The Program Memory has a capaci ty of 3K×16 to 8K×16 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. T able data, which c an b e se tup i n a ny l ocation wi thin t he Pr ogram Me mory, i s a ddressed b y a se parate t able pointer registers. 000H Initialisation Veto 004H 0BFFH 1 its Inteupt Vetos Look-up Tale n00H nFFH BS87B12A-3 Initialisation Veto 1 its Inteupt Vetos Look-up Tale Initialisation Veto 1 its Inteupt Vetos Look-up Tale 0FFFH 03CH BS87C16A-3 BS87D20A-3 1FFFH Program Memory Structure Special Vectors Within the Program Memory , certai n locations are reserved for the reset and interrupts. The location 000H is reserved for use by these devices reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution.

Rev. 1.20 3 Deee 0 201 Rev. 1.20 37 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. T o use the look-up table, the table pointer must first be setup by placing the address of the look up data to be retrieved in the table pointer register , TBLP and TBHP . These registers define the total address of the look-up table. After se tting u p t he t able p ointer, t he t able d ata c an b e r etrieved f rom t he Pr ogram Me mory u sing the "T ABRD [m]" or "T ABRDL [m]" instructions respectively when the memory [m] is located in sector 0. If the memory [m] is locate d in other sectors except sector 0, the data can be retrieved from the program memory using the corresponding extended t able read i nstruction such a s "L TABRD [m]" or "L TABRDL [m]" respectively . When the instruction is executed, the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register [m] as specified in the instruction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as "0". The accompanying diagram illustrates the addressing data flow of the look-up table. Last Page o TBHP Registe Addess TBLP Registe Data 1 its Program Memory Registe TBLH Use Seleted Registe High Byte Low Byte Table Program Example The accompanying example shows how the table pointer and table data is defined and retrieved from the devic e. This example uses raw table data located in the last page which is stored there using the ORG st atement. T he va lue a t t his ORG st atement i s "1 F00H" whi ch re fers t o t he st art a ddress of the las t page within the 8K Program Memory of the device. The table pointer low byte regis ter is setup here to have an initial value of "06H". This will ensure that the first data read from the data table will be at the Program Memory address "1F06H" or 6 locations after the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page pointed by the TBHP register if the "T ABRD [m]" instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the "TABRD [m]" instruction is executed. Because the TBLH register is a read/write register and can be restored, care should be taken to ensure its protection if both the main routine and Interrupt S ervice Routine us e table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However , in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation.

Rev. 1.20 38 Deee 0 201 Rev. 1.20 39 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Table Read Program Example tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 mov a ,06h ; initialise low table pointer - note that this address is referenced mov t blp,a ; to the last page or the page that tbhp pointed mov a ,1fh ; initialise high table pointer mov tbhp,a tabrd t empreg1 ; transfers value in table referenced by table pointer data at program ; memory address "1F06H" transferred to tempreg1 and TBLH dec t blp ; reduce value of table pointer by one tabrd t empreg2 ; transfers value in table referenced by table pointer data at program ; memory address "1F05H" transferred to tempreg2 and TBLH in this ; example the data "1AH" is transferred to tempreg1 and data "0FH" to ; register tempreg2 org 1 F00h ; sets initial address of program memory dc 00 Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh In Circuit Programming – ICP The p rovision o f Fl ash t ype Pr ogram Me mory p rovides t he u ser wi th a m eans o f c onvenient a nd easy upgrades and modifications to their programs on the same device. As an additional convenience, Holtek has provided a means of programming the microcontroller in- circuit using a 4-pin interface. This provides manufacturers with the possibility of manufacturing their circuit boards complete with a programmed or un-programmed microcontroller , and then programming o r u pgrading t he p rogram a t a l ater st age. T his enables product m anufacturers to e asily keep thei r manufa ctured products supplied with the latest program releases without removal and re- insertion of the device. Holtek Writer Pins MCU Programming Pins Pin Description ICPDA PA0 Pogaing Seial Data/Addess ICPCK PA2 Pogaing Clok VDD VDD Powe Supply VSS VSS Gound The Program Memory and EEPROM data memory can be programmed serially in-circuit using this 4-wire interface. Data is downloaded and uploaded serially on a single pin with an additional line for the clock. T wo additional lines are required for the power supply . The technical details regarding the in-cir cuit programming of the device are beyond the scope of this document and will be supplied in supplementary literature. During the programming process, the user must take care of the ICPDA and ICPCK pins for data and clock programming purposes to ensure that no other outputs are connected to these two pins.

Rev. 1.20 38 Deee 0 201 Rev. 1.20 39 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP * * Wite_VDD ICPDA ICPCK Wite_VSS To othe Ciuit VDD PA0 PA2 VSS Wite Conneto Signals MCU Pogaing Pins Note: * may be resistor or capacito r. The resistance of * must be great er than 1k or the capacitance of * must be less than 1nF. On-Chip Debug Support – OCDS There are EV chips named BS87BV12A, BS87CV16A and BS87DV20A which are used to emulate the real MCU device named BS87B12A-3, BS87C16A-3 and BS87D20A-3 respectively . The EV chip device also provides the "On-Chip Debug" function to debug the real MCU device during development process. The EV chips and real MCU devices are almost functional compatible except the "On-Chip Debug" function. Users can use the EV chip device to emulate the real MCU device behaviors by connecting the OCDSDA and OCDSCK pins to the Holtek HT-IDE development tools. The OCDSDA pin is the OCDS Data/Address input/output pin while the OCDSCK pin is the OCDS clock input pin. When users use the EV chip device for debugging, the corresponding pin functions shared with the OCDSDA and OCDSCK pins in the real MCU device will have no ef fect in the EV chip. Howe ver, t he t wo OCDS pins whi ch are pin-share d wi th t he ICP program ming pins are st ill used as the Flash Memory programm ing pins for ICP . For more detailed OCDS information, refer to the corresponding document named "Holtek e-Link for 8-bit MCU OCDS User’s Guide". Holtek e-Link Pins EV Chip OCDS Pins Pin Description OCDSDA OCDSDA On-Chip Deug Suppot Data/Addess input/output OCDSCK OCDSCK On-Chip Deug Suppot Clok input VDD VDD Powe Supply VSS VSS Gound

Rev. 1.20 40 Deee 0 201 Rev. 1.20 41 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Data Memory The Dat a Mem ory is an 8-bit wide RAM inte rnal me mory and is the locat ion where te mporary information is stored. Structure Divided into two types, the first of Data Memory is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. M any of these registers can be read from and w ritten to directly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. The Da ta Me mory i s subdi vided i nto se veral se ctors, a ll of wh ich a re i mplemented i n 8-b it wi de Memory. Each of the Data Memory sectors is categorized into two types, the Special Purpose Data Memory and the General Purpose Data Memory. The address range of the Special Purpose Data Memory for the device is from 00H to 7FH while the General Purpose Data Memory address range is from 80H to FFH. Switching between the dif ferent Data Memory sectors is achieved by properly setting the Memory Pointers to correct value. Device Special Purpose Data Memory General Purpose Data Memory Sector : Address Capacity Sector : Address BS87B12A-3 0~2: 00H~7FH (EEC @40H only aessile in Seto 1) 384 x 8 0~2: 80H~FFH BS87C1A-3 0~3: 00H~7FH (EEC @40H only aessile in Seto 1) 12 x 8 0~3: 80H~FFH BS87D20A-3 0~: 00H~7FH (EEC @40H only aessile in Seto 1) 78 x 8 0~: 80H~FFH Data Memory Summary 00H 7FH 80H FFH Speial Pupose Data Meoy Geneal Pupose Data Meoy Seto 0 Seto 1 Seto N (Seto 0 ~ Seto 1) (Seto 0 ~ Seto N) 40H in Seto 1 Note: N=2 fo BS87B12A-3; N=3 fo BS87C1A-3; N= fo BS87D20A-3 FH in Seto 1 Data Memory Structure

Rev. 1.20 40 Deee 0 201 Rev. 1.20 41 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Data Memory Addressing For these devices that support the extended instructions, there is no Bank Pointer for Data Memory . For Data Memory the desired Sector is pointed by the MP1H or MP2H register and the certain Data Memory address in the selected sector is specified by the MP1L or MP2L register when using indirect addressing access. Direct Addressing can be used in all sectors using the corresponding instruction which can address all available data memory space. For the accessed data memory which is located in any data memory s ectors except s ector 0, the extended ins tructions can be us ed to acces s the data memory instead o f u sing t he i ndirect a ddressing a ccess. T he m ain d ifference b etween st andard i nstructions and exten ded instructions is that the data memory address "m" in the extended instructions can be from 10 to 1 1 bits depending upon which device is selected, the high byte indicates a sector and the low byte indicates a specific address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieve d for use later . It is this area of RAM memory that is known as General Purpose Data Mem ory. T his a rea of Da ta Mem ory i s ful ly a ccessible by t he user program ming for bot h reading and writing operations. By using the bit operation instructions individual bits can be set or reset under program control gi ving the user a lar ge range of flexibili ty for bi t manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writeable but some are protected and are readable only , the details of which are located under the relevant Special Function Register section. Note that for locat ions that are unused, any read instruction to these addresses will return the value "00H".

Rev. 1.20 42 Deee 0 201 Rev. 1.20 43 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP 00H IAR0 01H MP0 02H IAR1 03H MP1L 04H 0H ACC 0H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH 0DH 0EH 0FH 10H INTC0 11H 12H 19H PAPU 18H PAWU 1BH 1AH 1DH 1CH 1FH PA PAC 13H 14H 17H : Unused ead as 00H 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 27H EEA 40H 41H 42H 43H 44H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH EED 1EH EEC Seto 0~2 Seto 0 2 Seto 1 H H H H AH BH FH 70H30H 31H 32H 38H 3CH 33H 34H 37H 3BH 39H 3AH 71H 72H 73H 74H 7BH 3DH 3FH 3EH 7FH MP1H IAR2 MP2L MP2H AH BH CH DH EH FH OCVPCCAL INTEG INTC1 INTC2 CTM0C0 77H 78H 79H 7AH IFS ACERL 7CH 7DH 7EH INTC3 LVDC LVRC TBC PSCR SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 SADOL SADC0 SADOH SADC1 SLEDC1 SLEDC0 EH DH CH USR UCR1 UCR2 TXR_RXR BRG SMOD PBC PBPU PB WDTC PCC PCPU PC TMPC0 SLCDC0 SLCDC1 SLCDC2 OCVPC0 CTRL OCVPC1 OCVPC2 OCVPC3 PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH TKTMR TKC0 TK1DL TK1DH TKC1 TKM01DL TKM01DH TKM0ROL TKM0ROH TKM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH TKM0C1 TKM11DL TKM11DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM21DL TKM21DH TKM2ROL TKM2ROH TKM2C0 TKM2C1 OCVPOCAL OCVPDA Special Purpose Data Memory Structure – BS87B12A-3

Rev. 1.20 42 Deee 0 201 Rev. 1.20 43 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP 00H 01H MP0 02H IAR1 03H MP1L 04H 0H ACC 0H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH 0DH 0EH 0FH 10H INTC0 11H 12H 19H PAPU 18H PAWU 1BH 1AH 1DH 1CH 1FH PA PAC 13H 14H 17H : Unused ead as 00H 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 27H EEA 40H 41H 42H 43H 44H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH EED 1EH EEC Seto 0~3 Seto 0 2~3 Seto 1 H H H H AH BH FH 70H30H 31H 32H 38H 3CH 33H 34H 37H 3BH 39H 3AH 71H 72H 73H 74H 7BH 3DH 3FH 3EH 7FH MP1H IAR2 MP2L MP2H AH BH CH DH EH FH OCVPCCAL INTEG INTC1 INTC2 CTM0C0 77H 78H 79H 7AH MFI ACERL 7CH 7DH 7EH INTC3 LVDC LVRC TBC PSCR SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 SADOL SADC0 SADOH SADC1 SLEDC1 SLEDC0 EH DH CH USR UCR1 UCR2 TXR_RXR BRG SMOD PBC PBPU PB WDTC PCC PCPU PC PD PDC PDPU TMPC0 SLCDC0 SLCDC1 SLCDC2 OCVPC0 CTRL OCVPC1 OCVPC2 OCVPC3 PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH TKTMR TKC0 TK1DL TK1DH TKC1 TKM01DL TKM01DH TKM0ROL TKM0ROH TKM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH TKM0C1 TKM11DL TKM11DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM21DL TKM21DH TKM2ROL TKM2ROH TKM2C0 TKM2C1 OCVPOCAL OCVPDA SLCDC3 IAR0 TKM31DL TKM31DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH Special Purpose Data Memory Structure – BS87C16A-3

Rev. 1.20 44 Deee 0 201 Rev. 1.20 4 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP 00H 01H MP0 02H IAR1 03H MP1L 04H 0H ACC 0H PCL 07H TBLP 08H TBLH 09H TBHP 0AH STATUS 0BH 0CH 0DH 0EH 0FH 10H INTC0 11H 12H 19H PAPU 18H PAWU 1BH 1AH 1DH 1CH 1FH PA PAC 13H 14H 17H : Unused ead as 00H 20H 21H 22H 29H 28H 2BH 2AH 2DH 2CH 2FH 2EH 23H 24H 27H EEA 40H 41H 42H 43H 44H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH EED 1EH EEC Seto 0~ Seto 0 2~ Seto 1 H H H H AH BH FH 70H30H 31H 32H 38H 3CH 33H 34H 37H 3BH 39H 3AH 71H 72H 73H 74H 7BH 3DH 3FH 3EH 7FH MP1H IAR2 MP2L MP2H AH BH CH DH EH FH OCVPCCAL INTEG INTC1 INTC2 77H 78H 79H 7AH MFI ACERL 7CH 7DH 7EH INTC3 LVDC LVRC TBC PSCR SIMTOC SIMC0 SIMC1 SIMD SIMA/SIMC2 SADOL SADC0 SADOH SADC1 SLEDC1 SLEDC0 EH DH CH USR UCR1 UCR2 TXR_RXR BRG SMOD PBC PBPU PB WDTC PCC PCPU PC PD PDC PDPU TMPC0 SLCDC0 SLCDC1 SLCDC2 OCVPC0 CTRL OCVPC1 OCVPC2 OCVPC3 PTM0C0 PTM0C1 PTM0DL PTM0DH PTM0AL PTM0AH PTM0RPL PTM0RPH TKM11DL TKM11DH TKM1ROL TKM1ROH TKM1C0 TKM1C1 TKM21DL TKM21DH TKM2ROL TKM2ROH TKM2C0 TKM2C1 OCVPOCAL OCVPDA SLCDC3 IAR0 TKM31DL TKM31DH TKM3ROL TKM3ROH TKM3C0 TKM3C1 PTM1C0 PTM1C1 PTM1DL PTM1DH PTM1AL PTM1AH PTM1RPL PTM1RPH PE PEC PEPU TKTMR TKC0 TK1DL TK1DH TKC1 PF PFC PFPU SLEDC2 SLCDC4 SLCDC TMPC1 TKM0C1 TKM0ROL TKM0ROH TKM0C0 TKM01DL TKM01DH TKM41DL TKM41DH TKM4ROL TKM4ROH TKM4C0 TKM4C1 CTM0C0 CTM0C1 CTM0DL CTM0DH CTM0AL CTM0AH CTM1C0 CTM1C1 CTM1DL CTM1DH CTM1AL CTM1AH Special Purpose Data Memory Structure – BS87D20A-3

Rev. 1.20 44 Deee 0 201 Rev. 1.20 4 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Special Function Register Description Most of the Special Function Register details will be described in the relevant functional section. However, several registers require a separate description in this section. Indirect Addressing Registers – IAR0, IAR1, IAR2 The Indirect Addressing Registers, IAR0, IAR1 and IAR2, although having their locations in normal RAM r egister sp ace, d o n ot a ctually p hysically e xist a s n ormal r egisters. T he m ethod o f i ndirect addressing for RAM da ta m anipulation use s t hese Indi rect Addre ssing Re gisters a nd Me mory Pointers, i n c ontrast t o di rect m emory a ddressing, where t he a ctual m emory a ddress i s spe cified. Actions on t he IAR0, IAR1 a nd IAR2 re gisters wi ll re sult i n no a ctual re ad or write ope ration t o these registers but rather to the memory location specified by their corresponding Memory Pointers, MP0, MP1L/MP1H or MP2L/MP2H. Acting as a pair , IAR0 and MP0 can together access data only from Sector 0 while the IAR1 register together with MP1L/MP1H register pair and IAR2 register together with MP2L/MP2H register pair can access data from any Data Memory sector . As the Indirec t Addressing Regi sters a re not physi cally i mplemented, rea ding t he Indirec t Addressing Registers indirectl y will return a result of "00H" and writing to the registers indirectly will result in no operation. Memory Pointers – MP0, MP1H/MP1L, MP2H/MP2L Five Memory Pointers, known as MP0, MP1L, MP1H, MP2L and MP2H, are provided. These Memory Pointers are phys ically implemented in the D ata M emory and can be manipulated in the same wa y a s n ormal r egisters p roviding a c onvenient wa y wi th wh ich t o a ddress a nd t rack d ata. When any operati on to the relevant Indirect Addressing Registers is carried out, the actual address that the microcontroller is directed to is the address specified by the related Memory Pointer . MP0, together with Indirect Addressing Register , IAR0, are used to access data from Sector 0, while MP1L/MP1H together with IAR1 and MP2L/MP2H together with IAR2 are used to access data from all data sectors according to the corresponding MP1H or MP2H register. Direct Addressing can be used in all data sectors using the corresponding instruction which can address all available data memory space. Indirect Addressing Program Example

Example 1 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 code org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp0,a ; setup memory pointer with first RAM address loop: clr IAR0 ; clear the data at address defined by MP0 inc mp0 ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue:

Rev. 1.20 4 Deee 0 201 Rev. 1.20 47 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

Example 2 data .section ‘data’ adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0 ‘code’ org 00h start: mov a,04h ; setup size of block mov block,a mov a,01h ; setup the memory sector mov mp1h,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp1l,a ; setup memory pointer with first RAM address loop: clr IAR1 ; clear the data at address defined by MP1 inc mp1l ; increment memory pointer MP1L sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses. Direct Addressing Program Example using extended instructions data .section ‘data’ temp db ? code .section at 0 code org 00h start: lmov a ,[m] ; move [m] data to acc lsub a , [m+1] ; compare [m] and [m+1] data snz c ; [m]>[m+1]? jmp continue ; no lmov a ,[m] ; yes, exchange [m] and [m+1] data mov temp,a lmov a,[m+1] lmov [m],a mov a,temp lmov [m+1],a continue: Note: Here "m" is a data memory address located in any data memory sectors. For example, m=1F0H, it indicates address 0F0H in Sector 1. Accumulator – ACC The A ccumulator is central to the operation of any microcontroller and is clos ely related w ith operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. W ithout the Accumulator it would be necessary to write the result of each c alculation or l ogical ope ration suc h a s a ddition, subt raction, shi ft, e tc., t o t he Da ta Me mory resulting i n highe r program ming and t iming overheads. Da ta t ransfer operat ions usual ly i nvolve the t emporary st orage func tion of t he Ac cumulator; for e xample, whe n t ransferring da ta be tween one user -defined register and another , it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted.

Rev. 1.20 4 Deee 0 201 Rev. 1.20 47 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Program Counter Low Register – PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to programmers by locating it within the Special Purpose area of the Data Memory . By manipulating this register , direct jumps to other program locations are easily implemented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory location; however, as the register is only 8-bit wide, only jumps within the current Program Memory page are permitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers – TBLP, TBHP, TBLH These t hree spe cial func tion re gisters a re use d t o c ontrol ope ration of t he l ook-up t able whi ch is st ored i n t he Pr ogram Me mory. T he T BLP a nd T BHP r egisters a re t he t able p ointer p air a nd indicates t he l ocation wh ere t he t able d ata i s l ocated. T heir v alue m ust b e se tup b efore a ny t able read instructions are executed. Thei r value can be changed, for examp le using the "INC" or "DEC" instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user defined location. Status Register – STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), SC flag, CZ flag, power down flag (PDF), and watchdog time-out flag (T O). These arithmetic/ logical o peration a nd sy stem m anagement fla gs a re u sed t o r ecord t he st atus a nd o peration o f t he microcontroller. With the exceptio n of the T O and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the T O or PDF flag. In addition, operations related to the status register may give dif ferent results due to the dif ferent instruction operati ons. The T O flag can be af fected only by a system power -up, a WDT time-out or by executing the "CLR WDT" or "HAL T" instruction. The PDF flag is af fected only by executing the "HALT" or "CLR WDT" instruction or during a system power-up. The Z, OV, AC, C, SC and CZ flags generally reflect the status of the latest operations.

C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction.
AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared.
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PDF is cleared by a system power-up or executing the "CLR WDT" instruction. PDF is set by executing the "HALT" instruction.
TO is cleared by a system power-up or executing the "CLR WDT" or "HALT" instruction. T O is set by a WDT time-out.
SC is the result of the "XOR" operation which is performed by the OV flag and the MSB of the current instruction operation result.
CZ is the operational result of different flags for different instructions. Refer to register definitions for more details.

Rev. 1.20 48 Deee 0 201 Rev. 1.20 49 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP In additio n, on entering an interrup t sequence or executing a subroutine call, the status register will not be pushed onto the stack automatically . If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. STATUS Register Bit 7 6 5 4 3 2 1 0 Nae SC CZ TO PDF OV Z AC C R/W R R R R R/W R/W R/W R/W "×": unknown Bit 7 SC: The result of the "XOR" operation which is performed by the OV flag and the MSB of the instruction operation result. Bit 6 CZ: The operational result of different flags for different instructions. For SUB/SUBM/LSUB/LSUBM instructions, the CZ flag is equal to the Z flag. For SBC/ SBCM/ LSBC/ LSBCM ins tructions, the CZ flag is the " AND" operation result which is performed by the previous operation CZ flag and current operation zero flag. For other instructions, the CZ flag will not be affected. Bit 5 TO: W atchdog T ime-out flag 0: After power up or executing the "CLR WDT" or "HALT" instruction 1: A watchdog time-out occurred Bit 4 PDF: Power down flag 0: After power up or executing the "CLR WDT" instruction 1: By executing the "HALT" instruction Bit 3 OV: Overflow flag 0: No overflow 1: An operation results in a carry into the highest-order bit but not a carry out of the highest-order bit or vice versa Bit 2 Z: Zero flag 0: The result of an arithmetic or logical operation is not zero 1: The result of an arithmetic or logical operation is zero Bit 1 AC: Auxiliary flag 0: No auxiliary carry 1: An operation results in a carry out of the low nibbles, in addition, or no borrow from the high nibble into the low nibble in subtraction Bit 0 C: Carry flag 0: No carry-out 1: An operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation The "C" flag is also affected by a rotate through carry instruction.

Rev. 1.20 48 Deee 0 201 Rev. 1.20 49 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP EEPROM Data Memory These d evices c ontain a n a rea o f i nternal E EPROM Da ta Me mory. E EPROM, wh ich st ands f or Electrically E rasable Progra mmable Re ad Onl y Me mory, i s by i ts na ture a non-vol atile form of re-programmable memory , with data retention even when its power supply is removed. By incorporating this kind of data memory , a w hole new hos t of application pos sibilities are made available to the designer . The avail ability of EEPROM storage allows information such as product identification numbers, calibration values, specific user data, system setup data or other product information to be stored directly within the product microcontroller . The process of reading and writing data to the EEPROM memory has been reduced to a very trivial affair. Device Capacity Address BS87B12A-3 4 × 8 00H ~ 3FHBS87C1A-3 BS87D20A-3 EEPROM Data Memory Structure The EEPROM Data Memory capacity is 64×8 bits for the series of devices. Unlike the Program Memory and RAM Data Memory , the EEPROM Data Memory is not directly mapped into memory space and is there fore not directly addressable in the same way as the other types of memory . Read and W rite operatio ns to the EEPROM are carried out in single byte operations using an address and data register in sector 0 and a single control register in sector 1. EEPROM Registers Three registers control the overall operation of the internal EEPROM Data Memory . These are the address register , EEA, the data register , EED and a single control register , EEC. As both the EEA and EED registers are located in sector 0, they can be directly accessed in the same was as any other Special Function Register . The EEC register , however , being located in sector 1, can be read from or written to indirectly using the MP1H/MP1L or MP2H/MP2L Memory Pointer pair and Indirect Addressing Register , IAR1 or IAR2. Because the EEC control register is located at address 40H in se ctor 1, t he Me mory Poi nter l ow byt e re gister, MP1L or MP2L , m ust first be se t t o t he va lue 40H and the Memory Pointer high byte register , MP1H or MP2H, set to the value, 01H, before any operations on the EEC register are executed. Register Name Bit 7 6 5 4 3 2 1 0 EEA — — EEA EEA4 EEA3 EEA2 EEA1 EEA0 EED D7 D D D4 D3 D2 D1 D0 EEC — — — — WREN WR RDEN RD EEPROM Registers List EEA Register Bit 7 6 5 4 3 2 1 0 Nae — — EEA EEA4 EEA3 EEA2 EEA1 EEA0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0. Bit 5~0 EEA5~EEA0: Data EEPROM address bit 5 ~ bit 0

Rev. 1.20 0 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP EED Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: Data EEPROM data bit 7~bit0 EEC Register Bit 7 6 5 4 3 2 1 0 Nae — — — — WREN WR RDEN RD R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3 WREN: Data EEPROM write enable 0: Disable 1: Enable This is the D ata EEP ROM W rite Enable Bit w hich mus t be s et high before D ata EEPROM write operations are carried out. Clearing this bit to zero will inhibit Data EEPROM write operations. Bit 2 WR: EEPROM write control 0: W rite cycle has finished 1: Activate a write cycle This i s t he Da ta E EPROM W rite C ontrol B it a nd wh en se t h igh b y t he a pplication program will activ ate a write cycle. This bit will be automatically reset to zero by the hardware after the write cycle has finished. Setting this bit high will have no ef fect if the WREN has not first been set high. Bit 1 RDEN: Data EEPROM read enable 0: Disable 1: Enable This is the Data EEPROM Read Enable Bit which must be set high before Data EEPROM read operations are carried out. Clearing this bit to zero w ill inhibit D ata EEPROM read operations. Bit 0 RD: EEPROM read control 0: Read cycle has finished 1: Activate a read cycle This is the Data EEPROM Read Control Bit and when set high by the applic ation program will activ ate a read cycle. This bit will be automatically reset to zero by the hardware after the read cycle has finished. Setting this bit high will have no ef fect if the RDEN has not first been set high. Note: The WREN, WR, RDEN and RD can not be set to "1" at the same time in one instruction. The WR and RD can not be set to "1" at the same time.

Rev. 1.20 0 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Reading Data from the EEPROM To read data from the EEPROM, the EEPROM address of the data to be read must first be placed in the EEA register or EEAL/EEAH register pair . Then the read enable bit, RDEN, in the EEC register must be set high to enable the read function. If the RD bit in the EEC register is now set high, a read cycle will be initiated. Setting the RD bit high will not initiate a read operation if the RDEN bit has not been set. When the read cycle terminates, the RD bit will be automatically cleared to zero, after whi ch t he dat a c an be rea d from t he E ED regi ster. T he dat a wi ll rem ain i n t he E ED regi ster until another read or write operation is executed. The application program can poll the RD bit to determine when the data is valid for reading. Writing Data to the EEPROM To write data to the EEPROM, the EEPROM address of the data to be written must first be placed in the EEA registe r and the data placed in the EED register . T o initiate a write cycle the write enable bit, WREN, in the EEC register must first be set high to enable the write function. Aft er this, the WR bit in the EEC register must be imm ediately set high to initiate a write cycle successfully . These two instructions must be executed consecutively. The global interrupt bit EMI should also first be cleared before implementing any write operations, and then set high again after the write cycle has started. Note that setting the WR bit high will not initiate a write cycle if the WREN bit has not been set. As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock, a certain time will elapse before the data will have been written into the EEPROM. Detecting when the write cycle has finished can be impl emented either by polling the WR bit in the EEC regis ter or by us ing the EEP ROM interrupt. When the w rite cycle terminates, the WR bit will be automatically cleared to zero by the microcontroller , informing the user that the data h as b een wr itten t o t he E EPROM. T he a pplication p rogram c an t herefore p oll t he W R b it t o determine when the write cycle has ended. Write Protection Protection against inadvertent write operation is provided in several ways. After the device is powered on, the W rite Enable bit in the control register will be cleared preventing any write operations. Also at power -on the Memory Pointer high byte register , MP1H or MP2H, will be reset to zero, which means that Data Memory sector 0 will be selected. As the EEPROM control register is located in sector 1, this adds a further measure of protection against spurious write operations. During normal program operation, ensuring that the W rite Enable bit in the control register is cleared will safeguard against incorrect write operations. EEPROM Interrupt The EEPROM write interrupt is generated when an EEPROM write cycle has ended. The EEPROM interrupt must first be enabled by setting the DEE bit in the relevant interrupt register . When an EEPROM write cycle ends, the DEF request flag will be set. If the global, EEPROM interrupt is enabled and the stack is not full, a jump to the associated Interrupt vector will take place. When the interrupt is serviced the EEPROM interrupt flag will be automatically reset.

Rev. 1.20 2 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Programming Considerations Care must be taken that data is not inadvertently written to the EEPROM. Protection can be enhanced by ensuring that the W rite Enable bit is normally cleared to zero when not writing. A lso the Memory Pointer high byte register could be normally cleared to zero as this would inhibit access to sector 1 where the EEPROM control register exist. Although certainly not necessary , consideration might be given in the application program to the checking of the validity of new write data by a simple read back process. When writing data the WR bit must be set high immediately after the WREN bit has been set high, to ensure the write cycle executes correctly . The global interrupt bit EMI should also be cleared before a write cycle is executed and then re-enabled after the write cycle starts. Note that the device should not enter the IDLE or SLEEP mode until the EEPROM read or write operation is totally complete. Otherwise, the EEPROM read or write operation will fail. Programming Examples

Reading data from the EEPROM – polling method MOV A , EEPROM_ADRES ; user defined address MOV E EA, A MOV A , 040H ; setup memory pointer low byte MP1L MOV M P1L, A ; MP1L points to EEC register MOV A , 01H ; setup Memory Pointer high byte MP1H MOV M P1H, A S E T I A R 1 . 1 ; s e t R D E N b i t , e n a b l e r e a d o p e r a t i o n s S E T I A R 1 . 0 ; s t a r t R e a d C y c l e - s e t R D b i t BACK: S Z I A R 1 . 0 ; c h e c k f o r r e a d c y c l e e n d JMP B ACK C L R I A R 1 ; d i s a b l e E E P R O M w r i t e CLR M P1H M O V A , E E D ; m o v e r e a d d a t a t o r e g i s t e r MOV R EAD_DATA, A
Writing Data to the EEPROM – polling method MOV A , EEPROM_ADRES ; user defined address MOV E EA, A MOV A , EEPROM_DATA ; user defined data MOV E ED, A MOV A , 040H ; setup memory pointer low byte MP1L MOV M P1L, A ; MP1L points to EEC register MOV A , 01H ; setup Memory Pointer high byte MP1H MOV M P1H, A CLR E MI SET I AR1.3 ; set WREN bit, enable write operations S E T I A R 1 . 2 ; s t a r t W r i t e C y c l e - s e t W R b i t SET E MI BACK: S Z I A R 1 . 2 ; c h e c k f o r w r i t e c y c l e e n d JMP B ACK C L R I A R 1 ; d i s a b l e E E P R O M w r i t e CLR M P1H

Rev. 1.20 2 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Oscillators Various oscillator types offer the user a wide range of functions according to their various application requirements. The flexible features of the oscillator functions ensure that the best optimisation can be achieved in terms of speed and power saving. Oscillator selections and operation are selected through a combination of configuration options and relevant control registers. Oscillator Overview In additio n to being the source of the main system clock the oscillators also provide clock sources for t he W atchdog T imer a nd T ime B ase I nterrupts. E xternal o scillators r equiring so me e xternal components as well as fully integrated internal oscillators, requiring no external components, are provided t o fo rm a wi de ra nge of bo th fa st a nd sl ow syst em osc illators. Al l osc illator op tions a re selected through the corresponding configuration options. The higher frequency oscillators provide higher perform ance but ca rry wi th i t t he disadva ntage of higher power requirem ents, whil e t he opposite is of course true for the lower frequency oscillators. W ith the capability of dynamically switching be tween fa st a nd sl ow syst em c lock, t he de vice ha s t he fl exibility t o opt imize t he performance/power ratio, a feature es pecially important in pow er s ensitive portable applications . Note that the exte rnal low speed crystal oscillator , LXT , is only availa ble for the BS87C16A-3 and BS87D20A-3 devices Type Name Frequency Pins Intenal High Speed RC HIRC 8/12/1 MHz — Intenal Low Speed RC LIRC 32 kHz — Extenal Low Speed Cystal* LXT* 32.78 kHz XT1/XT2 Oscillator Types System Clock Configurations There are three methods of generating the system clock, one high speed oscillators and two low speed oscillators for all devices. The high speed oscillator is the internal 8/12/16 MHz RC oscillator , HIRC. The two low speed oscillators are the internal 32 kHz RC oscillator , LIRC, and the external 32.768 kHz crystal oscillator , LXT . Selecting whether the low or high speed oscillator is used as the system oscillator is implemented using the HLCLK and CKS2~CKS0 bits in the SMOD register and as the system clock can be dynamically selected. The actual source clock used for the low speed oscillators is chosen via the corresponding configuration option. The frequency of the slow speed or high speed system clock is determined using the HLCLK and CKS2~CKS0 bits in the SMOD register . Note that two oscillator selections must be made nam ely one hi gh speed and one low speed system osci llators. It is not possi ble to choose a no-oscillator selection for either the high or low speed oscillator.

Rev. 1.20 4 Deee 0 201 Rev. 1.20 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Pesale LIRC High Speed Osillato Low Speed Osillato fH/2 fH/1 fH/4 fH/8 fH/4 fH/32 HLCLK CKS2~CKS0 its fSYS fSUB fSUB Configuation Option LXT * fLIRC HIRC fH fLXT Note: The LXT osillato is only availale fo BS87C1A-3 and BS87D20A-3 System Clock Configurations Internal High Speed RC Oscillator – HIRC The internal RC oscillator is a fully integrated system oscillator requiring no external components. The internal RC oscillator has a power -on default frequency of 8MHz but can be selected to be either 8MHz, 12MHz or 16MHz via a configuration option and the HIRCS1 and HIRCS0 bi ts in the CTRL register . Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised. Internal 32kHz Oscillator – LIRC The Internal 32 kHz System Oscillator is one of the low frequency oscillator choices, which is selected via a configuration option for the BS87C16A-3 and BS87D20A-3 devices. For the BS87B12A-3 de vice t here i s onl y one l ow fre quency osc illator known a s t he L IRC osc illator. It is a fully integrated RC oscillator with a typical frequency of 32 kHz at 5V , requiring no external components for its implementation. Device trimming during the manufacturing process and the inclusion of i nternal fre quency c ompensation c ircuits a re use d t o e nsure t hat t he i nfluence of the power supply voltage, temperature and process variations on the oscillation frequency are minimised.

Rev. 1.20 4 Deee 0 201 Rev. 1.20 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP External 32.768 kHz Crystal Oscillator – LXT – for BS87C16A-3/BS87D20A-3 The Exte rnal 32.768 kHz Crystal System Oscillator is one of the low frequency oscillator choices, which is selected via a configuration option. This clock source has a fixed frequency of 32.768 kHz and requires a 32.768 kHz crystal to be connected between pins XT1 and XT2. The external resistor and capacitor components connected to the 32.768 kHz crystal are necessary to provide oscillation. For a pplications wh ere p recise f requencies a re e ssential, t hese c omponents m ay b e r equired t o provide frequency compensation due to dif ferent crystal manufacturing tolerances. During power -up there is a time delay associated with the LXT oscillator waiting for it to start-up. When the microco ntroller enters the SLEEP or IDLE Mode, the system clock is switched of f to stop microcontroller a ctivity a nd t o c onserve powe r. Howe ver, i n m any m icrocontroller a pplications it may be necessary to keep the internal timers operational even when the microcontroller is in the SLEEP or IDLE Mode. T o do this, another clock, independent of the system clock, must be provided. However, for some crystals, to ensure oscillation and accurate frequency generation, it is necessary to add two small value external capacitors, C1 and C2. The exact values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer ’s specification. The external parallel feedback resistor, Rp, is required. The configuration option determines if the XT1/XT2 pins are used for the LXT oscillator or as I/O or other pin-shared functions.

If the LXT oscillator is not used for any clock source, the XT1/XT2 pins can be used as normal I/O or other pin-shared functions.
If the LXT oscillator is used for any clock source, the 32.768 kHz crystal should be connected to the XT1/XT2 pins. For oscillator stability and to minimise the ef fects of noise and crosstalk, it is important to ensure that the crystal and any associated resistors and capacitors along with interconnecting lines are all located as close to the MCU as possible. Note: 1. RP C1 and C2 ae equied. 2. Although not shown XT1/XT2 pins have a paasiti apaitane of aound 7pF. To intenal iuits Internal Oscillator Circuit XT1 XT2 R P 32.78 kHz Intenal RC Osillato External LXT Oscillator LXT Oscillarot C1 and C2 Values Crystal Frequency C1 C2 32.78kHz 10pF 10pF Note: 1. C1 and C2 value ae fo guidane only. 2. RP=MΩ~10MΩ is eoended. 32.768kHz Crystal Capacitor Recommended Value

Rev. 1.20 Deee 0 201 Rev. 1.20 7 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LXT Oscillator Low Power Function The LXT oscillator can function in one of two modes, the Quick Start Mode and the Low Power Mode. The mode selection is executed using the LXTLP bit in the CTRL register. LXTLP LXT Mode

0 Quik Stat

1 Low Powe

After power on, the LXTLP bit will be automatically cleared to zero ensuring that the LXT oscillator is in the Quick Start operating mode. In the Quick Start Mode the LXT oscillator will power up and stabilise quickly . However , after the LXT oscillator has fully powered up it can be placed into t he L ow-power m ode b y se tting t he L XTLP b it h igh. T he o scillator wi ll c ontinue t o r un b ut with reduced current consumption, as the higher current consumption is only required during the LXT oscillator start-up. In power sensitive applications, such as battery applications, where power consumption must be kept to a minimum, it is therefore recommended that the application program sets the LXTLP bit high about 2 seconds after power-on. It shou ld be no ted t hat, no m atter wha t c ondition t he L XTLP bi t i s se t t o, t he L XT osc illator wi ll always function normally . The only dif ference is that it will take more time to start up if in the Low- power mode.

Rev. 1.20 Deee 0 201 Rev. 1.20 7 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Operating Modes and System Clocks Present day appl ications require that their mi crocontrollers have high performance but often sti ll demand that they consume as little power as possible, conflicting requirements that are especially true i n ba ttery powe red por table a pplications. T he fa st c locks re quired for hi gh pe rformance wi ll by their nature increase current consumption and of course vice-versa lower speed clocks reduce current consumption. As Holtek has provided thes e devices with both high and low speed clock sources and the means to switch between them dynamically , the user can optimise the operation of their microcontroller to achieve the best performance/power ratio. System Clocks Each device has dif ferent clock sources for both the CPU and peripheral function operation. By providing the user with a wide range of clock selections using register programming, a clock system can be configured to obtain maximum application performance. The main system clock, can come from either a high frequency , fH, or low frequency , fSUB, source, and is selected using the HLCLK bit and CKS2~CKS0 bits in the SMOD register . The high speed system clock is s ourced from the H IRC os cillator. The low s peed s ystem clock s ource can be sourced from the internal clock fSUB. If fSUB is selected then it can be sourced by either the LXT or LIRC oscillators, selected via a configuration option. The other choice, which is a divided version of the high speed system oscillator has a range of fH/2~fH/64. Pesale LIRC High Speed Osillato Low Speed Osillato fH/2 fH/1 fH/4 fH/8 fH/4 fH/32 HLCLK CKS2~CKS0 its fSYS fSUB fSUB Configuation Option LXT * fLIRC HIRC fH fLXT Note: The LXT osillato is only availale fo BS87C1A-3 and BS87D20A-3 LVR WDT fSYS/4 fPSC0 Tie Base 0 CLKSEL0[1:0] fSUB fSYS Pesale 0 TB0[2:0] fSYS/4 CLKSEL1[1:0] fSUB fSYS fPSC1 Tie Base 1Pesale 1 TB1[2:0] fH fH fSUB fSUB Device Clock Configurations Note: When the system clock source fSYS is switched to fSUB from fH, the high speed oscillation will stop to conserve the power. Thus there is no fH~fH/64 for peripheral circuit to use.

Rev. 1.20 8 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP System Operation Modes There a re f ive d ifferent m odes o f o peration f or t he m icrocontroller, e ach o ne wi th i ts o wn special characteristics and which can be chosen according to the specific performance and power requirements of the appl ication. There are two modes all owing normal operati on of the microcontroller, the F AST Mode and SLOW Mode. The remaining three modes, the SLEEP , IDLE0 and IDLE1 Mode are used when the microcontroller CPU is switched off to conserve power. Operation Mode CPU fSYS fSUB FAST On fH~fH/4 On SLOW On fSUB On IDLE0 Off Off On IDLE1 Off On On SLEEP Off Off On FAST Mode As the name suggests this is one of the main operating modes where the microcontroller has all of its functions operational and where the system clock is provided by the high speed oscillator . This mode operates allo wing the microco ntroller to operate normally with a clock source will come from the high speed oscillator , HIRC. The high speed oscillator will however first be divided by a ratio ranging from 1 to 64, the actual ratio being selected by the CKS2~CKS0 and HLCLK bits in the SMOD regis ter. A lthough a high s peed os cillator is us ed, running the microcontroller at a divided clock ratio reduces the operating current. SLOW Mode This is also a mode where the microcontroller operates normally altho ugh now with a slower speed clock source. The clock source used will be from fSUB. The fSUB clock is derived from either the LIRC or LXT oscillator for BS87C16A-3 and BS87D20A-3 devices while the fSUB clock is from the LIRC o scillator f or t he B S87B12A-3 d evice. R unning t he m icrocontroller i n t his m ode a llow i t t o run with much lower operating currents. In the SLOW Mode, the fH is off. SLEEP Mode The S LEEP M ode is entered w hen an H ALT instruction is executed and w hen the ID LEN bit in the SMOD registe r is low . In the SLEEP mode the CPU will be stopped and both the high and low speed oscillators will be switched of f. However the fSUB clock will continue to operate as the WDT function is always enabled. IDLE0 Mode The IDLE0 Mode is entered when an HAL T instruction is executed and when the IDLEN bit in the SMOD regi ster i s high and t he FSYSON bit i n t he CTRL regi ster i s l ow. In t he IDLE 0 Mode t he system oscillator will be switched off and therefore will be inhibited from driving the CPU and some peripheral functions. IDLE1 Mode The IDLE1 Mode is entered when an HAL T instruction is executed and when the IDLEN bit in the SMOD registe r is high and the FSYSON bit in the CTRL register is high. In the IDLE1 Mode the system oscillator will be inhibited from driving the CPU but may continue to provide a clock source to keep some peripheral functions operational. In the IDLE1 Mode, the system oscillator will continue to run and this system oscillator may be the high speed or low speed oscillator.

Rev. 1.20 8 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Control Registers The register, SMOD, is used to control the internal clocks within the device. Register Name Bit 7 6 5 4 3 2 1 0 SMOD CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK CTRL FSYSON — HIRCS1 HIRCS0 LXTLP LVRF LRF WRF System Operating Mode Control Registers List SMOD Register Bit 7 6 5 4 3 2 1 0 Nae CKS2 CKS1 CKS0 — LTO HTO IDLEN HLCLK R/W R/W R/W R/W — R R R/W R/W POR 0 0 0 — 0 0 1 1 Bit 7~5 CKS2~CKS0: System clock selection when HLCLK is "0" 000: fSUB (LIRC or LXT) 001: fSUB (LIRC or LXT) 010: fH/64 011: fH/32 100: fH/16 101: fH/8 110: fH/4 111: fH/2 These three bits are used to select which clock is used as the system clock source. In addition to the system clock source, which can be either the LXT or LIRC, a divided version of the high speed system oscillator can also be chosen as the system clock source. Bit 4 Unimplemented, read as 0. Bit 3 LTO: Low speed system oscillator ready flag 0: Not ready 1: Ready This is the low speed system oscilla tor ready flag which indicates when the low speed system oscillator is stable after pow er on reset or a wake-up has occurred. The flag will be low when in the SLEEP Mode but after a wake-up has occurred, the flag will change to a high level after 128 clock cycles if LXT oscillator is used and 1~2 clock cycles if the LIRC oscillator is used. Bit 2 HTO: High speed system oscillator ready flag 0: Not ready 1: Ready This i s t he hi gh spe ed syst em osc illator re ady fl ag whi ch i ndicates whe n t he hi gh speed system oscillator is stable after a wake-up has occurred. This flag is cleared to zero by hardware when the device is powered on and then changes to a high level after the high speed system oscillator is stable. Therefore, this flag will always be read as "1" by the application program after device power -on. The flag will be low when in the SLEEP or IDLE0 Mode but after power on reset or a wake-up has occurred, the flag will change to a high level after 15~16 clock cycles if the HIRC oscillator is used.

Rev. 1.20 0 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 1 IDLEN: IDLE Mode Control 0: Disable 1: Enable This bit is the IDLE Mode control bit and determines what happens when the HAL T instruction is executed. If this bit is high, when a HAL T instruction is executed the device wi ll e nter t he I DLE Mo de. I n t he I DLE1 Mo de t he C PU wi ll st op r unning but t he syst em c lock wi ll c ontinue t o ke ep t he pe ripheral fun ctions op erational, i f FSYSON bit is high. If the FSYSON bit is low , the CPU and the system clock will all stop in the IDLE0 Mode. If the bit is low the device will enter the SLEEP Mode when a HALT instruction is executed. Bit 0 HLCLK: System clock selection 0: fH/2~ fH/64 or fSUB 1: fH This b it i s u sed t o se lect i f t he fH c lock, t he fH/2~ fH/64 o r fSUB c lock i s u sed a s t he system c lock. W hen t his b it i s h igh t he fH clock w ill be s elected and if low the fH/2~ fH/64 or fSUB clock will be selected. When the system clock is switched from the fH clock to the fSUB clock, the fH clock will automatically be switched off to conserve power. CTRL Register – BS87B12A-3 Bit 7 6 5 4 3 2 1 0 Nae FSYSON — HIRCS1 HIRCS0 — LVRF LRF WRF R/W R/W — R/W R/W — R/W R/W R/W POR 0 — 0 0 — × 0 0 "×": unknown CTRL Register – BS87C16A-3 & BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae FSYSON — HIRCS1 HIRCS0 LXTLP LVRF LRF WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 × 0 0 "×": unknown Bit 7 FSYSON: fSYS Control in IDLE Mode 0: Disable 1: Enable Bit 6 Unimplemented, read as 0. Bit 5~4 HIRCS1~HIRCS0: HIRC frequency clock selection 00: 8 MHz 01: 12 MHz 10: 16 MHz 11: 8 MHz It is recommended that the HIRC frequency selected by these two bits is the same with the frequency determined by the configuration option to keep the HIRC frequency accuracy specified in the A.C. characteristics. Bit 3 LXTLP: LXT low power control 0: Quick Start mode 1: Low Power mode Note that this bit is used to selec the operating mode of the LXT oscillator which is only available for BS87C16A-3 and BS87D20A-3 devices. For the BS87B12A-3 device this bit is unimplemented and is read as "0". Bit 2 LVRF: LVR function reset flag Described elsewhere Bit 1 LRF: LVR control register software reset flag Described elsewhere Bit 0 WRF: WDT control register software reset flag Described elsewhere

Rev. 1.20 0 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Operating Mode Switching These devices can switch between operating modes dynamically allowing the user to select the best performance/power ratio for the pres ent task in hand. In this w ay microcontroller operations that do not require high performance can be executed using slower clocks thus requiring less operating current and prolonging battery life in portable applications. In simple terms, Mode Switching between the F AST Mode and SLOW Mode is executed using the HLCLK and CKS2~CKS0 bits in the SMOD register while Mode Switching from the F AST/SLOW Modes to the SLEEP/IDLE Modes is executed via the HALT instruction. When an HALT instruction is executed, whether the device enters the IDLE Mode or the SLEEP Mode is determined by the condition of the IDLEN bit in the SMOD register and the FSYSON bit in the CTRL register. When the HLCLK bit switches to a low level, which implies that clock source is switched from the high speed clock source, fH, to the clock source, fH/2~ fH/64 or fSUB. If the clock is from the fSUB, the high speed clock source will stop running to conserve power . When this happens it must be noted that the fH/16 and fH/64 internal clock sources will also stop running. The accompanying flowchart shows what happens when the device moves between the various operating modes. FAST fSYS=fH~fH/4 fH on CPU un fSYS on fSUB on WDT on SLOW fSYS=fSUB fSUB on CPU un fSYS on fH off WDT on IDLE0 HALT instution exeuted CPU stop IDLEN=1 FSYSON=0 fSYS off fSUB on WDT on SLEEP HALT instution exeuted CPU stop IDLEN=0 fSYS off fSUB on WDT on IDLE1 HALT instution exeuted CPU stop IDLEN=1 FSYSON=1 fSYS on fSUB on WDT on

Rev. 1.20 2 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP FAST Mode to SLOW Mode Switching When runni ng i n t he F AST Mode , whi ch use s t he hi gh spe ed syst em osc illator, a nd t herefore consumes more power , the system clock can switch to run in the SLOW Mode by clearing the HLCLK bit to zero and setting the CKS2~CKS0 bits to "000" or "001" in the SMOD register . This will then use the low speed system oscillator which will consume less power . Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption. The SLOW Mode is sourced from the LXT or LIRC oscillator and therefore requires the specific oscillator to stable before full mode switching occurs. FAST Mode SLOW Mode CKS2~CKS0 = 00xB & HLCLK = 0 SLEEP Mode IDLEN=0 & HALT instution is exeuted IDLE0 Mode IDLEN=1 FSYSON=0 HALT instution is exeuted IDLE1 Mode IDLEN=1 FSYSON=1 HALT instution is exeuted

Rev. 1.20 2 Deee 0 201 Rev. 1.20 3 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SLOW Mode to FAST Mode Switching In SLOW mode the system uses the fSUB clock derived from either the LXT or LIRC low speed oscillator as system clock. When system clock is switched back to the F AST mode from fSUB, where the high speed system oscillator is used, the HLCLK bit should be set high or HLCLK bit is low but the CKS2~CKS0 bits are set to "010 ~1 11" and then the system clock will respectively be switched to fH~ fH/64. However, i f fH i s not use d i n SL OW m ode a nd t hus swi tched of f, i t wi ll t ake som e t ime t o re - oscillate and stabilise when switching back to the F AST mode from the SLOW Mode and the status of the HT O flag should be checked. The time duration required for the high speed system oscillator stabilization is specified in the relevant characteristics. SLOW Mode FAST Mode CKS2~CKS0≠00xB & as HLCLK=0 o HLCLK = 1 SLEEP Mode IDLEN=0 & HALT instution is exeuted IDLE0 Mode IDLEN=1 FSYSON=0 HALT instution is exeuted IDLE1 Mode IDLEN=1 FSYSON=1 HALT instution is exeuted Entering the SLEEP Mode There is only one way for the device to enter the SLEEP Mode and that is to execute the "HAL T" instruction in the application program with the IDLEN bit in the SMOD register equal to "0". In this mode all the clocks and functions will be switched of f except the WDT function. When this instruction is executed under the conditions described above, the following will occur:

The system clock will be stopped and the application program will stop at the "HALT" instruction.
The Data Memory contents and registers will maintain their present condition.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag PDF will be set, and WDT timeout flag T O will be cleared.
The WDT will be cleared and resume counting as the WDT function is always enabled.

Rev. 1.20 4 Deee 0 201 Rev. 1.20 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Entering the IDLE0 Mode There is only one way for the device to enter the IDLE0 Mode and that is to execute the "HAL T" instruction in the application program with the IDLEN bit in the SMOD register equal to "1" and the FSYSON bit in the CTRL register equal to "0". When this instruction is executed under the conditions described above, the following will occur:

The system clock will be stopped and the application program will stop at the "HALT" instruction, but the low frequency clock fSUB will be on.
The Data Memory contents and registers will maintain their present condition.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag PDF will be set, and WDT timeout flag T O will be cleared.
The WDT will be cleared and resume counting. Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the "HAL T" instruction i n t he a pplication progra m wi th t he IDL EN bi t i n t he SMOD re gister i s e qual t o "1" and the FSYSON bit in the CTRL register equal to "1". When this instruction is executed under the conditions described above, the following will occur:
The system and the low frequency fSUB clocks will be on but the application program will stop at the "HALT" instruction.
The Data Memory contents and registers will maintain their present condition.
The I/O ports will maintain their present conditions.
In the status register, the Power Down flag PDF will be set, and WDT timeout flag T O will be cleared.
The WDT will be cleared and resume counting. Standby Current Considerations As the main reason for entering the SLEEP or IDLE Mode is to keep the current consumption of the device to as low a value as possible, perhaps only in the order of several micro-amps except in the IDLE1 Mode , t here a re ot her c onsiderations whi ch m ust a lso be t aken i nto a ccount by t he c ircuit designer if the power consumption is to be minimised. Special attention must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased current consumption. This also applies to devices which have dif ferent package types, as there may be unbonded pins. These must either be setup as outputs or if setup as inputs must have pull-high resistors connected. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be consumed if the LIRC oscillator has enabled. In the IDLE1 Mode the system oscillator is on, if the peripheral function clock source is derived from the high speed oscillator , the additional standby current will also be perhaps in the order of several hundred micro-amps.

Rev. 1.20 4 Deee 0 201 Rev. 1.20 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Wake-up To minimise power consumption the device can enter the SLEEP or any IDLE Mode, where the CPU will be switched of f. However , when the device is woken up again, it will take a considerable time for the original system oscillator to restart, stabilise and allow normal operation to resume. After the system enters the SLEEP or IDLE Mode, it can be woken up from one of various sources listed as follows:

An external falling edge on Port A
A system interrupt
A WDT overflow When the device executes the "HAL T" instruction, the PDF flag will be set to 1. The PDF flag will be cleare d to 0 if the device experi ences a system power -up or executes the clear W atchdog T imer instruction. If the system is woken up by a WDT overflow , a W atchdog T imer reset will be initiated and the T O flag will be set to 1. The T O flag is set if a WDT time-out occurs and causes a wake-up that only resets the Program Counter and Stack Pointer, other flags remain in their original status. Each pin on Port A can be setup using the P AWU register to permit a negative transition on the pin to wake up the system . When a Port A pin wake-up occurs, the program wil l resume executi on at the instruction following the "HAL T" instruction. If the system is woken up by an interrupt, then two possible situations may occur . The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume execution at the instruction following the "HAL T" instruction. In this situation, the interrupt which woke up the device will not be immediately serviced, but will rather be serviced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag i s se t hi gh be fore e ntering t he SLE EP or IDL E Mode, t he wa ke-up func tion of t he re lated interrupt will be disabled. System Oscillator Wake-up Time (SLEEP Mode) Wake-up Time (IDLE0 Mode) Wake-up Time (IDLE1 Mode) HIRC 1~1 HIRC yles 1~2 HIRC yles LIRC 1~2 LIRC yles 1~2 LIRC yles LXT* 128 LXT yles 1~2 LXT yles Note: The LXT oscillator is only available for the BS87C16A-3 and BS87D20A-3 devices. Wake-up Time Programming Considerations The high speed and low speed oscillators both use the same SST counter . For example, if the system is woken up from the SLEEP Mode the HIRC oscillator needs to start-up from an of f state. If the device is woken up from the SLEEP Mode to the F AST Mode, the high speed system oscillator needs an SST period. The device will execute the first instruction after HT O is high. At this time, the LXT oscillator may not be stability if fSUB is from LXT oscillator . The same situation occurs in the power-on state. The LXT oscillator is not ready yet when the first instruction is executed.

Rev. 1.20 Deee 0 201 Rev. 1.20 7 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Watchdog Timer The W atchdog T imer is provided to prevent program malfunctions or sequences from jumping to unknown locations, due to certain uncontrollable external events such as electrical noise. Watchdog Timer Clock Source The W atchdog T imer clock source is provided by the internal fSUB cloc k shich is in turn supplied by either the LXT or LIRC oscillator selected by a configuration option. The LIRC internal oscillator has an approximate frequency of 32 kHz and this specified internal clock period can vary with VDD, temperature and process variations. The LXT oscillator is supplied by an external 32.768 kHz crystal. T he W atchdog T imer so urce c lock i s t hen su bdivided b y a r atio o f 28 t o 218 t o g ive l onger timeouts, the actual value being chosen using the WS2~WS0 bits in the WDTC register. Watchdog Timer Control Register A single register , WDTC, controls the required timeout period as well as the enable control. This register controls the overall operation of the W atchdog T imer. The WD TC regis ter is initiated to 01010011B at any reset except the WDT time-out hardware warm reset. WDTC Register Bit 7 6 5 4 3 2 1 0 Nae WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 0 1 1 Bit 7~3 WE4~WE0: WDT function control 01010 or 10101: Enabled Other values: Reset MCU If these bits are changed due to adverse environmental conditions, the microcontroller will be reset. The reset operation will be activated after a delay time, tSRESET, and the WRF bit in the RSTFC register will be set to 1. Bit 2~0 WS2~WS0: WDT time-out period selection 000: 28/fSUB 001: 210/fSUB 010: 212/fSUB 011: 214/fSUB 100: 215/fSUB 101: 216/fSUB 110: 217/fSUB 111: 218/fSUB These t hree b its d etermine t he d ivision r atio o f t he wa tchdog t imer so urce c lock, which in turn determines the time-out period. CTRL Register Bit 7 6 5 4 3 2 1 0 Nae FSYSON — HIRCS1 HIRCS0 LXTLP LVRF LRF WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 × 0 0 "×": unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Described elsewhere Bit 6 Unimplemented, read as 0. Bit 5~4 HIRCS1~HIRCS0: HIRC frequency clock selection Described elsewhere

Rev. 1.20 Deee 0 201 Rev. 1.20 7 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 3 LXTLP: LXT low power control Described elsewhere Bit 2 LVRF: LVR function reset flag Described elsewhere Bit 1 LRF: LVR control register software reset flag Described elsewhere Bit 0 WRF: WDT control register software reset flag 0: Not occur 1: Occurred This b it i s se t h igh b y t he W DT c ontrol r egister so ftware re set a nd c leared b y t he application program. Note that this bit can only be cleared to zero by the application program. Watchdog Timer Operation The W atchdog T imer ope rates by provi ding a de vice re set whe n i ts t imer ove rflows. T his m eans that i n t he a pplication pro gram a nd dur ing nor mal ope ration t he use r ha s t o st rategically c lear t he Watchdog T imer before it overfl ows to prevent the W atchdog T imer from executing a res et. This is done using the clear watchdog instruction. If the program malfunctions for whatever reason, jumps to an unknown location, or enters an endless loop, the clear instruction will not be executed in the correct manner , in which case the W atchdog T imer will overflow and reset the device. W ith regard to the W atchdog T imer enable/disable function, there are five bits, WE4~WE0, in the WDTC register to of fer the enable and reset control of the W atchdog T imer. The WDT function will be enabled when the WE4~WE0 bits are set to a value of 01010B or 10101B. If the WE4~WE0 bits are changed to any other values rather than 01010B and 10101B, which is caused by the environmental noise, it will reset the device after a delay time, tSRESET. After power on these bits will have a value of 01010B. WE4 ~ WE0 Bits WDT Function 10101B o 01010B Enale Any othe value Reset MCU Watchdog Timer Enable/Reset Control Under norm al progra m ope ration, a W atchdog T imer t ime-out wi ll i nitialise a de vice re set a nd se t the status bit T O. However , if the system is in the SLEEP or IDLE Mode, when a W atchdog T imer time-out occurs, the T O bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the W atchdog T imer. The first is a WDT reset, which means a certain value except 01010B and 10101B written into the WE4~WE0 field, the second is using the W atchdog T imer software cle ar instruction and the third is via a HALT instruction. There is only one method of using software instruction to clear the W atchdog T imer. That is to use the single "CLR WDT" instruction to clear the WDT contents. The maximum time out period is when the 218 division ratio is selected. As an example, with a 32 kHz LIRC oscillator as its source clock, this will give a maximum watchdog period of around 8 second for the 218 division ratio and a minimum timeout of 8ms for the 28 division ration.

Rev. 1.20 8 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP “CLR WDT”Instution 8-stage Divide WDT Pesale WE4~WE0 itsWDTC Registe Reset MCU LIRC fSUB/28 8-to-1 MUX CLR WS2~WS0 (fSUB/28 ~ fSUB/218) WDT Tie-out (28/fSUB ~ 218/fSUB) “HALT”Instution fSUB LXT* Configuation option Note: The LXT osillato is only availale fo BS87C1A-3 and BS87D20A-3 Watchdog timer Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller . In this case, internal circuitry will ensure that the mi crocontroller, after a short del ay, will be in a well defined state and rea dy to execute t he fir st p rogram i nstruction. Af ter t his p ower-on r eset, c ertain i mportant i nternal r egisters will be set to defined states before the program commences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. The W atchdog T imer overflow is one of many reset types and will reset the microcontroller . Another reset exists in the form of a Low V oltage Reset, L VR, where a full reset implemented in situations where the power supply voltage falls below a certain threshold. All types of reset operations result in different register conditions being setup. Reset Functions There are several ways in which a microcontroller reset can occur , through events occurring internally. Power-on Reset The m ost fund amental a nd una voidable re set i s t he one t hat oc curs a fter powe r i s first a pplied t o the microcontroller . As well as ensuring that the Program Memory begins execution from the first memory address, a pow er-on reset als o ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. VDD Powe-on Reset SST Tie-out tRSTD Note: tRSTD is power-on delay with typical time=50 ms Power-On Reset Timing Chart

Rev. 1.20 8 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Low Voltage Reset – LVR The micr ocontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device. The L VR function is always enabled with a specific L VR voltag e, VLVR. If the supply voltage of the device drops to within a range of 0.9V~VLVR such as might occur when changing the battery , the L VR will automatically reset the device internally and the L VRF bit in the CTRL register will also be set to 1. For a valid L VR signal, a low supply voltage, i.e., a voltage in the range between 0.9V~VLVR must exist for a tim e greater than that specified by tLVR in the L VD/LVR characteristics. If the low supply voltage state does not exceed this value, the L VR will ignore the low supply voltage and will not perform a reset functio n. The actual VLVR value is fixed at a voltage value of 2.55V by the L VS bits in the L VRC register . If the L VS7~LVS0 bits have any other value, which may perhaps occur due to adverse environmental conditions such as noise, the L VR will reset the device after a d elay t ime, tSRESET. W hen t his h appens, t he L RF b it i n t he C TRL r egister wi ll b e se t t o 1 . Af ter power on the register will have the default value of 01010101B. Note that the L VR function will be automatically disabled when the device enters the SLEEP/IDLE mode. LVR Intenal Reset tRSTD + tSST Note: tRSTD is power-on delay with typical time=50 ms Low Voltage Reset Timing Chart

LVRC Register Bit 7 6 5 4 3 2 1 0 Nae LVS7 LVS LVS LVS4 LVS3 LVS2 LVS1 LVS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 1 0 1 0 1 0 1 Bit 7~0 LVS7~LVS0: LVR voltage select 01010101: 2.55V 00110011: 2.55V 10011001: 2.55V 10101010: 2.55V Other values: Generates a MCU reset – register is reset to POR value When an actual low voltage condit ion occurs, as specified by the L VR voltage value above, an MCU reset will be generated. The reset operation will be act ivated after the low voltage condition keeps for greater than a tLVR time. In this situation the register contents will remain the same after such a reset occurs. Any register value, other than the four defined register values above, will also result in the generation of an MCU reset. The reset operation will be activate d after a delay time, tSRESET. However in this situation the register contents will be reset to the POR value.

Rev. 1.20 70 Deee 0 201 Rev. 1.20 71 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

CTRL Register Bit 7 6 5 4 3 2 1 0 Nae FSYSON — HIRCS1 HIRCS0 LXTLP LVRF LRF WRF R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 × 0 0 "×": unknown Bit 7 FSYSON: fSYS Control in IDLE Mode Described elsewhere Bit 6 Unimplemented, read as 0. Bit 5~4 HIRCS1~HIRCS0: HIRC frequency clock selection Described elsewhere Bit 3 LXTLP: LXT low power control Described elsewhere Bit 2 LVRF: LVR function reset flag 0: Not occurred 1: Occurred This bit is set to 1 when a specific low voltage reset condition occurs. Note that this bit can only be cleared to 0 by the application program. Bit 1 LRF: LVR control register software reset flag 0: Not occurred 1: Occurred This bit is set to 1 by the L VRC control register contains any undefined L VR voltage register values. This in ef fect acts like a software-reset function. Note that this bit can only be cleared to 0 by the application program. Bit 0 WRF: WDT control register software reset flag Described elsewhere. Watchdog Time-out Reset during Normal Operation The W atchdog time-out Reset during normal operation is the same as the hardw are Low V oltage Reset except that the W atchdog time-out flag T O will be set to "1". WDT Tie-out Intenal Reset tRSTD + tSST Note: tRSTD is power-on delay with typical time=16.7 ms WDT Time-out Reset during NORMAL Operation Timing Chart Watchdog Time-out Reset during SLEEP or IDLE Mode The W atchdog time-out Reset during SLEEP or IDLE Mode is a little dif ferent from other kinds of re set. Mo st of t he c onditions re main unc hanged e xcept t hat t he Pro gram Count er a nd t he St ack Pointer will be cleared to "0" and the T O flag will be set to "1". Refer to the A.C. Characteristics for tSST details. WDT Tie-out Intenal Reset tSST WDT Time-out Reset during SLEEP or IDLE Mode Timing Chart

Rev. 1.20 70 Deee 0 201 Rev. 1.20 71 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Reset Initial Conditions The dif ferent types of reset described af fect the reset flags in dif ferent ways. These flags, known as P DF and T O are located in the s tatus regis ter and are controlled by various microcontroller operations, su ch a s t he SL EEP o r I DLE Mo de f unction o r W atchdog T imer. T he r eset f lags a re shown in the table: TO PDF Reset Function 0 0 Powe-on eset u u LVR eset duing NORMAL o SLOW Mode opeation 1 u WDT tie-out eset duing NORMAL o SLOW Mode opeation 1 1 WDT tie-out eset duing IDLE o SLEEP Mode opeation "u" stands fo unhanged The following table indicates the way in which the various components of the microcontroller are affected after a power-on reset occurs. Item Reset Function Poga Counte Reset to zeo Inteupts All inteupts will e disaled WDT Ti e Base Clea afte eset WDT egins ounting Tie Modules Tie Modules will e tuned off Input/Output Pots I/O pots will e setup as inputs Stak pointe Stak pointe will point to the top of the stak The dif ferent kinds of resets all af fect the internal registers of the micr ocontroller in dif ferent ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects the microcontroller internal registers. Register BS87B12A-3 BS87C16A-3 BS87D20A-3 Power On Reset LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE/SLEEP)* IAR0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu IAR1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP1L ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP1H ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ACC ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL ● ● ● 0000 0000 0000 0000 0000 0000 0000 0000 TBLP ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBHP ● ● ---- xxxx ---- uuuu ---- uuuu ---- uuuu TBHP ● ---x xxxx ---u uuuu ---u uuuu ---u uuuu STATUS ● ● ● xx00 xxxx uuuu uuuu xx1u uuuu uu11 uuuu SMOD ● ● ● 000- 0011 000- 0011 000- 0011 uuu- uuuu IAR2 ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu MP2L ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu MP2H ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu

Rev. 1.20 72 Deee 0 201 Rev. 1.20 73 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Register BS87B12A-3 BS87C16A-3 BS87D20A-3 Power On Reset LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE/SLEEP)* INTC0 ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu INTC1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC2 ● 000- 000- 000- 000- 000- 000- uuu- uuu- INTC2 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu INTC3 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PA ● ● ● 1--1 1111 1--1 1111 1--1 1111 u--u uuuu PAC ● ● ● 1--1 1111 1--1 1111 1--1 1111 u--u uuuu PAPU ● ● ● 0--0 0000 0--0 0000 0--0 0000 u--u uuuu PAWU ● ● ● 0--0 0000 0--0 0000 0--0 0000 u--u uuuu PB ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PBPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC ● ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PCPU ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PD ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PDC ● ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PDPU ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PE ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PEC ● 1111 1111 1111 1111 1111 1111 uuuu uuuu PEPU ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLEDC0 ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu SLEDC1 ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu SLEDC2 ● --01 0101 --01 0101 --01 0101 --uu uuuu WDTC ● ● ● 0101 0011 0101 0011 0101 0011 uuuu uuuu TBC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu LVRC ● ● ● 0101 0101 0101 0101 0101 0101 uuuu uuuu EEA ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu EED ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMTOC ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SIMC0 ● ● ● 111- 0000 111- 0000 111- 0000 uuu- uuuu SIMC1 ● ● ● 1000 0001 1000 0001 1000 0001 uuuu uuuu SIMD ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu SIMA/SIMC2 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu USR ● ● ● 0000 1011 0000 1011 0000 1011 uuuu uuuu UCR1 ● ● ● 0000 00x0 0000 00x0 0000 00x0 uuuu uuuu UCR2 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu BRG ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TXR_RXR ● ● ● xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu

Rev. 1.20 72 Deee 0 201 Rev. 1.20 73 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Register BS87B12A-3 BS87C16A-3 BS87D20A-3 Power On Reset LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE/SLEEP)* SADOL ● ● ● xxxx ---- xxxx ---- xxxx ---- uuuu ---- (ADRFS=0) uuuu uuuu (ADRFS=1) SADOH ● ● ● xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu (ADRFS=0) ---- uuuu (ADRFS=1) SADC0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SADC1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu ACERL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TMPC0 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu SLCDC0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC2 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC3 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu SLCDC4 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu LVDC ● ● ● --00 0000 --00 0000 --00 0000 --uu uuuu OCVPC0 ● ● ● 1100 1000 1100 1000 1100 1000 uuuu uuuu MFI ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTRL ● 0-00 -x00 0-00 -x00 0-00 -x00 u-uu -uuu CTRL ● ● 0-00 0x00 ---- u1uu ---- uuuu ---- uuuu OCVPC1 ● ● ● 0000 --00 0000 --00 0000 --00 uuuu --uu OCVPC2 ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu OCVPC3 ● ● ● 0000 --00 0000 --00 0000 --00 uuuu --uu TKTMR ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKC0 ● ● ● -000 0000 -000 0000 -000 0000 -uuu uuuu TK1DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TK1DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM01DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM01DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM0C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM11DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM11DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu

Rev. 1.20 74 Deee 0 201 Rev. 1.20 7 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Register BS87B12A-3 BS87C16A-3 BS87D20A-3 Power On Reset LVR Reset (Normal Operation) WDT Time-out (Normal Operation) WDT Time-out (IDLE/SLEEP)* TKM1C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM1C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM21DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM21DH ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2ROL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM2C1 ● ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM31DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM31DH ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3ROL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3C0 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM3C1 ● ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu TKM41DL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM41DH ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4ROL ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4C0 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu TKM4C1 ● 0-00 0000 0-00 0000 0-00 0000 u-uu uuuu CTM0C0 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0C1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM0AL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0C1 ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0DL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0AL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM0RPL ● ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1C1 ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1DL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1AL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu PTM1RPL ● ● 0000 0000 0000 0000 0000 0000 uuuu uuuu CTM1C0 ● 0000 0000 0000 0000 0000 0000 uuuu uuuu

Rev. 1.20 7 Deee 0 201 Rev. 1.20 77 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Input/Output Ports Holtek m icrocontrollers of fer c onsiderable fle xibility on t heir I/ O port s. W ith t he i nput or out put designation of every pin fully under user program control, pull-high selections for all ports and wake-up selections on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. These de vices provi de bi directional i nput/output l ines. T hese I/ O port s a re m apped t o t he RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports c an be use d for i nput and out put opera tions. For i nput opera tion, t hese ports a re non-latching, which means the inputs must be ready at the T2 rising edge of instruction "MOV A, [m]", where "m" denotes the port address. For output operation, all the data is latched and remains unchanged until the output latch is rewritten. Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 — — PA4 PA3 PA2 PA1 PA0 PAC PAC7 — — PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 — — PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 — — PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB PB PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC PBC PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU PBPU PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC PC PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC PCC PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU PCPU PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 IFS — — — — CTP0BPS CTP0PS OCVPAI2PS OCVPAI1PS "—": Unipleented ead as "0". I/O Logic Function Registers List – BS87B12A-3 Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 — — PA4 PA3 PA2 PA1 PA0 PAC PAC7 — — PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 — — PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 — — PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB PB PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC PBC PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU PBPU PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC PC PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC PCC PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU PCPU PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD7 PD PD PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC PDC PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU PDPU PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 "—": Unipleented ead as "0". I/O Logic Function Registers List – BS87C16A-3

Rev. 1.20 7 Deee 0 201 Rev. 1.20 77 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Register Name Bit 7 6 5 4 3 2 1 0 PA PA7 — — PA4 PA3 PA2 PA1 PA0 PAC PAC7 — — PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 — — PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 — — PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 PB PB7 PB PB PB4 PB3 PB2 PB1 PB0 PBC PBC7 PBC PBC PBC4 PBC3 PBC2 PBC1 PBC0 PBPU PBPU7 PBPU PBPU PBPU4 PBPU3 PBPU2 PBPU1 PBPU0 PC PC7 PC PC PC4 PC3 PC2 PC1 PC0 PCC PCC7 PCC PCC PCC4 PCC3 PCC2 PCC1 PCC0 PCPU PCPU7 PCPU PCPU PCPU4 PCPU3 PCPU2 PCPU1 PCPU0 PD PD7 PD PD PD4 PD3 PD2 PD1 PD0 PDC PDC7 PDC PDC PDC4 PDC3 PDC2 PDC1 PDC0 PDPU PDPU7 PDPU PDPU PDPU4 PDPU3 PDPU2 PDPU1 PDPU0 PE PE7 PE PE PE4 PE3 PE2 PE1 PE0 PEC PEC7 PEC PEC PEC4 PEC3 PEC2 PEC1 PEC0 PEPU PEPU7 PEPU PEPU PEPU4 PEPU3 PEPU2 PEPU1 PEPU0 PF — — — — PF3 PF2 PF1 PF0 PFC — — — — PFC3 PFC2 PFC1 PFC0 PFPU — — — — PFPU3 PFPU2 PFPU1 PFPU0 "—": Unipleented ead as "0". I/O Logic Function Registers List – BS87D20A-3 Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an external resistor . T o eliminate the need for these external resistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor . These pull-high resistors are selected using the relevant pull-high control registers and are implemented using weak PMOS transistors. PxPU Register Bit 7 6 5 4 3 2 1 0 Nae PxPU7 PxPU PxPU PxPU4 PxPU3 PxPU2 PxPU1 PxPU0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 PxPUn: I/O Port x Pin pull-high function control 0: Disable 1: Enable The PxPUn bit is used to control the pin pull-high function. Here the "x" is the Port name which can be A, B, C, D, E and F depending upon the selected device. However, the actual available bits for each I/O Port may be different.

Rev. 1.20 78 Deee 0 201 Rev. 1.20 79 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Port A Wake-up The HAL T instruction forces the microcontroller into the SLEEP or IDLE Mode which preserves power, a feature that is important for battery and other low-power applications. V arious methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low . This function is especially suitable for applications that can be woken up via extern al switches. Each pin on Port A can be selected individually to have this wake-up feature using the PAWU register. PAWU Register Bit 7 6 5 4 3 2 1 0 Nae PAWU7 — — PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R/W R/W — — R/W R/W R/W R/W R/W POR 0 — — 0 0 0 0 0 Bit 7, 4~0 P AWU7, PAWU4~PAWU0 : Port A pin W ake-up function control 0: Disable 1: Enable Bit 6~5 Unimplemented, read as 0. I/O Port Control Registers Each Port has i ts own control regi ster whi ch cont rols t he i nput/output c onfiguration. W ith t his control register , each I/O pin with or without pull-high resistors can be reconfigured dynamically under software control. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a "1". This will then allow the logic state of the input pin to be directly read by instructio ns. When the corresponding bit of the control registe r is written as a "0", the I/O pin will be setup as a CMOS output. If the pin is currently setup as an output, instructions can still be use d t o rea d t he output regi ster. Howe ver, i t shoul d be note d t hat t he progra m wi ll i n fac t only read the status of the output data latch and not the actual logic status of the output pin. PxC Register Bit 7 6 5 4 3 2 1 0 Nae PxC7 PxC PxC PxC4 PxC3 PxC2 PxC1 PxC0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 1 1 1 1 1 1 1 1 PxCn: I/O Port x Pin type selection 0: Output 1: Input The PxCn bit is used to control the pin type selection. Here the "x" is the Port name which can be A, B, C, D, E and F depending upon the selected device. However, the actual available bits for each I/O Port may be different.

Rev. 1.20 78 Deee 0 201 Rev. 1.20 79 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP I/O Port Source Current Selection These devices support dif ferent output source current driving capability for each I/O port. W ith the selection register , SLEDCn, specific I/O port can support four levels of the source current driving capability. Users should refer to the I/O Port characteristics section to select the desired output source current for different applications. Register Name Bit 7 6 5 4 3 2 1 0 SLEDC0 PBPS3 PBPS2 PBPS1 PBPS0 PAPS3 PAPS2 PAPS1 PAPS0 SLEDC1 — — — — PCPS3 PCPS2 PCPS1 PCPS0 I/O Port Source Current Selection Registers List – BS87B12A-3 Register Name Bit 7 6 5 4 3 2 1 0 SLEDC0 PBPS3 PBPS2 PBPS1 PBPS0 PAPS3 PAPS2 PAPS1 PAPS0 SLEDC1 PDPS3 PDPS2 PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCPS0 I/O Port Source Current Selection Registers List – BS87C16A-3 Register Name Bit 7 6 5 4 3 2 1 0 SLEDC0 PBPS3 PBPS2 PBPS1 PBPS0 PAPS3 PAPS2 PAPS1 PAPS0 SLEDC1 PDPS3 PDPS2 PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCPS0 SLEDC2 — — PFPS1 PFPS0 PEPS3 PEPS2 PEPS1 PEPS0 I/O Port Source Current Selection Registers List – BS87D20A-3 SLEDC0 Register Bit 7 6 5 4 3 2 1 0 Nae PBPS3 PBPS2 PBPS1 PBPS0 PAPS3 PAPS2 PAPS1 PAPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PBPS3~PBPS2: PB7~PB4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 5~4 PBPS1~PBPS0: PB3~PB0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 3~2 PAPS3~PAPS2: PA7 and PA4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PAPS1~PAPS0: PA3~PA0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.)

Rev. 1.20 80 Deee 0 201 Rev. 1.20 81 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SLEDC1 Register – BS87B12A-3 Bit 7 6 5 4 3 2 1 0 Nae — — — — PCPS3 PCPS2 PCPS1 PCPS0 R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3~2 PCPS3~PCPS2: PC7~PC4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PCPS1~PCPS0: PC3~PC0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) SLEDC1 Register – BS87C16A-3 & BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae PDPS3 PDPS2 PDPS1 PDPS0 PCPS3 PCPS2 PCPS1 PCPS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PDPS3~PDPS2: PD7~PD4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 5~4 PDPS1~PDPS0: PD3~PD0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 3~2 PCPS3~PCPS2: PC7~PC4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PCPS1~PCPS0: PC3~PC0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.)

Rev. 1.20 80 Deee 0 201 Rev. 1.20 81 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SLEDC2 Register – BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae — — PFPS1 PFPS0 PEPS3 PEPS2 PEPS1 PEPS0 R/W — — R/W R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as 0. Bit 5~4 PFPS1~PFPS0: PF3~PF0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 3~2 PEPS3~PEPS2: PE7~PE4 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Bit 1~0 PEPS1~PEPS0: PE3~PE0 source current selection 00: source current=Level 0 (min.) 01: source current=Level 1 10: source current=Level 2 11: source current=Level 3 (max.) Pin-remapping Function – BS87B12A-3 only The flexibility of the microcontroller range is greatly enhanced by the use of pins that have more than one function. Limited numbers of pins can force serious design constraints on designers but by suppl ying pi ns wi th m ulti-functions, m any of t hese di fficulties c an be ove rcome. T he wa y i n which the pin function of specific pins is selected is dif ferent for each function and a priority order is established where more than one pin function is selected simultaneously . Note that the pin- remapping function is only available for the BS87B12A-3 device. Pin-remapping Selection Register The limited number of supplied pins in a package can i mpose restrictions on the amount of functions a certain device can contain. However by allowing the same pins to share several dif ferent functions and providing a means of function selection, a wide range of dif ferent functions can be incorporated into even relatively small package sizes.

IFS Register Bit 7 6 5 4 3 2 1 0 Nae — — — — CTP0BPS CTP0PS OCVPAI2PS OCVPAI1PS R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as 0. Bit 3 CTP0BPS: CTP0B pin remapping function selection 0: CTP0B on PC6 1: CTP0B on PC2 Bit 2 CTP0PS: CTP0 pin remapping function selection 0: CTP0 on PC7 1: CTP0 on PC3 Bit 1 OCVPAI2P: OCVPAI2 pin remapping function selection 0: OCVPAI2 on PC7 1: OCVPAI2 on PC3

Rev. 1.20 82 Deee 0 201 Rev. 1.20 83 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 0 OCVPAI1P: OCVPAI1 pin remapping function selection 0: OCVPAI1 on PC6 1: OCVPAI1 on PC2 I/O Pin Structures The accompanyin g diagram illustrates the internal structures of the I/O logic function. As the exact logical construction of the I/O pin will dif fer from this drawing, it is supplied as a guide only to assist with the functional understanding of the logic function I/O pins. The wide range of pin-shared structures does not permit all types to be shown. M U X VDD Contol Bit Data Bit Data Bus Wite Contol Registe Chip Reset Read Contol Registe Read Data Registe Wite Data Registe Syste Wake-up wake-up Selet I/O pin Weak Pull-up Pull-high Registe Selet Q D CK Q D CK Q Q S S PA only Logic Function Input/Output Structure Programming Considerations Within the user program, one of the things firs t to consider is port initialisation. After a res et, all of the I/O data and port control registers will be set to high. This means that all I/O pins will be defaulted to an input state, the level of which depends on the other connected circuitry and whether pull-high selections have been chosen. If the port control registers are then programmed to setup some pins as outputs, these output pins will have an initial high output value unless the associated port data registers are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control register or by programming individual bits in the port control register using the "SET [m].i" and "CLR [m].i" instructions. Note that when using these bit control instructions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then rewrite this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the SLEEP or IDLE Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function.

Rev. 1.20 82 Deee 0 201 Rev. 1.20 83 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Timer Modules – TM One of the most fundamental functions in any microcontroller devices is the ability to control and measure time. T o implement time related functions the device includes several T imer Modules, generally abbrevia ted to the name TM. The TMs are multi-purpose timi ng units and serve to provide operations such as T imer/Counter, Input Capture, Compare Match Output and Single Pulse Output as we ll a s be ing t he fun ctional uni t for t he ge neration of PW M si gnals. E ach of t he T Ms ha s t wo interrupts. The addition of input and output pins for each TM ensures that users are provided with timing units with a wide and flexible range of features. The common features of the dif ferent TM types are described here with more detailed information provided in the individual Compact and Periodic TM sections. Introduction These devices contain s everal TM s and each individual TM can be categoris ed as a certain type, namely Compact T ype TM or Periodic T ype TM. Although similar in nature, the dif ferent TM types vary in thei r feature complexit y. The comm on features to al l of the Com pact and Periodic TMs will be described in this section and the detailed operation regarding each of the TM types will be described in separate sections. The main features and dif ferences between the two types of TMs are summarised in the accompanying table. TM Function CTM PTM Tie/Counte √ √ Input Captue — √ Copae Math Output √ √ PWM Channels 1 1 Single Pulse Output — 1 PWM Alignent Edge Edge PWM Adjustent Peiod & Duty Duty o Peiod Duty o Peiod TM Function Summary Device CTM PTM BS87B12A-3 CTM0 PTM0 BS87C1A-3 CTM0 PTM0 PTM1 BS87D20A-3 CTM0 CTM1 PTM0 PTM1 TM Name/Type Summary TM Operation The dif ferent types of TM of fer a diverse range of functions, from simple timing operations to PWM signal generation. The key to understanding how the TM operates is to see it in terms of a free running count-up counter whose value is then compared with the value of pre-programmed internal comparators. W hen t he f ree r unning c ount-up c ounter h as t he sa me v alue a s t he p re-programmed comparator, known a s a c ompare m atch si tuation, a T M i nterrupt si gnal wi ll be ge nerated whi ch can clear the counter and perhaps also change the condition of the TM output pin. The internal TM counter is driven by a user selectable clock source, which can be an internal clock or an external pin.

Rev. 1.20 84 Deee 0 201 Rev. 1.20 8 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP TM Clock Source The c lock so urce wh ich d rives t he m ain c ounter i n e ach T M c an o riginate f rom v arious so urces. The selection of the required clock source is implemented using the xTnCK2~xTnCK0 bits in the xTMn control regis ters, w here " x" stands for C or P type TM and " n" stands for the specific TM serial number . The clock source can be a ratio of the system clock, fSYS, or the internal high clock, fH, the fSUB clock source or the external xTCKn pin. The xTCKn pin clock source is used to allow an external signal to drive the TM as an external clock source for event counting. TM Interrupts The Compact or Periodic type TM each has two internal interrupt, one for each of the internal comparator A or comparator P , which generate a TM interrupt when a compare match condition occurs. When a TM interrupt is generated, it can be used to clear the counter and also to change the state of the TM output pin. TM External Pins Each of the T Ms, irrespective of what type, has two T M input pins, with the label xTCKn and PTPnI respectively. The xTMn input pin, xTCKn, is essentially a clock source for the xTMn and is selected using the xTnCK2~xTnCK0 bits in the xTMnC0 register . This external TM input pin allows an external clock source to drive the internal TM. The xTCKn input pin can be chosen to have either a rising or falling active edge. The PTCKn pins are also used as the exter nal trigger input pin in single pulse output mode for the PTMn. The ot her PT M i nput pi n, PT PnI, i s t he c apture i nput whose a ctive e dge c an be a ri sing e dge, a falling edge or both rising and fallin g edges and the active edge transit ion type is selected using the PTnIO1~PTnIO0 bits in the PTMnC1 register . There is another capture input, PTCKn, for PTMn capture input mode, which can be used as the external trigger input source except the PTPnI pin. The TMs each have two output pin, xTPn and xTPnB. When the TM is in the Compare Match Output Mode, these pins can be controlled by the TM to switch to a high or low level or to toggle when a compare match situation occurs. The external xTPn and xTPnB output pins are also the pins where the xTMn generates the PWM output waveform. As the xTMn output pins are pin-shared with other functio ns, the TM output function must first be setup using the relevant registers. A signal bit in the register determines if its associated pin is to be used as an external TM output pin or if it is to have another function. The number of external pins for each TM type is dif ferent, the details are provided in the accompanying table. Device CTM PTM Input Output Input Output BS87B12A-3 CTCK0 CTP0 CTP0B PTCK0 PTP0I PTP0 PTP0B BS87C1A-3 CTCK0 CTP0 CTP0B PTCK0 PTP0I PTCK1 PTP1I PTP0 PTP0B PTP1 PTP1B BS87D20A-3 CTCK0 CTCK1 CTP0 CTP0B CTP1 CTP1B PTCK0 PTP0I PTCK1 PTP1I PTP0 PTP0B PTP1 PTP1B TM External Pins

Rev. 1.20 84 Deee 0 201 Rev. 1.20 8 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP TM Input/Output Pin Control Register Selecting t o ha ve a T M i nput/output or whe ther t o re tain i ts ot her sha red func tion i s i mplemented using one register , with a single bit in the register corresponding to a TM input/output pin. Setting the bit high will setup the corresponding pin as a TM input/output, if reset to zero the pin will retain its original other function. TMPC0 Register – BS87B12A-3 Bit 7 6 5 4 3 2 1 0 Nae VREFS — — — PTM0PC1 PTM0PC0 CTM0PC1 CTM0PC0 R/W R/W — — — R/W R/W R/W R/W POR 0 — — — 0 0 0 0 Bit 7 VREFS: VREF pin control 0: Disabled 1: Enabled Bit 6~4 Unimplemented, read as 0. Bit 3 PTM0PC1: PTP0B pin control 0: Disabled 1: Enabled Bit 2 PTM0PC0: PTP0 pin control 0: Disabled 1: Enabled Bit 1 CTM0PC1: CTP0B pin control 0: Disabled 1: Enabled Bit 0 CTM0PC0: CTP0 pin control 0: Disabled 1: Enabled TMPC0 Register – BS87C16A-3 & BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae VREFS — PTM1PC1 PTM1PC0 PTM0PC1 PTM0PC0 CTM0PC1 CTM0PC0 R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 0 0 0 Bit 7 VREFS: VREF pin control 0: Disabled 1: Enabled Bit 6 Unimplemented, read as 0. Bit 5 PTM1PC1: PTP1B pin control 0: Disabled 1: Enabled Bit 4 PTM1PC0: PTP1 pin control 0: Disabled 1: Enabled Bit 3 PTM0PC1: PTP0B pin control 0: Disabled 1: Enabled Bit 2 PTM0PC0: PTP0 pin control 0: Disabled 1: Enabled

Rev. 1.20 8 Deee 0 201 Rev. 1.20 87 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 1 CTM0PC1: CTP0B pin control 0: Disabled 1: Enabled Bit 0 CTM0PC0: CTP0 pin control 0: Disabled 1: Enabled TMPC1 Register – BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae — — — — — — CTM1PC1 CTM1PC0 Bit 7~2 Unimplemented, read as 0. Bit 1 CTM1PC1: CTP1B pin control 0: Disabled 1: Enabled Bit 0 CTM1PC0: CTP1 pin control 0: Disabled 1: Enabled CTM0 PA4/CTCK0 PC/CTP0B CCR output CTCK0 input PC7 PC CTM0PC0 PC7 Output Funtion CTM0PC1 PC Output Funtion PC7/CTP0 CTM0 Function Pin Control Block Diagram CTM1 PF0/CTCK1 PF2/CTP1B CCR output CTCK1 input PF1 PF2 CTM1PC0 PF1 Output Funtion CTM1PC1 PF2 Output Funtion PF1/CTP1 CTM1 Function Pin Control Block Diagram – BS87D20A-3

Rev. 1.20 8 Deee 0 201 Rev. 1.20 87 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PTM0 PA0/PTCK0 PC4/PTP0B CCR output PTCK0 input PC PC4 PTM0PC0 PC Output Funtion PTM0PC1 PC4 Output Funtion PC/PTP0 PT0CAPTS PTM0 Captue input PA2/PTP0I PTM0 Function Pin Control Block Diagram PTM1 PB/PTCK1 PD3/PTP1B CCR output PTCK1 input PB PD3 PTM1PC0 PB Output Funtion PTM1PC1 PD3 Output Funtion PB/PTP1 PT1CAPTS PTM1 Captue input PB7/PTP1I PTM1 Function Pin Control Block Diagram – BS87C16A-3 & BS87D20A-3

Rev. 1.20 88 Deee 0 201 Rev. 1.20 89 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Programming Considerations The TM Counter Registers and the Capture/Compare CCRA and CCRP registers, all have a low and high byte structure. The high bytes can be directly accessed, but as the low bytes can only be accessed via an internal 8-bit buf fer, reading or writing to these registe r pairs must be carried out in a specific way . The important point to note is that data transfer to and from the 8-bit buf fer and its related l ow b yte o nly t akes p lace wh en a wr ite o r r ead o peration t o i ts c orresponding h igh b yte i s executed. As the CCRA and CCRP registers are implemented in the way shown in the following diagram and accessing these register pairs is carried out in a specific way as described above, it is recommended to us e the " MOV" instruction to access the CCRA and CCRP low byte registers, named xTMnAL and PTMnRPL, using the following access procedures. Acces sing the CCRA or CCRP low byte registers without following these access procedures will result in unpredictable values. Data Bus 8-it Buffe xTMnDHxTMnDL xTMnAHxTMnAL xTMn Counte Registe (Read only) xTMn CCRA Registe (Read/Wite) PTMnRPHPTMnRPL PTMn CCRP Registe (Read/Wite) The following steps show the read and write procedures:

Writing Data to CCRA or CCRP ♦ Step 1. W rite data to Low Byte xTMnAL or PTMnRPL –note that here data is only written to the 8-bit buffer. ♦ Step 2. W rite data to High Byte xTMnAH or PTMnRPH –here data is written directly to the high byte regis ters and simultaneously data is latched from the 8-bit buffer to the Low Byte registers.
Reading Data from the Counter Registers and CCRA or CCRP ♦ Step 1. Read data from the High Byte xTMnDH, xTMnAH or PTMnRPH –here d ata i s r ead d irectly f rom t he Hi gh B yte r egisters a nd si multaneously d ata i s l atched from the Low Byte register into the 8-bit buffer. ♦ Step 2. Read data from the Low Byte xTMnDL, xTMnAL or PTMnRPL –this step reads data from the 8-bit buffer.

Rev. 1.20 88 Deee 0 201 Rev. 1.20 89 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Compact Type TM – CTM0, CTM1 The Compact T ype TM contains three operating modes, which are Compare Match Output, T imer/ Event Counter and PWM Output modes. The Compact TM can also be controlled with an external input pin and can drive two external output pins. Device CTM Core CTM Input Pin CTM Output Pin Note BS87B12A-3 10-it CTM (CTM0) CTCK0 CTP0 CTP0B n=0 BS87C1A-3 10-it CTM (CTM0) CTCK0 CTP0 CTP0B n=0 BS87D20A-3 10-it CTM (CTM0 CTM1) CTCK0 CTCK1 CTP0 CTP0B CTP1 CTP1B n=0 1 fSYS fSYS/4 fH/4 fH/1 fSUB CTCKn 000 001 010 011 100 101 110 111 CTnCK2~CTnCK0 10-it Count-up Counte 3-it Copaato P CCRP 7~9 0~10 10-it Copaato A CTnON CTnPAU Copaato A Math Copaato P Math Counte Clea 0 Output Contol Polaity Contol Output Copleentay CTPn CTnOC CTnM1 CTnM0 CTnIO1 CTnIO0 CTMnAF Inteupt CTMnPF Inteupt CTnPOL CCRA CTnCCLRfSUB CTPnB Compact Type TM Block Diagram – n=0 or 1 Compact Type TM Operation The size of Compact TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or externa l clock source. There are also two internal comparators with the names, Comparato r A and Comparator P . These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP comparator is 3-bit wide whose value is compared with the highest 3 bits in the counter while the CCRA is the 10 bits and therefore compares all counter bits. The onl y way of changing the value of the 10-bit counte r using the appl ication program , is to clear t he c ounter by c hanging t he CT nON bi t from l ow t o hi gh. T he c ounter wi ll a lso be c leared automatically by a counter overflow or a compare match with one of its associated comparators. When these conditions occur , a CTM interrupt signal will also usually be generated. The Compact Type TM can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control an output pin. All operating setup conditions are selected using relevant internal registers.

Rev. 1.20 90 Deee 0 201 Rev. 1.20 91 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Compact Type TM Register Description Overall operation of the Compact TM is controlled using a series of registers. A read only register pair e xists t o st ore t he i nternal c ounter 10 -bit va lue, whi le a re ad/write re gister pa ir e xists t o st ore the internal 10-bit CCRA value. The remaining two registers are control registers which setup the different operating and control modes as well as the CCRP bits. Register Name Bit 7 6 5 4 3 2 1 0 CTMnC0 CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0 CTMnC1 CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR CTMnDL D7 D D D4 D3 D2 D1 D0 CTMnAL D7 D D D4 D3 D2 D1 D0 10-bit Compact TypeTM Registers List – n=0 or 1 CTMnDL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 CTMn Counter Low Byte Register bit 7 ~ bit 0 CTMn 10-bit Counter bit 7 ~ bit 0 CTMnDH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2: Unimplemented, read as 0. Bit 1~0: CTMn Counter High Byte Register bit 1 ~ bit 0 CTMn 10-bit Counter bit 9 ~ bit 8 CTMnAL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 CTMn CCRA Low Byte Register bit 7 ~ bit 0 CTMn 10-bit CCRA bit 7 ~ bit 0 CTMnAH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2: Unimplemented, read as 0. Bit 1~0: CTMn CCRA High Byte Register bit 1 ~ bit 0 CTMn 10-bit CCRA bit 9 ~ bit 8

Rev. 1.20 90 Deee 0 201 Rev. 1.20 91 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP CTMnC0 Register Bit 7 6 5 4 3 2 1 0 Nae CTnPAU CTnCK2 CTnCK1 CTnCK0 CTnON CTnRP2 CTnRP1 CTnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CTnPAU: CTMn Counter Pause control 0: Run 1: Pause The c ounter c an be pa used by se tting t his bi t hi gh. Cl earing t he bi t t o z ero re stores normal counter operation. When in a Pause condition the CTMn will remain powered up a nd c ontinue t o c onsume po wer. T he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. Bit 6~4 CTnCK2~CTnCK0: Select CTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: CTCKn rising edge clock 111: CTCKn falling edge clock These t hree bi ts a re use d t o se lect t he c lock sourc e for t he CT Mn. T he e xternal pi n clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section. Bit 3 CTnON: CTMn Counter On/Off control 0: Off 1: On This bit controls the overall on/of f function of the CTMn. Setting the bit high enables the counter to run while clearing the bit disables the CTMn. Clearing this bit to zero will stop the counter from counting and turn off the CTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. If the CTMn is in the Compare Match Output Mode then the CTMn output pin will be reset to its initial condition, as specified by the CTnOC bit, when the CTnON bit changes from low to high. Bit 2~0 CTnRP2~CTnRP0: CTMn CCRP 3-bit register, compared with the CTMn counter bit 9~bit 7 Comparator P match period = 0: 1024 CTMn clocks 1~7: (1~7) x 128 CTMn clocks These three bits are used to setup the value on the internal CCRP 3-bit register , which are then compared with the internal counter ’s highest 3 bits. The result of this comparison can be selected to clear the internal counter if the CTnCCLR bit is set to zero. Setting the CTnCCLR bit to zero ensures that a compare match with the CCRP values will reset the internal counter . As the CCRP bits are only compared with the highest three counter bits, the compare values exist in 128 clock cycle multiples. Clearing a ll e ight bi ts t o z ero i s i n e ffect a llowing t he c ounter t o ove rflow a t i ts maximum value.

Rev. 1.20 92 Deee 0 201 Rev. 1.20 93 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP CTMnC1 Register Bit 7 6 5 4 3 2 1 0 Nae CTnM1 CTnM0 CTnIO1 CTnIO0 CTnOC CTnPOL CTnDPX CTnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 CTnM1~CTnM0: Select CTMn Operating Mode 00: Compare Match Output Mode 01: Undefined 10: PWM Output Mode 11: T imer/Counter Mode These bits s etup the required operating mode for the CTM n. T o ens ure reliable operation the CTMn should be switched of f before any changes are made to the CTnM1 a nd C TnM0 b its. I n t he T imer/Counter Mo de, t he C TMn o utput p in c ontrol will be disabled. Bit 5~4 CTnIO1~CTnIO0: Select CTMn external pin CTPn function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: T oggle output PWM Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Undefined Timer/Counter Mode Unused These two bits are used to determin e how the CTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the CTMn is running. In the Compare Match Output Mode, the CTnIO1 and CTnIO0 bits determine how the CTMn o utput p in c hanges st ate wh en a c ompare m atch o ccurs f rom t he C omparator A. The CTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the CTMn output pi n sho uld be se tup usi ng t he C TnOC bi t i n t he C TMnC1 re gister. Not e t hat the output level requested by the CTnIO1 and CTnIO0 bits must be dif ferent from the initial value setup using the CTnOC bit otherwise no change will occur on the CTMn output pi n when a com pare match occurs. After the CTMn output pi n changes state, it can be reset to its initial level by changing the level of the CTnON bit from low to high. In t he PW M out put m ode, t he CT nIO1 a nd CTnIO0 bi ts de termine how t he CT Mn output pin changes state when a certain compare match condition occurs. The PWM output function is modified by changing these two bits. It is necessary to only change the values of the CTnIO1 and CTnIO0 bits only after the CTMn has been switched off. Unpredictable PWM outputs will occur if the CTnIO1 and CTnIO0 bits are changed when the CTMn is running.

Rev. 1.20 92 Deee 0 201 Rev. 1.20 93 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 3 CTnOC: CTMn CTPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode 0: Active low 1: Active high This i s t he ou tput c ontrol bi t fo r t he CT Mn o utput pi n. It s op eration de pends up on whether CT Mn i s be ing used i n t he Com pare Ma tch Output Mode or i n t he PWM Output Mode. It has no ef fect if the CTMn is in the T imer/Counter Mode. In the Compare Match O utput Mode it determines the logic level of the CTMn output pin before a compare match occurs. In the PWM Output Mode it determin es if the PWM signal is active high or active low. Bit 2 CTnPOL: CTMn CTPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the pol arity of the CTPn out put pin. When the bit is set high the CTMn output pin will be inverted and not inverted when the bit is zero. It has no effect if the CTMn is in the T imer/Counter Mode. Bit 1 CTnDPX: CTMn PWM duty/period control 0: CCRP – period; CCRA – duty 1: CCRP – duty; CCRA – period This b it d etermines wh ich o f t he C CRA a nd C CRP r egisters a re u sed f or p eriod a nd duty control of the PWM waveform. Bit 0 CTnCCLR: CTMn Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. Re member t hat t he CTMn contains two comparators, Comparator A and Comparator P , either of which can be selected to clear the internal counter . W ith the CTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bi t i s l ow, t he c ounter wi ll be c leared whe n a c ompare m atch oc curs from t he Comparator P or with a counter overflow . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The CTnCCLR bit is not used in the PWM Output Mode.

Rev. 1.20 94 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Compact Type TM Operation Modes The Compact T ype TM can operate in one of three operating modes, Compare Match Output Mode, PWM Output Mode or T imer/Counter Mode. The operating mode is selected using the CTnM1 and CTnM0 bits in the CTMnC1 register. Compare Match Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register , should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow , a compare match from Comparator A and a compare match from Comparator P . When the CTnCCLR bit is low , there are two ways in which the counter can be cleared. One is when a compare match from Comparator P , the other is when the CCRP bits are all zero which allows the counter to overflow . Here both CTMnAF and CTMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the CTnCCLR bit in the CTMnC1 register is high then the counter will be cleared when a compare match occurs from Com parator A. However , here onl y the CTMnAF interrupt request flag wil l be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when CTnCCLR is high no CTM nPF interrupt request flag will be generated. If the CCRA bits are all zero, the counter will overflow when it reaches its maximum value. However , here the CTMnAF interrupt request flag will not be generated. As the name of the mode suggests, after a comparison is made, the CTMn output pin, will change state. The CTMn output pin condition however only changes state when a CTMnAF interrupt request flag is generated after a compare match occurs from Comparat or A. The CTMnPF interrupt request fla g, g enerated f rom a c ompare m atch o ccurs f rom C omparator P , wi ll h ave n o e ffect o n the CTMn output pin. The way in which the CTMn output pin changes state are determined by the condition of the CTnIO1 and CTnIO0 bits in the CTMnC1 register . The CTMn output pin can be selected using the CTnIO1 and CTnIO0 bits to go high, to go low or to toggle from its present condition when a compare match occurs from Comparator A. The initial condition of the CTMn output pin, which is setup after the CTnON bit changes from low to high, is setup using the CTnOC bit. Note that if the CTnIO1 and CTnIO0 bits are zero then no pin change will take place.

Rev. 1.20 94 Deee 0 201 Rev. 1.20 9 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value 0x3FF CCRP CCRA CTnON CTnPAU CTnPOL CCRP Int. flag CTMnPF CCRA Int. flag CTMnAF CTMn O/P Pin Tie CCRP=0 CCRP > 0 Counte oveflow CCRP > 0 Counte leaed y CCRP value Pause Resue Stop Counte Restat CTnCCLR = 0; CTnM [1:0] = 00 Output pin set to initial Level Low if CTnOC=0 Output Toggle with CTMnAF flag Note CTnIO [1:0] = 10 Ative High Output seletHee CTnIO [1:0] = 11 Toggle Output selet Output not affeted y CTMnAF flag. Reains High until eset y CTnON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when CTnPOL is high Compare Match Output Mode – CTnCCLR=0 Note: 1. W ith CTnCCLR=0 a Comparator P match will clear the counter 2. The CTMn output pin is controlled only by the CTMnAF flag 3. The output pin is reset to its initial state by a CTnON bit rising edge 4. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 9 Deee 0 201 Rev. 1.20 97 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value 0x3FF CCRP CCRA CTnON CTnPAU CTnPOL CTMn O/P Pin Tie CCRA=0 CCRA = 0 Counte oveflowCCRA > 0 Counte leaed y CCRA value Pause Resue Stop Counte Restat Output pin set to initial Level Low if CTnOC=0 Output Toggle with CTMnAF flag Note CTnIO [1:0] = 10 Ative High Output seletHee CTnIO [1:0] = 11 Toggle Output selet Output not affeted y CTMnAF flag. Reains High until eset y CTnON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when CTnPOL is high CTMnPF not geneated No CTMnAF flag geneated on CCRA oveflow Output does not hange CTnCCLR = 1; CTnM [1:0] = 00 CCRA Int. flag CTMnAF CCRP Int. flag CTMnPF Compare Match Output Mode – CTnCCLR=1 Note: 1. W ith CTnCCLR=1 a Comparator A match will clear the counter 2. The CTMn output pin is controlled only by the CTMnAF flag 3. The output pin is reset to its initial state by a CTnON bit rising edge 4. A CTMnPF flag is not generated when CTnCCLR=1 5. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 9 Deee 0 201 Rev. 1.20 97 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Timer/Counter Mode To se lect t his m ode, bi ts CT nM1 and CT nM0 i n t he CTMnC1 regi ster shoul d be se t t o 1 1 respectively. The T imer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the T imer/Counter Mode the CTMn output pin is not used. Therefore the above description and T iming Diagrams for the Compare Match Output Mode can be used to understand its function. As the CTMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits CTnM1 and CTnM0 in the CTMnC1 register should be set to 10 respectively. The PWM function within the CTMn is useful for applications which require functions such a s m otor c ontrol, he ating c ontrol, i llumination c ontrol, e tc. By pr oviding a si gnal of fi xed frequency but of varying duty cycle on the CTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform is extremely flexible. In the PWM mode, the CTnCCLR bit has no ef fect as the PWM period. Both of the CCRA and CCRP registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency , while the other one is used to control the duty cycle. Which register is used to control either frequency or duty cycle is determ ined using the CTnDPX bit in the CTMnC1 register . The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP , will be generated when a compare match occurs from either Comparator A or Comparator P . The CTnOC bit in the CTMnC1 register is used to select the required polarity of the PWM waveform while the tw o CTnIO1 and CTnIO0 bits are used to enable the PWM output or to force the CTMn output pin to a fixed high or low level. The CTnPOL bit is used to reverse the polarity of the PWM output waveform.

10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=0 CCRP 1~7 0 Peiod CCRP×128 1024 Duty CCRA If fSYS=16MHz, CTMn clock source is fSYS/4, CCRP=4 and CCRA=128, The CTMn PWM output frequency=(fSYS/4)/(4×128)=fSYS/2048=8 kHz, duty=128/(4×128)= 25%. If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.
10-bit CTMn, PWM Mode, Edge-aligned Mode, CTnDPX=1 CCRP 1~7 0 Peiod CCRA Duty CCRP×128 1024 The PWM output period is determi ned by the CCRA register value together with the CTMn clock while t he PW M d uty c ycle i s d efined b y t he C CRP r egister v alue e xcept wh en t he C CRP v alue i s equal to 0.

Rev. 1.20 98 Deee 0 201 Rev. 1.20 99 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value CCRP CCRA CTnON CTnPAU CTnPOL CTMn O/P Pin (CTnOC=1) Tie Counte leaed y CCRP Pause Resue Counte Stop if CTnON it low Counte Reset when CTnON etuns high PWM Duty Cyle set y CCRA PWM esues opeationOutput ontolled y othe pin-shaed funtion Output Invets when CTnPOL = 1 PWM Peiod set y CCRP CTMn O/P Pin (CTnOC=0) CCRA Int. flag CTMnAF CCRP Int. flag CTMnPF CTnDPX = 0; CTnM [1:0] = 10 PWM Output Mode – CTnDPX=0 Note: 1. Here CTnDPX=0 – Counter cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when CTnIO [1:0]=00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 98 Deee 0 201 Rev. 1.20 99 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value CCRP CCRA CTnON CTnPAU CTnPOL CCRP Int. flag CTMnPF CCRA Int. flag CTMnAF CTMn O/P Pin (CTnOC=1) Tie Counte leaed y CCRA Pause Resue Counte Stop if CTnON it low Counte Reset when CTnON etuns high PWM Duty Cyle set y CCRP PWM esues opeationOutput ontolled y othe pin-shaed funtion Output Invets when CTnPOL = 1 PWM Peiod set y CCRA CTMn O/P Pin (CTnOC=0) CTnDPX = 1; CTnM [1:0] = 10 PWM Output Mode – CTnDPX=1 Note: 1. Here CTnDPX=1 – Counter cleared by CCRA 2. A counter clear sets the PWM Period 3. The internal PWM function continues even when CTnIO [1:0]=00 or 01 4. The CTnCCLR bit has no influence on PWM operation 5. n=0 or 0~1 depending upon which device is selected.

Rev. 1.20 100 Deee 0 201 Rev. 1.20 101 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Periodic Type TM – PTM The Pe riodic T ype T M c ontains fiv e operating m odes, wh ich a re C ompare Ma tch Ou tput, T imer/ Event Counter , Capture Input, Single Pulse Output and PWM Output modes. The Periodic TM can also be controlled with two external input pins and can drive two external output pin. Device PTM Core PTM Input Pin PTM Output Pin Note BS87B12A-3 10-it PTM (PTM0) PTCK0 PTP0 PTP0B n=0 BS87C1A-3 10-it PTM (PTM0 PTM1) PTCK0 PTCK1 PTP0 PTP0B PTP1 PTP1B n=0 1 BS87D20A-3 10-it PTM (PTM0 PTM1) PTCK0 PTCK1 PTP0 PTP0B PTP1 PTP1B n=0 1 fSYS fSYS/4 fH/4 fH/1 fSUB PTCKn 000 001 010 011 100 101 110 111 PTnCK2~PTnCK0 10-it Count-up Counte 10-it Copaato P CCRP 0~9 0~9 10-it Copaato A PTnON PTnPAU Copaato A Math Copaato P Math Counte Clea 0 Output Contol Polaity Contol Output Copleentay PTPn PTnOC PTnM1 PTnM0 PTnIO1 PTnIO0 PTMnAF Inteupt PTMnPF Inteupt PTnPOL CCRA PTnCCLR Edge Deteto PTPnI PTnIO1 PTnIO0 fSUB PTnCAPTS PTPnB 10-bit Periodic Type TM Block Diagram – n=0 or 1 Periodic TM Operation The size of Periodic TM is 10-bit wide and its core is a 10-bit count-up counter which is driven by a user selectable internal or externa l clock source. There are also two internal comparators with the names, Comparato r A and Comparator P . These comparators will compare the value in the counter with CCRP and CCRA registers. The CCRP and CCRA comparators are 10-bit wide whose value is respectively compared with all counter bits. The onl y wa y of c hanging t he va lue of t he 10-bi t c ounter usi ng t he a pplication program i s t o clear the counter by changing the PTnON bit from low to high. The counter will also be cleared automatically by a counter overflow or a compare match with one of its associated comparators. When t hese c onditions occ ur, a PT M i nterrupt si gnal wi ll a lso usua lly be ge nerated. T he Pe riodic Type TM can operate in a number of dif ferent operational modes, can be driven by dif ferent clock sources including an input pin and can also control the output pins. All operating setup conditions are selected using relevant internal registers.

Rev. 1.20 100 Deee 0 201 Rev. 1.20 101 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Periodic Type TM Register Description Overall operation of the Periodic TM is controlled using a series of registers. A read only register pair exists to store the internal counter 10-bit value, while two read/write register pairs exist to store the internal 10-bit CCRA and CCRP value. The remaining two registers are control registers which setup the different operating and control modes. Register Name Bit 7 6 5 4 3 2 1 0 PTMnC0 PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — PTMnC1 PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCAPTS PTnCCLR PTMnDL D7 D D D4 D3 D2 D1 D0 PTMnAL D7 D D D4 D3 D2 D1 D0 PTMnRPL PTnRP7 PTnRP PTnRP PTnRP4 PTnRP3 PTnRP2 PTnRP1 PTnRP0 PTMnRPH — — — — — — PTnRP9 PTnRP8 10-bit Periodic TM Registers List – n=0 or 1 PTMnDL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R R R R R R R R POR 0 0 0 0 0 0 0 0 Bit 7~0 PTMn Counter Low Byte Register bit 7 ~ bit 0 PTMn 10-bit Counter bit 7 ~ bit 0 PTMnDH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTMn Counter High Byte Register bit 1 ~ bit 0 PTMn 10-bit Counter bit 9 ~ bit 8 PTMnAL Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTMn CCRA Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRA bit 7 ~ bit 0 PTMnAH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTMn CCRA High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRA bit 9 ~ bit 8

Rev. 1.20 102 Deee 0 201 Rev. 1.20 103 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PTMnRPL Register Bit 7 6 5 4 3 2 1 0 Nae PTnRP7 PTnRP PTnRP PTnRP4 PTnRP3 PTnRP2 PTnRP1 PTnRP0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 PTnRP7~PTnRP0: PTMn CCRP Low Byte Register bit 7 ~ bit 0 PTMn 10-bit CCRP bit 7 ~ bit 0 PTMnRPH Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 PTnRP9~PTnRP8: PTMn CCRP High Byte Register bit 1 ~ bit 0 PTMn 10-bit CCRP bit 9 ~ bit 8 PTMnC0 Register Bit 7 6 5 4 3 2 1 0 Nae PTnPAU PTnCK2 PTnCK1 PTnCK0 PTnON — — — R/W R/W R/W R/W R/W R/W — — — POR 0 0 0 0 0 — — — Bit 7 PTnPAU: PTMn Counter Pause control 0: Run 1: Pause The c ounter c an be pa used by se tting t his bi t hi gh. Cl earing t he bi t t o z ero re stores normal counter operation. When in a Pause condition the PTMn will remain powered up a nd c ontinue t o c onsume po wer. T he c ounter wi ll re tain i ts re sidual va lue whe n this bit changes from low to high and res ume counting from this value w hen the bit changes to a low value again. Bit 6~4 PTnCK2~PTnCK0: Select PTMn Counter clock 000: fSYS/4 001: fSYS 010: fH/16 011: fH/64 100: fSUB 101: fSUB 110: PTCKn rising edge clock 111: PTCKn falling edge clock These three bits are used to select the clock source for the PTMn. The external pin clock source can be chosen to be active on the rising or falling edge. The clock source fSYS is the system clock, while fH and fSUB are other internal clocks, the details of which can be found in the oscillator section.

Rev. 1.20 102 Deee 0 201 Rev. 1.20 103 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 3 PTnON: PTMn Counter On/Off control 0: Off 1: On This bit controls the overall on/of f function of the PTMn. Setting the bit high enables the counter to run while clearing the bit disables the PTMn. Clearing this bit to zero will stop the counter from counting and turn off the PTMn which will reduce its power consumption. When the bit changes state from low to high the internal counter value will be reset to zero, however when the bit changes from high to low , the internal counter will retain its residual value until the bit returns high again. If the PTMn is in the Compare Match Output Mode then the PTMn output pin will be reset to its initial condition, as specified by the PTnOC bit, when the PTnON bit changes from low to high. Bit 2~0 Unimplemented, read as "0" PTMnC1 Register Bit 7 6 5 4 3 2 1 0 Nae PTnM1 PTnM0 PTnIO1 PTnIO0 PTnOC PTnPOL PTnCAPTS PTnCCLR R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 PTnM1~PTnM0: Select PTMn Operating Mode 00: Compare Match Output Mode 01: Capture Input Mode 10: PWM Output Mode or Single Pulse Output Mode 11: T imer/Counter Mode These bits setup the required operating mode for the PTMn. T o ensure reliable operation the PTMn should be switched of f before any changes are made to the PTnM1 and PTnM0 bits. In the T imer/Counter Mode, the PTMn output pin control will be disabled. Bit 5~4 PTnIO1~PTnIO0: Select PTMn external pin PTPn or PTPnI function Compare Match Output Mode 00: No change 01: Output low 10: Output high 11: T oggle output PWM Output Mode/Single Pulse Output Mode 00: PWM output inactive state 01: PWM output active state 10: PWM output 11: Single Pulse Output Capture Input Mode 00: Input capture at rising edge of PTPnI or PTCKn 01: Input capture at falling edge of PTPnI or PTCKn 10: Input capture at rising/falling edge of PTPnI or PTCKn 11: Input capture disabled Timer/Counter Mode Unused These two bits are used to determine how the PTMn output pin changes state when a certain condition is reached. The function that these bits select depends upon in which mode the PTMn is running.

Rev. 1.20 104 Deee 0 201 Rev. 1.20 10 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP In the Compare Match Output Mode, the PTnIO1 and PTnIO0 bits determine how the PTMn output pin changes state when a compare match occurs from the Comparator A. The PTMn output pin can be setup to switch high, switch low or to toggle its present state when a compare match occurs from the Comparator A. When the bits are both zero, then no change will take place on the output. The initial value of the PTMn output pin should be setup us ing the PTnOC bit in the PTMnC1 regis ter. Note that the output level requested by the PTnIO1 and PTnIO0 bits must be dif ferent from the initial value setup using the PTnOC bit otherwise no change will occur on the PTMn output pin when a compare match occurs. After the PTMn output pin changes state, it can be reset to its initial level by changing the level of the PTnON bit from low to high. In the PWM Mode, the PTnIO1 and PTnIO0 bits determine how the TM output pin changes state when a certain compare match condition occurs. The PTMn output function i s m odified b y c hanging t hese t wo b its. I t i s n ecessary t o o nly c hange t he values of the PTnIO1 and PTnIO 0 bits only after the PTMn has been switched of f. Unpredictable PWM outputs will occur if the PTnIO1 and PTnIO0 bits are changed when the PTMn is running. Bit 3 PTnOC: PTMn PTPn Output control Compare Match Output Mode 0: Initial low 1: Initial high PWM Output Mode/Single Pulse Output Mode 0: Active low 1: Active high This is the output control bit for the PTMn output pin. Its operation depends upon whether PTMn is being used in the Compare Match Output Mode or in the PWM Output Mode/Single Pulse Output Mode. It has no ef fect if the PTMn is in the T imer/ Counter Mo de. I n t he C ompare Ma tch Ou tput Mo de i t d etermines t he l ogic l evel o f t he PTMn output pin before a compare match occurs. In the PWM Output Mode/Single Pulse Output Mode it determines if the PWM signal is active high or active low. Bit 2 PTnPOL: PTMn PTPn Output polarity control 0: Non-inverted 1: Inverted This bit controls the polarity of the PTPn output pin. When the bit is set high the PTMn output pin will be inverted and not inverted when the bit is zero. It has no ef fect if the PTMn is in the T imer/Counter Mode. Bit 1 PTnCAPTS: PTMn Capture T rigger Source selection 0: From PTPnI pin 1: From PTCKn pin Bit 0 PTnCCLR: PTMn Counter Clear condition selection 0: Comparator P match 1: Comparator A match This bi t i s use d t o se lect t he m ethod whi ch c lears t he c ounter. Re member t hat t he Periodic T M c ontains t wo c omparators, Com parator A a nd Com parator P , e ither of which can be selected to clear the internal counter . W ith the PTnCCLR bit set high, the counter will be cleared when a compare match occurs from the Comparator A. When the bit is low , the counter will be cleared when a compare match occurs from the Comparator P or with a counter overflow . A counter overflow clearing method can only be implemented if the CCRP bits are all cleared to zero. The PTnCCLR bit is not used in the PWM Output, Single Pulse Output or Capture Input Mode.

Rev. 1.20 104 Deee 0 201 Rev. 1.20 10 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Periodic Type TM Operation Modes The Periodic T ype TM can operate in one of five operating modes, Compare Match Output Mode, PWM Output Mode, Single Pulse Output Mode, Capture Input Mode or T imer/Counter Mode. The operating mode is selected using the PTnM1 and PTnM0 bits in the PTMnC1 register. Compare Match Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register , should be set to 00 respectively. In this mode once the counter is enabled and running it can be cleared by three methods. These are a counter overflow , a compare match from Comparator A and a compare match from Comparator P . When the PTnCCLR bit is low , there are two ways in which the counter can be cleared. One is when a compare match from Comparator P , the other is when the CCRP bits are all zero which allows the counter to overflow . Here both PTMnAF and PTMnPF interrupt request flags for Comparator A and Comparator P respectively, will both be generated. If the PTnCCLR bit in the PTMnC1 register is high then the counter will be cleared when a compare match occurs from Comparator A. However , here only the PTMnAF interrupt request flag will be generated even if the value of the CCRP bits is less than that of the CCRA registers. Therefore when PTnCCLR is high no PTMnPF interrupt request flag will be generated. In the Compare Match Output Mode, the CCRA can not be set to "0". As the name of the mode suggests, after a comparison is made, the PTMn output pin will change state. The PTMn output pin condition however only changes state when a PTMnAF interrupt request flag is generated after a compare match occurs from Comparator A. The PTMnPF interrupt request flag, generated from a compare match occurs from Comparator P , will have no ef fect on the PTMn output pin. The way in which the PTMn output pin changes state are determined by the condition of the PTnIO1 and PTnIO0 bits in the PTMnC1 register . The PTMn output pin can be selected using the PT nIO1 a nd PT nIO0 bi ts t o go hi gh, t o go l ow or t o t oggle fr om i ts pre sent c ondition whe n a compare match occurs from Comparator A. The initial condition of the PTMn output pin, which is setup afte r the PTnON bit changes from low to high, is setup using the PTnOC bit. Note that if the PTnIO1 and PTnIO0 bits are zero then no pin change will take place.

Rev. 1.20 10 Deee 0 201 Rev. 1.20 107 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value 0x3FF CCRP CCRA PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin Tie CCRP=0 CCRP > 0 Counte oveflow CCRP > 0 Counte leaed y CCRP value Pause Resue Stop Counte Restat Output pin set to initial Level Low if PTnOC=0 Output Toggle with PTMnAF flag Note PTnIO [1:0] = 10 Ative High Output selet Hee PTnIO [1:0] = 11 Toggle Output selet Output not affeted y PTMnAF flag. Reains High until eset y PTnON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when PTnPOL is high PTnCCLR = 0; PTnM [1:0] = 00 Compare Match Output Mode – PTnCCLR=0 Note: 1. W ith PTnCCLR=0, a Comparator P match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. The 10-bit PTM maximum counter value is 0x3FF 5. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 10 Deee 0 201 Rev. 1.20 107 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value 0x3FF CCRP CCRA PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin Tie CCRA=0 CCRA = 0 Counte oveflowCCRA > 0 Counte leaed y CCRA value Pause Resue Stop Counte Restat Output pin set to initial Level Low if PTnOC=0 Output Toggle with PTMnAF flag Note PTnIO [1:0] = 10 Ative High Output seletHee PTnIO [1:0] = 11 Toggle Output selet Output not affeted y PTMnAF flag. Reains High until eset y PTnON it Output Pin Reset to Initial value Output ontolled y othe pin-shaed funtion Output Invets when PTnPOL is high PTMnPF not geneated No PTMnAF flag geneated on CCRA oveflowOutput does not hange PTnCCLR = 1; PTnM [1:0] = 00 Compare Match Output Mode – PTnCCLR=1 Note: 1. W ith PTnCCLR=1, a Comparator A match will clear the counter 2. The PTMn output pin is controlled only by the PTMnAF flag 3. The output pin is reset to its initial state by a PTnON bit rising edge 4. A PTMnPF flag is not generated when PTnCCLR =1 5. The 10-bit PTM maximum counter value is 0x3FF 6. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 108 Deee 0 201 Rev. 1.20 109 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Timer/Counter Mode To se lect t his mode , bi ts PT nM1 and PT nM0 i n t he PT MnC1 regi ster should be se t t o 1 1 respectively. The T imer/Counter Mode operates in an identical way to the Compare Match Output Mode generating the same interrupt flags. The exception is that in the T imer/Counter Mode the PTMn ou tput pin is not used. T herefore the above description a nd T iming Diagrams for the Compare Match Output Mode can be used to understand its function. As the PTMn output pin is not used in this mode, the pin can be used as a normal I/O pin or other pin-shared function. PWM Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 10 respectively . The PWM function within the PTMn is useful for applications which require functions such as motor control, heating control, illumination control, etc. By providing a signal of fixed frequency but of varying duty cycle on the PTMn output pin, a square wave AC waveform can be generated with varying equivalent DC RMS values. As both the period and duty cycle of the PWM waveform can be controlled, the choice of generated waveform i s e xtremely fle xible. In t he PW M m ode, t he PT nCCLR bi t ha s no e ffect a s t he PW M period. Both of the CCRP and CCRA registers are used to generate the PWM waveform, one register is used to clear the internal counter and thus control the PWM waveform frequency , while the other one is used to control the duty cycl e. The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers. An interrupt flag, one for each of the CCRA and CCRP , will be generated when a compare match occurs from either Comparator A or Comparator P . The PTnOC bit in the PTMnC1 register is used to select the required polari ty of the PWM waveform whi le the two PTnIO1 and PTnIO0 bi ts are used to enable the PWM output or to force the PTMn output pin to a fixed high or low level. The PTnPOL bit is used to reverse the polarity of the PWM output waveform.

10-bit PTMn, PWM Output Mode CCRP 1~1023 0 Peiod 1~1023 1024 Duty CCRA If fSYS=16MHz, TM clock source select fSYS/4, CCRP=512 and CCRA=128, The PTMn PWM output frequency=(fSYS/4)/512=fSYS/2048=8kHz, duty=128/512=25%, If the Duty value defined by the CCRA register is equal to or greater than the Period value, then the PWM output duty is 100%.

Rev. 1.20 108 Deee 0 201 Rev. 1.20 109 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value CCRP CCRA PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin (PTnOC=1) Tie Counte leaed y CCRP Pause Resue Counte Stop if PTnON it low Counte Reset when PTnON etuns high PWM Duty Cyle set y CCRA PWM esues opeationOutput ontolled y othe pin-shaed funtion Output Invets When PTnPOL = 1 PWM Peiod set y CCRP PTMn O/P Pin (PTnOC=0) PTnM [1:0] = 10 PWM Mode Note: 1. The counter is cleared by CCRP 2. A counter clear sets the PWM Period 3. The internal PWM function continues running even when PTnIO [1:0]=00 or 01 4. The PTnCCLR bit has no influence on PWM operation 5. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 110 Deee 0 201 Rev. 1.20 111 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Single Pulse Output Mode To select this mode, bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 10 respectively and also the PTnIO1 and PTnIO0 bits should be set to 1 1 respectively . The Single Pulse Output Mode, as the name suggests, will generate a single shot pulse on the PTMn output pin. The t rigger f or t he p ulse o utput l eading e dge i s a l ow t o h igh t ransition o f t he PT nON b it, wh ich can be implement ed using the application program. However in the Single Pulse Mode, the PTnON bit can also be made to automatically change from low to high using the external PTCKn pin, which will in turn initiate the Single Pulse output. When the PTnON bit transitions to a high level, the counter will start running and the pulse leading edge will be generated. The PTnON bit should remain high when the pulse is in its active state. The generated pulse trailing edge will be generated when the PTnON bit is cleared to zero, which can be implemented using the application program or when a compare match occurs from Comparator A. However a compa re match from Comparator A will also automatically clear the PTnON bit and thus generate the Single Pulse output trailing edge. In this way the CCRA value can be used to control the pulse width. A compare match from Comparator A will also generate a PTMn interrupt. The counter can only be res et back to zero w hen the PTnO N bit changes from low to high w hen the counter restarts. In the Single Pulse Mode CCRP is not used. The PTnCCLR is not used in this Mode. PTnON it 0 à 1 S/W Coand SET“PTnON” o PTCKn Pin Tansition PTnON it 1 à 0 CCRA Tailing Edge S/W Coand CLR“PTnON” o CCRA Copae Math PTPn Output Pin Pulse Width = CCRA Value CCRA Leading Edge Single Pulse Generation – n=0 or 1

Rev. 1.20 110 Deee 0 201 Rev. 1.20 111 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value CCRP CCRA PTnON PTnPAU PTnPOL CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF PTMn O/P Pin (PTnOC=1) Tie Counte stopped y CCRA Pause Resue Counte Stops y softwae Counte Reset when PTnON etuns high Pulse Width set y CCRA Output Invets when PTnPOL = 1 No CCRP Inteupts geneated PTMn O/P Pin (PTnOC=0) PTCKn pin Softwae Tigge Cleaed y CCRA ath PTCKn pin Tigge Auto. set y PTCKn pin Softwae Tigge Softwae Clea Softwae Tigge Softwae Tigge PTnM [1:0] = 10 ; PTnIO [1:0] = 11 Single Pulse Mode Note: 1. Counter stopped by CCRA 2. CCRP is not used 3. The pulse triggered by the PTCKn pin or by setting the PTnON bit high 4. A PTCKn pin active edge will automatically set the PTnON bit high 5. In the Single Pulse Mode, PTnIO [1:0] must be set to "11" and can not be changed 6. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 112 Deee 0 201 Rev. 1.20 113 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Capture Input Mode To select this mode bits PTnM1 and PTnM0 in the PTMnC1 register should be set to 01 respectively. This mode enables external s ignals to capture and s tore the pres ent value of the internal counter and can therefore be used for applic ations such as pulse width measurements. The external signal is supplied on the PTPnI or PTCKn pin, selected by the PTnCAPTS bit in the PTMnC1 register . The input pin active edge can be either a rising edge, a falling edge or both rising and falling edges; the active edge transition type is select ed using the PTnIO1 and PTnIO0 bits in the PTMnC1 register . The counter is started when the PTnON bit changes from low to high which is initiated using the application program. When the required edge transition appears on the PTPnI or PTCKn pin the present value in the counter will be latched into the CCRA registers and a PTMn interrupt generated. Irrespective of what events occur on the PTPnI or PTCKn pin the counter will continu e to free run until the PTnON bit changes from high to low . When a CCRP compare match occurs the counter will reset back to zero; in this way the CCRP value can be used to control the maximum counter value. When a CCRP compare match occurs from Comparator P , a PTMn interrupt will also be generated. Counting the number of overflow interrupt signals from the CCRP can be a useful method in measuring long pulse widths. The PTnIO1 and PTnIO0 bits can select the active trigger edge on the PTPnI or PTCKn pin to be a rising edge, falling edge or both edge types. If the PTnIO1 and PTnIO0 bits are both set high, then no capture operation will take place irrespective of what happens on the PTPnI or PTCKn pin, however it must be noted that the counter will continue to run. As the PTPnI or PTCKn pin is pin shared with other functions, care must be taken if the PTMn is in the Input Capture Mode. This is because if the pin is setup as an output, then any transitions on this pin may cause an input capture operation to be executed. The PTnCCLR, PTnOC and PTnPOL bits are not used in this Mode.

Rev. 1.20 112 Deee 0 201 Rev. 1.20 113 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Counte Value YY CCRP PTnON PTnPAU CCRP Int. Flag PTMnPF CCRA Int. Flag PTMnAF CCRA Value Tie Counte leaed y CCRP Pause Resue Counte Reset PTnM[1:0] = 01 PTMn Captue Pin PTPnI o PTCKn XX Counte Stop PTnIO [1:0] Value Ative edge Ative edge Ative edge 00 - Rising edge 01 - Falling edge 10 - Both edges 11 - Disale Captue XX YY XX YY Capture Input Mode Note: 1. PTnM [1:0]=01 and active edge set by the PTnIO [1:0] bits 2. A PTMn Capture input pin active edge transfers the counter value to CCRA 3. PTnCCLR bit not used 4. No output function – PTnOC and PTnPOL bits are not used 5. CCRP determin es the counter value and the counter has a maximum count value when CCRP is equal to zero 6. n=0 or 0~1 is dependent upon which device is selected

Rev. 1.20 114 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However , to properly process these signals by a microcontroller , they must first be converted into digital signals by A/D converters. By integrating the A/D conversion electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview These devices contain a multi-channel analog to digital converter which can directly interface to external analog signals, such as that from sensors or other control signals and convert these signals directly into a 12-bit digital value. It also can convert the internal signals, such as the internal reference voltage, into a 12-bit digital value. The external or internal analog signal to be converted is determined by the SAINS and SACS bit fields. When the external analog signal is to be converted, the corresponding external channel input pin function should first be properly configured and then the desired external channel input should be selected using the SAINS and SACS fields. Note that when the internal analog signal is selected to be converted, all external channel analog input pin function should first be deselected and then properly configured the SAINS and SACS fields. More detailed information about the A/D input signal selection will be described in the "A/D converter Control Registers" and "A/D Converter Input Signals" section respectively. Device External Input Channels Internal Signal A/D Signal Select BS87B12A-3 BS87C1A-3 BS87D20A-3 AN0~AN7 VBG VOCVPAO SAINS2~SAINS0 SACS3~SACS0 The accompanyin g block diagram shows the internal structure of the A/D converter together with its associated registers and control bits. SAINS2~ SAINS0 A/D Convete START ADBZ VSS A/D Clok ÷ 2N (N=0~7) fSYS SACKS2~ SACKS0 VDD ADCEN SADOL SADOH AN0 AN1 AN7 A/D Data Registes VBG VOCVPAO ADRFS A/D Convete Refeene Voltage AN4 ACE7~ACE0 SACS3~SACS0 VREF VREF VREFS SAVRS1~SAVRS0 A/D Converter Structure

Rev. 1.20 114 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Registers Descriptions Overall operation of the A /D converter is controlled us ing fi ve regis ters. A read only regis ter pair exists to store the A/D Converter data 12-bit value. The remaining three registers, SADC0, SADC1 and ACERL, are control registers which setup the operating conditions and control function of the A/D converter. Register Name Bit 7 6 5 4 3 2 1 0 SADOL (ADRFS=0) D3 D2 D1 D0 — — — — SADOL (ADRFS=1) D7 D D D4 D3 D2 D1 D0 S ADOH (ADRFS=0) D11 D10 D9 D8 D7 D D D4 SADOH (ADRFS=1) — — — — D11 D10 D9 D8 SADC0 START ADBZ ADCEN ADRFS SACS3 SACS2 SACS1 SACS0 SADC1 SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0 ACERL ACE7 ACE ACE ACE4 ACE3 ACE2 ACE1 ACE0 A/D Converter Registers List A/D Converter Data Registers – SADOL, SADOH As these devices contain an internal 12-bit A/D converter , it requires two data registers to store the converted value. These are a high byte register , known as SADOH, and a low byte register , known as SADOL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. As only 12 bits of the 16-bit register space is ut ilised, t he form at i n whi ch t he da ta i s st ored i s c ontrolled by t he ADRFS bi t i n t he SADC0 register as shown in the accompanying table. D0~D1 1 are the A/D conversion result data bits. Any unused bits will be read as zero. The A/D data registers contents will be unchanged if the A/D converter is disabled. ADRFS SADOH SADOL 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 D11 D10 D9 D8 D7 D D D4 D3 D2 D1 D0 0 0 0 0

1 0 0 0 0 D11 D10 D9 D8 D7 D D D4 D3 D2 D1 D0 A/D Converter Data Registers A/D Converter Control Registers – SADC0, SADC1, ACERL To control the function and operation of the A/D converter, three control registers known as SADC0, SADC1 and ACERL are provided. These 8-bit registers define functions such as the selection of which analog s ignal is connected to the internal A /D converter , the digitis ed data format, the A /D clock source as well as controlling the start function and monitoring the A/D converter busy status. As these devices contain only one actual analog to digital converter hardware circuit, each of the external and intern al analog signals must be routed to the converter . The SAINS field in the SADC1 register and SACS field in the SADC0 register are used to determine which analog signal derived from the external or internal signals will be connected to the A/D converter. The ACERL register contains the ACE7~ACE0 bits which determine which pins on I/O Ports are used as analog inputs for the A/D converter input and which pins are not. Setting the corresponding bit high will select the A/D input function while clearing the bit to zero will select either the I/O or other pin-shared function. When the pin is selected to be an A/D input, its original function whether it is an I/O or other pin-shared function will be removed. In addition, any internal pull-high resistor connected to the pin will be automatically removed if the pin is selected to be an A/D converter input.

Rev. 1.20 11 Deee 0 201 Rev. 1.20 117 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

SADC0 Register Bit 7 6 5 4 3 2 1 0 Nae START ADBZ ADCEN ADRFS SACS3 SACS2 SACS1 SACS0 R/W R/W R R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 START: Start the A/D Conversion 0→1→0: Start This bit is used to initiate an A/ D conversion process. The bit is normally low but if set high and then cleared low again, the A/D converter will initiate a conversion process. Bit 6 ADBZ: A/D Converter busy flag 0: No A/D conversion is in progress 1: A/D conversion is in progress This read only flag is us ed to indicate w hether the A /D convers ion is in progress or not. When the ST ART bit is set from low to high and then to low again, the ADBZ flag will be set to 1 to indicate that the A/D conversion is initiated. The ADBZ flag will be cleared to 0 after the A/D conversion is complete. Bit 5 ADCEN: A/D Converter function enable control 0: Disable 1: Enable This bit controls the A/D internal function. This bit should be set to one to enable the A/ D c onverter. If t he bi t i s se t l ow, t hen t he A/ D c onverter wi ll be swi tched of f reducing the device power consumption. When the A/D converter function is disabled, the contents of the A/D data register pair known as SADOH and SADOL will be unchanged. Bit 4 ADRFS: A/D conversion data format select 0: A/D converter data format → SADOH=D [11:4]; SADOL=D [3:0] 1: A/D converter data format → SADOH=D [11:8]; SADOL=D [7:0] This bit controls the format of the 12-bit converted A/D value in the two A/D data registers. Details are provided in the A/D converter data register section. Bit 3~0 SACS3~SACS0: A/D converter external analog input channel select 0000: External AN0 input 0001: External AN1 input 0010: External AN2 input 0011: External AN3 input 0100: External AN4 input 0101: External AN5 input 0110: External AN6 input 0111: External AN7 input 1xxx: Non-existed channel, input floating if selected. These bi ts a re use d t o se lect whi ch e xternal a nalog i nput c hannel i s t o be c onverted. When the external analog input channel is selected, the SAINS bit field must be set to "000", "101" or "1 1x". Details are summarized in the "A/D Converter Input Signal Selection" table.

Rev. 1.20 11 Deee 0 201 Rev. 1.20 117 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

SADC1 Register Bit 7 6 5 4 3 2 1 0 Nae SAINS2 SAINS1 SAINS0 SAVRS1 SAVRS0 SACKS2 SACKS1 SACKS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~5 SAINS2~SAINS0: A/D converter input signal select 000: External source – External analog channel intput, ANn 001: Internal source – Internal signal derived from the internal bandgap reference voltage, VBG 010: Internal source – Reserved, connected to ground 011: Internal source – Internal signal derived from the OCVP OPA output signal, VOCVPAO 100: Internal source – Reserved, connected to ground 101~111: External source – External analog channel intput, ANn Care must be taken if the SAINS field is set to "001" or "01 1" to select the internal analog signal to be converted. When the internal analog signal is selected to be converted, the external channel input pin must never be selected as the A/D input signal b y p roperly se tting t he SAC S b it fie ld wi th a v alue o f "1x xx". Ot herwise, t he external channel input will be connected together with the internal analog signal. This will result in unpredictable situations such as an irreversible damage. Bit 4~3 SA VRS1~SA VRS0: A/D converter reference voltage select 00: External VREF pin 01: Internal A/D converter power, VDD. 1x: External VREF pin These b its a re u sed t o se lect t he A/ D c onverter r eference v oltage so urce. C are m ust be taken if the SA VRS field is set to "01" to select the internal A/D converter power voltage as the reference voltage source. When the internal reference voltage source is selected, the external VREF cannot be configured as the reference voltage input by properly configuring the VREFS bit in the TMP C0 register . Otherw ise, the external input voltage on the VREF pin will be connected to the internal A/D converter power. Bit 2~0 SACKS2~SACKS0: A/D conversion clock source select 000: fSYS 001: fSYS/2 010: fSYS/4 011: fSYS/8 100: fSYS/16 101: fSYS/32 110: fSYS/64 111: fSYS/128 These bits are used to select the cloc k source for the A/D converter . It is recommended that the A /D convers ion clock frequency s hould be in the range from 500 kH z to 1MHz by properly configuring the SACKS2~SACKS0 bits.
ACERL Register Bit 7 6 5 4 3 2 1 0 Nae ACE7 ACE ACE ACE4 ACE3 ACE2 ACE1 ACE0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 ACE7: AN7 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN7 Bit 6 ACE6: AN6 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN6

Rev. 1.20 118 Deee 0 201 Rev. 1.20 119 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 5 ACE5: AN5 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN5 Bit 4 ACE4: AN4 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN4 Bit 3 ACE3: AN3 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN3 Bit 2 ACE2: AN2 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN2 Bit 1 ACE1: AN1 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN1 Bit 0 ACE0: AN0 input pin enable control 0: Disable – not A/D input 1: Enable – A/D input, AN0 A/D Converter Reference Voltage The actua l reference voltage supply to the A/D Converter can be supplied from the positive power supply pin, VDD, or an external reference source supplied on pin VREF determined by the SA VRS bit field in the SADC1 register . When the SA VRS field is set to "01", the A/D converter reference voltage will come from the VDD pin. Otherwise, the A/D converter reference voltage will come from the VREF pin if the SA VRS field is set to any other value excep t "01". When the VREF pin is selected as the reference voltage supply pin, the VREFS bit in the TMPC0 register should first be properly configured to enable the VREF pin function as it is pin-s hared with other functions. However, if the internal A/D converter power is selected as the reference voltage, the external VREF pin must not be configured as the reference voltage input function to avoid the internal connection between the VREF pin to the internal A/D converter power . Note that the analog input values must not be allowed to exceed the value of the selected reference voltage, VDD or VREF. A/D Converter Input Signals All of the external A/D analog input pins are pin-shared with the I/O pins as well as other functions. The c orresponding pi n-shared func tion sel ection bi ts ACEn i n t he ACERL re gister de termine whether the external input pins are setup as A/D converter analog channel inputs or whether they have other functio ns. If the corresponding pin is setup to be an A/D converter analog channel input by se tting t he AC En b it h igh, t he o riginal p in f unction wi ll b e d isabled. I n t his wa y, p ins c an b e changed under program control to change their function between A/ D inputs and other functions. All pull-high resistors, which are setup through register programming, will be automatically disconnected if the pins are setup as A/D inputs. Note that it is not necessary to first setup the A/D pin as an input in the port control register to enable the A/D input as when the relevant A/D input function selection bits enable an A/D input, the status of the port control register will be overridden. As these devices contain only one actual analog to digital converter hardware circuit, one of the external or internal analog signals must be routed to the converter . The SAINS2~SAINS0 bits in the SADC1 register are used to determine that the analog signal to be converted comes from the external channel input or internal analog signal. The SACS3~SACS0 bits in the SADC0 register are used to determine which external channel input is selected to be converted. If the SAINS2~SAINS0 bits are set to "000", "101" or "1 1x", the external channel input will be selected to be converted and the SACS3~SACS0 bits can determine which external channel is selected.

Rev. 1.20 118 Deee 0 201 Rev. 1.20 119 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP When the SAINS field is set to the value of "001" or "01 1", the internal analog signal derived from the Bandgap reference voltage or OCVP OP A output signal will be selected. If the internal analog signal is selected to be converted, the external channel signal input must be switched of f by setting the SACS field to a value of "1xxx". Otherwise, the internal analog signal will be connected together with the external channel input. This will result in unpredictable situations. SAINS [2:0] SACS [3:0] Input Signals Description 000 101 11x 0000~0111 AN0~AN7 Extenal hannel analog input ANn. 1xxx — Floating no extenal hannel is seleted. 001 1xxx VBG Intenal Bandgap efeene voltage 010 100 1xxx GND Conneted to the gound. 011 1xxx VOCVPAO Intenal OCVP OPA output signal A/D Converter Input Signal Selection A/D Converter Operation The ST ART bit in the SADC0 register is used to start the AD conversion. When the microcontroller sets t his b it f rom l ow t o h igh a nd t hen l ow a gain, a n a nalog t o d igital c onversion c ycle wi ll b e initiated. The ADBZ bi t i n t he SADC0 re gister i s use d t o i ndicate whe ther t he a nalog t o di gital c onversion process is in progres s or not. This bit w ill be automatically s et to 1 by the microcontroller after an A/D conversion is successfully initiated. When the A/D conversion is complete, the ADBZ bit will be cleared to 0. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register , and if the A /D interrupt is enabled, an internal A /D interrupt s ignal w ill be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D internal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can poll the ADBZ bit in the SADC0 register to check whether it has been cleared as an alternative method of detecting the end of an A/D conversion cycle. The clock source for the A/D converter , which originates from the system clock fSYS, can be chosen to be either fSYS or a subdivided version of fSYS. The division ratio value is determined by the SACKS bit field in the SADC1 register . Although the A/D clock source is determined by the system clock fSYS and by bits SACKS2~SACKS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the recommended range of permissible A/D clock period, tADCK, is from 0.5μs to 10μ , care must be taken for system clock frequencies . For example, if the system clock operates at a frequency of 8MHz, the SACKS2~SACKS0 bits should not be set to 000, 001 or 1 11. Doing so will give A/D clock periods that are less than the minimum A/D clock period which m ay re sult i n i naccurate A/ D c onversion va lues. Re fer t o t he fol lowing t able for e xamples, where values marked with an asteri sk * show where, depending upon the device, special care must be taken, as the values may be less than the specified minimum A/D Clock Period. fSYS A/D Clock Period (tADCK) SACKS [2:0]=000 (fSYS) SACKS [2:0]=001 (fSYS/2) SACKS [2:0]=010 (fSYS/4) SACKS [2:0]=011 (fSYS/8) SACKS [2:0]=100 (fSYS/16) SACKS [2:0]=101 (fSYS/32) SACKS [2:0]=110 (fSYS/64) SACKS [2:0]=111 (fSYS/128)

1 MHz 1μs 2μs 4μs 8μs 1μs * 32μs * 4μs * 128μs *

2 MHz 00ns 1μs 2μs 4μs 8μs 1μs * 32μs * 4μs *

4 MHz 20ns * 00ns 1μs 2μs 4μs 8μs 1μs * 32μs *

8 MHz 12ns * 20ns * 00ns 1μs 2μs 4μs 8μs 1μs *

12 MHz 83ns * 17ns * 333ns * 7ns 1.33μs 2.7μs .33μs 10.7μs * 1 MHz 2.ns * 12ns * 20ns * 00ns 1μs 2μs 4μs 8μs A/D Clock Period Examples

Rev. 1.20 120 Deee 0 201 Rev. 1.20 121 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Controlling t he powe r on/ off func tion of t he A/ D c onverter c ircuitry i s i mplemented usi ng t he ADCEN bit in the SADC0 register . This bit must be set high to power on the A/D converter . When the ADCEN bit is set high to power on the A/D converter internal circuitry , a certain delay , as indicated in the timing diagram, must be allowed before an A/D conversion is initiated. Even if no pins are selected for use as A/D inputs, if the ADCEN bit is high, then some power will still be consumed. In power conscious applications it is therefore recommended that the ADCEN is set low to reduce power consumption when the A/D converter function is not being used. Conversion Rate and Timing Diagram A com plete A/D conversi on contains two parts, dat a sampli ng and dat a conversi on. The dat a sampling which is defined as tADS takes 4 A/D clock cycles and the data conversion takes 12 A/D clock cycles. Therefore a total of 16 A/D clock cycles for an analog signal A/D conversion which is defined as tADC are necessary. Maximum single A/D conversion rate=A/D clock period/16 The accompanying diagram shows graphically the various stages involved in an external channel input signal analo g to digital conversion process and its associated timing. After an A/D conversion process h as b een i nitiated b y t he a pplication p rogram, t he m icrocontroller i nternal h ardware wi ll begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is 16 tADCK clock cycles where tADCK is equal to the A/D clock period. ADCEN START ADBZ SACS[3:0] off on off on tON2ST tADS A/D sapling tie tADS A/D sapling tie Stat of A/D onvesion Stat of A/D onvesion Stat of A/D onvesion End of A/D onvesion End of A/D onvesion tADC A/D onvesion tie tADC A/D onvesion tie tADC A/D onvesion tie 0011B 0010B 0000B 0001B A/D hannel swith (SAINS=000) A/D Conversion Timing – External Channel Input

Rev. 1.20 120 Deee 0 201 Rev. 1.20 121 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Summary of A/D Conversion Steps The following summarises the individual steps that should be executed in order to implement an A/D conversion process.

Step 1 Select the required A/D conversion clock by properly programming the SACKS2~SACKS0 bits in the SADC1 register.
Step 2 Enable the A/D converter by setting the ADCEN bit in the SADC0 register to one.
Step 3 Select which signal is to be connec ted to the internal A/D converter by correctly configuring the SACS and SAINS bit fields Selecting the external channel input to be converted, go to Step 4. Selecting the internal analog signal to be converted, go to Step 5.
Step 4 If t he SAINS fie ld i s 000, 101 or 1 1x, t he e xternal c hannel i nput c an be se lected. T he de sired external channel input is selected by configuring the SACS field. When the A/D input signal comes from the external channel input, the corresponding pin should be configured as an A/D input function by selecting the relevant pin-shared function control bits, ACE n. T hen go to Step 6.
Step 5 If the SAINS field is set to 001 or 01 1, the relevant internal analog signal can be selected. Before the A/D input signal is selected to come from the internal analog signal by properly configuring the SAINS field, the SACS field must be set to "1xxx" to select a non-existed channel input. Then go to Step 6.
Step 6 Select the A/D converter output data format by configuring the ADRFS bit.
Step 7 Select the A/D converter reference voltage source by configuring the SAVRS bit field. Select the PGA input signal and the desired PGA gain if the PGA output voltage, VR, is selected as the A/D converter reference voltage.
Step 8 If A/D conversion interrupt is used, the interrupt control registers must be correctly configured to ensure the A/D interrupt function is active. The master interrupt control bit, EMI, and the A/D conversion interrupt control bit, ADE, must both be set high in advance.
Step 9 The A/D conversion procedure can now be initi alized by setting the ST ART bit from low to high and then low again.
Step 10 If A/ D conversi on i s i n progre ss, t he ADBZ fla g wi ll be se t high. Aft er t he A/ D conversi on process is complete, the A DBZ flag w ill go low and then the output data can be read from SADOH and SADOL registers. Note: When checking for the end of the conversion process, if the met hod of polling the ADBZ bit in the SADC0 register is used, the interrupt enable step above can be omitted.

Rev. 1.20 122 Deee 0 201 Rev. 1.20 123 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Programming Considerations During m icrocontroller ope rations where t he A/D c onverter i s not be ing use d, t he A/D i nternal circuitry can be s witched of f to reduce pow er cons umption, by s etting bit A DCEN low in the SADC0 regist er. When thi s happens, the int ernal A/ D converter ci rcuits wi ll not consume power irrespective of what analog voltage is applied to their input lines. If the A/D converter input lines are used as normal I/Os, then care must be taken as if the input voltage is not at a valid logic level, then this may lead to some increase in power consumption. A/D Transfer Function As the devices contain a 12-bit A/D converter , its full-scale converted digitised value is equal to FFFH. Since the full-scale analog input value is equal to the actual A/D converter reference voltage, VREF, this gives a single bit analog input value of reference voltage value divided by 4096.

1 LSB=VREF ÷ 4096

The A/D Converter input voltage value can be calculated using the following equation: A/D input voltage=A/D output digital value × VREF ÷ 4096 The diagram shows the ideal transfer function between the analog input value and the digitised output val ue for t he A/ D conve rter. E xcept for t he di gitised ze ro val ue, t he subsequent digi tised values will change at a point 0.5 LSB below where they would change without the of fset, and the last full scale digitised value will change at a point 1.5 LSB below the VREF level. Note that here the VREF voltage is the actual A/D converter reference voltage source determined by the SAVRS field. FFFH FFEH FFDH 03H 02H 01H 0 1 2 3 4093 4094 409 409 VREF 409 Analog Input Voltage A/D Conversion Result 1. LSB 0. LSB Ideal A/D Transfer Function

Rev. 1.20 122 Deee 0 201 Rev. 1.20 123 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP A/D Programming Examples The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the ADBZ bit in the SADC0 register is used to detect when the conversion cycle is complete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. Example: using an ADBZ polling method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H ; select fSYS/8 as A/D clock and A/D input mov SADC1,a ; signal comes from external channel mov a,00H ; select VREF pin voltage as A/D reference voltage source mov SADC0,a ; and AN0 is selected as the external channel input set ADCEN ; enable the A/D converter mov a,01H ; setup ACERL to configure pin AN0 as analog input mov ACERL,a start_conversion: clr START ; high pulse on start bit to initiate conversion set START ; reset A/D clr START ; start A/D polling_EOC: sz ADBZ ; poll the SADC0 register ADBZ bit to detect end of A/D conversion jmp polling_EOC ; continue polling mov a,SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register jmp start_conversion ; start next A/D conversion

Rev. 1.20 124 Deee 0 201 Rev. 1.20 12 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Example: using the interrupt method to detect the end of conversion clr ADE ; disable ADC interrupt mov a,03H ; select fSYS/8 as A/D clock and A/D input mov SADC1,a ; signal comes from external channel mov a,00H ; select VREF pin voltage as A/D reference voltage source mov SADC0,a ; and AN0 is selected as the external channel input set ADCEN ; enable the A/D converter mov a,01H ; setup ACERL to configure pin AN0 as analog input mov ACERL,a Start_conversion: clr START ; high pulse on START bit to initiate conversion set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set ADE ; enable ADC interrupt set EMI ; enable global interrupt ADC_ISR: ; ADC interrupt service routine mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory mov a,SADOL ; read low byte conversion result value mov SADOL_buffer,a ; save result to user defined register mov a,SADOH ; read high byte conversion result value mov SADOH_buffer,a ; save result to user defined register EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti

Rev. 1.20 124 Deee 0 201 Rev. 1.20 12 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Touch Key Function Each device provides multiple touch key functions. The touch key function is fully integrated and requires no external components, allowing touch key functions to be implemented by the simple manipulation of internal registers. Touch Key Structure The touch keys are pin-s hared w ith the I/O pins, w ith the desired function chos en via the corresponding selection register bits. Keys are organised into several groups, with each group known as a m odule and havi ng a m odule numbe r, M0 to Mn. Ea ch m odule i s a full y i ndependent se t of four T ouch Keys and each T ouch Key has its own oscillator . Each module contains its own control logic circ uits and register set. Examination of the register names will reveal the module number it is referring to. Device Total Key Number Touch Key Module Touch Key BS87B12A-3 12 Mn (n=0~2) M0 KEY1~KEY4 M1 KEY~KEY8 M2 KEY9~KEY12 BS87C1A-3 1 Mn (n=0~3) M0 KEY1~KEY4 M1 KEY~KEY8 M2 KEY9~KEY12 M3 KEY13~KEY1 BS87D20A-3 20 Mn (n=0~4) M0 KEY1~KEY4 M1 KEY~KEY8 M2 KEY9~KEY12 M3 KEY13~KEY1 M4 KEY17~KEY20 Touch Key Structure

Rev. 1.20 12 Deee 0 201 Rev. 1.20 127 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Key OSC TKRCOV Multi- frequency MnDFEN TKMn16DH / TKMn16DL TKCFOV TK16DL / TK16DH Mux . TKTMR Reference Oscillator TKMnROH / TKMnROL Filter 16-bit C/F Counter fSYS/4 M U X MnTSS MnMXS1~MnMXS0 8-bit Time Slot Counter 5-bit unit period counter 8-bit Time Slot Counter Preload RegisterTKTMR Overflow 16-bit Counter TK16OV M U X TK16S1~TK16S0 fSYS/4 fSYS/2 fSYS fSYS/8 MnROEN MnKOEN Key OSC Key OSC Key OSC KEY1 KEY2 KEY3 KEY4 MnK4IO~MnK1IO Touch Key Module n Note: T he st ructure c ontained i n t he d ash l ine i s i dentical f or e ach t ouch k ey m odule wh ich c ontains f our t ouch keys. Touch Key Function Block Diagram Touch Key Register Definition Each t ouch k ey m odule, wh ich c ontains f our t ouch k ey f unctions, h as i ts o wn su ite r egisters. T he following table shows the register set for each touch key module. The Mn within the register name refers to the T ouch Key module number . The series of devices has up to five T ouch Key Modules dependent upon the selected device. Name Description TKTMR Touh key tie slot 8-it ounte peload egiste TKC0 Touh key funtion Contol egiste 0 TK1DL Touh key funtion 1-it ounte low yte TK1DH Touh key funtion 1-it ounte high yte TKC1 Touh key funtion Contol egiste 1 TKMn1DL Touh key odule n 1-it C/F ounte low yte TKMn1DH Touh key odule n 1-it C/F ounte high yte TKMnROL Touh key odule n efeene osillato apaito selet low yte TKMnROH Touh key odule n efeene osillato apaito selet high yte TKMnC0 Touh key odule n Contol egiste 0 TKMnC1 Touh key odule n Contol egiste 1 Touch Key Module Registers List

Rev. 1.20 12 Deee 0 201 Rev. 1.20 127 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Register Name Bit 7 6 5 4 3 2 1 0 TKTMR D7 D D D4 D3 D2 D1 D0 TKC0 — TKRCOV TKST TKCFOV TK1OV TSCS TK1S1 TK1S0 TK1DL D7 D D D4 D3 D2 D1 D0 TK1DH D1 D14 D13 D12 D11 D10 D9 D8 TKMn1DL D7 D D D4 D3 D2 D1 D0 TKMn1DH D1 D14 D13 D12 D11 D10 D9 D8 TKMnROL D7 D D D4 D3 D2 D1 D0 TKMnC0 MnMXS1 MnMXS0 MnDFEN D4 MnSOFC MnSOF2 MnSOF1 MnSOF0 TKMnC1 MnTSS — MnROEN MnKOEN MnK4IO MnK3IO MnK2IO MnK1IO Touch Key Function Registers List TKTMR Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 D7~D0: T ouch key time slot 8-bit counter preload register The touch key time slot counter preload register is used to determine the touch key time slot overflow time. The time slot unit period is obtained by a 5-bit counter and equal t o 32 t ime sl ot c lock c ycles. T herefore, t he t ime sl ot c ounter ove rflow t ime i s equal to the following equation shown. Time sl ot c ounter o verflow t ime=(256-TKTMR[7:0])×32tTSC, wh ere tTSC i s t he t ime slot counter clock period. TKC0 Register Bit 7 6 5 4 3 2 1 0 Nae — TKRCOV TKST TKCFOV TK1OV TSCS TK1S1 TK1S0 R/W — R/W R/W R/W R/W R/W R/W R POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 TKRCOV: T ouch key time slot counter overflow flag 0: No overflow occurs 1: Overflow occurs If the module 0 or all module time slot counter , selected by the TSCS bit, overflows, the T ouch Key Interrupt request flag, TKMF , will be set and all module key OSCs and reference OSCs will automatically stop. The touch key module 16-bit C/F counter , touch key functi on 16-bit counter , 5-bit time slot unit period counter and 8-bi t time slot counter will be automatically switched off. Bit 5 TKST: T ouch key detection Start control 0: Stopped or no operation 0→1: Start detection In all modules the touch key module 16-bit C/F counter , touch key function 16-bit counter and 5-bit time slot unit period counter will automatically be cle ared when this bit is clea red to zero. However , the 8-bit programmable time slot counter will not be cleared. When this bit is changed from low to high, the touch key module 16-bit C/F counter, touch key function 16-bit counter , 5-bit time slot unit period counter and 8-bit time slot counter will be switched on together with the key and reference oscillators to drive the corresponding counters.

Rev. 1.20 128 Deee 0 201 Rev. 1.20 129 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 4 TKCFOV: T ouch key module 16-bit C/F counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set high by the touch key module 16-bit C/F counter overflow and must be cleared to 0 by application programs. Bit 3 TK16OV: T ouch key function 16-bit counter overflow flag 0: No overflow occurs 1: Overflow occurs This bit is set high by the touch key function 16-bit counter overflow and must be cleared to 0 by application programs. Bit 2 TSCS: T ouch key time slot counter select 0: Each touch key module uses its own time slot counter 1: All touch key modules use Module 0 time slot counter Bit 1~0 TK16S1~TK16S0: T ouch key function 16-bit counter clock source select 00: fSYS 01: fSYS/2 10: fSYS/4 11: fSYS/8 TKC1 Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 TKFS1~TKFS0: T ouch Key oscillator and Reference oscillator frequency select 00: 500 kHz 01: 1000 kHz 10: 1500 kHz 11: 2000 kHz TK16DH/TK16DL – Touch Key Function 16-bit Counter Register Pair Register TK16DH TK16DL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D12 D11 D10 D9 D8 D7 D D D4 D3 D2 D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This regis ter pair is us ed to s tore the touch key function 16-bit counter value. This 16-bit counter can be used to calibrate the reference or key oscillator frequency . When the touch key time slot counter overflows, this 16-bit counter will be stopped and the counter content will be unchanged. This register pair will be cleared to zero when the TKST bit is set low.

Rev. 1.20 128 Deee 0 201 Rev. 1.20 129 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP TKMn16DH/TKMn16DL – Touch Key Module n 16-bit C/F Counter Register Pair Register TKMn16DH TKMn16DL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Nae D1 D14 D13 D12 D11 D10 D9 D8 D7 D D D4 D3 D2 D1 D0 R/W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key module n 16-bit C/F counter value. This 16-bit C/F counter will be stopped and the counter content will be kept unchanged when the touch key time slot counter overflows. This register pair will be cleared to zero when the TKST bit is set low. TKMnROH/TKMnROL – Touch Key Module n Reference Oscillator Capacitor Select Register Pair Register TKMnROH TKMnROL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Nae — — — — — — D9 D8 D7 D D D4 D3 D2 D1 D0 R/W — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W POR — — — — — — 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key module n reference oscillator capacitor value. This register pair will be loaded with the corresponding next time slot capac itor value from the dedicated touch key data memory at the end of the current time slot when the auto scan mode is selected. The reference oscillator internal capacitor value = (TKMnRO[9:0]×50pF)/1024. TKMnC0 Register Bit 7 6 5 4 3 2 1 0 Nae MnMXS1 MnMXS0 MnDFEN D4 MnSOFC MnSOF2 MnSOF1 MnSOF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 MnMXS1~MnMXS0: Multiplexer Key Select Bit Touch Key Module Number MnMXS[1:0] M0 M1 M2 M3 M4

00 KEY1 KEY KEY9 KEY13 KEY17

01 KEY2 KEY KEY10 KEY14 KEY18

10 KEY3 KEY7 KEY11 KEY1 KEY19

11 KEY4 KEY8 KEY12 KEY1 KEY20

Bit 5 MnDFEN: T ouch key module n multi-frequency control 0: Disable 1: Enable This bit is used to control the touch key oscillator frequency doubling function. When this bit is set to 1, the key oscillator frequency will be doubled. Bit 4 D4: Data bit for test only The bit is used for test purpose only and must be kept as "0" for normal operations.

Rev. 1.20 130 Deee 0 201 Rev. 1.20 131 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 3 MnSOFC: T ouch key module n C-to-F oscillator frequency hopping function control select 0: Controlled by the MnSOF2~MnSOF0 1: Controlled by hardware circuit This bit is used to select the touch key oscillator frequency hopping function control method. When this bit is set to 1, the key oscillator frequency hopping function is controlled by the hardware circuit regardless of the MnSOF2~MnSOF0 bits value. Bit 2~0 MnSOF2~MnSOF0: T ouch key module n Reference and Key oscillators hopping frequency select 000: fHOP0 – Min. hopping frequency 001: fHOP1 010: fHOP2 011: fHOP3 100: fHOP4 – Selected touch key oscillator frequency 101: fHOP5 110: fHOP6 111: fHOP7 – Max. hopping frequency These bits are used to select the touch key oscillator frequency for the hopping function. Note that these bits are only available when the MnSOFC bit is cleared to 0. TKMnC1 Register Bit 7 6 5 4 3 2 1 0 Nae MnTSS — MnROEN MnKOEN MnK4IO MnK3IO MnK2IO MnK1IO R/W R/W — R/W R/W R/W R/W R/W R/W POR 0 — 0 0 0 0 0 0 Bit 7 MnTSS: T ouch key module n time slot counter clock source select 0: T ouch key module n reference oscillator 1: fSYS/4 Bit 6 Unimplemented, read as "0" Bit 5 MnROEN: T ouch key module n Reference oscillator enable control 0: Disable 1: Enable Bit 4 MnKOEN: T ouch key module n Key oscillator enable control 0: Disable 1: Enable Bit 3 MnK4IO: T ouch key module n KEY 4 enable control MnK4IO Touch Key Module n – Mn M0 M1 M2 M3 M4 0: Disale I/O o othe funtions 1: Enale KEY4 KEY8 KEY12 KEY1 KEY20 Bit 2 MnK3IO: T ouch key module n KEY 3 enable control MnK3IO Touch Key Module n – Mn M0 M1 M2 M3 M4 0: Disale I/O o othe funtions 1: Enale KEY3 KEY7 KEY11 KEY1 KEY19

Rev. 1.20 130 Deee 0 201 Rev. 1.20 131 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 1 MnK2IO: T ouch key module n KEY 2 enable control MnK2IO Touch Key Module n – Mn M0 M1 M2 M3 M4 0: Disale I/O o othe funtions 1: Enale KEY2 KEY KEY10 KEY14 KEY18 Bit 0 MnK1IO: T ouch key module n KEY 1 enable control MnK1IO Touch Key Module n – Mn M0 M1 M2 M3 M4 0: Disale I/O o othe funtions 1: Enale KEY1 KEY KEY9 KEY13 KEY17 Touch Key Operation When a finger t ouches or i s i n proxi mity t o a t ouch pa d, t he c apacitance of t he pa d wi ll i ncrease. By using this capa citance variation to change slightly the frequency of the internal sense oscillator , touch act ions can be sensed by mea suring these frequency changes. Using an internal programmable divider the reference clock is used to generate a fixed time period. By counting a number of generated clock cycles from the sense oscillator during this fixed time period touch key actions can be determined. TKST MnKOEN MnROEN KEY OSC CLK Refeene OSC CLK fCFTMCK Enale fCFTMCK (MnDFEN=0) fCFTMCK (MnDFEN=0) TKRCOV Hadwae set to “0” Set Touh Key inteupt equest flag Touch Key Scan Mode Timing Diagram

Rev. 1.20 132 Deee 0 201 Rev. 1.20 133 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Each touch key module contains four touch key inputs which are shared with logical I/O pins, and the desired function is selected using register bits. Each touch key has its own independent sense oscillator. Therefore, there are four sense oscillators within each touch key module. During this reference clock fixed interval, the number of clock cycles generated by the s ense oscillator is measured, and it is this value that is used to determine if a touch action has been made or not. At the end of the fixed reference clock time interval a T ouch Key interrupt signal will be generated. Using the TSCS bit in the TKC0 register can select the module 0 time slot counter as the time slot counter for all modules. All modules use the same started signal, TKST , in the TKC0 register . The touch key module 16-bit C/F counter , touch key function 16-bit counter , 5-bit time slot unit period counter in all modules will be automatically cleared when the TKST bit is cleared to zero, but the 8-bit programmable tim e slot counter will not be cleared. The overflow time is setup by user . When the TKST bit changes from low to high, the 16-bit C/F counter , touch key function 16-bit counter , 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched on. The key oscillator and reference oscillator in all modules will be autom atically stopped and the 16- bit C/F counter , touch key function 16-bit counter , 5-bit time slot unit period counter and 8-bit time slot timer counter will be automatically switched of f when the time slot counter overflows. The clock source for the time slot counter is sourced from the reference oscillator or fSYS/4 which is selected using the MnTSS bit in the TKMnC1 register . The reference oscillator and key oscillator will be enabled by setting the MnROEN bit and MnKOEN bits in the TKMnC1 register. When the time s lot counter in all the touch key modules or in the touch key module 0 overflow s, an actual touch key interrupt will take place. The touch keys mentioned here are the keys which are enabled. Each touch key module consists of four touch keys, KEY1 ~ KEY4 are contained in module 0, KEY5 ~ KE Y8 a re c ontained i n m odule 1, KE Y9 ~ KE Y12 a re c ontained i n m odule 2, e tc. E ach touch key module has an identical structure. Touch Key Interrupt The touch key only has single inter rupt, when the time slot counter in all the touch key modules or in the touch key module 0 overflows, an actual touch key interrupt will take place. The touch keys mentioned he re a re t he ke ys whi ch a re e nabled. T he 16-bi t C/ F c ounter, 16-bi t c ounter, 5-bi t t ime slot unit period counter and 8-bit time slot counter in all modules will be automatically cleared. The TKCFOV flag which is the 16-bit C/F counter overflow flag will go high when any of the T ouch Key Module 16-bit C/F counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. The TK16OV flag which is the 16-bit counter overflow flag will go high when the 16-bit counter overflows. As this flag will not be automatically cleared, it has to be cleared by the application program. More de tails re garding t he t ouch ke y i nterrupt i s l ocated i n t he i nterrupt se ction of t he datasheet. Programming Considerations After the relevant registers are setup, the touch key detection process is initiated by changing the TKST bit from low to high. This will enable and synchronise all relevant oscillators. The TKRCOV flag which is the time slot counter flag will go high when the counter overflows. When this happens an interrupt signal will be generated. When the external touch key size and layout are defined, their related capacitances will then determine the sensor oscillator frequency.

Rev. 1.20 132 Deee 0 201 Rev. 1.20 133 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Serial Interface Module – SIM These devices contain a Serial Interface Module, which includes both the four -line SPI interface or two-line I2C interface types, to allow an easy method of communication with external peripheral hardware. Ha ving re latively si mple c ommunication prot ocols, t hese se rial i nterface t ypes a llow the microcontroller to interface to external SPI or I2C based hardware such as sensors, Flash or EEPROM memory , etc. The SIM interface pins are pin-shared with other I/O pins and therefore the SIM i nterface func tional pi ns m ust fi rst be se lected usi ng t he c orresponding pi n-shared func tion selection bits. As both interface types share the same pins and registers, the choice of whether the SPI or I2C type is used is made using the SIM operating mode control bits, named SIM2~SIM0, in the SIMC0 registe r. These pull-high resistors of the SIM pin-shared I/O pins are selected using pull- high control registers when the SIM function is enabled. It i s sugge sted t hat t he use r shoul d not e nter t he powe r down m ode by e xecuting t he "HAL T" instruction during the SIM communication in progress. SPI Interface The SPI interface is often used to communicate with external peripheral devices such as sensors, Flash or E EPROM m emory de vices, e tc. Ori ginally de veloped by Mot orola, t he four l ine SPI interface is a synchronous serial data interface that has a relatively simple communication protocol simplifying the programming requirements when communicating with external hardware devices. The communication is full duplex and operates as a slave/master type, where the devices can be either mas ter or s lave. A lthough the S PI interface s pecification can control multiple s lave devices from a single master , these devices provided only one SCS pin. If the master needs to control multiple slave devices from a single master, the master can use I/O pin to select the slave devices. SPI Interface Operation The SPI i nterface i s a f ull d uplex sy nchronous se rial d ata l ink. I t i s a f our l ine i nterface wi th p in names SDI, SDO, SCK and SCS. Pins SDI and SDO are the Serial Data Input and Serial Data Output lines, SCK is the Serial Clock line and SCS is the Slave Select line. As the SPI interface pins are pin-shared with normal I/O pins and with the I2C function pins, the SPI interface pins must first be selected by configuring the pin-shared function selection bits and setting the correct bits in the SIMC0 and SIMC2 registers. After the desired SPI configuration has been set it can be disabled or enabled us ing the S IMEN bit in the S IMC0 regis ter. Communication betw een devices connected to t he SPI i nterface i s c arried out i n a sl ave/master m ode wi th a ll da ta t ransfer i nitiations be ing implemented by the master . The Master also controls the clock signal. As the device only contains a single SCS pin only one slave device can be utilized. The SCS pin is controlled by software, set CSEN bit to 1 to enable SCS pin function, set CSEN bit to 0 the SCS pin will be floating state. The SPI function in this device offers the following features:

Full duplex synchronous data transfer
Both Master and Slave modes
LSB first or MSB first data transmission modes
Transmission complete flag
Rising or falling active clock edge The status of the SPI interface pins is determined by a number of facto rs such as whether the device is in the master or slave mode and upon the condition of certain control bits such as CSEN and SIMEN.

Rev. 1.20 134 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SCK SPI Maste SDO SDI SCS SCK SPI Slave SDI SDO SCS SPI Master/Slave Connection SIMD TX/RX Shift RegisterSDI Pin Clock Edge/Polarity Control CKEG bit CKPOLB bit Clock Source Select fSYS fSUB PTM0 CCRP match frequency/2 SCK Pin CSEN bit Busy Status SDO Pin TRF Flag SCS Pin Data Bus ICF Flag WCOL Flag SPI Block Diagram SPI Registers There are three internal registers which control the overall operation of the SPI interface. These are the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only used by the I2C interface. Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF SIMC2 D7 D CKPOLB CKEG MLS CSEN WCOL TRF SIMD D7 D D D4 D3 D2 D1 D0 SPI Registers List

Rev. 1.20 134 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by both the SPI and I2C functions. Before the device writes data to the SPI bus, the actual data to be transmitted must be placed in the SIMD register . After the data is received from the SPI bus, the device can read it from the SIMD register . Any transmission or reception of data from the SPI bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W "×": unknown There are also two control registers for the SPI interface, SIMC0 and SIMC2. Note that the SIMC2 register also has the name SIMA which is used by the I2C function. The SIMC1 register is not used by the SPI functio n, only by the I2C function. Register SIMC0 is used to control the enable/disable function and to set the data transmi ssion clock frequency . Register SIMC2 is used for other control functions such as LSB/MSB selection, write collision flag, etc.
SIMC0 Register Bit 7 6 5 4 3 2 1 0 Nae SIM2 SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF R/W R/W R/W R/W — R/W R/W R/W R/W POR 1 1 1 — 0 0 0 0 Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS/4 001: SPI master mode; SPI clock is fSYS/16 010: SPI master mode; SPI clock is fSYS/64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is PTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operatin g mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slav e selection and the SPI Master clock frequency . The SPI clock is a function of the system clock but can also be chosen to be sourced from PTM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce T ime Selection The SIMD EB1~SIMDEB0 bits are only used in the I2C mode and the detailed definition is described in the I2C interface section.

Rev. 1.20 13 Deee 0 201 Rev. 1.20 137 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bi t is the overa ll on/of f control for the SIM interface. Whe n the SIMEN bi t is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a mini mum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective. If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initiali sed by the applic ation program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: SIM SPI slave mode Incomplete T ransfer Flag 0: SIM SPI slave mode incomplete condition not occurred 1: SIM SPI slave mode incomplete condition occurred This bit is only available when the SIM is configured to operate in an SPI slave mode. If the SPI operate s in the slave mode with the SIMEN and CSEN bits both being set to 1 but the SCS line is pulled high by the external master device before the SPI data transfer is completely finished, the SIMICF bit will be set to 1 togethe r with the TRF bit. When this condition occurs, the corresponding interrupt will occur if the interrupt function is enabled. However , the TRF bit will not be set to 1 if the SIMICF bit is set to 1 by software application program.

SIMC2 Register Bit 7 6 5 4 3 2 1 0 Nae D7 D CKPOLB CKEG MLS CSEN WCOL TRF R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~6 Undefined bits These bits can be read or written by the application program. Bit 5 CKPOLB: SPI clock line base condition selection 0: The SCK line will be high when the clock is inactive. 1: The SCK line will be low when the clock is inactive. The CKPOLB bi t de termines the ba se condition of the clock line, if the bi t is hi gh, then t he SCK l ine wi ll be l ow whe n t he c lock i s i nactive. W hen t he CKPOL B bi t i s low, then the SCK line will be high when the clock is inactive. Bit 4 CKEG: SPI SCK clock active edge type selection CKPOLB=0 0: SCK is high base level and data capture at SCK rising edge 1: SCK is high base level and data capture at SCK falling edge CKPOLB=1 0: SCK is low base level and data capture at SCK falling edge 1: SCK is low base level and data capture at SCK rising edge The CKEG and CKPOLB bits are used to setup the way that the clock signal outputs and inputs data on the SPI bus. These two bits must be configured before data transfer is e xecuted ot herwise a n e rroneous c lock e dge m ay be ge nerated. T he CKPOL B bi t determines t he ba se c ondition of t he c lock l ine, i f t he bi t i s hi gh, t hen t he SCK l ine will be low when the clock is inact ive. When the CKPOLB bit is low , then the SCK line will be high when the clock is inactive. The CKEG bit determines active clock edge type which depends upon the condition of CKPOLB bit.

Rev. 1.20 13 Deee 0 201 Rev. 1.20 137 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 3 MLS: SPI data shift order 0: LSB first 1: MSB first This is the data shift select bit and is used to select how the data is transferred, either MSB or LSB first. Setting the bit high will select MSB first and low for LSB first. Bit 2 CSEN: SPI SCS pin control 0: Disable 1: Enable The CSEN bit is used as an enable/disable for the SCS pin. If this bit is low , then the SCS pin will be disabled and placed into I/O pin or other pin-shared functions. If the bit is high, the SCS pin will be enabled and used as a select pin. Bit 1 WCOL: SPI write collision flag 0: No collision 1: Collision The WCOL flag is used to detect whether a data collision has occurred or not. If this bit is high, it means that data has been attempted to be written to the SIMD register during a data transfer operation. This writing operation will be ignored if data is being transferred. This bit can be cleared by the application program. Bit 0 TRF: SPI T ransmit/Receive complete flag 0: SPI data is being transferred 1: SPI data transfer is completed The TRF bit is the T ransmit/Receive Complete flag and is set to 1 automatically when an SPI data transfer is completed, but must cleared to 0 by the application program. It can be used to generate an interrupt. SPI Communication After t he SPI i nterface i s e nabled by se tting t he SIME N bi t hi gh, t hen i n t he Ma ster Mode , whe n data is written to the SIMD register , transmission/reception will begin simultaneously . When the data t ransfer i s c omplete, t he T RF fl ag wi ll be se t a utomatically, but m ust be c leared usi ng t he application program. In the Slave Mode, when the clock signal from the master has been received, any data in the SIMD register will be transmitted and any data on the SDI pin will be shifted into the SIMD register . The master should output a SCS signal to enable the slave devices before a clock signal is provided. The slave data to be transferred should be well prepared at the appropriate moment relative to the SCS signal depending upon the configurations of the CKPOLB bit and CKEG bit. The accompanying timing diagram shows the relationship between the slave data and SCS signal for various configurations of the CKPOLB and CKEG bits. The SPI will continue to function in specific IDLE Mode if the clock source used by the SPI interface is still active.

Rev. 1.20 138 Deee 0 201 Rev. 1.20 139 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SCK (CKPOLB=1 CKEG=0) SCK (CKPOLB=0 CKEG=0) SCK (CKPOLB=1 CKEG=1) SCK (CKPOLB=0 CKEG=1) SCS SDO (CKEG=0) SDO (CKEG=1) SDI Data Captue Wite to SIMD SIMEN CSEN=1 SIMEN=1 CSEN=0 (Extenal Pull-high) D7/D0 D/D1 D/D2 D4/D3 D3/D4 D2/D D1/D D0/D7 D7/D0 D/D1 D/D2 D4/D3 D3/D4 D2/D D1/D D0/D7 SPI Master Mode Timing SCK (CKPOLB=1) SCK (CKPOLB=0) SCS SDO SDI Data Captue Wite to SIMD (SDO does not hange until fist SCK edge) D7/D0 D/D1 D/D2 D4/D3 D3/D4 D2/D D1/D D0/D7 SPI Slave Mode Timing – CKEG=0 SCK (CKPOLB=1) SCK (CKPOLB=0) SCS SDO SDI Data Captue D7/D0 D/D1 D/D2 D4/D3 D3/D4 D2/D D1/D D0/D7 Wite to SIMD (SDO hanges as soon as witing ous; SDO is floating if SCS=1) Note: Fo SPI slave ode if SIMEN=1 and CSEN=0 SPI is always enaled and ignoes the SCS level. SPI Slave Mode Timing – CKEG=1

Rev. 1.20 138 Deee 0 201 Rev. 1.20 139 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Clea WCOL Wite Data into SIMD WCOL=1? Tansission opleted? (TRF=1?) Read Data fo SIMD Clea TRF END Tansfe finished? ASPI Tansfe Maste o Slave SIMEN=1 Configue CKPOLB CKEG CSEN and MLS A SIM[2:0]=000 001 010 011 o 100 SIM[2:0]=101 Maste Slave Y Y N N N Y SPI Transfer Control Flow Chart I2C Interface The I2C interface is used to communicate with external peripheral devices such as sensors, EEPROM m emory e tc. Or iginally d eveloped b y Ph ilips, i t i s a t wo l ine l ow sp eed se rial i nterface for synchronous serial data transfer . The advantage of only two lines for communication, relatively simple communication protocol and the ability to accommodate multiple devices on the same bus has made it an extremely popular interface type for many applications. Devie Slave Devie Maste Devie Slave VDD SDA SCL I2C Master/Slave Bus Connection

Rev. 1.20 140 Deee 0 201 Rev. 1.20 141 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP I2C interface Operation The I2C serial interface is a two line interf ace, a serial data line, SDA, and serial clock line, SCL. As many devices may be connected together on the same bus, their outputs are both open drain types. For this reason it is necessary that external pull-high resistors are connected to these outputs. Note that no chip select line exists, as each device on the I2C bus is identified by a unique address which will be transmitted and received on the I2C bus. When two device s communicate with each other on the bidirectional I2C bus, one is known as the master device and one as the slave device. Both master and slave can transmit and receive data; however, it is the master device that has overall control of the bus. For these devices, which only operate in slave mode, there are two methods of transferring data on the I2C bus, the slave transmit mode and the slave receive mode. The pull-high control function pin-shared with the SCL or SDA pin is still applicable even if the I2C interface is activated and the related internal pull-up resistor could be controlled by its corresponding pull-up control register. Shift Registe Tansit/ Reeive Contol Unit fSYS fSUB Data Bus Slave Addess Registe (SIMA) I2C Data Registe (SIMD) Addess Copaato Read/Wite Slave SRW Bit Detet Stat o Stop Tie-out Contol SIMTOF Addess Math I2C Inteupt Deoune Ciuity SCL Pin M U X TXAK Data out SIMTOEN Addess Math SIMDEB1 SIMDEB0 SDA Pin Data in Dietion Contol HTX Bit 8-it Data Coplete SIMTOF Bit HCF Bit HBB Bit HAAS Bit I2C Block Diagram START signal fo Maste Send slave addess and R/W it fo Maste Aknowledge fo slave Send data yte fo Maste Aknowledge fo slave STOP signal fo Maste

Rev. 1.20 140 Deee 0 201 Rev. 1.20 141 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP The SIMDEB1 and SIMDEB0 bits determine the debounce time of the I2C interface. This uses the system clock to in ef fect add a debounce time to the external clock to reduce the possibility of gl itches on t he c lock l ine c ausing e rroneous ope ration. T he de bounce t ime, i f se lected, c an be chosen to be either 2 or 4 sys tem clocks. T o achieve the required I2C data trans fer speed, there exists a relationship between the system clock, fSYS, and the I2C debounce time. For either the I2C Standard or Fast mode operation, users must take care of the selected system clock frequency and the configured debounce time to match the criterion shown in the following table. I2C Debounce Time Selection I2C Standard Mode (100kHz) I2C Fast Mode (400kHz) No Devoune fSYS > 2 MHz fSYS > MHz 2 syste lok deoune fSYS > 4 MHz fSYS > 10 MHz 4 syste lok deoune fSYS > 8 MHz fSYS > 20 MHz I2C Minimum fSYS Frequency I2C Registers There a re t hree c ontrol re gisters a ssociated wi th t he I2C bus, SIMC0, SIMC1 a nd SIMT OC, one slave a ddress r egister, SI MA, a nd o ne d ata r egister, SI MD. An y t ransmission o r r eception o f d ata from the I2C bus must be made via the SIMD register . Bit SIMEN and bits SIM2~SIM0 in register SIMC0 are used by the I2C interfac e as well as the SPI interf ace. The SIMT OC register is used for the I2C time-out control. Note that the SIMA register also has the name SIMC2 which is used by the SPI function. Register Name Bit 7 6 5 4 3 2 1 0 SIMC0 SIM2 SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF SIMC1 HCF HAAS HBB HTX TXAK SRW IAMWU RXAK SIMA IICA IICA IICA4 IICA3 IICA2 IICA1 IICA0 — SIMD D7 D D D4 D3 D2 D1 D0 SIMTOC SIMTOEN SIMTOF SIMTOS SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 I2C Registers List

SIMD Register The SIMD register is used to store the data being transmitted and received. The same register is used by bot h t he SPI a nd I2C fun ctions. Be fore t he de vice wr ites da ta t o t he I2C bus, t he a ctual da ta t o be transmitted must be placed in the SIMD register . After the data is received from the I2C bus, the device can read it from the SIMD register . Any transmission or reception of data from the I2C bus must be made via the SIMD register. Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W "×": unknown

Rev. 1.20 142 Deee 0 201 Rev. 1.20 143 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

SIMA Register The SIMA registe r is also used by the SPI interface but has the name SIMC2. The SIMA register is the location where the 7-bit slave address of the slave device is stored. Bits 7~1 of the SIMA register define the device slave address. Bit 0 is not implemented. When a master device, which is connected to the I2C bus, sends out an address, which matches the slave address in the SIMA register , the slave device will be selected. Note that the SIMA register is the same register address as SIMC2 which is used by the SPI interface. Bit 7 6 5 4 3 2 1 0 Nae IICA IICA IICA4 IICA3 IICA2 IICA1 IICA0 — R/W R/W R/W R/W R/W R/W R/W R/W — "×": unknown Bit 7~1 IICA6~IICA0: I2C slave address IICA6~IICA0 is the I2C slave address bit 6 ~ bit 0 Bit 0 Unimplemented, read as "0". There are also two control registers for the I2C interface, SIMC0 and SIMC1. The register SIMC0 is used to control the enable/disable function and to set the data transmission clock frequency . The SIMC1 register contains the relevant flags which are used to indicate the I2C communication status.
SIMC0 Register Bit 7 6 5 4 3 2 1 0 Nae SIM2 SIM1 SIM0 — SIMDEB1 SIMDEB0 SIMEN SIMICF R/W R/W R/W R/W — R/W R/W R/W R/W POR 1 1 1 — 0 0 0 0 Bit 7~5 SIM2~SIM0: SIM Operating Mode Control 000: SPI master mode; SPI clock is fSYS /4 001: SPI master mode; SPI clock is fSYS /16 010: SPI master mode; SPI clock is fSYS /64 011: SPI master mode; SPI clock is fSUB 100: SPI master mode; SPI clock is PTM0 CCRP match frequency/2 101: SPI slave mode 110: I2C slave mode 111: Non SIM function These bits setup the overall operatin g mode of the SIM function. As well as selecting if the I2C or SPI function, they are used to control the SPI Master/Slav e selection and the SPI Master clock frequency . The SPI clock is a function of the system clock but can also be chosen to be sourced from PTM0. If the SPI Slave Mode is selected then the clock will be supplied by an external Master device. Bit 4 Unimplemented, read as "0" Bit 3~2 SIMDEB1~SIMDEB0: I2C Debounce T ime Selection 00: No debounce 01: 2 system clock debounce 1x: 4 system clock debounce These bits are used to select the I2C debounce time when the SIM is configured as the I2C interface function by setting the SIM2~SIM0 bits to "110".

Rev. 1.20 142 Deee 0 201 Rev. 1.20 143 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 1 SIMEN: SIM Enable Control 0: Disable 1: Enable The bi t is the overa ll on/of f control for the SIM interface. When the SIMEN bi t is cleared to zero to disable the SIM interface, the SDI, SDO, SCK and SCS, or SDA and SCL lines will lose their SPI or I2C function and the SIM operating current will be reduced to a mini mum value. When the bit is high the SIM interface is enabled. The SIM configuration option must have first enabled the SIM interface for this bit to be effective.If the SIM is configured to operate as an SPI interface via the SIM2~SIM0 bits, the contents of the SPI control registers will remain at the previous settings when the SIMEN bit changes from low to high and should therefore be first initiali sed by the applic ation program. If the SIM is configured to operate as an I2C interface via the SIM2~SIM0 bits and the SIMEN bit changes from low to high, the contents of the I2C control bits such as HTX and TXAK will remain at the previous setti ngs and should therefore be first initialised by the application program while the relevant I2C flags such as HCF, HAAS, HBB, SRW and RXAK will be set to their default states. Bit 0 SIMICF: SIM SPI Incomplete Flag The SIMICF bit is only used in the SPI mode and the detailed definiti on is described in the SPI interface section.

SIMC1 Register Bit 7 6 5 4 3 2 1 0 Nae HCF HAAS HBB HTX TXAK SRW IAMWU RXAK R/W R R R R/W R/W R/W R/W R POR 1 0 0 0 0 0 0 1 Bit 7 HCF: I2C Bus data transfer completion flag 0: Data is being transferred 1: Completion of an 8-bit data transfer The HCF flag is the data transfer flag. This flag will be zero when data is being transferred. Upon completion of an 8-bit data transfer the flag will go high and an interrupt will be generated. Bit 6 HAAS: I2C Bus data transfer completion flag 0: Not address match 1: Address match The HAAS fla g i s t he a ddress m atch fla g. T his fla g i s use d t o de termine i f t he sl ave device address is the same as the master transmit address. If the addresses match then this bit will be high, if there is no match then the flag will be low. Bit 5 HBB: I2C Bus busy flag 0: I2C Bus is not busy 1: I2C Bus is busy The HBB flag is the I2C busy flag. T his flag will be "1" when the I2C bus is busy which will occur when a ST ART signal is detected. The flag will be set to "0" when the bus is free which will occur when a STOP signal is detected. Bit 4 HTX: I2C slave device transmitter/receiver selection 0: Slave device is the receiver 1: Slave device is the transmitter Bit 3 TXAK: I2C bus transmit acknowledge flag 0: Slave send acknowledge flag 1: Slave does not send acknowledge flag The TXAK bit is the transmit acknowledge flag. After the slave device receipt of 8-bits of data, this bit will be transmitted to the bus on the 9th clock from the slave device. The slave device must always set TXAK bit to "0" before further data is received.

Rev. 1.20 144 Deee 0 201 Rev. 1.20 14 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 2 SRW: I2C slave read/write flag 0: Slave device should be in receive mode 1: Slave device should be in transmit mode The SR W f lag i s t he I2C Sl ave R ead/Write f lag. T his f lag d etermines wh ether the master device wishes to transmit or receive data from the I2C bus. When the transmitted address and slave address is match, that is when the HAAS flag is set high, the slave device will check the SR W flag to determine whether it should be in transmit mode or receive mode. If the SR W flag is high, the master is requesting to read data from the bus, so the slave device should be in transmit mode. When the SR W flag is zero, the master will write data to the bus, therefore the slave device should be in receive mode to read this data. Bit 1 IAMWU: I2C Address Match W ake-Up control 0: Disable 1: Enable – must be cleared by the application program after wake-up This bit should be set to 1 to enabl e the I2C address match wake up from the SLEEP or IDLE Mode. If the IAMWU bit has been set before entering either the SLEEP or IDLE mode to enable the I2C address match wake up, then this bit must be cleared by the application program after wake-up to ensure correction device operation. Bit 0 RXAK: I2C bus receive acknowledge flag 0: Slave receives acknowledge flag 1: Slave does not receive acknowledge flag The R XAK f lag i s t he r eceiver a cknowledge f lag. W hen t he R XAK f lag i s "0 ", i t means that a acknowledge signal has been received at the 9th clock, after 8 bits of data have been transmitted. When the slave device in the transmit mode, the slave device checks the RXAK flag to determine if the master receiver wishes to receive the next byte. T he sl ave t ransmitter wi ll t herefore c ontinue se nding out da ta unt il t he RXAK flag is "1". When this occurs, the slave transmitter will release the SDA line to allow the master to send a STOP signal to release the I2C Bus. I2C Bus Communication Communication on the I2C bus requires four separate steps, a ST ART signal, a slave device address transmission, a data transmission and finally a ST OP signal. When a ST ART signal is placed on the I2C bus, all devices on the bus will receive this signal and be notified of the imminent arrival of data on the bus. The first seven bits of the data will be the slave address with the first bit being the MSB. If the address of the slave device matches that of the transmitted address, the HAAS bit in the SIMC1 register will be set and an I2C interrupt will be generated. After entering the interrupt service routine, the slave device must first check the condition of the HAAS and SIMT OF bits to determine whether t he i nterrupt sou rce o riginates fr om a n a ddress m atch, 8 -bit d ata t ransfer c ompletion o r I2C bus time-out occurrence. During a data transfer , note that after the 7-bit slave address has been transmitted, the following bit, which is the 8th bit, is the read/write bit whose value will be placed in the SRW bit. This bit will be checked by the slave device to determine whether to go into transmit or receive mode. Before any transfer of data to or from the I2C bus, the microcontroller must initialise the bus; the following are steps to achieve this:

Step 1 Set the SIM2~SIM 0 bits to "1 10" and SIMEN bit to "1" in the SIMC0 register to enable the I2C bus.
Step 2 Write the slave address of the device to the I2C bus address register SIMA.
Step 3 Set the SIME bit in the interrupt control register to enable the SIM interrupt.

Rev. 1.20 144 Deee 0 201 Rev. 1.20 14 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Stat Set SIM[2:0]=110 Set SIMEN Wite Slave Addess to SIMA I2C Bus Inteupt=? Clea SIMEN Poll SIMF to deide when to go to I2C Bus ISR Set SIME Wait fo Inteupt Goto Main Poga Goto Main Poga I2C Bus Inisialisation Flow Chart I2C Bus Start Signal The ST ART signal can only be generated by the master device connec ted to the I2C bus and not by the slave device. This ST ART signal will be detected by all devices connected to the I2C bus. When detected, this indicates that the I2C bus is busy and therefore the HBB bit will be set. A ST ART condition occurs when a high to low transition on the SDA line takes place when the SCL line remains high. I2C Slave Address The t ransmission o f a ST ART si gnal b y t he m aster wi ll b e d etected b y a ll d evices o n t he I2C bus. To determine which slave device the master wishes to communicate with, the address of the slave device will be sent out immediately following the ST ART signal. All slave devices, after receiving this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by the maste r matche s the internal address of the microcontroller slave device, then an internal I2C bus interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines the read/write status and will be saved to the SR W bit of the SIMC1 register . The slave device will then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set the status flag HAAS when the addresses match. As a n I2C bus i nterrupt c an c ome from t hree sourc es, whe n t he progra m e nters t he i nterrupt subroutine, the HAAS and SIMT OF bits should be examined to see whether the interrupt source has come from a matching slave address, the completion of a data byte transfer or the I2C bus time-out occurrence. When a slave address is matched, the devices must be placed in either the transmit mode and then write data to the SIMD register , or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Bus Read/Write Signal The SR W bit in the SIMC1 registe r defines whether the slave device wishes to read data from the I2C bus or write data to the I2C bus. The slave device should exami ne this bit to determine if it is to be a transmitter or a receiver . If the SR W flag is "1" then this indicates that the master device wishes to read data from the I2C bus, theref ore the slave device must be setup to send data to the I2C bus as a transmitter . If the SR W flag is "0" then this indicates that the master wishes to send data to the I2C bus, therefore the slave device must be setup to read data from the I2C bus as a receiver.

Rev. 1.20 14 Deee 0 201 Rev. 1.20 147 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP I2C Bus Slave Address Acknowledge Signal After the mas ter has trans mitted a calling addres s, any s lave device on the I2C bus, w hose own internal address matches the calling address, must generate an acknowledge signal. The acknowledge signal will inform the master that a slave device has accepted its calling address. If no acknowledge signal is received by the master then a ST OP signal must be transmitted by the master to end the communication. When the HAAS flag is high, the addresses have matched and the slave device must check the SR W flag to determine if it is to be a transmitter or a receiver . If the SR W flag is high, the slave device should be setup to be a transmitter so the HTX bit in the SIMC1 register should be set to "1". If the SR W flag is low , then the microcontroller slave device should be setup as a receiver and the HTX bit in the SIMC1 register should be set to "0". I2C Bus Data and Acknowledge Signal The transmitted data is 8-bits wide and is transmitted after the slave device has acknowledged receipt o f i ts sl ave a ddress. T he o rder o f se rial b it t ransmission i s t he MSB fir st a nd t he L SB l ast. After receipt of 8-bits of data, the receiver must transmit an acknowledge signal, level "0", before it can receive the next data byte. If the slave transmitter does not recei ve an acknowledge bit signal from the master receiver , then the slave transmitter will release the SDA line to allow the master to send a ST OP signal to release the I2C Bus. The corresponding data will be stored in the SIMD register. If setup as a transmitter , the slave device must first write the data to be transmitted into the SIMD register . If setup as a receive r, the slave device must read the transmitted data from the SIMD register. When the slave receiver receives the data byte, it must generate an acknowledge bit, known as TXAK, on the 9th clock. The slave device, which is setup as a transmi tter will check the RXAK bit in the SIMC1 register to determine if it is to send another data byte, if not then it will release the SDA line and await the receipt of a STOP signal from the master. StatSCL SDA SCL SDA S=Stat (1 it) SA=Slave Addess (7 its) SR=SRW it (1 it) M=Slave devie send aknowledge it (1 it) D=Data (8 its) A=ACK (RXAK it fo tansitte TXAK it fo eeive 1 it) P=Stop (1 it) ACKSlave Addess SRW StopData ACK 1101010 10010100 S SA SR M D A D A …… S SA SR M D A D A …… P Note: *When a slave address is matched, the devices must be placed in either the transmit mode and then write data to the SIMD register , or in the receive mode where it must implement a dummy read from the SIMD register to release the SCL line. I2C Communication Timing Diagram

Rev. 1.20 14 Deee 0 201 Rev. 1.20 147 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Stat SIMTOF=1? SET SIMTOEN CLR SIMTOF RETI HAAS=1? HTX=1? SRW=1? Read fo SIMD to elease SCL Line RETI RXAK=1? Wite data to SIMD to elease SCL Line CLR HTX CLR TXAK Duy ead fo SIMD to elease SCL Line RETI RETI SET HTX Wite data to SIMD to elease SCL Line RETI CLR HTX CLR TXAK Duy ead fo SIMD to elease SCL Line RETI YesNo No Yes Yes NoYesNo No Yes I2C Bus ISR Flow Chart I2C Time-out Control In order to reduce the I2C lockup problem due to reception of erroneous clock s ources, a time-out function is provided. If the clock source connected to the I2C bus is not received for a while, then the I2C circuitry a nd re gisters wi ll be re set a fter a c ertain t ime-out pe riod. T he t ime-out c ounter st arts to count on an I2C bus "ST ART" & "address match" condition, and is cleared by an SCL falling edge. Before the next SCL falling edge arrives, if the time elapsed is greater than the time-out period specified by the SIMT OC register , then a time-out condition will occur . The time-out function will stop when an I2C "STOP" condition occurs.

Rev. 1.20 148 Deee 0 201 Rev. 1.20 149 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP StatSCL SDA SCL SDA 1 0 ACKSlave Addess SRW Stop 1101010 10010100 I2C tie-out ounte stat I2C tie-out ounte eset on SCL negative tansition I2C Time-out When an I2C time-out counter overflow occurs, the counter will stop and the SIMT OEN bit will be c leared t o z ero a nd t he SIMT OF bi t wi ll be se t hi gh t o i ndicate t hat a t ime-out c ondition ha s occurred. The time-out condition will also generate an interrupt which uses the I2C interrupt vector . When an I2C time-out occurs, the I2C internal circuitry will be reset and the registers will be reset into the following condition: Register After I2C Time-out SIMD SIMA SIMC0 No hange SIMC1 Reset to POR ondition I2C Register after Time-out The SIMTOF flag can be cleared by the application program. There are 64 time-out period selections which can be selected using the SIMT OS bits in the SIMT OC register . The time-out duration is calculated by the formula: ((1~64)×(32/fSUB)). This gives a time-out period which ranges from about 1ms to 64ms.

SIMTOC Register Bit 7 6 5 4 3 2 1 0 Nae SIMTOEN SIMTOF SIMTOS SIMTOS4 SIMTOS3 SIMTOS2 SIMTOS1 SIMTOS0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 SIMTOEN: SIM I2C T ime-out control 0: Disable 1: Enable Bit 6 SIMTOF: SIM I2C T ime-out flag 0: No time-out occurred 1: T ime-out occurred This bit is set high by the I2C time-out circuitry and cleared to zero by the application program. Bit 5~0 SIMTOS5~SIMTOS0: SIM I2C T ime-out period selection I2C T ime-out clock source is fSUB/32 I2C T ime-out period is equal to (SIMTOS[5:0]+1)×(32/fSUB)

Rev. 1.20 148 Deee 0 201 Rev. 1.20 149 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP UART Interface These devices contain an integrated full-duplex asynchronous serial communications UAR T interface t hat e nables c ommunication wi th e xternal de vices t hat c ontain a se rial i nterface. T he UART function has many features and can transmit and receive data serially by transferring a frame of data with eight or nine data bits per transmission as well as being able to detect errors when the data is ove rwritten or i ncorrectly fra med. The UAR T funct ion possesse s i ts own i nternal i nterrupt which can be used to indicate when a reception occurs or when a transmission terminates. The integrated UART function contains the following features:

Full-duplex, asynchronous communication
8 or 9 bits character length
Even, odd or no parity options
One or two stop bits
Baud rate generator with 8-bit prescaler
Parity, framing, noise and overrun error detection
Support for interrupt on address detect (last character bit=1)
Separately enabled transmitter and receiver
2-byte Deep FIFO Receive Data Buffer
RX pin wake-up function
Transmit and receive interrupts
Interrupts can be initialized by the following conditions: ♦ Transmitter Empty ♦ Transmitter Idle ♦ Receiver Full ♦ Receiver Overrun ♦ Address Mode Detect Tansitte Shift Registe (TSR) Reeive Shift Registe (RSR) TX Pin RX Pin Baud Rate Geneato TX Registe (TXR) RX Registe (RXR) Data to e tansitted Data eeived BuffefSYS MCU Data Bus UART Data Transfer Block Diagram UART External Pins To communicate with an external serial interface, the internal UAR T has two external pins known as TX and RX. The TX and RX pins are the UAR T transmitter and receiver pins respectively . Along with the UAR TEN, TXEN and RXEN bits, if set, will automatically setup the TX and RX pins to their respective TX output and RX input conditions and disable any pull-high resistor option which may exist on the TX and RX pins. When the TX or RX pin function is disabled by clearing the UARTEN, TX EN or RXEN bit, the TX or RX pin will be used as a general purpose I/O or other pin- shared functional pin.

Rev. 1.20 10 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP UART Data Transfer Scheme The a bove di agram shows t he ove rall da ta t ransfer st ructure a rrangement for t he UAR T i nterface. The a ctual da ta t o be t ransmitted from t he MCU i s fi rst t ransferred t o t he T XR re gister by t he application program. The data will then be transferred to the T ransmit Shift Register from where it will be shifted out, LSB first, onto the TX pin at a rate controlled by the Baud Rate Generator . Only the TXR register is mapped onto the MCU Data Memory , the Transmit Shift Register is not mapped and is therefore inaccessible to the application program. Data to be received by the UAR T is accepted on the external RX pin, from where it is shifted in, LSB fi rst, t o t he Re ceiver Shi ft R egister a t a ra te c ontrolled by t he B aud Ra te Ge nerator. W hen the shift register is full, the data will then be transferred from the shift register to the internal RXR register, where it is buf fered and can be manipulated by the application program. Only the RXR register i s m apped ont o t he MCU Da ta Me mory, t he Re ceiver Shift Re gister i s not m apped a nd i s therefore inaccessible to the application program. It should be noted that the actual register for data transmission and reception, although referred to in the text, and in application programs, as separate TXR and RXR registers, only exists as a single shared register in the Data Memory . This shared register known as the TXR_RXR register is used for both data transmission and data reception. UART Status and Control Registers There are five control registers associated with the UAR T function. The USR, UCR1 and UCR2 registers c ontrol t he o verall f unction o f t he UAR T, wh ile t he B RG r egister c ontrols t he B aud r ate. The actua l data to be transmitted and received on the serial interface is managed through the TXR_ RXR data registers. Register Name Bit 7 6 5 4 3 2 1 0 USR PERR NF FERR OERR RIDLE RXIF TIDLE TXIF UCR1 UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 UCR2 TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE TXR_RXR TXRX7 TXRX TXRX TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 BRG BRG7 BRG BRG BRG4 BRG3 BRG2 BRG1 BRG0 UART Registers List USR Register The USR r egister i s t he st atus r egister f or t he UAR T, wh ich c an b e r ead b y t he p rogram t o determine the present status of the UAR T. All flags within the USR register are read only and further explanations are given below. Bit 7 6 5 4 3 2 1 0 Nae PERR NF FERR OERR RIDLE RXIF TIDLE TXIF R/W R R R R R R R R POR 0 0 0 0 1 0 1 1 Bit 7 PERR: Parity error flag 0: No parity error is detected 1: Parity error is detected The PERR flag is the parity error flag. When this read only flag is "0", it indicates a parity error has not been detected. When the flag is "1", it indicates that the parity of the received word is incorrect. This error flag is applicable only if Parity mode (odd or even) is selected. The flag can also be cleared by a software sequence which involves a read to the status register USR followed by an access to the TXR_RXR data register.

Rev. 1.20 10 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 6 NF: Noise flag 0: No noise is detected 1: Noise is detected The NF fla g is the noise fla g. Whe n thi s read only fla g is "0", it indi cates no noise condition. When the flag is "1", it indicates that the UAR T has detected noise on the receiver input. The NF flag is set during the same cycle as the RXIF flag but will not be set in the case of as overrun. The N F flag can be cleared by a softw are sequence which will involve a read to the status register USR followed by an access to the TXR_RXR data register. Bit 5 FERR: Framing error flag 0: No framing error is detected 1: Framing error is detected The FERR flag is the framing error flag. When this read only flag is "0", it indicates that there is no framing error . When the flag is " 1", it indicates that a framing error has been detected for the current character . The flag can also be cleared by a software sequence which will involve a read to the status register USR followed by an access to the TXR_RXR data register. Bit 4 OERR: Overrun error flag 0: No overrun error is detected 1: Overrun error is detected The OERR flag is the overrun error flag which indicates when the rece iver buf fer has overflowed. When this read only flag is "0", it indicates that there is no overrun error . When the flag is "1", it indicates that an overrun error occurs which will inhibit further transfers to the TX R_RXR receive data regis ter. The flag is cleared by a softw are sequence, which is a read to the status register USR followed by an access to the TXR_RXR data register. Bit 3 RIDLE: Receiver status 0: data reception is in progress (data being received) 1: no data reception is in progress (receiver is idle) The RIDLE flag is the receiver status flag. When this read only flag is "0", it indicates that the receiver is between the init ial detection of the start bit and the completion of the stop bit. When the flag is "1", it indicates that the receiver is idle. Between the completion of the stop bit and the detection of the next start bit, the RIDLE bit is "1" indicating that the UART receiver is idle and the RX pin stays in logic high condition. Bit 2 RXIF: Receive TXR_RXR data register status 0: TXR_RXR data register is empty 1: TXR_RXR data register has available data The RXIF flag is the receive data register status flag. When this read only flag is "0", it i ndicates t hat t he T XR_RXR re ad da ta re gister i s e mpty. W hen t he fl ag i s "1 ", i t indicates that the TXR_RXR read data register contains new data. When the contents of the shift registe r are transferred to the TXR_RXR register , an interru pt is generated if RIE=1 in the UCR2 register . If one or more errors are detected in the received word, the appropriate receive-related flags NF , FERR, and/or PERR are set within the same clock cycle. The RXIF flag will eventually be cleared when the USR register is read with RXIF set, followed by a read from the TXR_RXR register , and if the TXR_RXR register has no more new data available. Bit 1 TIDLE: T ransmission status 0: data transmission is in progress (data being transmitted) 1: no data transmission is in progress (transmitter is idle) The TIDLEn flag is known as the transmission complete flag. When this read only flag is "0", it indicates that a transmission is in progress. This flag will be set to "1" when the TXIF flag is "1" and when there is no transmit data or break character being transmitted. When TIDLE is equal to 1, the TX pin becomes idle with the pin state in logic high condition. The TIDLE flag is cleared by reading the USR register with TIDLE set and then writing to the TXR_RXR register . The flag is not generated when a data character or a break is queued and ready to be sent.

Rev. 1.20 12 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 0 TXIF: T ransmit TXR data register status 0: character is not transferred to the transmit shift register 1: character has transferred to the transmit shift register (TXR_RXR data register is empty) The TXIF flag is the transmit data register empty flag. When this read only flag is "0", it indicat es that the character is not transferred to the transmitter shift register . When the flag is "1", it indicates that the transmitter shift register has received a character from the TXR_RXR data register . The TXIF flag is cleared by reading the UAR T status register (USR) with TXIF set and then writing to the TXR_RXR data register . Note that when the TXEN bit is set, the TXIF flag bit will also be set since the transmit data register is not yet full. UCR1 Register The UCR1 register together with the UCR2 register are the UAR T control registers that are used to set the various options for the UAR T function such as overall on/of f control, parity control, data transfer bit length, etc. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Nae UARTEN BNO PREN PRT STOPS TXBRK RX8 TX8 R/W R/W R/W R/W R/W R/W R/W R W POR 0 0 0 0 0 0 × 0 "×": unknown Bit 7 UARTEN: UART function enable control 0: Disable UART; TX and RX pins are as I/O or other pin-shared functional pins 1: Enable UART; TX and RX pins function as UART pins The UAR TEN bit is the UAR T enable bit. When this bit is equal to "0", the UAR T will be disabled and the RX pin as well as the TX pin will be as the general purpose I/O or other pin-shared functional pins. When the bit is equal to "1", the UAR T will be enabled and the TX and RX pins will function as defined by the TXEN and RXEN enable control bits. When the UAR T is disabled, it will empty the buf fer so any character remainin g in the buf fer will be discarded. In addition, the value of the baud rate counter will be reset. If the UAR T is disabled, all error and status flags will be reset. Also the TXEN, RXEN, TXBRK, RXIF , OERR, FERR, PERR and NF bits will be cleared, while the TIDLE, TXIF and RIDLE bits will be set. Other control bits in UCR1, UCR2 and BRG registers will remain unaffected. If the UART is active and the UARTEN bit is cleared, all pending transmi ssions and receptions will be terminated and the module will be reset as defined above. When the UAR T is re-enabled, it will restart in the same configuration. Bit 6 BNO: Number of data transfer bits selection 0: 8-bit data transfer 1: 9-bit data transfer This bit is used to select the data length format, which can have a choice of either 8-bit or 9-bit format. When this bit is equal to "1", a 9-bit data length format will be selected. If the bit is equal to "0", then an 8-bit data length format will be selected. If 9-bit data length format is selected, then bits RX8 and TX8 will be used to store the 9th bit of the received and transmitted data respectively. Note: 1. If BNO=1 (9-bi t da ta t ransfer) a nd pa rity func tion i s e nabled, t he 9th bi t of data is the parity bit which will not be transferred to RX8. 2. If BNO=0 (8-bi t da ta t ransfer) a nd pa rity func tion i s e nabled, t he 8th bi t of data is the parity bit which will not be transferred to RX7. Bit 5 PREN: Parity function enable control 0: Parity function is disabled 1: Parity function is enabled This bit is the parity function enable bit. When this bit is equal to 1, the parity function will be enabled. If the bit is equal to 0, then the parity function will be disabled.

Rev. 1.20 12 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 4 PRT: Parity type selection bit 0: Even parity for parity generator 1: Odd parity for parity generator This bit is the parity type selection bit. When this bit is equal to 1, odd parity type will be selected. If the bit is equal to 0, then even parity type will be selected. Bit 3 STOPS: Number of stop bits selection 0: One stop bit format is used 1: T wo stop bits format is used This bit determines if one or two stop bits are to be used. When this bit is equal to "1", two stop bits format are used. If the bit is equal to "0", then only one stop bit format is used. Bit 2 TXBRK: T ransmit break character 0: No break character is transmitted 1: Break characters transmit The T XBRK bi t i s t he T ransmit Bre ak Cha racter bi t. W hen t his bi t i s e qual t o "0", there are no break characters and the TX pin operates normally . When the bit is equal to "1", there are transmit break characters and the transmitter will send logic zeros. W hen t his bi t i s e qual t o "1", a fter t he buf fered da ta ha s be en t ransmitted, t he transmitter output is held low for a minimum of a 13-bit length and until the TXBRK bit is reset. Bit 1 RX8: Receive data bit 8 for 9-bit data transfer format (read only) This bit is only used if 9-bit data transfers are used, in which case this bit location will store the 9th bit of the receive d data known as RX8. The BNO bit is used to determ ine whether data transfers are in 8-bit or 9-bit format. Bit 0 TX8: T ransmit data bit 8 for 9-bit data transfer format (write only) This bit is only us ed if 9-bit data transfers are us ed, in w hich cas e this bit location will store the 9th bit of the transmitted data known as TX8. The BNO bit is used to determine whether data transfers are in 8-bit or 9-bit format. UCR2 Register The UCR2 register is the second of the UAR T control registers and serves several purposes. One of its main functions is to control the basic enable/disable operation if the UAR T T ransmitter and Receiver as well as enabling the various UAR T interrupt sources. The register also serves to control the baud rate speed, receiver wake-up function enable and the address detect function enable. Further explanation on each of the bits is given below. Bit 7 6 5 4 3 2 1 0 Nae TXEN RXEN BRGH ADDEN WAKE RIE TIIE TEIE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TXEN: UART T ransmitter enable control 0: UART T ransmitter is disabled 1: UART T ransmitter is enabled The TXEN bit is the T ransmitter Enable Bit. When this bit is equal to "0", the transmitter will be disabled with any pending data transmissions being aborted. In addition the buf fers will be reset. In this situation the TX pin will be used as an I/O or other pin-shared functional pin. If the T XEN bit is equal to "1" and the UARTEN bit is also equal to 1, the transmitter will be enabled and the TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the data transmission to be aborted and will reset the transmitter.

Rev. 1.20 14 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 6 RXEN: UART Receiver enable control 0: UART Receiver is disabled 1: UART Receiver is enabled The RXEN bit is the Receiver Enable Bit. When this bit is equal to "0", the receiver will be disabled with any pending data receptions being aborted. In addition the receiver buf fers will be reset. In this situation the RX pin will be used as an I/O or other pin-shared functional pin. If the RXEN bit is equal to "1" and the UAR TEN bit is also equal to 1, the receiver will be enabled and the RX pin will be controlled by the UART. Clearing the RXEN bit during a reception will cause the data reception to be aborted and will reset the receiver. Bit 5 BRGH: Baud Rate speed selection 0: Low speed baud rate 1: High speed baud rate The bit named BRGH selects the high or low speed mode of the Baud Rate Generator . This bit, together w ith the value placed in the baud rate regis ter, BRG , controls the baud rate of the UART. If the bit is equal to 0, the low speed mode is selected. Bit 4 ADDEN: Address detect function enable control 0: Address detection function is disabled 1: Address detection function is enabled The bit named ADDEN is the address detection function enable control bit. When this bit is equal to 1, the address detection function is enabled. When it occurs, if the 8th bit, which corresponds to RX7 if BNO=0, or the 9th bit, which corresponds to RX8 if BNO=1, ha s a va lue of "1 ", t hen t he re ceived word wi ll be i dentified a s a n a ddress, rather than data. If the corresponding interrupt is enabled, an interrupt request will be generated each time the received word has the address bit set, which is the 8th or 9th bit depending on the value of the BNO bit. If the address bit known as the 8th or 9th bit of the received word is "0" with the address detection function being enabled, an interrupt will not be generated and the received data will be discarded. Bit 3 WAKE: RX pin falling edge wake-up function enable control 0: RX pin wake-up UART function is disabled 1: RX pin wake-up UART function is enabled The bit is used to control the wake-up UAR T function when a falling edge on the RX pin occurs. Note that this bit is only available when the UAR T clock, fSYS, is switched off. There will be no RX pin wake-up UAR T function if the UAR T clock, fSYS, exists. If t he W AKE b it i s e qual t o 1 a nd t he UAR T c lock, fSYS, i s swi tched o ff, a UAR T wake-up request w ill be initiated w hen a falling edge on the RX pin occurs. When this reque st happens and the corresponding inte rrupt i s enable d, an RX pin wake-up UART interrupt will be generated to inform the MCU to wake up the UAR T function by switching on the UAR T clock, fSYS, via the application programs. Otherwise, the UART function can not resume even if there is a falling edge on the RX pin when the WAKE bit is cleared to 0. Bit 2 RIE: Receiver interrupt enable control 0: Receiver related interrupt is disabled 1: Receiver related interrupt is enabled The bit enables or disables the rece iver interrupt. If this bit is equal to 1 and when the receiver overrun flag OERR or received data available flag RXIF is set, the UAR T interrupt request flag will be set. If this bit is equal to 0, the UAR T interrupt request flag will not be influenced by the condition of the OERR or RXIF flags. Bit 1 TIIE: T ransmitter Idle interrupt enable control 0: T ransmitter idle interrupt is disabled 1: T ransmitter idle interrupt is enabled The bit enables or disables the transmitter idle interrupt. If this bit is equal to 1 and when t he t ransmitter i dle fla g T IDLE i s se t, due t o a t ransmitter i dle c ondition, t he UART interrupt request flag will be set. If this bit is equal to 0, the UAR T interrupt request flag will not be influenced by the condition of the TIDLE flag.

Rev. 1.20 14 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 0 TEIE: T ransmitter Empty interrupt enable control 0: T ransmitter empty interrupt is disabled 1: T ransmitter empty interrupt is enabled The bit enables or disables the transmitter empty interrupt. If this bit is equal to 1 and when the transmit ter empty flag TXIF is set, due to a transmitter empty condition, the UART interrupt request flag will be set. If this bit is equal to 0, the UAR T interrupt request flag will not be influenced by the condition of the TXIF flag. TXR_RXR Register The TXR_RXR register is the data register which is used to store the data to be transmitted on the TX pin or being received from the RX pin. Bit 7 6 5 4 3 2 1 0 Nae TXRX7 TXRX TXRX TXRX4 TXRX3 TXRX2 TXRX1 TXRX0 R/W R/W R/W R/W R/W R/W R/W R/W R/W "×": unknown Bit 7~0 TXRX7~TXRX0: UART T ransmit/Receive Data bits Baud Rate Generator To setup the speed of the serial data communication, the UAR T function contains its own dedicated baud ra te ge nerator. T he ba ud ra te i s c ontrolled by i ts own i nternal fre e runni ng 8-bi t t imer, t he period o f wh ich i s d etermined b y t wo f actors. T he f irst o f t hese i s t he v alue p laced i n t he B RG register and the second is the value of the BRGH bit within the UCR2 control register . The BRGH bit decides, if the baud rate generat or is to be used in a high speed mode or low speed mode, which in turn determines the formula that is used to calculate the baud rate. The value in the BRG register , N, which is used in the following baud rate calculation formula determines the division factor . Note that N is the decimal value placed in the BRG register and has a range of between 0 and 255. UCR2 BRGH Bit 0 1 Baud Rate (BR) fSYS / [4 (N+1)] fSYS / [1 (N+1)] By programming the BRGH bit which allows selection of the related formula and programming the required value in the BRG register , the required baud rate can be setup. Note that because the actual baud rate is determ ined using a discrete value, N, placed in the BRG register , there will be an error associated between the actual and requested value. The following example shows how the BRG register value N and the error value can be calculated. BRG Register Bit 7 6 5 4 3 2 1 0 Nae BRG7 BRG BRG BRG4 BRG3 BRG2 BRG1 BRG0 R/W R/W R/W R/W R/W R/W R/W R/W R/W "×": unknown Bit 7~0 BRG7~BRG0: Baud Rate values By programming the BRGH bit in the UCR2 register which allows selection of the related formula described above and programming the required value in the BRG register, the required baud rate can be setup.

Rev. 1.20 1 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Calculating the Baud Rate and Error Values For a clock frequency of 4MHz, and with BRGH set to 0 determine the BRG register value N, the actual baud rate and the error value for a desired baud rate of 4800. From the above table the desired baud rate BR=fSYS / [64 (N+1)] Re-arranging this equation gives N=[fSYS / (BR×64)] - 1 Giving a value for N=[4000000 / (4800×64)] - 1=12.0208 To obtain the closest value, a decim al value of 12 should be placed into the BRG register . This gives an actual or calculated baud rate value of BR=4000000 / [64×(12+1)]=4808 Therefore the error is equal to (4808 - 4800) / 4800=0.16% UART Setup and Control For data transfer , the UAR T functio n utilizes a non-return-to-zero, more commonly known as NRZ, format. This is compos ed of one s tart bit, eight or nine data bits and one or tw o s top bits . P arity is supporte d by t he UAR T hardwa re and ca n be se tup t o be eve n, odd or no pari ty. For the m ost common data format, 8 data bits along with no parity and one stop bit, denoted as 8, N, 1, is used as the default setti ng, which is the setting at power -on. The number of data bits and stop bits, along with the parity , are setup by programming the corresponding BNO, PR T, PREN and ST OPS bits in the UCR1 register . The baud rate used to transmit and receive data is setup using the internal 8-bit baud rate generator , while the data is transmitted and received LSB first. Although the transmitter and receiver of the UART are functionally independent, they both use the same data format and baud rate. In all cases stop bits will be used for data transmission. Enabling/Disabling the UART Interface The basic on/of f function of the internal UAR T function is controlled using the UAR TEN bit in the UCR1 register . If the UAR TEN, TXEN and RXEN bits are set, then these two UAR T pins will act as n ormal T X o utput p in a nd R X i nput p in r espectively. I f n o d ata i s b eing t ransmitted o n t he T X pin, then it will default to a logic high value. Clearing the UAR TEN bit will disable the TX and RX pins and then these two pins can be used as an I/O or other pin-shared function al pins by properly configurations. When the UAR T function is disabled, the buf fer will be reset to an empty condition, at the same time discarding any remaining residual data. Disabling the UAR T will also reset the enable control, the error and status flags with bits TXEN, RXEN, TXBRK, RXIF , OERR, FERR, PERR and NF being cleared while bits TIDLE, TXIF and RIDLE will be set. The remaining control bits in the UCR1, UCR2 and BRG registers will remain unaf fected. If the UAR TEN bit in the UCR1 register is cleared while the UAR T is active, then all pending transmissions and receptions will be immediately suspended and the UAR T will be reset to a condition as defined above. If the UAR T is then subsequently re-enabled, it will restart again in the same configuration.

Rev. 1.20 1 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Data, Parity and Stop Bit Selection The format of the data to be transferred is composed of various factors such as data bit length, parity on/off, parity type, address bits and the number of stop bits. T hese factors are determined by the setup of various bits within the UCR1 register . The BNO bit controls the number of data bits which can be set to either 8 or 9. The PR T bit controls the choice if odd or even parity . The PREN bit controls the parity on/of f function. The ST OPS bit decides whether one or two stop bits are to be used. The following table shows various formats for data transmission. The address bit, which is the MSB of the data byte, identifies the frame as an address character or data if the address detect function is enabled. The number of stop bits, which can be either one or two, is independent of the data length. Start Bit Data Bits Address Bits Parity Bit Stop Bit Example of 8-bit Data Formats 1 8 0 0 1 1 7 0 1 1 1 7 1 0 1 Example of 9-bit Data Formats 1 9 0 0 1 1 8 0 1 1 1 8 1 0 1 Transmitter Receiver Data Format The following diagram shows the transmit and receive waveforms for both 8-bit and 9-bit data formats. Bit 0 8-bit Data Format Bit 1 Stop Bit Next Stat Bit Stat Bit Paity Bit Bit 2 Bit 3 Bit 4 Bit Bit Bit 7 Bit 0 9-bit Data Format Bit 1Stat Bit Bit 2 Bit 3 Bit 4 Bit Bit Stop Bit Next Stat Bit Paity Bit Bit 8Bit 7 UART Transmitter Data word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register. W hen B NO b it i s se t, t he wo rd l ength wi ll b e se t t o 9 b its. I n t his c ase t he 9th b it, wh ich is the MSB, needs to be stored in the TX8 bit in the UCR1 register . At the transmitter core lies the T ransmitter Sh ift R egister, m ore c ommonly k nown a s t he T SR, wh ose d ata i s o btained f rom the t ransmit d ata r egister, wh ich i s k nown a s t he T XR_RXR r egister. T he d ata t o b e t ransmitted is loaded into this TXR_RXR register by the application program. The TSR register is not written to with new data unt il the stop bi t from the previous transm ission ha s been sent out. As soon as this stop bit has been transmitted, the TSR can then be loaded with new data from the TXR_RXR register, if it is available. It should be noted that the TSR register , unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. An actual transmission of data will normally be enabled when the TXENn bit is set, but the data will not be transmitted until the TXR_RXR register has been loaded with data and the baud rate generator has defined a shift clock source. However , the transmission can also be initiated by first loading data into the TXR_RXR register , after which the TXEN bit can be set. When a transmission of data begins, the TSR is normally empt y, in which case a transfer to the TXR_RXR register will result in an immediate transfer to the TSR. If during a transmission the TXEN bit is cleared, the transmission will immediately cease and the transmitter will be reset. The TX output pin can then return to the I/O or other pin-shared function by properly configurations.

Rev. 1.20 18 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Transmitting Data When the UAR T is transmitting data, the data is shifted on the TX pin from the shift register , with the least significant bit LSB first. In the transmit mode, the TXR_RXR register forms a buf fer between the intern al bus and the transmitter shift register . It should be noted that if 9-bit data format has been selected, then the MSB will be taken from the TX8 bit in the UCR1 register . The steps to initiate a data transfer can be summarized as follows:

Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits.
Setup the BRG register to select the desired baud rate.
Set the TXEN bit to ensure that the UART transmitter is enabled and the TX pin is used as a UART transmitter pin.
Access the USR register and write the data that is to be transmitted into the TXR_RXR register. Note that this step will clear the TXIF bit. This sequence of events can now be repeated to send additional data. It should be noted that when TXIF=0, data will be inhibited from being written to the TXR_RXR register . Clearing the TXIF flag is always achieved using the following software sequence: 1. A USR register access 2. A TXR_RXR register write execution The read-only TXIF flag is set by the UAR T hardware and if set indicates that the TXR_RXR register is empty and that other data can now be written into the TXR_RXR register without overwriting the previous data. If the TEIE bit is set, then the TX IF flag w ill generate an interrupt. During a data transmission, a write instruction to the TXR_RXR register will place the data into the TXR_RXR registe r, which will be copied to the shift register at the end of the present transmission. When t here i s n o d ata t ransmission i n p rogress, a wr ite i nstruction t o t he T XR_RXR r egister wi ll place the data directly into the shift register , resulting in the commencement of data transmission, and the TXIF bit being immediately set. When a frame transmission is complete, which happens after stop bits are sent or after the break frame, the TIDLE bit will be set. T o clear the TIDLEn bit the following software sequence is used: 1. A USR register access 2. A TXR_RXR register write execution Note that both the TXIF and TIDLE bits are cleared by the same software sequence. Transmitting Break If the TXBRK bit is set, then the break characters will be sent on the next transmission. Break character transmission consists of a start bit, followed by 13xN "0" bits, where N=1, 2, etc. If a break character is to be transmitted, then the TXBRK bit must be first set by the application program and then cleared to generate the stop bits. T ransmitting a break character will not generate a transmit interrupt. Note that a break condition length is at least 13 bits long. If the TXBRK bit is continually kept a t a l ogic hi gh l evel, t hen t he t ransmitter c ircuitry wi ll t ransmit c ontinuous bre ak c haracters. After the application program has cleared the TXBRK bit, the transmitter will finish transmitting the last break character and subsequently send out one or two stop bits. The automatic logic high at the end of the last break character will ensure that the start bit of the next frame is recognized.

Rev. 1.20 18 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP UART Receiver The UART is capable of receiving word lengths of either 8 or 9 bits can be selected by programming the BNO bit in the UCR1 register . When BNO bit is set, the word length will be set to 9 bits. In this c ase t he 9th b it, wh ich i s t he MSB , wi ll b e st ored i n t he R X8 b it i n t he UC R1 r egister. At t he receiver core lies the Receiver Shift Register more commonly known as the RSR. The data which is receive d on the RX external input pin is sent to the data recovery block. The data recovery block operating speed is 16 times that of the baud rate, while the main receiv e serial shifter operates at the baud rate. After the RX pin is sampled for the stop bit, the received data in RSR is transferred to the receive data register, if the register is empty. The data which is received on the external RX input pin is sample d three times by a majority detect circuit to determine the logic level that has been placed onto the RX pin. It should be noted that the RSR register , unlike many other registers, is not directly mapped into the Data Memory area and as such is not available to the application program for direct read/write operations. Receiving Data When the UAR T receiver is receiv ing data, the data is serially shifted in on the external RX input pin to the shift register , with the least significant bit LSB first. The TXR_RXR register is a two byte deep FIFO data buffer, where two bytes can be held in the FIFO while the 3rd byte can continue to be received. Note that the application program must ensure that the data is read from TXR_RXR before the 3rd byte has been completely shifted in, otherwise the 3rd byte will be discarded and an overrun error OERR will be subsequently indicated. The steps to initiate a data transfer can be summarized as follows:

Make the correct selection of the BNO, PRT, PREN and STOPS bits to define the required word length, parity type and number of stop bits.
Setup the BRG register to select the desired baud rate.
Set the RXEN bit to ensure that the UART receiver is enabled and the RX pin is used as a UART receiver pin. At this point the receiver will be enabled which will begin to look for a start bit. When a character is received, the following sequence of events will occur:
The RXIF bit in the USR register will be set when the TXR_RXR register has data available. There will be at most one more character that can be read.
When the contents of the shift register have been transferred to the TXR_RXR register and if the RIE bit is set, then an interrupt will be generated.
If during reception, a frame error, noise error, parity error or an overrun error has been detected, then the error flags can be set. The RXIF bit can be cleared using the following software sequence: 1. A USR register access 2. A TXR_RXR register read execution

Rev. 1.20 10 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Receiving Break Any break character received by the UAR T will be managed as a framing error . The receiver will count and expect a certain number of bit times as specified by the value s programmed into the BNO and ST OPS bits. If the break is much longer than 13 bit times, the reception will be considered as complete a fter t he num ber of bi t t imes spe cified by BNO a nd ST OPS. T he RXIF bi t i s se t, FE RR is set, zeros are loaded into the receive data register , interrupts are generated if appropriate and the R IDLE b it i s se t. A b reak i s r egarded a s a c haracter t hat c ontains o nly z eros wi th t he FE RR flag being set. If a long break signal has been detected, the receiver will regard it as a data frame including a st art bi t, da ta bi ts a nd t he i nvalid st op bi t a nd t he FE RR fla g wi ll be se t. T he re ceiver must wa it f or a v alid st op b it b efore l ooking f or t he n ext st art b it. T he r eceiver wi ll n ot m ake t he assumption that the break condition on the line is the next start bit. The break character will be loaded into the buf fer and no further data will be received until stop bits are received. It should be noted that the RIDLE read only flag will go high when the stop bits have not yet been received. The reception of a break character on the UART registers will result in the following:

The framing error flag, FERR, will be set.
The receive data register, TXR_RXR, will be cleared.
The OERR, NF, PERR, RIDLE or RXIF flags will possibly be set. Idle Status When the receiver is reading data, which means it will be in between the detection of a start bit and the readin g of a stop bit, the receiver status flag in the USR register , otherwise known as the RIDLE flag, will have a zero value. In between the reception of a stop bit and the detection of the next start bit, the RIDLE flag will have a high value, which indicates the receiver is in an idle condition. Receiver Interrupt The re ad onl y re ceive i nterrupt fla g, RXIF , i n t he USR re gister i s se t by a n e dge ge nerated by t he receiver. An i nterrupt i s ge nerated i f RIE =1, whe n a word i s t ransferred from t he Re ceive Shi ft Register, RSR, t o t he Rec eive Da ta Regi ster, T XR_RXR. An ove rrun e rror c an a lso ge nerate a n interrupt if RIE=1. Managing Receiver Errors Several types of reception errors can occur within the UART module, the following section describes the various types and how they are managed by the UART. Overrun Error – OERR The TXR_RXR regist er is composed of a t wo byte deep FIFO data buf fer, where two bytes ca n be held in the FIFO register , while a 3th byte can continue to be received. Before the 3th byte has been enti rely shifted in, the data should be read from the TXR_RXR register . If this is not done, the overrun error flag OERR will be consequently indicated. In the event of an overrun error occurring, the following will happen:
The OERR flag in the USR register will be set.
The TXR_RXR contents will not be lost.
The shift register will be overwritten.
An interrupt will be generated if the RIE bit is set. The OERR flag can be cleared by an access to the USR register followed by a read to the TXR_ RXR register.

Rev. 1.20 10 Deee 0 201 Rev. 1.20 11 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Noise Error – NF Over-sampling i s u sed f or d ata r ecovery t o i dentify v alid i ncoming d ata a nd n oise. I f n oise i s detected within a frame, the following will occur:

The read only noise flag, NF, in the USR register will be set on the rising edge of the RXIF bit.
Data will be transferred from the shift register to the TXR_RXR register.
No interrupt will be generated. However this bit rises at the same time as the RXIF bit which itself generates an interrupt. Note that the NF flag is reset by an USR register read operation followed by a TXR_RXR register read operation. Framing Error – FERR The read only framing error flag, FERR, in the USR register , is set if a zero is detected instead of stop bits. If two stop bits are selected, both stop bits must be high. Otherwise the FERR flag will be set. The FERR flag and the rece ived data will be recorded in the USR and TXR_RXR registers respectively and the FERR flag will be cleared in any reset. Parity Error – PERR The read only parity error flag, PERR, in the USR register , is set if the parity of the received word is incorrect. This error flag is only applicable if the parity function is enabled, PREN=1, and if the parity type, odd or even, is selected. The read only PERR flag and the received data will be recorded in the USR and TXR_RXR registers respectively and the flag will be cleared on any reset. It should be noted that the FERR and PERR flags in the USR register should first be read by the application programs before reading the data word. UART Interrupt Structure Several i ndividual UAR T c onditions c an ge nerate a UAR T i nterrupt. W hen t hese c onditions e xist, a low pulse will be generated to get the attention of the microcontroller . These conditions are a transmitter data register empty , trans mitter idle, receiver data available, receiver overrun, addres s detect and an RX pin wake-up. When any of these conditions are created, if its corresponding interrupt cont rol is enabled and the sta ck is not ful l, the progra m wil l jump to it s corresponding interrupt vector w here it can be s erviced before returning to the main program. Four of thes e conditions h ave t he c orresponding USR r egister fla gs wh ich wi ll g enerate a UAR T i nterrupt i f i ts associated interrupt enable control bit in the UCR2 register is set. The two transmitter interrupt conditions have their own corresponding enable control bits, while the two receiver interrupt conditions have a shared enable control bit. These enable bits can be used to mask out individual UART interrupt sources. The address det ect condit ion, whic h is al so a UAR T i nterrupt source, does not have an associa ted flag, but will generate a UAR T interrupt when an address detect condition occurs if its function is e nabled by se tting t he ADDE N bi t i n t he UCR2 re gister. An RX pi n wa ke-up, whi ch i s a lso a UART interrupt source, does not have an associated flag, but will generate a UAR T interrupt if the microcontroller is woken up from the IDLE0 or SLEEP mode by a falling edge on the RX pin if the WAKE and RIE bits in the UCR2 register are set. Note that in the event of an RX wake-up interrupt occurring, there will be a certain period of delay , commonly known as the System Start-up T ime, for the oscillator to restart and stabilize before the system resumes normal operation.

Rev. 1.20 12 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Note t hat t he USR r egister f lags a re r ead o nly a nd c annot b e c leared o r se t b y t he a pplication program, neither will they be cleared when the program jumps to the corresponding interrupt servicing routine, as is the cas e for some of the other interrupts. The flags will be cleared automatically whe n c ertain a ctions a re t aken by t he UAR T, t he de tails of whi ch a re gi ven i n t he UART regi ster se ction. The overal l UAR T i nterrupt ca n be di sabled or ena bled by t he rel ated interrupt enable control bits in the interrupt control registers of the microcontroller to decide whether the interrupt requested by the UART module is masked out or allowed. USR Registe Tansitte Epty Flag TXIF WAKE Inteupt signal to MCU Tansitte Idle Flag TIDLE Reeive Oveun Flag OERR Reeive Data Availale RXIF RX Pin Wake-up UCR2 Registe OR ADDEN RIE TIIE TEIE TXR_RXR.7 if BNO=0 RX 8 if BNO=1 UCR2 Registe UART Inteupt Request Flag URF URE 0 EMI UART Interrupt Structure Address Detect Mode Setting the Address Detect function enable control bit, ADDEN, in the UCR2 register , enables this special function. If this bit is set to 1, then an additional qualifier will be placed on the generation of a Re ceiver Da ta A vailable i nterrupt, whi ch i s re quested by t he RXIF fl ag. If t he ADDE N bi t is equal to 1, then when the data is available, an interrupt will only be generated, if the highest received bit has a high value. Note that the related interrupt enable control bit and the EMI bit of the microcontroller must also be enabled for correct interrupt generation. The highest address bit is the 9th bit if the bit BNO=1 or the 8th bit if the bit BNO=0. If the highest bit is high, then the received word wi ll be de fined a s a n a ddress ra ther t han da ta. A Da ta A vailable i nterrupt wi ll be ge nerated every tim e the last bit of the receiv ed word is set. If the ADDEN bit is equal to 0, then a Receive Data A vailable interrupt will be generated each time the RXIF flag is set, irrespective of the data last bit status. The address detection and parity functions are mutually exclusive functions. Therefore, if the address detect function is enable d, then to ensure correct operation, the parity function should be disabled by resetting the parity function enable bit PREN to zero. ADDEN Bit 9 if BNO=1 Bit 8 if BNO=0 UART Interrupt Generated 0 √ 1 √ 0 × 1 √ ADDEN Bit Function

Rev. 1.20 12 Deee 0 201 Rev. 1.20 13 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP UART Power Down and Wake-up When the system clock, fSYS, is switched of f, the UAR T will cease to function. If the MCU executes the "HAL T" instruction which results in the system clock being switched of f while a transmission is still in progress, then the transmission will be paused until the UAR T clock source derived from the microcontroller is activated. In a similar way , if the MCU executes the "HAL T" instructure which results in the system clock being switched of f while receiving data, then the reception of data will likewise be paused. When the MCU enters the power down mode, note that the USR, UCR1, UCR2, transmit and recei ve registers, as well as the BRG register will not be af fected. It is recommended to make sure first that the UA RT data transmis sion or reception has been finished before the microcontroller enters the power down mode. The UA RT function contains a receiver RX pin wake-up function, which is enabled or disabled by the W AKE bit in the UCR2 register . If this bit, along with the UAR T enable bit, UAR TEN, the receiver enable bit, RXEN and the receiver interrupt bit, RIE, are all set before the MCU enters the power down mode with the UAR T clock fSYS being switched of f, then a falling edge on the RX pin will initiate a RX pin wake-up UART interrupt. Note that as it takes certain system clock cycles after a wake-up, before normal microcon troller operation resumes, any data received during this time on the RX pin will be ignored. For a UAR T wake-up interrupt to occur , in addition to the bits for the wake-up being set, the global interrupt enable bit, EMI, and the UART interrupt enable bit, URE, must be set. If the EMI and URE bits are not set then only a wake up event will occur and no interrupt will be generated. Note also that as it takes certain system clock cycles after a wake-up before normal microcontroller resumes, the UART interrupt will not be generated until after this time has elapsed.

Rev. 1.20 14 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Over Current/Voltage Protection Function – OCVP The series of devices includes a current/voltage protection function which provides a protection mechanism for applications, for example, over current or over voltage protection, etc. The current on the OCVP AI0, OCVP AI1 and OCVP AI2 pins are converted to a releva nt voltage level according to the current value using the OCVP operational amplifier . It is then compared with a reference voltage generated by an 8-bit D/A converter . The voltage on the OCVPCI pin is compared with a reference voltage generated by the 8-bit D/A converter . When the OCVPF flag changes from 0 to 1 and if the corresponding interrupt control is enabled, an OCVP interrupt will be generated to indicate a specific current or voltage condition has occurred. OCVP Operation The OCVP circuit is used to prevent the input current or voltage from being in an unexpected level range. The current on the OCVP AI0, OCVP AI1 or OCVP AI2 pin is converted to a voltage and then amplified by the OCVP operational amplifier with a programmable gain from 1 to 65 selected by the OCVPG2~OCVPG0 bits in the OCVPC2 register . This is known as the Programmable Gain Amplifier or PGA. This PGA can also be configured to operate in the non-inverting, inverting or input of fset cancellation mode determined by the OCVPSW7~OCVPSW0 bits in the OCVPC0 register. After the current is converted and amplified to a specific voltage level, it will be compared with a reference voltage provided by an 8-bit D/A converter . The voltag e on the OCVPCI pin is also compared with a reference provided by the 8-bit D/A converter. 8-bit D/AOCVPDA[7:0] Debounce To A/D internal input 6.6KΩ or 13.2KΩ OCVPO OCVPG[2:0] fDEB=fSYS OCVPSWn (n=0~6) OPA VDD OCVPVR OCVPVRS OCVPSPOL OCVPCOUT OCVPDEB[2:0] OCVPAO OCVPINTCMP OCVPAI1 OCVPCPS OCVPEN OCVPCI OCVPEN OCVPSW7 OCVPG2XEN OCVPAI2 S6 OCVPAI0 S1 OCVPCHY OCVPEN OCVPCOUT OCVP Block Diagram To compare the OCVP AO output signal or the OCVPCI input signal with the D/A converter output voltage is selected using the OCVPCPS bit in the OCVPC1 register . The 8-bit D/A converter power can be supplied by the external power pin, VDD or OCVPVR, selected by the OCVPVRS bit in the OCVPC1 register . The comparator output, OCVPCOUT , will first be filtered with a certain de- bounce time period selected by the OCVPDEB2~OCVPDEB0 bits in the OCVPC2 register . Then a filtered OCVP digital comparator output, OCVPO, is obtained to indicate whether a user -defined current or voltage condition occurs or not. If the the OCVPS POL bit is cleared to 0 and the comparator inputs force the OCVPO bit to change from 0 t o 1, or i f t he OCVPSPOL bi t i s se t t o 1 a nd t he c omparator i nputs forc e t he OCVPO bi t changes from 1 to 0, the corresponding interrupt will be generated if the relevant interrupt control bit is enabled. It is important to note that, only an OCVPINT rising edge can trigger an OCVP interrupt request, a s shown i n t he fol lowing di agram, so t he OCVPSPOL bi t m ust be properl y c onfigured according to user’s application requirements.

Rev. 1.20 14 Deee 0 201 Rev. 1.20 1 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Note t hat t he d ebounce c lock, fDEB, c omes fr om t he syst em c lock, fSYS. T he o perational a mplifier output voltage also can be read out by the A/D converter through an A/D internal input channel. The DAC output voltage is controlled by the OCVPDA register and the DAC output is defined as below: DAC VOUT=(DAC reference voltage/256)×D[7:0] OCVP Control Registers Overall operation of the OCVP function is controlled using several registers. One register is used to provide the reference voltages for the OCVP circuit. There are two registers used to cancel out the operational amplifi er and comparato r input of fset. The remaining four registers are control registers which control the OCVP functi on, D/A converter reference voltage select, switches on/of f control, PGA ga in se lect, c omparator non-i nverting i nput se lect, c omparator de -bounce t ime, c omparator hysteresis function and comparator output polarity control, etc. Each OCVP related input or output signal has a corresponding control bit in the OCVPC3 register . For a more detailed description regarding the input of fset voltage cancellation procedures, refer to the corresponding input of fset cancellation sections. Register Name Bit 7 6 5 4 3 2 1 0 OCVPC0 OCVPSW7 OCVPSW OCVPSW OCVPSW4 OCVPSW3 OCVPSW2 OCVPSW1 OCVPSW0 OCVPC1 OCVPEN OCVPCHY OCVPO OCVPSPOL — — OCVPCPS OCVPVRS OCVPC2 — OCVPG2XEN OCVPG2 OCVPG1 OCVPG0 OCVPDEB2 OCVPDEB1 OCVPDEB0 OCVPC3 OCVPCIEN OCVPAI2EN OCVPAI1EN OCVPAI0EN — — OCVPOPEN OCVPCPEN OCVPDA D7 D D D4 D3 D2 D1 D0 OCVPOCAL OCVPOOFM OCVPORSP OCVPOOF OCVPOOF4 OCVPOOF3 OCVPOOF2 OCVPOOF1 OCVPOOF0 OCVPCCAL OCVPCOUT OCVPCOFM OCVPCRSP OCVPCOF4 OCVPCOF3 OCVPCOF2 OCVPCOF1 OCVPCOF0 OCVP Registers List OCVPC0 Register Bit 7 6 5 4 3 2 1 0 Nae OCVPSW7 OCVPSW OCVPSW OCVPSW4 OCVPSW3 OCVPSW2 OCVPSW1 OCVPSW0 R/W R/W R/W R/W R R/W R/W R/W R/W POR 1 1 0 0 1 0 0 0 Bit 7 OCVPSW7: OCVP switch S7 on/off control 0: Off 1: On Bit 6 OCVPSW6: OCVP switch S6 on/off control 0: Off 1: On Bit 5 OCVPSW5: OCVP switch S5 on/off control 0: Off 1: On Bit 4 OCVPSW4: OCVP switch S4 on/off control 0: Off 1: On Bit 3 OCVPSW3: OCVP switch S3 on/off control 0: Off 1: On Bit 2 OCVPSW2: OCVP switch S2 on/off control 0: Off 1: On

Rev. 1.20 1 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 1 OCVPSW1: OCVP switch S1 on/off control 0: Off 1: On Bit 0 OCVPSW0: OCVP switch S0 on/off control 0: Off 1: On OCVPC1 Register Bit 7 6 5 4 3 2 1 0 Nae OCVPEN OCVPCHY OCVPO OCVPSPOL — — OCVPCPS OCVPVRS R/W R/W R/W R R/W — — R/W R/W POR 0 0 0 0 — — 0 0 Bit 7 OCVPEN: OCVP function enable control 0: Disable 1: Enable When thi s bi t is cleared to 0, the overall OCVP operation will be disabled and the comparator output, OCVPCOUT, will be equal to 0. Bit 6 OCVPCHY: OCVP Comparator Hysteresis function enable control 0: Disable 1: Enable Bit 5 OCVPO: OCVP Comparator debounced output This bit is the debounced version of the OCVPCOUT bit Bit 4 OCVPSPOL: OCVPO polarity control 0: Not inverted 1: Inverted Bit 3~2 Unimplemented, read as "0" Bit 1 OCVPCPS: OCVP Comparator non-inverting input selection 0: From OCVPAO – OPA output 1: From OCVPCI pin Bit 0 OCVPVRS: OCVP D/A converter reference voltage selection 0: From VDD pin 1: From OCVPVR pin OCVPC2 Register Bit 7 6 5 4 3 2 1 0 Nae — OCVPG2XEN OCVPG2 OCVPG1 OCVPG0 OCVPDEB2 OCVPDEB1 OCVPDEB0 R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 OCVPG2XEN: OCVP PGA R2/R1 ratio doubling enable control 0: Disable (R1=13.2kΩ) 1: Enable (R1=6.6kΩ) When this bit is set to 1, the R2/R1 ratio selected by the OCVPG2~OCVPG0 bits will be doubled.

Rev. 1.20 1 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 5~3 OCVPG2~OCVPG0: OCVP PGA R2/R1 ratio selection 000: R2/R1=1 001: R2/R1=4 010: R2/R1=6 011: R2/R1=10 100: R2/R1=15 101: R2/R1=25 110: R2/R1=40 111: R2/R1=65 The internal res istors, R1 and R2, should be used when the gain is determined by these bits. This means the S4 or S5 switch together with the S7 switch should be on. Otherwise, the gai n accuracy will not be guaranteed. When the OCVPG2XEN bi t is set to 1 to enable the R2/R1 ratio doubling function, the above R2/R1 values will be doubled. The calculating formula of the PGA gain for the inverting and non-inverting mode is described in the "Input V oltage Range" section. Bit 2~0 OCVPDEB2~OCVPDEB0: OCVP Comparator output debounce time selection 000: Bypass, no debounce 001: (1~2) × tDEB 010: (3~4) × tDEB 011: (7~8) × tDEB 111: (127~128) × tDEB Note: tDEB=1/fDEB, fDEB=fSYS OCVPC3 Register Bit 7 6 5 4 3 2 1 0 Nae OCVPCIEN OCVPAI2EN OCVPAI1EN OCVPAI0EN — — OCVPOPEN OCVPCPEN R/W R/W R/W R/W R/W — — R/W R/W POR 0 0 0 0 — — 0 0 Bit 7 OCVPCIEN: OCVPCI input signal control 0: Disable 1: Enable When the OCVPEN bit is set to 0 to disable the OCVP , the OCVPCI input will be forced to disable. Bit 6 OCVPAI2EN: OCVPAI2 input signal control 0: Disable 1: Enable When the OCVPEN bit is set to 0 to disable the OCVP , the OCVP AI2 input will be forced to disable. Bit 5 OCVPAI1EN: OCVPAI1 input signal control 0: Disable 1: Enable When the OCVPEN bit is set to 0 to disable the OCVP , the OCVP AI1 input will be forced to disable. Bit 4 OCVPAI0EN: OCVPAI0 input signal control 0: Disable 1: Enable When the OCVPEN bit is set to 0 to disable the OCVP , the OCVP AI0 input will be forced to disable. Bit 3~2 Unimplemented, read as "0"

Rev. 1.20 18 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 1 OCVPOPEN: OCVPAO output signal control 0: Disable 1: Enable When the OCVPEN bit is set to 0 to disable the OCVP , the OCVP OP A output will be forced to disable. Bit 0 OCVPCPEN: OCVPCOUT output signal control 0: Disable 1: Enable When the OCVPEN bit is set to 0 to disable the OCVP , the OCVP comparator output will be forced to disable. OCVPDA Register Bit 7 6 5 4 3 2 1 0 Nae D7 D D D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 OCVP D/A Converter Data register bit 7 ~ bit 0 OCVP D/A Converter Output=(DAC reference voltage/256)×D[7:0] OCVPOCAL Register Bit 7 6 5 4 3 2 1 0 Nae OCVPOOFM OCVPORSP OCVPOOF OCVPOOF4 OCVPOOF3 OCVPOOF2 OCVPOOF1 OCVPOOF0 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 1 0 0 0 0 0 Bit 7 OCVPOOFM: OCVP Operational Amplifier operating mode selection 0: Normal operating mode 1: Offset cancellation mode This bit is used to select the OCVP Operational Amplifier operating mode. T o select the Operational Amplifier input of fset cancellation mode, the OCVPSW bit field must first be set to 28H and then the OCVPOOFM bit must be set to 1 followed by the OCVPCOFM bit being cleared to 0. Refer to the "Operational Amplifier Input Of fset Cancellation" section for the detailed offset cancellation procedures. Bit 6 OCVPORSP: OCVP Operational Amplifier input offset cancellation reference input selection 0: Operational Amplifier inverting input 1: Operational Amplifier non-inverting input Bit 5~0 OCVPOOF5~OCVPOOF0: OCVP Operational Amplifier input offset cancellation value This 6-bit field is used to perform the Operational Amplifier input of fset cancellation operation a nd t he v alue a fter t he i nput o ffset c ancellation c an b e r estored i nto t his field. More de tailed i nformation i s de scribed i n t he "Ope rational Am plifier In put Offset Cancellation" section.

Rev. 1.20 18 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP OCVPCCAL Register Bit 7 6 5 4 3 2 1 0 Nae OCVPCOUT OCVPCOFM OCVPCRSP OCVPCOF4 OCVPCOF3 OCVPCOF2 OCVPCOF1 OCVPCOF0 R/W R R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 1 0 0 0 0 Bit 7 OCVPCOUT: OCVP Comparator output 0: Non-inverting input voltage < D/A converter output voltage 1: Non-inverting input voltage > D/A converter output voltage This bit is used to indicate whether the non-onverting input voltage is greater than the D/A converter output voltage. If the OCVPCOUT bit is set to 1, it means that the non- onverting i nput vol tage i s grea ter t han t he D/ A c onverter out put vol tage. Ot herwise, the non-inverting input voltage is less than the D/A converter output voltage. This bit value can be output on the OCVPCOUT pin. Bit 6 OCVPCOFM: OCVP Comparator operating mode selection 0: Normal operating mode 1: Offset cancellation mode This bit is used to select the OCVP comparator operating mode. T o select the comparator input of fset cancellation mode, the OCVPSW bit field must first be set to 28H and then the OCVPCOFM bit must be set to 1 followed by the OCVPOOFM bit being cle ared to 0. Refer to the "Comparator Input Of fset Cancellation" section for the detailed offset cancellation procedures. Bit 5 OCVPCRSP: OCVP Comparator input offset cancellation reference input selection 0: Comparator inverting input 1: Comparator non-inverting input Bit 4~0 OCVPCOF4~OCVPCOF0: OCVP Comparator input offset cancellation value This 5-bit field is used to perform the comparator input of fset cancellation operation and the value afte r the input of fset cancellation can be restored into this field. Refer to the "Comparator Input Offset Cancellation" section for more detailed information. Input Voltage Range Together with dif ferent PGA operating modes, the input voltage can be positive or negative to provide di verse a pplications for t he devi ce. T he PGA out put for t he posi tive or nega tive i nput voltage i s r espectively c alculated b ased o n d ifferent f ormulas a nd d escribed b y t he f ollowing examples.

For VIN > 0, the PGA operates in the non-inverting mode and the PGA output is obtained using the formula below: IN OUT V )R R(1V x 
When the PGA operates in the non-inverting mode, a unity gain buffer is provided. If the OCVPSW6~OCVPSW4 bits are set to "000", the PGA gain will be equal to 1 and the PGA will act as a unity gain buffer. The switches, S6, S5 and S4, will be switched off internally and the PGA output voltage is equal to VIN. INOUT V V
If S3 and S4 are switched on, the input node is OCVPAI0. For 0 > VIN > -0.4, the PGA operates in the inverting mode and the PGA output is obtained using the formula below. Note that if the input voltage, VIN, is negative, it can not be lower than (-0.4V) which will result in current leakage. IN OUT VR RV x 

Rev. 1.20 170 Deee 0 201 Rev. 1.20 171 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Input Offset Cancellation To operate in the input of fset cancellation mode for the OCVP circuit, the OCVPSW7~OCVPSW0 bits should first be set to "28H". For operational amplifier and compar ator input of fset cancellation, the procedures are similar except for setting the respective control bits. Operational Amplifier Input Offset Cancellation Setp 1. Set OCVPSW [7:0]=28H (S3 and S5 are ON, other switches are OFF). Set OCVPOOFM=1, OCVPCOFM=0, OCVPORSP=1, OCVPCPS=0 Now the OCVP is operating in the Operational Amplifier input offset cancellation mode. Setp 2. Set OCVPDA [7:0]=40H Setp 3. Set OCVPOOF [5:0]=000000 and read the OCVPCOUT bit Setp 4. Increase the OCVPOOF [5:0] value by 1 and then read the OCVPCOUT bit. If t he OCVPCOUT bi t st ate i s not c hanged, t hen re peat Ste p 4 unt il t he OCVPCOUT bi t state is changed. If the OCVPCOUT bit state is changed, then record the current OCVPOOF field value as VOOS1 and then go to Step 5. Setp 5. Set OCVPOOF [5:0]=111111 and read the OCVPCOUT bit Setp 6. Decrease the OCVPOOF [5:0] value by 1 and then read the OCVPCOUT bit. If t he OCVPCOUT bi t st ate i s not c hanged, t hen re peat Ste p 6 unt il t he OCVPCOUT bi t state is changed. If the OCVPCOUT bit state is changed, then record the current OCVPOOF field value as VOOS2 and then go to Step 7. Setp 7. Restore the operational amplifier input of fset cancellation value VOOS into the OCVPOOF [5:0] bit field. The of fset cancellatio n procedure is now finished with the VOOS value as the following formula shown. VOOS2VOOS1VOOS 

Rev. 1.20 170 Deee 0 201 Rev. 1.20 171 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Comparator Input Offset Cancellation Before the of fset cancellationexecuted, the hysteresis voltage shoule be zero by setting the OCVPCHY bit to 0. Setp 1. Set OCVPSW [7:0]=28H (S3 and S5 are ON, other switches are OFF). Set OCVPCOFM=1, OCVPOOFM=0, OCVPCRSP=0 Now the OCVP is operating in the Comparator input offset cancellation mode. Setp 2. Set OCVPDA [7:0]=40H Setp 3. Set OCVPCOF [4:0]=00000 and read the OCVPCOUT bit Setp 4. Increase the OCVPCOF [4:0] value by 1 and then read the OCVPCOUT bit. If t he OCVPCOUT bi t st ate i s not c hanged, t hen re peat Ste p 4 unt il t he OCVPCOUT bi t state is changed. If t he OC VPCOUT b it st ate i s c hanged, t hen r ecord t he c urrent OC VPCOF fie ld v alue a s VCOS1 and then go to Step 5. Setp 5. Set OCVPCOF [4:0]=11111 and read the OCVPCOUT bit Setp 6. Decrease the OCVPCOF [4:0] value by 1 and then read the OCVPCOUT bit. If t he OCVPCOUT bi t st ate i s not c hanged, t hen re peat Ste p 6 unt il t he OCVPCOUT bi t state is changed. If t he OC VPCOUT b it st ate i s c hanged, t hen r ecord t he c urrent OC VPCOF fie ld v alue a s VCOS2 and then go to Step 7. Setp 7. Restore t he com parator i nput of fset ca ncellation val ue VCOS i nto t he OCVPCOF [4:0] bit field. The of fset cancellation procedure is now finished with the VCO S value as the following formula shown. VCOS2VCOS1VCOS  OCVP Interrupt The OCVP po ssesses i ts own i nterrupt fun ction. W hen t he OC VP c omparator de bounced ou tput changes st ate, i ts re levant i nterrupt fl ag wi ll be se t, a nd i f t he c orresponding i nterrupt e nable bi t is set, then a jump to its relevant interrupt vector will be executed. If the microcontroller is in the SLEEP or IDLE Mode and the OCVP function is enabled, then if the external input lines cause the OCVP Comparato r debounced output to change state, the resulting generated interrupt flag will also generate a wa ke-up. I f i t i s r equired t o d isable a wa ke-up f rom o ccurring, t hen t he i nterrupt fla g should be first set high before entering the SLEEP or IDLE Mode. Programming Considerations If the OCVP is enabled, it will remain active when the microcontroller enters the SLEEP or IDLE Mode, h owever a s i t wi ll c onsume a c ertain a mount o f p ower, t he u ser m ay wi sh t o c onsider disabling it before the SLEEP or IDLE Mode is entered.

Rev. 1.20 172 Deee 0 201 Rev. 1.20 173 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Software Controlled LCD Driver The devices have the capability of driving external LCD panels. The common pins, SCOM0~SCOM3, and segment pins, SSEG0~SSEGm, where m is dependent upon which device is selected, for LCD driving are pin-shared with certain pins on the I/O ports. The LCD signals (COM and SEG) are generated using the application program. LCD Operation An external LCD panel can be driven using the devices by configuring the I/O pins as common pins and segment pins. The LCD driver function is controlled using the LCD control registers which in addition to controlling the overall on/of f function also controls the R-type bias current on the SCOMn and SSEGm pins. This enables the LCD COM driver to generate the necessary voltage levels, VSS, (1/3)VDD, (2/3)VDD and VDD, for LCD 1/3 bias operation. The LCDEN bit in the SLCDC0 register is the overall master control for the LCD driver . This bit is used in conjunction with the corresponding pin-s hared function selection bits, COMnEN and SEGmEN, for the SCOMn and SSEGm pins to selecte which I/O pins are used for LCD driving. Note that the corresponding Port Control register does not need to first setup the pins as outputs to enable the LCD driver operation. VDD (2/3) VDD (1/3) VDD VDD LCD Voltage Selet Ciuit LCD COM/SEG Analog Swith LCDEN ISEL[1:0] SEGEN & COMnEN pin-shaed seletion FRAME SCOM0 SCOM3 SSEG0 SSEG =1 fo BS87B12A-3 =19 fo BS87C1A-3 =3 fo BS87D20A-3 Software Controlled LCD Driver Structure Device SCOM Pins SSEG Pins BS87B12A-3 SCOM0~SCOM3 SSEG0~SSEG1 BS87C1A-3 SCOM0~SCOM3 SSEG0~SSEG19 BS87D20A-3 SCOM0~SCOM3 SSEG0~SSEG3 Software Controlled LCD Driver Pins Summary

Frame 0 To select Frame 0, clear the FRAME bit in the SLCDC 0 register to 0. In frame 0, the COM signal output can have a value of VDD or a VBIAS value of (1/3)×VDD. The SEG signal output can have a value of VSS or a VBIAS value of (2/3)×VDD.
Frame 1 To select Frame 1, set the FRAME bit in the SLCDC0 register to 1. In frame 1, the COM signal output can have a value of VSS or a VBIAS value of (2/3)×VDD. The SEG signal output can have a value of VDD or a VBIAS value of (1/3)×VDD. The COMn wa veform i s c ontrolled by t he a pplication program usi ng t he FRAME bi t i n t he SLCDC0 register and the corresponding pin-shared I/O data bit for the respective SCOM pin to determine whe ther t he COMn out put ha s a va lue of VDD, VSS or VBIAS. T he SE Gm wa veform i s controlled in a similar way using the FRAME bit and the corresponding pin-shared I/O data bit for the respective SSEG pin to determine whether the SEGm output has a value of VDD, VSS or VBIAS. The accompanyin g waveform diagram shows a typical 1/3 bias LCD waveform generated using the application program together with the LCD voltage select circuit. Note that the depiction of a "1" in the diagram illustrates an illuminated LCD pixel. The COM and SEG signals polarity generated on pins SCOMn and SSEGm, whether "0" or "1", are generated using the corresponding pin-shared I/O data register bit. COM0 VDD (2/3) VDD (1/3) VDD VSS VDD (2/3) VDD (1/3) VDD VSS COM1 COM2 VDD (2/3) VDD (1/3) VDD VSS VDD (2/3) VDD (1/3) VDD VSS COM3 VDD (2/3) VDD (1/3) VDD VSS SEG0 VDD (2/3) VDD (1/3) VDD VSS SEG1 Fae 0 Fae 1 Fae 0 Fae 1 Fae 0 Fae 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Note: The logical value shown in the above diagram is the corresponding pin-shared I/O data bit value. 1/3 Bias LCD Waveform – 4-COM & 2-SEG Application

Rev. 1.20 174 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LCD Control Registers The LCD COM and SEG driver enables a range of selections to be provided to suit the requirement of the LCD panel which are being used. The bias current choice is implemented using the ISEL1 and ISE L0 bi ts i n t he SL CDC0 re gister. Al l COM a nd SE G pi ns a re pi n-shared wi th I/ O pi ns a nd selected as SCOMn and SSEGm pins using the corresponding pin-shared function selection bits. Register Name Bit 7 6 5 4 3 2 1 0 SLCDC0 FRAME ISEL1 ISEL0 LCDEN COM3EN COM2EN COM1EN COM0EN SLCDC1 SEG7EN SEGEN SEGEN SEG4EN SEG3EN SEG2EN SEG1EN SEG0EN SLCDC2 SEG1EN SEG14EN SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN SEG8EN Software Controlled LCD Registers List – BS87B12A-3 Register Name Bit 7 6 5 4 3 2 1 0 SLCDC0 FRAME ISEL1 ISEL0 LCDEN COM3EN COM2EN COM1EN COM0EN SLCDC1 SEG7EN SEGEN SEGEN SEG4EN SEG3EN SEG2EN SEG1EN SEG0EN SLCDC2 SEG1EN SEG14EN SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN SEG8EN SLCDC3 — — — — SEG19EN SEG18EN SEG17EN SEG1EN Software Controlled LCD Registers List – BS87C16A-3 Register Name Bit 7 6 5 4 3 2 1 0 SLCDC0 FRAME ISEL1 ISEL0 LCDEN COM3EN COM2EN COM1EN COM0EN SLCDC1 SEG7EN SEGEN SEGEN SEG4EN SEG3EN SEG2EN SEG1EN SEG0EN SLCDC2 SEG1EN SEG14EN SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN SEG8EN SLCDC3 SEG23EN SEG22EN SEG21EN SEG20EN SEG19EN SEG18EN SEG17EN SEG1EN SLCDC4 SEG31EN SEG30EN SEG29EN SEG28EN SEG27EN SEG2EN SEG2EN SEG24EN SLCDC — — — — SEG3EN SEG34EN SEG33EN SEG32EN Software Controlled LCD Registers List – BS87D20A-3 SLCDC0 Register Bit 7 6 5 4 3 2 1 0 Nae FRAME ISEL1 ISEL0 LCDEN COM3EN COM2EN COM1EN COM0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 FRAME: Frame 0 or Frame 1 outptu selection 0: Frame 0 1: Frame 1 Bit 6~5 ISEL1~ISEL0: SCOM/SSEG typical bias current selection (@VDD=5V) 00: 8.3μA 01: 16.7μA 10: 50μA 11: 100μA Bit 4 LCDEN: Software controlled LCD Driver enable control 0: Disable 1: Enable The SCOMn a nd SSE Gm l ines c an be e nabled usi ng t he c orresponding pi n-shared selection bits , CO MnEN and S EGmEN, if the LCD EN bit is s et to 1. When the LCDEN bit is clea red to 0, then the SCOMn and SSEGm outputs will be fixed at a VSS level. Not e t hat t he c orresponding pi n-shared se lection bi ts shoul d first be prope rly configured before the SCOMn or SSEGm function is enabled.

Rev. 1.20 174 Deee 0 201 Rev. 1.20 17 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 3 COM3EN: SCOM3 pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SCOM3 Bit 2 COM2EN: SCOM2 pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SCOM2 Bit 1 COM1EN: SCOM1 pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SCOM1 Bit 0 COM0EN: SCOM0 pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SCOM0 SLCDC1 Register Bit 7 6 5 4 3 2 1 0 Nae SEG7EN SEGEN SEGEN SEG4EN SEG3EN SEG2EN SEG1EN SEG0EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 SEG7EN~SEG0EN: SSEG7~SSEG0 individual pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SSEG7~SSEG0 SLCDC2 Register Bit 7 6 5 4 3 2 1 0 Nae SEG1EN SEG14EN SEG13EN SEG12EN SEG11EN SEG10EN SEG9EN SEG8EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 SEG15EN~SEG8EN: SSEG15~SSEG8 individual pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SSEG15~SSEG8 SLCDC3 Register – BS87C16A-3 Bit 7 6 5 4 3 2 1 0 Nae — — — — SEG19EN SEG18EN SEG17EN SEG1EN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~0 SEG19EN~SEG16EN: SSEG19~SSEG16 individual pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SSEG19~SSEG16 SLCDC3 Register – BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae SEG23EN SEG22EN SEG21EN SEG20EN SEG19EN SEG18EN SEG17EN SEG1EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 SEG23EN~SEG16EN: SSEG23~SSEG16 individual pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SSEG23~SSEG16

Rev. 1.20 17 Deee 0 201 Rev. 1.20 177 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SLCDC4 Register – BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae SEG31EN SEG30EN SEG29EN SEG28EN SEG27EN SEG2EN SEG2EN SEG24EN R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7~0 SEG31EN~SEG24EN: SSEG31~SSEG24 individual pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SSEG31~SSEG24 SLCDC5 Register – BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae — — — — SEG3EN SEG34EN SEG33EN SEG32EN R/W — — — — R/W R/W R/W R/W POR — — — — 0 0 0 0 Bit 7~4 Unimplemented, read as "0" Bit 3~0 SEG35EN~SEG32EN: SSEG35~SSEG32 individual pin function control 0: Disable – I/O or other pin-shared functions 1: Enable – SSEG35~SSEG32

Rev. 1.20 17 Deee 0 201 Rev. 1.20 177 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Low Voltage Detector – LVD Each device has a Low V oltage Detector function, also known as L VD. This enabled the device to monitor the power supply voltage, VDD, and provide a warning signal should it fall below a certain level. This function may be especially useful in battery applications where the supply voltage will gradually reduce as the battery ages, as it allows an early warning battery low signal to be generated. The Low V oltage Detector also has the capability of generating an interrupt signal. LVD Register The Low Voltage Detector function is controlled using a single register with the name L VDC. Three bits in this register, VL VD2~VLVD0, are used to select one of five fixed voltages below which a low voltage condition will be determined. A low voltage condition is indicated when the L VDO bit is set. If the L VDO bit is low , this indicates that the VDD voltage is above the preset low voltage value. The L VDEN bit is used to control the overall on/of f function of the low voltage detector . Setting the bit high will enabl e the low voltage detector . Clearing the bit to zero will switch of f the internal low voltage detector circuits. As the low voltage detector will consume a certain amount of power, it may be desirable to switch of f the circuit when not in use, an important consideration in power sensitive battery powered applications. LVDC Register Bit 7 6 5 4 3 2 1 0 Nae — — LVDO LVDEN VBGEN VLVD2 VLVD1 VLVD0 R/W — — R R/W R/W R/W R/W R/W POR — — 0 0 0 0 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 LVDO: LVD output flag 0: No Low V oltage Detected 1: Low V oltage Detected Bit 4 LVDEN: Low V oltage Detector Enable control 0: Disable 1: Enable Bit 3 VBGEN: Bandgap V oltage Output Enable control 0: Disable 1: Enable Bit 2~0 VLVD2~VLVD0: LVD V oltage selection 000: 2.0V 001: 2.2V 010: 2.4V 011: 2.7V 100: 3.0V 101: 3.3V 110: 3.6V 111: 4.0V Since the VLVR is fixed at 2.55V, the VLVD should be set to 2.7V~4.0V.

Rev. 1.20 178 Deee 0 201 Rev. 1.20 179 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LVD Operation The Low V oltage Detector function operates by comparing the power supply voltage, VDD, with a pre-specified volta ge level stored in the L VDC register . This has a range of between 2.7V and 4.0V . When the power supply voltage, VDD, falls below this pre-determined value, the L VDO bit will be set high indicating a low power supply voltage condition. The Low V oltage Detector function is supplied by a reference voltage which will be automatically enabled. When the device is powered down the low voltage detector will remain active if the L VDEN bit is high. After enabling the Low Voltage Detector , a time delay tLVDS should be allowed for the circuitry to stabilise before reading the LVDO bit. Note also that as the VDD voltage may rise and fall rather slowly , at the voltage nears that of VLVD, there may be multiple bit LVDO transitions. VDD LVDEN LVDO VLVD tLVDS LVD Operation The Low V oltage Detector also has its own interrupt which is contained within one of the Multi- function interrupts, providing an alternative means of low voltage detection, in addition to polling the L VDO bit. The interrupt will only be generated after a delay of tLVD after the L VDO bit has been set high by a low voltage condition. When the device is powered down the Low V oltage Detector will rema in active if the L VDEN bit is high. In this case, the L VF interrupt request flag will be set, causing an interru pt to be generated if VDD falls below the preset L VD voltage. This will cause the device to wake-up from the SLEEP or IDLE Mode, however if the Low V oltage Detector wake up function is not required then the LVF flag should be first set high before the device enters the SLEEP or IDLE Mode.

Rev. 1.20 178 Deee 0 201 Rev. 1.20 179 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Interrupts Interrupts are an important part of any microcontroller s ystem. When an external event or an internal function such as a T imer Module or an A/D converter requires microcontroller attention, their corresponding interrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. These devices contain several external interrupt and internal interrupts functions. The external interrupts are generated by the action of the external INT0 ~ INT3 pins, while the internal interrupts are generated by various internal functions such as the TMs, T ime Base, LVD, EEPROM, SIM, UART and the A/D converter, etc. Interrupt Registers Overall interrupt control, w hich bas ically means the s etting of reques t flags w hen certain microcontroller conditions occur and the setting of interrupt enable bits by the application program, is control led by a series of registers, located in the Special Purpose Data Memory , as shown in the accompanying table. The number of registers depends upon the device chosen but fall into three categories. T he first i s t he INT C0~INTC3 re gisters whi ch se tup t he pri mary i nterrupts, t he se cond is the MFI registers which setup the Multi-function interrupts. Finally there is an INTEG register to setup the external interrupt trigger edge type. Each register contains a number of enable bits to enable or disable individual interrupts as well as i nterrupt fla gs t o i ndicate t he p resence o f a n i nterrupt r equest. T he n aming c onvention o f t hese follows a specific pattern. First is listed an abbreviated interrupt type, then the (optional) number of that interrupt followed by either an "E" for enable/disable bit or "F" for request flag. Function Enable Bit Request Flag Notes Gloal EMI — — INT Pin INTE INTF — Touh Key Module TKME TKMF — OCVP OCVPE OCVPF — Multi-funtion MFE MFF Fo BS87C1A-3 & BS87D20A-3 only SIM SIME SIMF — EEPROM wite opeation DEE DEF — UART URnE URnF — LVD LVE LVF — A/D Convete ADE ADF — Tie Base TBnE TBnF n=0 ~ 1 PTM PTMnPE PTMnPF n=0 fo BS87B12A-3 n=0 ~ 1 fo BS87C1A-3 & BS87D20A-3PTMnAE PTMnAF CTM CTMnPE CTMnPF n=0 fo BS87B12A-3 & BS87C1A-3 n=0 ~ 1 fo BS87D20A-3CTMnAE CTMnAF Interrupt Register Bit Naming Conventions Register Name Bit 7 6 5 4 3 2 1 0 INTC0 — OCVPF TKMF INTF OCVPE TKME INTE EMI INTC1 PTM0AF PTM0PF CTM0AF CTM0PF PTM0AE PTM0PE CTM0AE CTM0PE INTC2 URF DEF SIMF — URE DEE SIME — INTC3 TB1F TB0F ADF LVF TB1E TB0E ADE LVE Interrupt Registers List – BS87B12A-3

Rev. 1.20 180 Deee 0 201 Rev. 1.20 181 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Register Name Bit 7 6 5 4 3 2 1 0 INTC0 — OCVPF TKMF INTF OCVPE TKME INTE EMI INTC1 PTM0AF PTM0PF CTM0AF CTM0PF PTM0AE PTM0PE CTM0AE CTM0PE INTC2 URF DEF SIMF MFF URE DEE SIME MFE INTC3 TB1F TB0F ADF LVF TB1E TB0E ADE LVE MFI — — PTM1AF PTM1PF — — PTM1AE PTM1PE Interrupt Registers List – BS87C16A-3 Register Name Bit 7 6 5 4 3 2 1 0 INTC0 — OCVPF TKMF INTF OCVPE TKME INTE EMI INTC1 PTM0AF PTM0PF CTM0AF CTM0PF PTM0AE PTM0PE CTM0AE CTM0PE INTC2 URF DEF SIMF MFF URE DEE SIME MFE INTC3 TB1F TB0F ADF LVF TB1E TB0E ADE LVE MFI CTM1AF CTM1PF PTM1AF PTM1PF CTM1AE CTM1PE PTM1AE PTM1PE Interrupt Registers List – BS87D20A-3 INTEG Register Bit 7 6 5 4 3 2 1 0 Bit 7~2 Unimplemented, read as "0" Bit 1~0 INTS1~INTS0: Interrupt edge control for INT pin 00: Disable 01: Rising edge 10: Falling edge 11: Rising and falling edges INTC0 Register Bit 7 6 5 4 3 2 1 0 Nae — OCVPF TKMF INTF OCVPE TKME INTE EMI R/W — R/W R/W R/W R/W R/W R/W R/W POR — 0 0 0 0 0 0 0 Bit 7 Unimplemented, read as "0" Bit 6 OCVPF: OCVP interrupt request flag 0: no request 1: interrupt request Bit 5 TKMF: T ouch key module interrupt request flag 0: No request 1: Interrupt request Bit 4 INTF: INT interrupt request flag 0: No request 1: Interrupt request Bit 3 OCVPE: OCVP interrupt control 0: Disable 1: Enable

Rev. 1.20 180 Deee 0 201 Rev. 1.20 181 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 2 TKME: T ouch key module interrupt control 0: Disable 1: Enable Bit 1 INTE: INT interrupt control 0: Disable 1: Enable Bit 0 EMI: Global interrupt control 0: Disable 1: Enable INTC1 Register Bit 7 6 5 4 3 2 1 0 Nae PTM0AF PTM0PF CTM0AF CTM0PF PTM0AE PTM0PE CTM0AE CTM0PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 PTM0AF: PTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6 PTM0PF: PTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5 CTM0AF: CTM0 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 CTM0PF: CTM0 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 PTM0AE: PTM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 2 PTM0PE: PTM0 Comparator P match Interrupt control 0: Disable 1: Enable Bit 1 CTM0AE: CTM0 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 CTM0PE: CTM0 Comparator P match Interrupt control 0: Disable 1: Enable INTC2 Register – BS87B12A-3 Bit 7 6 5 4 3 2 1 0 Nae URF DEF SIMF — URE DEE SIME — R/W R/W R/W R/W — R/W R/W R/W — POR 0 0 0 — 0 0 0 — Bit 7 URF: UART transfer interrupt request flag 0: No request 1: Interrupt request Bit 6 DEF: Data EEPROM Interrupt request flag 0: No request 1: Interrupt request

Rev. 1.20 182 Deee 0 201 Rev. 1.20 183 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Bit 5 SIMF: SIM Interrupt request flag 0: No request 1: Interrupt request Bit 4 Unimplemented, read as "0" Bit 3 URE: UART transfer interrupt control 0: Disable 1: Enable Bit 2 DEE: Data EEPROM Interrupt control 0: Disable 1: Enable Bit 1 SIME: SIM Interrupt control 0: Disable 1: Enable Bit 0 Unimplemented, read as "0" INTC2 Register – BS87C16A-3 & BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae URF DEF SIMF MFF URE DEE SIME MFE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 URF: UART transfer interrupt request flag 0: No request 1: Interrupt request Bit 6 DEF: Data EEPROM Interrupt request flag 0: No request 1: Interrupt request Bit 5 SIMF: SIM Interrupt request flag 0: No request 1: Interrupt request Bit 4 MFF: Multi-function interrupt request flag 0: No request 1: Interrupt request Bit 3 URE: UART transfer interrupt control 0: Disable 1: Enable Bit 2 DEE: Data EEPROM Interrupt control 0: Disable 1: Enable Bit 1 SIME: SIM Interrupt control 0: Disable 1: Enable Bit 0 MFE: Multi-function interrupt control 0: Disable 1: Enable

Rev. 1.20 182 Deee 0 201 Rev. 1.20 183 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP INTC3 Register Bit 7 6 5 4 3 2 1 0 Nae TB1F TB0F ADF LVF TB1E TB0E ADE LVE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TB1F: T ime Base 1 interrupt request flag 0: No request 1: Interrupt request Bit 6 TB0F: T ime Base 0 interrupt request flag 0: No request 1: Interrupt request Bit 5 ADF: A/D Converter interrupt request flag 0: No request 1: Interrupt request Bit 4 LVF: LVD Interrupt request flag 0: No request 1: Interrupt request Bit 3 TB1E: T ime Base 1 interrupt control 0: Disable 1: Enable Bit 2 TB0E: T ime Base 0 interrupt control 0: Disable 1: Enable Bit 1 ADE: A/D Converter interrupt control 0: Disable 1: Enable Bit 0 LVE: LVD Interrupt control 0: Disable 1: Enable MFI Register – BS87C16A-3 Bit 7 6 5 4 3 2 1 0 Nae — — PTM1AF PTM1PF — — PTM1AE PTM1PE R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 Unimplemented, read as "0" Bit 5 PTM1AF: PTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 PTM1PF: PTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3~2 Unimplemented, read as "0" Bit 1 PTM1AE: PTM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 PTM1PE: PTM1 Comparator P match Interrupt control 0: Disable 1: Enable

Rev. 1.20 184 Deee 0 201 Rev. 1.20 18 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP MFI Register – BS87D20A-3 Bit 7 6 5 4 3 2 1 0 Nae CTM1AF CTM1PF PTM1AF PTM1PF CTM1AE CTM1PE PTM1AE PTM1PE R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 CTM1AF: CTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 6 CTM1PF: CTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 5 PTM1AF: PTM1 Comparator A match Interrupt request flag 0: No request 1: Interrupt request Bit 4 PTM1PF: PTM1 Comparator P match Interrupt request flag 0: No request 1: Interrupt request Bit 3 CTM1AE: CTM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 2 CTM1PE: CTM1 Comparator P match Interrupt control 0: Disable 1: Enable Bit 1 PTM1AE: PTM1 Comparator A match Interrupt control 0: Disable 1: Enable Bit 0 PTM1PE: PTM1 Comparator P match Interrupt control 0: Disable 1: Enable

Rev. 1.20 184 Deee 0 201 Rev. 1.20 18 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Interrupt Operation When the conditions for an interrupt event occur , such as a T ouch Key Counter overflow , a TM Comparator P or Com parator A m atch or A/ D c onversion c ompletion, e tc, t he re levant i nterrupt request flag will be set. Whether the request flag actually generates a program jump to the relevant interrupt vector is determined by the condition of the interrupt enable bit. If the enable bit is set high then the program will jump to its relevant vector; if the enable bit is zero then although the interrupt request flag is set an actual interrupt will not be generated and the program will not jump to the relevant interrupt vector. The global interrupt enable bit, if cleared to zero, will disable all interrupts. When an interrupt is generated, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new address which will be the value of the corresponding interrupt vector . The microcontroller will then fetch its next instruction from this interrupt vector . The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI, which retrieves the original Program Counter address from the stack and allow s the microcontroller to continue w ith normal execution at the point w here the interrupt occurred. The various interrupt enable bits, together with their associated request flags, are shown in the accompanying diagrams with their order of priority . Some interrupt sources have their own individual vector w hile others s hare the s ame multi-function interrupt vector . O nce an interrupt subroutine is serviced, all other interrupts will be blocked, as the global interrupt enable bit, EMI bit will be cleared automatically . This will prevent any further interrupt nesting from occurring. However, i f ot her i nterrupt re quests oc cur duri ng t his i nterval, a lthough t he i nterrupt wi ll not be immediately serviced, the request flag will still be recorded. If an interrupt requires immediate servicing while the program is alread y in another interrupt service routine, the EMI bit should be set after entering the routine to allow interrupt nesting. If the stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. In case of simultaneous requests, the accompanying diagram shows the priority that is a pplied. Al l o f t he i nterrupt r equest fla gs wh en se t wi ll wa ke-up t he d evice i f i t i s i n SL EEP o r IDLE Mode, however to prevent a wake-up from occurring the corresponding flag should be set before the device is in SLEEP or IDLE Mode.

Rev. 1.20 18 Deee 0 201 Rev. 1.20 187 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PTM0AF EMI 04H EMI 08H EMI 0CH EMI 10H EMI 14H EMI 18H EMI 1CH Inteupt Nae Request Flags Enale Bits Maste Enale Vector EMI auto disaled in ISR Pioity High Low 20H EMI 24H EMI 28H EMI 2CH INT Pin Touh Key Module INTF TKMF INTE TKME OCVP OCVPF OCVPE CTM0 Cop. P CTM0PF CTM0PE EMI 30H EMI 34H EMI 38H EMI 3CH SIM SIMF SIME CTM0 Cop. A PTM0 Cop. P PTM0 Cop. A CTM0AF CTM0AE PTM0AE PTM0PF PTM0PE Tie Base 0 TB0F TB0E Tie Base 1 TB1F TB1E A/D ADF ADE EEPROM DEF DEE UART URF URE LVD LVF LVE Interrupt Structure – BS87B12A-3

Rev. 1.20 18 Deee 0 201 Rev. 1.20 187 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PTM0AF EMI 04H EMI 08H EMI 0CH EMI 10H EMI 14H EMI 18H EMI 1CH Inteupt Nae Request Flags Enale Bits Maste Enale Vector EMI auto disaled in ISR Pioity High Low Inteupts ontained within Multi-Funtion Inteupts EMI 20H EMI 24H Multi-Funtion MFF MFE EMI 28H EMI 2CH INT Pin Touh Key Module INTF TKMF INTE TKME PTM1PF PTM1PE PTM1AF PTM1AE Enale Bits Request Flag auto eset in ISR Legend Request Flag no auto eset in ISRxxF xxF xxE OCVP OCVPF OCVPE CTM0 Cop. P CTM0PF CTM0PE EMI 30H EMI 34H EMI 38H EMI 3CH SIM SIMF SIME CTM0 Cop. A PTM0 Cop. P PTM0 Cop. A CTM0AF CTM0AE PTM0AE PTM0PF PTM0PE Tie Base 0 TB0F TB0E Tie Base 1 TB1F TB1E A/D ADF ADE EEPROM DEF DEE UART URF URE LVD LVF LVE PTM1 Cop. P PTM1 Cop. A Inteupt Nae Request Flags Enale Bits Interrupt Structure – BS87C16A-3

Rev. 1.20 188 Deee 0 201 Rev. 1.20 189 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP PTM0AF EMI 04H EMI 08H EMI 0CH EMI 10H EMI 14H EMI 18H EMI 1CH Inteupt Nae Request Flags Enale Bits Maste Enale Vector EMI auto disaled in ISR Pioity High Low Inteupts ontained within Multi-Funtion Inteupts EMI 20H EMI 24H Multi-Funtion MFF MFE EMI 28H EMI 2CH INT Pin Touh Key Module INTF TKMF INTE TKME PTM1PF PTM1PE PTM1AF PTM1AE Enale Bits Request Flag auto eset in ISR Legend Request Flag no auto eset in ISRxxF xxF xxE OCVP OCVPF OCVPE CTM0 Cop. P CTM0PF CTM0PE EMI 30H EMI 34H EMI 38H EMI 3CH SIM SIMF SIME CTM1PF CTM1PE CTM1AF CTM1AE CTM0 Cop. A PTM0 Cop. P PTM0 Cop. A CTM0AF CTM0AE PTM0AE PTM0PF PTM0PE Tie Base 0 TB0F TB0E Tie Base 1 TB1F TB1E A/D ADF ADE EEPROM DEF DEE UART URF URE LVD LVF LVE CTM1 Cop. P CTM1 Cop. A PTM1 Cop. P PTM1 Cop. A Inteupt Nae Request Flags Enale Bits Interrupt Structure – BS87D20A-3

Rev. 1.20 188 Deee 0 201 Rev. 1.20 189 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP External Interrupt The e xternal i nterrupt i s c ontrolled by si gnal t ransitions on t he pi n INT . An e xternal i nterrupt request will take place when the external interrupt request flag, INTF , is set, which will occur when a transition, whose type is chosen by the edge select bits, appears on the external interrupt pin. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and res pective external interrupt enable bit, IN TE, mus t fi rst be s et. A dditionally the correct interrupt edge type mus t be s elected us ing the IN TEG regis ter to enable the external interrupt function and to choose the trigger edge type. As the external interrupt pin is pin-shared with I/O pins, they can only be configured as an external interrupt pin if the external interrupt enable bit in the corresponding interrupt register has been set. The pin must also be setup as an input by setting the corresponding bit in the port control register . When the interrupt is enabled, the stack is not full and the correct transition type appears on the external interrupt pin, a subroutine call to the external interrupt vector , will take place. When the interrupt is serviced, the external interrupt request flags, INTF, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor selections on the external interrupt pins will remain valid even if the pin is used as an external interrupt input. The INTEG register is used to select the type of active edge that will trigger the external interrupt. A choice of either rising or falling or both edge types can be chosen to trigger an external interrupt. Note that the INTEG register can also be used to disable the external interrupt function. Touch Key Module Interrupt For a T ouch Key interrupt to occur, the global interrupt enable bit, EMI, and the T ouch Key interrupt enable bit, TKME, must be first set. An actual T ouch Key interrupt will take place when the T ouch Key interrupt request flag, TKMF , is set, a situation that will occur when the time slot counter overflows. When the interrupt is enabled, the stack is not full and the T ouch Key time slot counter overflow occurs, a subroutine call to the relevant interrupt vector , will take place. When the interrupt is serviced, the T ouch Key interrupt request flag will be automatically reset and the EMI bit will also be automatically cleared to disable other interrupts. OCVP Interrupt An OCVP interrupt request will take place when the OCVP interrupt request flag, OCVPF , is set, which occurs when the OCVP circuit detects a specific current or voltage condition. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the OCVP interrupt enable bit, OCVPE, must first be set. When the interrupt is enabled, the stack is not full and a user -defined current or voltage condition occurs, a subroutine call to the OCVP interrupt vector will take place. When the OCVP interrupt is serviced, the EMI bit will automatically be cleare d to disable other interrupt s and the OCVP interrupt request flag will also be automatically cleared. TM Interrupts The Compact and Periodic TMs have two interrupts, one comes from the comparator A match situation and the other comes from the comparator P match s ituation. The CTM 0 and P TM0 interrupts h ave t heir o wn i ndividual i nterrupt v ectors r espectively wh ile t he C TM1 a nd PT M1 a re contained within the Multi-function Interrupts. For the CTM0 and PTM0 there are two interrupt request fla gs and two enable control bit s. A TM int errupt reque st wi ll ta ke plac e when any of the TM re quest fla gs a re se t, a si tuation whi ch oc curs whe n a T M c omparator P or A m atch si tuation happens.

Rev. 1.20 190 Deee 0 201 Rev. 1.20 191 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP To allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and respective TM Interrupt enable bit must first be set for CTM0 and PTM0. However , the relevant Multi-function Interrupt enable bit, MF E, must also be set for CTM1 or PTM 1. When the interrup t is enabled, the stack is not full and a TM compara tor match situation occurs, a subroutine call to the relevant TM Interrupt vector locations will take place. When the TM interrupt is serviced, the EMI bit will be automatically cleared to disable other interrupts. The CTM0 or PTM0 int errupt request fla g wi ll aut omatically be cl eared. However , for CTM1 or PT M1 only the related MFF flag will be automatica lly cleared. The CTM1 or PTM1 interrupt request flags will be kept unchanged. As the CTM or PTM1 interrupt request flags will not be automatically cleared, they have to be cleared by the application program. Multi-function Interrupt – BS87C16A-3 & BS87D20A-3 Within t he spe cific de vice t here i s on e Mul ti-function i nterrupts. Unl ike t he ot her i ndependent interrupts, t his i nterrupt ha s no i ndependent sou rce, bu t ra ther a re fo rmed fr om ot her e xisting interrupt sources, namely the PTM1 or CTM1/PTM1 interrupts, dependent upon which device is selected. A Mu lti-function i nterrupt r equest wi ll t ake p lace wh en t he Mu lti-function i nterrupt r equest f lag MFF are set. The Multi-function interrupt flag will be set when any of its included functions generate an interr upt request flag. T o allow the program to branch to its respective interrupt vector address, when the Multi-function interrupt is enabled and the stack is not full, and one of the interrupts contained within the Multi-function interrupt occurs, a subroutine call to one of the Multi- function interrupt vectors will take place. When the interrupt is serviced, the related Multi-Function request flag will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. However, i t m ust be not ed t hat, a lthough t he Mul ti-function Int errupt re quest fl ag wi ll be automatically reset when the interrupt is serviced, the request flags from the original source of the M ulti-function interrupt w ill not be automatically reset and must be manually reset by the application program. Serial Interface Module Interrupt The Se rial Int erface Modul e Int errupt, al so known as the SIM int errupt, is an indivi dual int errupt source with its own interrupt vector . A SIM Interrupt request will take place when the SIM Interrupt request flag, SIMF , is set, which occurs when a byte of data has been received or transmitted by the SIM interface, an I2C slave address match or I2C bus time-out happens. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and the Serial Interface Int errupt e nable bi t, SIME , m ust first be se t. W hen t he i nterrupt i s e nabled, t he st ack i s not full and any of the above described situations occurs, a subroutine call to the corresponding iInterrupt vector will take place. When the Serial Interface Interrupt is serviced, the SIM interrupt request flag, SIMF , will be automat ically cleared and the EMI bit will also be automatically cleared to disable other interrupts.

Rev. 1.20 190 Deee 0 201 Rev. 1.20 191 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP EEPROM Interrupt The EEPROM W rite Interrupt is an individual interrupt source with its own interrupt vector . An EEPROM W rite Interrupt request will take place when the EEPROM W rite Interrupt request flag, DEF, is set, which occurs when an EEPROM W rite cycle ends. T o all ow the program to branch to its r espective i nterrupt v ector a ddress, t he g lobal i nterrupt e nable b it, E MI, a nd E EPROM W rite Interrupt enable bit, DEE, must first be set. When the interrupt is enabled, the stack is not full and an EEPROM W rite cycle ends, a subroutine call to the respective interrupt vector will take place. When the EEPROM W rite Interrupt is serviced, the DEF flag will be automatically cleared and the EMI bit will also be automatically cleared to disable other interrupts. UART Transfer Interrupt The UAR T T ransfer Interrupt is controlled by several UAR T transfer conditions. When one of these conditions occurs, an interrupt pulse will be generated to get the attention of the microcontroller . These conditions are a transmitter data register empty , transmitter idle, receiver data available, receiver overrun, address detect and an RX pin wake-up. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and UAR T Interrupt enable bit, URE, must first be set. When the interrupt is enabled, the stack is not full and any of the conditions described above occurs, a subroutine call to the UAR T Interrupt vector , will take place. When the interrupt is serviced, the UAR T Interrupt flag, URF , will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. LVD Interrupt The Low V oltage Detector Interrupt is an individual interrupt source with its own interrupt cevtor . An L VD Interrupt reques t w ill take place w hen the L VD Interrupt reques t fl ag, L VF, is s et, w hich occurs when the Low V oltage Detector function detects a low power supply voltage. T o allow the program to branch to its respective interrupt vector address, the global interrupt enable bit, EMI, and Low V oltage Interrupt enable bit, L VE, must first be set. When the interrupt is enabled, the stack is not full and a low voltage condition occurs, a subroutine call to the relevant interrupt vector will take plac e. When the Low V oltage Interrupt is serviced, the L VF flag will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts. A/D Converter Interrupt The A/D Converter Interrupt is controlled by the termination of an A/D conversion process. An A/ D Converter Interrupt request will take place when the A/D Converter Interrupt request flag, ADF , is set, which occurs when the A/D conversion process finishes. T o allow the program to branch to its respective interrupt vector a ddress, the global interrupt enable bit, EMI, a nd A/ D Interrupt enable bit, ADE, must first be set. When the interrupt is enabled, the stack is not full and the A/D conversion process has ended, a subroutine call to the A/D Converter Interrupt vector will take place. When the interrupt is serviced, the A/D Converter Interrupt flag, ADF , will be automatically cleared. The EMI bit will also be automatically cleared to disable other interrupts.

Rev. 1.20 192 Deee 0 201 Rev. 1.20 193 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Time Base Interrupts The function of the T ime Base Interrupt is to provide regular time signal in the form of an internal interrupt. It is controlled by the overflow signal from its internal timer . When this happens its interrupt request flag, TBnF , will be set. T o allow the program to branch to its respective interrupt vector addresses, the global interrup t enable bit, EMI and T ime Base enable bit, TBnE, must first be set. When the interrupt is enabl ed, the stack is not full and the T ime Base overflows, a subroutine call to its respective vector location will take place. When the interrupt is serviced, the interrupt request flag, TBnF , will be automatically reset and the EMI bit will be cleared to disable other interrupts. The purpose of the T ime Base Interrupt is to provide an interrupt signal at fixed time periods. Its clock source, fPSC0 or fPSC1, originates from the internal clock source fSYS, fSYS/4, fSUB or fH and then passes through a divider , the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges. The clock source which in turn controls the T ime Base interrupt period is selected using the CLKSEL0[1:0] and CLKSEL1[1:0] bits in the PSCR register respectively. M U X fSYS/4 fSYS fSUB Pesale 0 CLKSEL0[1:0] fPSC0 fPSC0/28 ~ fPSC0/21 M U X M U X TB0[2:0] TB1[2:0] Tie Base 0 Inteupt Tie Base 1 Inteupt TB0ON TB1ON M U X Pesale 1 CLKSEL1[1:0] fPSC1 fPSC1/28 ~ fPSC1/21 fH fSYS/4 fSYS fSUB fH Time Base Interrupts PSCR Register Bit 7 6 5 4 3 2 1 0 Nae — — CLKSEL11 CLKSEL10 — — CLKSEL01 CLKSEL00 R/W — — R/W R/W — — R/W R/W POR — — 0 0 — — 0 0 Bit 7~6 unimplemented, read as "0" Bit 5~4 CLKSEL11~CLKSEL10: Prescaler 1 clock source fPSC1 selection 00: fSYS 01: fSYS/4 10: fSUB 11: fH Bit 3~2 unimplemented, read as "0" Bit 1~0 CLKSEL01~CLKSEL00: Prescaler 0 clock source fPSC0 selection 00: fSYS 01: fSYS/4 10: fSUB 11: fH

Rev. 1.20 192 Deee 0 201 Rev. 1.20 193 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP TBC Register Bit 7 6 5 4 3 2 1 0 Nae TB1ON TB12 TB11 TB10 TB0ON TB02 TB01 TB00 R/W R/W R/W R/W R/W R/W R/W R/W R/W POR 0 0 0 0 0 0 0 0 Bit 7 TB1ON: T ime Base 1 Enable Control 0: Disable 1: Enable Bit 6~4 TB12~TB10: T ime Base 1 time-out period selection 000: 28/fPSC1 001: 29/fPSC1 010: 210/fPSC1 011: 211/fPSC1 100: 212/fPSC1 101: 213/fPSC1 110: 214/fPSC1 111: 215/fPSC1 Bit 3 TB0ON: T ime Base 0 Enable Control 0: Disable 1: Enable Bit 2~0 TB02~TB00: T ime Base 0 time-out period selection 000: 28/fPSC0 001: 29/fPSC0 010: 210/fPSC0 011: 211/fPSC0 100: 212/fPSC0 101: 213/fPSC0 110: 214/fPSC0 111: 215/fPSC0 Interrupt Wake-up Function Each of the int errupt funct ions has the capa bility of waki ng up the mi crocontroller when in the SLEEP o r I DLE Mo de. A wa ke-up i s g enerated wh en a n i nterrupt r equest fla g c hanges f rom l ow to high and is independent of whether the interrupt is enabled or not. Therefore, even though these devices are in the SLEEP or IDLE Mode and its system oscillator stopped, situations such as external edge transitions on the external interrupt pins, a low power supply voltage or comparator input change may cause their respective interrupt fl ag to be set hi gh and consequently generate an i nterrupt. C are m ust t herefore b e t aken i f sp urious wa ke-up si tuations a re t o b e a voided. I f a n interrupt wake-up function is to be disabled then the corresponding interrupt request flag should be set high before the device enters the SLEEP or IDLE Mode. The interr upt enable bits have no ef fect on the interrupt wake-up function.

Rev. 1.20 194 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Programming Considerations By di sabling t he re levant i nterrupt e nable bi ts, a re quested i nterrupt c an be pre vented from be ing serviced, however , once an interrupt request flag is set, it will remain in this condition in the interrupt register until the corresponding interrupt is serviced or until the request flag is cleared by the application program. Where a certain interrupt is contained w ithin a M ulti-function interrupt, then w hen the interrupt service routine is executed, as only the Multi-function interrupt request flags, MFnF , will be automatically cleared, the individual request flag for the function needs to be cleared by the application program. It is recommended that programs do not use the "CALL" instruction within the interrupt service subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately . If only one stack is left and the inte rrupt is not well controlled, the original control sequence will be damaged once a CALL subroutine is executed in the interrupt subroutine. Every interrupt has the capability of waking up the microcontroller when it is in the SLEEP or IDLE Mode, the wake up being generated when the interrupt request flag changes from low to high. If it is required to prevent a certain interru pt from waking up the microcontrol ler then its respective request flag should be first set high before enter SLEEP or IDLE Mode. As only the Program Counter is pushed onto the stack, then when the interrupt is serviced, if the contents of the accumulator , status register or other registers are altered by the interrupt service program, t heir c ontents shoul d be sa ved t o t he m emory a t t he be ginning of t he i nterrupt se rvice routine. To return from an interrupt subroutine, either a RET or RETI instruction may be executed. The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts. The RET instruction however only executes a return to the main program leaving the EMI bit in its present zero state and therefore disabling the execution of further interrupts.

Rev. 1.20 194 Deee 0 201 Rev. 1.20 19 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Configuration Options Configuration options refer to certa in options within the MCU that are programmed into the device during the programming process. During the development process, these options are selected using the HT -IDE software development tools. As these options are programmed into the device using the hardwa re programm ing tools, once they are sel ected they cannot be changed la ter using the application program. All options must be defined for proper system function, the details of which are shown in the table. No. Options Oscillator Option

1 Low Speed Syste Osillato Seletion – fSUB:

2 HIRC Fequeny Seletion – fHIRC:

Note that when the HIRC has been configured at a frequency shown in this table the HIRCS1 and HIRCS0 bits are recommended to be setup to select the same frequency to keep the HIRC frequency accuracy specified in the A.C characteristics.

Rev. 1.20 19 Deee 0 201 Rev. 1.20 197 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Application Circuits VDD VSS KEY1 0.1uF I/O Pins SIM Pins VDD KEY2 KEYn UART Pins SCOM&SSEG Pins XT1 XT2 OSC Ciuit See Osillato Setion AN0~AN7 OCVP Pins

Rev. 1.20 19 Deee 0 201 Rev. 1.20 197 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of program instruction codes that direc ts the microcontroller to perform certain operations. In the case of Holtek microcontroller , a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of programming overheads. For easier understanding of the various instruction codes, they have been subdivided into several functional groupings. Instruction Timing Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two ins truction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator , most instructions would be i mplemented wi thin 0.5 μs a nd bra nch or c all i nstructions woul d be i mplemented wi thin 1μs. Although instructions which require one more cycle to implement are generally limited to the JMP , CALL, RET , RETI and table read instructions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to implement. As instructions which change the contents of the PCL will imply a direct j ump t o t hat ne w a ddress, one m ore c ycle wi ll be re quired. E xamples of suc h i nstructions would be "CLR PCL" or "MOV PCL, A". For the case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The t ransfer of da ta wi thin t he m icrocontroller progra m i s one of t he m ost fre quently use d operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific immediate data directly into the Ac cumulator. One of t he m ost i mportant da ta t ransfer a pplications i s t o re ceive da ta from t he input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithm etic operations and data manipula tion is a necessary feature of most m icrocontroller a pplications. W ithin t he Hol tek m icrocontroller i nstruction se t a re a ra nge of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to ens ure correct handling of carry and borrow data w hen res ults exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified.

Rev. 1.20 198 Deee 0 201 Rev. 1.20 199 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Logical and Rotate Operation The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within t he Hol tek m icrocontroller i nstruction set . As wi th t he c ase of m ost i nstructions i nvolving data m anipulation, d ata m ust p ass t hrough t he Ac cumulator wh ich m ay i nvolve a dditional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one Bit right or left. Dif ferent rotate instructions exist depending on program requirements. Rotate instructions are useful for serial port progra mming a pplications whe re da ta c an be rot ated from a n i nternal re gister i nto t he Ca rry Bit from where it can be examined and the necessary serial Bit set high or low . Another application which rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or t o a su broutine usi ng t he CAL L i nstruction. T hey di ffer i n t he se nse t hat i n t he c ase of a subroutine call, the program mus t return to the ins truction immediately w hen the s ubroutine has been carried out. This is done by placing a return ins truction " RET" in the s ubroutine w hich w ill cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping of f point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual Bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These i nstructions a re t he ke y t o de cision m aking a nd bra nching wi thin t he progra m pe rhaps determined by the condition of certain input switches or by the condition of internal data Bits. Bit Operations The abili ty to provide single Bit operations on Data Memory is an extremely flexible feature of all Holtek m icrocontrollers. T his fe ature i s e specially use ful for out put port Bi t progra mming whe re individual Bits or port pins can be directly set high or low using either the "SET [m].i" or "CLR [m]. i" i nstructions r espectively. T he f eature r emoves t he n eed f or p rogrammers t o fir st r ead t he 8 -Bit output port, manip ulate the input data to ensure that other Bits are not changed and then output the port with the correct new data. This read-modify-write process is take n care of automatically when these Bit operation instructions are used. Table Read Operations Data st orage i s norm ally i mplemented by usi ng re gisters. Howeve r, whe n working wi th l arge amounts of fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory . T o overcome this problem, Holtek microcontrollers allow an area of Program Memory to be set as a table where data can be directly stored. A set of easy to use instructions provides the means by w hich this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the "HAL T" i nstruction f or Po wer-down o perations a nd i nstructions t o c ontrol t he o peration o f the W atchdog T imer for reliable program operations under extreme electric or electromagnetic environments. For their relevant operations, refer to the functional related sections.

Rev. 1.20 198 Deee 0 201 Rev. 1.20 199 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Instruction Set Summary The i nstructions re lated t o t he da ta m emory a ccess i n t he fol lowing t able c an be used whe n t he desired data memory is located in Data Memory sector 0. Table Conventions x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A[] Add Data Meoy to ACC 1 Z C AC OV SC ADDM A[] Add ACC to Data Meoy 1Note Z C AC OV SC ADD Ax Add iediate data to ACC 1 Z C AC OV SC ADC A[] Add Data Meoy to ACC with Cay 1 Z C AC OV SC ADCM A[] Add ACC to Data eoy with Cay 1Note Z C AC OV SC SUB Ax Sutat iediate data fo the ACC 1 Z C AC OV SC CZ SUB A[] Sutat Data Meoy fo ACC 1 Z C AC OV SC CZ SUBM A[] Sutat Data Meoy fo ACC with esult in Data Meoy 1Note Z C AC OV SC CZ SBC Ax Sutat iediate data fo ACC with Cay 1 Z C AC OV SC CZ SBC A[] Sutat Data Meoy fo ACC with Cay 1 Z C AC OV SC CZ SBCM A[] Sutat Data Meoy fo ACC with Cay esult in Data Me o y 1Note Z C AC OV SC CZ DAA [] Deial adjust ACC fo Addition with esult in Data Meoy 1Note C Logic Operation AND A[] Logial AND Data Meoy to ACC 1 Z OR A[] Logial OR Data Meoy to ACC 1 Z XOR A[] Logial XOR Data Meoy to ACC 1 Z ANDM A[] Logial AND ACC to Data Meoy 1Note Z ORM A[] Logial OR ACC to Data Meoy 1Note Z XORM A[] Logial XOR ACC to Data Meoy 1Note Z AND Ax Logial AND iediate Data to ACC 1 Z OR Ax Logial OR iediate Data to ACC 1 Z XOR Ax Logial XOR iediate Data to ACC 1 Z CPL [] Copleent Data Meoy 1Note Z CPLA [] Copleent Data Meoy with esult in ACC 1 Z Increment & Decrement INCA [] Ineent Data Meoy with esult in ACC 1 Z INC [] Ineent Data Meoy 1Note Z DECA [] Deeent Data Meoy with esult in ACC 1 Z DEC [] Deeent Data Meoy 1Note Z Rotate RRA [] Rotate Data Meoy ight with esult in ACC 1 None RR [] Rotate Data Meoy ight 1Note None RRCA [] Rotate Data Meoy ight though Cay with esult in ACC 1 C RRC [] Rotate Data Meoy ight though Cay 1Note C RLA [] Rotate Data Meoy left with esult in ACC 1 None RL [] Rotate Data Meoy left 1Note None RLCA [] Rotate Data Meoy left though Cay with esult in ACC 1 C RLC [] Rotate Data Meoy left though Cay 1Note C

Rev. 1.20 200 Deee 0 201 Rev. 1.20 201 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Mnemonic Description Cycles Flag Affected Data Move MOV A[] Move Data Meoy to ACC 1 None MOV []A Move ACC to Data Meoy 1Note None MOV Ax Move iediate data to ACC 1 None Bit Operation CLR [].i Clea it of Data Meoy 1Note None SET [].i Set it of Data Meoy 1Note None Branch Operation JMP add Jup unonditionally 2 None SZ [] Skip if Data Meoy is zeo 1Note None SZA [] Skip if Data Meoy is zeo with data oveent to ACC 1Note None SZ [].i Skip if it i of Data Meoy is zeo 1Note None SNZ [] Skip if Data Meoy is not zeo 1Note None SNZ [].i Skip if it i of Data Meoy is not zeo 1Note None SIZ [] Skip if ineent Data Meoy is zeo 1Note None SDZ [] Skip if deeent Data Meoy is zeo 1Note None SIZA [] Skip if ineent Data Meoy is zeo with esult in ACC 1Note None SDZA [] Skip if deeent Data Meoy is zeo with esult in ACC 1Note None CALL add Suoutine all 2 None RET Retun fo suoutine 2 None RET Ax Retun fo suoutine and load iediate data to ACC 2 None RETI Retun fo inteupt 2 None Table Read Operation TABRD [] Read table (specific page) to TBLH and Data Memory 2Note None TABRDL [] Read tale (last page) to TBLH and Data Meoy 2Note None ITABRD [] Increment table pointer TBLP first and Read table to TBLH and Data Memory 2Note None ITABRDL [] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Meoy 2Note None Miscellaneous NOP No opeation 1 None CLR [] Clea Data Meoy 1Note None SET [] Set Data Meoy 1Note None CLR WDT Clea Wathdog Tie 1 TO PDF SWAP [] Swap niles of Data Meoy 1Note None SWAPA [] Swap niles of Data Meoy with esult in ACC 1 None HALT Ente powe down ode 1 TO PDF Note: 1. For skip instructions, if the result of the comparison involves a skip then up to three cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the "CLR WDT" instruction the T O and PDF flags may be af fected by the execution status. The T O and PDF fla gs a re c leared a fter t he "CL R W DT" i nstructions i s e xecuted. Ot herwise t he T O a nd PDF flags remain unchanged.

Rev. 1.20 200 Deee 0 201 Rev. 1.20 201 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Extended Instruction Set The extended instructions are used to support the full range address access for the data memory . When the accessed data memory is located in any data memory sections except sector 0, the extended instructi on can be used to access the data memory instead of using the indirect addressing access to improve the CPU firmware performance. Mnemonic Description Cycles Flag Affected Arithmetic LADD A[] Add Data Meoy to ACC 2 Z C AC OV SC LADDM A[] Add ACC to Data Meoy 2Note Z C AC OV SC LADC A[] Add Data Meoy to ACC with Cay 2 Z C AC OV SC LADCM A[] Add ACC to Data eoy with Cay 2Note Z C AC OV SC LSUB A[] Sutat Data Meoy fo ACC 2 Z C AC OV SC CZ LSUBM A[] Sutat Data Meoy fo ACC with esult in Data Meoy 2Note Z C AC OV SC CZ LSBC A[] Sutat Data Meoy fo ACC with Cay 2 Z C AC OV SC CZ LSBCM A[] Sutat Data Meoy fo ACC with Cay esult in Data Me o y 2Note Z C AC OV SC CZ LDAA [] Deial adjust ACC fo Addition with esult in Data Meoy 2Note C Logic Operation LAND A[] Logial AND Data Meoy to ACC 2 Z LOR A[] Logial OR Data Meoy to ACC 2 Z LXOR A[] Logial XOR Data Meoy to ACC 2 Z LANDM A[] Logial AND ACC to Data Meoy 2Note Z LORM A[] Logial OR ACC to Data Meoy 2Note Z LXORM A[] Logial XOR ACC to Data Meoy 2Note Z LCPL [] Copleent Data Meoy 2Note Z LCPLA [] Copleent Data Meoy with esult in ACC 2 Z Increment & Decrement LINCA [] Ineent Data Meoy with esult in ACC 2 Z LINC [] Ineent Data Meoy 2Note Z LDECA [] Deeent Data Meoy with esult in ACC 2 Z LDEC [] Deeent Data Meoy 2Note Z Rotate LRRA [] Rotate Data Meoy ight with esult in ACC 2 None LRR [] Rotate Data Meoy ight 2Note None LRRCA [] Rotate Data Meoy ight though Cay with esult in ACC 2 C LRRC [] Rotate Data Meoy ight though Cay 2Note C LRLA [] Rotate Data Meoy left with esult in ACC 2 None LRL [] Rotate Data Meoy left 2Note None LRLCA [] Rotate Data Meoy left though Cay with esult in ACC 2 C LRLC [] Rotate Data Meoy left though Cay 2Note C Data Move LMOV A[] Move Data Meoy to ACC 2 None LMOV []A Move ACC to Data Meoy 2Note None Bit Operation LCLR [].i Clea it of Data Meoy 2Note None LSET [].i Set it of Data Meoy 2Note None

Rev. 1.20 202 Deee 0 201 Rev. 1.20 203 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Mnemonic Description Cycles Flag Affected Branch LSZ [] Skip if Data Meoy is zeo 2Note None LSZA [] Skip if Data Meoy is zeo with data oveent to ACC 2Note None LSNZ [] Skip if Data Meoy is not zeo 2Note None LSZ [].i Skip if it i of Data Meoy is zeo 2Note None LSNZ [].i Skip if it i of Data Meoy is not zeo 2Note None LSIZ [] Skip if ineent Data Meoy is zeo 2Note None LSDZ [] Skip if deeent Data Meoy is zeo 2Note None LSIZA [] Skip if ineent Data Meoy is zeo with esult in ACC 2Note None LSDZA [] Skip if deeent Data Meoy is zeo with esult in ACC 2Note None Table Read LTABRD [] Read tale to TBLH and Data Meoy 3Note None LTABRDL [] Read tale (last page) to TBLH and Data Meoy 3Note None LITABRD [] Increment table pointer TBLP first and Read table to TBLH and Data Memory 3Note None LITABRDL [] Increment table pointer TBLP first and Read table (last page) to TBLH and Data Meoy 3Note None Miscellaneous LCLR [] Clea Data Meoy 2Note None LSET [] Set Data Meoy 2Note None LSWAP [] Swap niles of Data Meoy 2Note None LSWAPA [] Swap niles of Data Meoy with esult in ACC 2 None Note: 1. For these extended skip instructions, if the result of the comparison involves a skip then up to four cycles are required, if no skip takes place two cycles is required. 2. Any extended instruction which changes the contents of the PCL register will also require three cycles for execution.

Rev. 1.20 202 Deee 0 201 Rev. 1.20 203 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Instruction Definition ADC A,[m] Add D ata M emory to A CC w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C ADCM A,[m] Add A CC to D ata M emory w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C ADD A,[m] Add D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C ADD A,x Add im mediate data to A CC Description The c ontents o f t he A ccumulator a nd t he s pecified im mediate data a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + x Affected fl ag(s) OV, Z , A C, C , S C ADDM A,[m] Add A CC to D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C AND A,[m] Logical A ND D ata M emory t o A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ [ m] Affected fl ag(s) Z AND A,x Logical A ND im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b it w ise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ x Affected fl ag(s) Z ANDM A,[m] Logical A ND A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ AND″ [ m] Affected fl ag(s) Z

Rev. 1.20 204 Deee 0 201 Rev. 1.20 20 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP CALL addr Subroutine c all Description Unconditionally c alls a s ubroutine a t t he s pecified a ddress. Th e P rogram C ounter t hen increments b y 1 to o btain t he a ddress o f t he n ext i nstruction w hich i s t hen p ushed o nto t he stack. T he sp ecified a ddress is t hen loaded a nd t he p rogram c ontinues e xecution f rom t his new a ddress. A s t his instruction re quires a n a dditional op eration, it is a t wo c ycle instruction. Operation Stack ← P rogram Counter + 1 Program C ounter ← a ddr Affected fl ag(s) None CLR [m] Clear D ata M emory Description Each b it o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m] ← 00H Affected fl ag(s) None CLR [m].i Clear bi t o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m].i ← 0 Affected fl ag(s) None CLR WDT Clear W atchdog T imer Description The T O, P DF fl ags a nd t he W DT a re al l c leared. Operation WDT cl eared TO ← 0 PDF ← 0 Affected fl ag(s) TO, P DF CPL [m] Complement D ata M emory Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Operation [m] ← [m] Affected fl ag(s) Z CPLA [m] Complement D ata M emory w ith r esult i n A CC Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Th e c omplemented r esult i s s tored i n the A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] Affected fl ag(s) Z DAA [m] Decimal-Adjust A CC f or addition w ith r esult i n D ata M emory Description Convert t he c ontents o f t he A ccumulator v alue to a B CD ( Binary C oded D ecimal) v alue resulting f rom t he p revious a ddition o f t wo B CD v ariables. I f t he low n ibble is greater t han 9 or i f A C fl ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. O therwise t he l ow n ibble remains u nchanged. I f t he h igh n ibble i s g reater t han 9 o r i f t he C fl ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. E ssentially, t he decimal c onversion i s p erformed b y a dding 00H, 0 6H, 6 0H o r 6 6H depending o n t he A ccumulator a nd fl ag c onditions. O nly t he C fl ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal B CD s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. Operation [m] ← A CC + 00H or [m] ← A CC + 06 H o r [m] ← A CC + 60H o r [m] ← A CC + 66H Affected fl ag(s) C

Rev. 1.20 204 Deee 0 201 Rev. 1.20 20 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP DEC [m] Decrement D ata M emory Description Data i n t he s pecified D ata M emory i s d ecremented b y 1 . Operation [m] ← [ m] − 1 Affected fl ag(s) Z DECA [m] Decrement D ata M emory wi th r esult i n A CC Description Data in t he sp ecified D ata M emory is d ecremented b y 1 . T he re sult is s tored in t he Accumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] − 1 Affected fl ag(s) Z HALT Enter p ower down m ode Description This i nstruction s tops t he p rogram e xecution a nd t urns o ff t he s ystem c lock. Th e c ontents o f the D ata M emory a nd r egisters a re r etained. Th e W DT a nd p rescaler a re c leared. Th e p ower down fl ag P DF i s s et a nd t he W DT t ime-out fl ag T O i s c leared. Operation TO ← 0 PDF ← 1 Affected fl ag(s) TO, P DF INC [m] Increment D ata M emory Description Data in t he sp ecified D ata M emory is incremented b y 1 . Operation [m] ← [ m] + 1 Affected fl ag(s) Z INCA [m] Increment D ata M emory wi th r esult i n A CC Description Data i n t he sp ecified D ata M emory i s i ncremented b y 1 . Th e re sult i s s tored i n t he A ccumulator. The c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] + 1 Affected fl ag(s) Z JMP addr Jump u nconditionally Description The c ontents o f t he P rogram C ounter a re re placed w ith t he sp ecified a ddress. P rogram execution t hen c ontinues f rom t his n ew a ddress. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ew a ddress is loaded, it is a t wo c ycle instruction. Operation Program Counter ← addr Affected fl ag(s) None MOV A,[m] Move D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. Operation ACC ← [ m] Affected fl ag(s) None MOV A,x Move im mediate data to A CC Description The im mediate data s pecified i s l oaded i nto t he A ccumulator. Operation ACC ← x Affected fl ag(s) None MOV [m],A Move A CC to D ata M emory Description The c ontents o f t he A ccumulator a re c opied to t he s pecified D ata M emory. Operation [m] ← A CC Affected fl ag(s) None

Rev. 1.20 20 Deee 0 201 Rev. 1.20 207 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP NOP No o peration Description No o peration i s p erformed. E xecution c ontinues w ith t he n ext i nstruction. Operation No operation Affected fl ag(s) None OR A,[m] Logical O R D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise logical O R op eration. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ [ m] Affected fl ag(s) Z OR A,x Logical OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical O R operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ x Affected fl ag(s) Z ORM A,[m] Logical OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical O R operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ OR″ [ m] Affected fl ag(s) Z RET Return from s ubroutine Description The P rogram C ounter is re stored f rom t he s tack. P rogram e xecution c ontinues a t t he re stored a ddress. Operation Program Counter ← S tack Affected fl ag(s) None RET A,x Return f rom su broutine and l oad im mediate data to A CC Description The P rogram C ounter i s r estored f rom t he s tack a nd t he A ccumulator l oaded w ith t he s pecified immediate data. P rogram e xecution c ontinues a t t he r estored a ddress. Operation Program Counter ← S tack ACC ← x Affected fl ag(s) None RETI Return from i nterrupt Description The P rogram C ounter is re stored f rom t he s tack a nd t he interrupts a re re -enabled b y s etting t he EMI b it. E MI i s t he m aster i nterrupt g lobal e nable b it. I f a n i nterrupt w as p ending w hen t he RETI instruction is e xecuted, t he p ending In terrupt ro utine w ill b e p rocessed b efore re turning to t he m ain p rogram. Operation Program Counter ← S tack EMI ← 1 Affected fl ag(s) None RL [m] Rotate D ata M emory l eft Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← [ m].7 Affected fl ag(s) None

Rev. 1.20 20 Deee 0 201 Rev. 1.20 207 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP RLA [m] Rotate D ata M emory left w ith re sult in A CC Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← [ m].7 Affected fl ag(s) None RLC [m] Rotate D ata M emory l eft t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated l eft b y 1 b it. B it 7 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← C C ← [ m].7 Affected fl ag(s) C RLCA [m] Rotate D ata M emory left t hrough C arry w ith re sult in A CC Description Data i n t he s pecified D ata M emory and t he carry fl ag are r otated l eft b y 1 b it. B it 7 r eplaces t he Carry b it a nd t he o riginal c arry fl ag i s r otated i nto t he b it 0 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← C C ← [ m].7 Affected fl ag(s) C RR [m] Rotate D ata M emory r ight Description The contents of t he s pecified D ata M emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← [ m].0 Affected fl ag(s) None RRA [m] Rotate D ata M emory right with result i n A CC Description Data i n t he s pecified D ata M emory i s r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← [ m].0 Affected fl ag(s) None RRC [m] Rotate D ata M emory r ight t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← C C ← [ m].0 Affected fl ag(s) C

Rev. 1.20 208 Deee 0 201 Rev. 1.20 209 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP RRCA [m] Rotate D ata M emory right th rough C arry with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 r eplaces the C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← C C ← [ m].0 Affected fl ag(s) C SBC A,[m] Subtract D ata M emory from A CC wi th C arry Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z SBC A, x Subtract im mediate data f rom A CC w ith Carry Description The immediate da ta a nd t he c omplement o f t he c arry fl ag a re s ubtracted f rom t he Accumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is negative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is p ositive o r z ero, t he C fl ag will be se t t o 1 . Operation ACC ← A CC - [ m] - C Affected fl ag(s) OV, Z , AC , C , S C, CZ SBCM A,[m] Subtract D ata M emory from A CC wi th C arry a nd r esult i n D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he D ata M emory. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z SDZ [m] Skip i f decrement D ata M emory i s 0 Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] − 1 Skip if [ m]=0 Affected fl ag(s) None SDZA [m] Skip i f decrement D ata M emory i s z ero w ith r esult i n A CC Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] − 1 Skip if A CC=0 Affected fl ag(s) None

Rev. 1.20 208 Deee 0 201 Rev. 1.20 209 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SET [m] Set D ata M emory Description Each b it o f t he s pecified D ata M emory i s s et t o 1 . Operation [m] ← F FH Affected fl ag(s) None SET [m].i Set b it o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s s et t o 1 . Operation [m].i ← 1 Affected fl ag(s) None SIZ [m] Skip i f i ncrement D ata M emory i s 0 Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] + 1 Skip if [ m]=0 Affected fl ag(s) None SIZA [m] Skip if increment D ata M emory is z ero w ith re sult in A CC Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] + 1 Skip if A CC=0 Affected fl ag(s) None SNZ [m].i Skip i f D ata M emory i s no t 0 Description If t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m].i ≠ 0 Affected fl ag(s) None SNZ [m] Skip i f D ata M emory i s no t 0 Description If t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m]≠ 0 Affected fl ag(s) None SUB A,[m] Subtract D ata M emory from A CC Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z

Rev. 1.20 210 Deee 0 201 Rev. 1.20 211 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP SUBM A,[m] Subtract D ata M emory from A CC wi th r esult i n D ata M emory Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he D ata M emory. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z SUB A,x Subtract im mediate data f rom A CC Description The im mediate data s pecified b y t he c ode i s s ubtracted f rom t he c ontents o f t he A ccumulator. The re sult is s tored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C flag w ill b e c leared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − x Affected fl ag(s) OV, Z , A C, C , S C, C Z SWAP [m] Swap ni bbles of D ata M emory Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Operation [m].3~[m].0 ↔ [ m].7~[m].4 Affected fl ag(s) None SWAPA [m] Swap ni bbles of D ata M emory w ith r esult i n A CC Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Th e result i s s tored i n t he A ccumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.3~ACC.0 ← [ m].7~[m].4 ACC.7~ACC.4 ← [ m].3~[m].0 Affected fl ag(s) None SZ [m] Skip i f D ata M emory i s 0 Description If t he contents of t he s pecified D ata M emory i s 0, t he following i nstruction i s s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m]=0 Affected fl ag(s) None SZA [m] Skip i f D ata M emory i s 0 w ith data m ovement to A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. I f t he v alue i s z ero, the f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] Skip if [ m]=0 Affected fl ag(s) None SZ [m].i Skip i f b it i of D ata M emory i s 0 Description If b it i o f t he sp ecified D ata M emory is 0 , t he f ollowing instruction is s kipped. A s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m].i=0 Affected fl ag(s) None

Rev. 1.20 210 Deee 0 201 Rev. 1.20 211 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP TABRD [m] Read ta ble ( specific p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( specific p age) a ddressed b y t he t able p ointer p air (TBLP a nd T BHP) i s mo ved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None TABRDL [m] Read t able (last p age) t o T BLH a nd D ata M emory Description The l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (TBLP) i s mo ved to t he s pecified D ata M emory a nd t he h igh b yte m oved to T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None ITABRD [m] Increment ta ble p ointer l ow b yte fir st and r ead ta ble to T BLH and D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he p rogram code addressed b y t he table p ointer ( TBHP and T BLP) i s m oved to t he s pecified D ata M emory and t he hi gh b yte moved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None ITABRDL [m] Increment t able p ointer l ow by te fi rst a nd r ead t able (last p age) t o T BLH a nd D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( TBLP) i s m oved to t he s pecified D ata M emory and the h igh by te mov ed t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None XOR A,[m] Logical X OR D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ [ m] Affected fl ag(s) Z XORM A,[m] Logical X OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ XOR″ [ m] Affected fl ag(s) Z XOR A,x Logical X OR im mediate data to A CC Description Data i n t he A ccumulator a nd t he s pecified im mediate data p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ x Affected fl ag(s) Z

Rev. 1.20 212 Deee 0 201 Rev. 1.20 213 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Extended Instruction Definition The extended instructions are used to directly access the data stored in any data memory sections. LADC A,[m] Add D ata M emory to A CC w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C LADCM A,[m] Add A CC to D ata M emory w ith Carry Description The c ontents o f t he s pecified D ata M emory, A ccumulator a nd t he c arry fl ag a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] + C Affected fl ag(s) OV, Z , A C, C , S C LADD A,[m] Add D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he A ccumulator. Operation ACC ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C LADDM A,[m] Add A CC to D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he A ccumulator a re a dded. The re sult is s tored in t he sp ecified D ata M emory. Operation [m] ← A CC + [ m] Affected fl ag(s) OV, Z , A C, C , S C LAND A,[m] Logical A ND D ata M emory t o A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″A ND″ [ m] Affected fl ag(s) Z LANDM A,[m] Logical A ND A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical A ND operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ AND″ [ m] Affected fl ag(s) Z LCLR [m] Clear D ata M emory Description Each b it o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m] ← 00H Affected fl ag(s) None LCLR [m].i Clear bi t o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s cl eared t o 0 . Operation [m].i ← 0 Affected fl ag(s) None

Rev. 1.20 212 Deee 0 201 Rev. 1.20 213 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LCPL [m] Complement D ata M emory Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Operation [m] ← [m] Affected fl ag(s) Z LCPLA [m] Complement D ata M emory w ith r esult i n A CC Description Each b it of t he s pecified D ata M emory i s l ogically complemented ( 1′s complement). B its w hich previously c ontained a 1 a re c hanged to 0 a nd v ice v ersa. Th e c omplemented r esult i s s tored i n the A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] Affected fl ag(s) Z LDAA [m] Decimal-Adjust A CC f or addition w ith r esult i n D ata M emory Description Convert t he c ontents o f t he A ccumulator v alue to a B CD ( Binary C oded D ecimal) v alue resulting f rom t he p revious a ddition o f t wo B CD v ariables. I f t he low n ibble is greater t han 9 or i f A C fl ag i s s et, t hen a v alue o f 6 w ill b e a dded to t he l ow n ibble. O therwise t he l ow n ibble remains u nchanged. I f t he h igh n ibble i s g reater t han 9 o r i f t he C fl ag i s s et, t hen a v alue o f 6 will b e a dded to t he h igh n ibble. E ssentially, t he decimal c onversion i s p erformed b y a dding 00H, 0 6H, 6 0H o r 6 6H depending o n t he A ccumulator a nd fl ag c onditions. O nly t he C fl ag may b e a ffected b y t his instruction w hich indicates t hat if t he o riginal B CD s um is greater t han 100, it al lows m ultiple p recision decimal a ddition. Operation [m] ← A CC + 00H or [m] ← A CC + 06 H o r [m] ← A CC + 60H o r [m] ← A CC + 66H Affected fl ag(s) C LDEC [m] Decrement D ata M emory Description Data i n t he s pecified D ata M emory i s d ecremented b y 1 . Operation [m] ← [ m] − 1 Affected fl ag(s) Z LDECA [m] Decrement D ata M emory wi th r esult i n A CC Description Data in t he sp ecified D ata M emory is d ecremented b y 1 . T he re sult is s tored in t he Accumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] − 1 Affected fl ag(s) Z LINC [m] Increment D ata M emory Description Data in t he sp ecified D ata M emory is incremented b y 1 . Operation [m] ← [ m] + 1 Affected fl ag(s) Z LINCA [m] Increment D ata M emory wi th r esult i n A CC Description Data i n t he sp ecified D ata M emory i s i ncremented b y 1 . Th e re sult i s s tored i n t he A ccumulator. The c ontents o f t he D ata M emory r emain u nchanged. Operation ACC ← [ m] + 1 Affected fl ag(s) Z

Rev. 1.20 214 Deee 0 201 Rev. 1.20 21 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LMOV A,[m] Move D ata M emory t o A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. Operation ACC ← [ m] Affected fl ag(s) None LMOV [m],A Move A CC to D ata M emory Description The c ontents o f t he A ccumulator a re c opied to t he s pecified D ata M emory. Operation [m] ← A CC Affected fl ag(s) None LOR A,[m] Logical O R D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise logical O R op eration. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″ OR″ [ m] Affected fl ag(s) Z LORM A,[m] Logical OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical O R operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ OR″ [ m] Affected fl ag(s) Z LRL [m] Rotate D ata M emory l eft Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← [ m].7 Affected fl ag(s) None LRLA [m] Rotate D ata M emory left w ith re sult in A CC Description The c ontents o f t he s pecified D ata M emory a re r otated l eft b y 1 b it w ith b it 7 r otated i nto b it 0 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← [ m].7 Affected fl ag(s) None LRLC [m] Rotate D ata M emory l eft t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated l eft b y 1 b it. B it 7 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 0 . Operation [m].(i+1) ← [ m].i; (i=0~6) [m].0 ← C C ← [ m].7 Affected fl ag(s) C LRLCA [m] Rotate D ata M emory left t hrough C arry w ith re sult in A CC Description Data i n t he s pecified D ata M emory and t he carry fl ag are r otated l eft b y 1 b it. B it 7 r eplaces t he Carry b it a nd t he o riginal c arry fl ag i s r otated i nto t he b it 0 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.(i+1) ← [ m].i; (i=0~6) ACC.0 ← C C ← [ m].7 Affected fl ag(s) C

Rev. 1.20 214 Deee 0 201 Rev. 1.20 21 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LRR [m] Rotate D ata M emory r ight Description The contents of t he s pecified D ata M emory are r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← [ m].0 Affected fl ag(s) None LRRA [m] Rotate D ata M emory right with result i n A CC Description Data i n t he s pecified D ata M emory i s r otated r ight b y 1 b it w ith b it 0 r otated i nto b it 7 . The r otated r esult i s s tored i n t he A ccumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← [ m].0 Affected fl ag(s) None LRRC [m] Rotate D ata M emory r ight t hrough Carry Description The c ontents o f t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 replaces t he C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Operation [m].i ← [ m].(i+1); (i=0~6) [m].7 ← C C ← [ m].0 Affected fl ag(s) C LRRCA [m] Rotate D ata M emory right th rough C arry with result i n A CC Description Data i n t he s pecified D ata M emory a nd t he c arry fl ag a re r otated r ight b y 1 b it. B it 0 r eplaces the C arry b it a nd t he o riginal c arry fl ag i s r otated i nto b it 7 . Th e r otated r esult i s s tored i n t he Accumulator a nd t he c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.i ← [ m].(i+1); (i=0~6) ACC.7 ← C C ← [ m].0 Affected fl ag(s) C LSBC A,[m] Subtract D ata M emory from A CC wi th C arry Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he A ccumulator. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z LSBCM A,[m] Subtract D ata M emory from A CC wi th C arry a nd r esult i n D ata M emory Description The c ontents o f t he s pecified D ata M emory a nd t he c omplement o f t he c arry fl ag a re subtracted f rom t he A ccumulator. T he re sult is s tored in t he D ata M emory. N ote t hat if t he result o f s ubtraction is n egative, t he C fl ag w ill b e c leared t o 0 , o therwise if t he re sult is positive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] − C Affected fl ag(s) OV, Z , A C, C , S C, C Z

Rev. 1.20 21 Deee 0 201 Rev. 1.20 217 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LSDZ [m] Skip i f decrement D ata M emory i s 0 Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] − 1 Skip if [ m]=0 Affected fl ag(s) None LSDZA [m] Skip i f decrement D ata M emory i s z ero w ith r esult i n A CC Description The c ontents o f t he s pecified D ata M emory a re fir st decremented b y 1 . I f t he r esult i s 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he r esult is n ot 0 , the p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] − 1 Skip if A CC=0 Affected fl ag(s) None LSET [m] Set D ata M emory Description Each b it o f t he s pecified D ata M emory i s s et t o 1 . Operation [m] ← F FH Affected fl ag(s) None LSET [m].i Set b it o f D ata M emory Description Bit i o f t he s pecified D ata M emory i s s et t o 1 . Operation [m].i ← 1 Affected fl ag(s) None LSIZ [m] Skip i f i ncrement D ata M emory i s 0 Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile the n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram proceeds w ith t he f ollowing i nstruction. Operation [m] ← [ m] + 1 Skip if [ m]=0 Affected fl ag(s) None LSIZA [m] Skip if increment D ata M emory is z ero w ith re sult in A CC Description The c ontents o f t he sp ecified D ata M emory a re fi rst incremented b y 1 . I f t he re sult is 0 , t he following instruction is s kipped. T he re sult is s tored in t he A ccumulator b ut t he sp ecified Data M emory c ontents r emain u nchanged. A s t his r equires t he i nsertion o f a dummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] + 1 Skip if A CC=0 Affected fl ag(s) None LSNZ [m].i Skip i f D ata M emory i s no t 0 Description If t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m].i ≠ 0 Affected fl ag(s) None

Rev. 1.20 21 Deee 0 201 Rev. 1.20 217 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LSNZ [m] Skip i f D ata M emory i s no t 0 Description If t he c ontent o f t he sp ecified D ata M emory is n ot 0 , t he f ollowing instruction is s kipped. A s this re quires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a two c ycle instruction. I f t he re sult is 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip i f [ m] ≠ 0 Affected fl ag(s) None LSUB A,[m] Subtract D ata M emory from A CC Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he A ccumulator. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation ACC ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z LSUBM A,[m] Subtract D ata M emory from A CC wi th r esult i n D ata M emory Description The s pecified D ata M emory i s s ubtracted f rom t he c ontents o f t he A ccumulator. Th e r esult i s stored in t he D ata M emory. N ote t hat if t he re sult o f s ubtraction is n egative, t he C fl ag w ill b e cleared to 0 , o therwise i f t he r esult i s p ositive o r z ero, t he C fl ag w ill b e s et to 1 . Operation [m] ← A CC − [ m] Affected fl ag(s) OV, Z , A C, C , S C, C Z LSWAP [m] Swap ni bbles of D ata M emory Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Operation [m].3~[m].0 ↔ [ m].7~[m].4 Affected fl ag(s) None LSWAPA [m] Swap ni bbles of D ata M emory w ith r esult i n A CC Description The l ow-order a nd h igh-order n ibbles o f t he s pecified D ata M emory a re i nterchanged. Th e result i s s tored i n t he A ccumulator. Th e c ontents o f t he D ata M emory r emain u nchanged. Operation ACC.3~ACC.0 ← [ m].7~[m].4 ACC.7~ACC.4 ← [ m].3~[m].0 Affected fl ag(s) None LSZ [m] Skip i f D ata M emory i s 0 Description If t he contents of t he s pecified D ata M emory i s 0, t he following i nstruction i s s kipped. A s t his requires t he insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo cycle instruction. I f t he re sult is n ot 0 t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m]=0 Affected fl ag(s) None LSZA [m] Skip i f D ata M emory i s 0 w ith data m ovement to A CC Description The c ontents o f t he s pecified D ata M emory a re c opied to t he A ccumulator. I f t he v alue i s z ero, the f ollowing instruction is s kipped. A s t his re quires t he insertion o f a d ummy instruction while t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 t he program p roceeds w ith t he f ollowing instruction. Operation ACC ← [ m] Skip if [ m]=0 Affected fl ag(s) None

Rev. 1.20 218 Deee 0 201 Rev. 1.20 219 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP LSZ [m].i Skip if b it i of D ata M emory i s 0 Description If b it i o f t he sp ecified D ata M emory is 0 , t he f ollowing instruction is s kipped. A s t his re quires the insertion o f a d ummy instruction w hile t he n ext instruction is f etched, it is a t wo c ycle instruction. I f t he re sult is n ot 0 , t he p rogram p roceeds w ith t he f ollowing instruction. Operation Skip if [ m].i=0 Affected fl ag(s) None LTABRD [m] Read ta ble ( current p age) to T BLH a nd D ata M emory Description The low b yte o f t he p rogram c ode ( current p age) a ddressed b y t he t able p ointer ( TBLP) is moved t o t he s pecified D ata M emory a nd t he h igh by te mo ved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LTABRDL [m] Read t able (last p age) t o T BLH a nd D ata M emory Description The l ow by te o f t he pr ogram c ode (last p age) a ddressed by t he t able p ointer (TBLP) i s mo ved to t he s pecified D ata M emory a nd t he h igh b yte m oved to T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LITABRD [m] Increment ta ble p ointer l ow b yte fir st and r ead ta ble to T BLH and D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he p rogram code addressed b y t he table p ointer ( TBHP and T BLP) i s m oved to t he s pecified D ata M emory and t he hi gh b yte moved t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LITABRDL [m] Increment t able p ointer l ow by te fi rst a nd r ead t able (last p age) t o T BLH a nd D ata M emory Description Increment ta ble p ointer l ow b yte, T BLP, fir st and t hen t he l ow b yte of t he p rogram code (last p age) addressed b y t he ta ble p ointer ( TBLP) i s m oved to t he s pecified D ata M emory and the h igh by te mov ed t o T BLH. Operation [m] ← pr ogram c ode (low by te) TBLH ← pr ogram c ode (high by te) Affected fl ag(s) None LXOR A,[m] Logical X OR D ata M emory to A CC Description Data i n t he A ccumulator a nd t he s pecified D ata M emory p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he A ccumulator. Operation ACC ← A CC ″X OR″ [ m] Affected fl ag(s) Z LXORM A,[m] Logical X OR A CC to D ata M emory Description Data i n t he s pecified D ata M emory a nd t he A ccumulator p erform a b itwise l ogical X OR operation. T he re sult is s tored in t he D ata M emory. Operation [m] ← A CC ″ XOR″ [ m] Affected fl ag(s) Z

Rev. 1.20 218 Deee 0 201 Rev. 1.20 219 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP

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Rev. 1.20 220 Deee 0 201 Rev. 1.20 221 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP 20-pin NSOP (150mil) Outline Dimensions /G32/G30 /G31 /G31/G31 /G31/G30 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A 0.228 0.23 0.244 B 0.14 0.14 0.11 C 0.009 — 0.012 C’ 0.382 0.390 0.398 D — — 0.09 E — 0.032 BSC — F 0.002 — 0.009 G 0.020 — 0.031 H 0.008 — 0.010 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A .80 .00 .20 B 3.70 3.90 4.10 C 0.23 — 0.30 C’ 9.70 9.90 10.10 D — — 1.7 E — 0.80 BSC — F 0.0 — 0.23 G 0.0 — 0.80 H 0.21 — 0.2 α 0° — 8°

Rev. 1.20 220 Deee 0 201 Rev. 1.20 221 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP 24-pin SOP (300mil) Outline Dimensions /G32/G34 /G31 /G31/G33 /G31/G32 /G41 /G42 /G43 /G44 /G45/G46 /G43/G27 /G47 /G48 /G61 Symbol Dimensions in inch Min. Nom. Max. A — 0.40 BSC — B — 0.29 BSC — C 0.012 — 0.020 C’ — 0.0 BSC — D — — 0.104 E — 0.00 BSC — F 0.004 — 0.012 G 0.01 — 0.00 H 0.008 — 0.013 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7. BSC — C 0.31 — 0.1 C’ — 1.4 BSC — D — — 2. E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8°

Rev. 1.20 222 Deee 0 201 Rev. 1.20 223 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP 28-pin SOP (300mil) Outline Dimensions /G32/G38 /G31 /G31/G35 /G31/G34 /G41 /G42 /G43 /G44 /G46 /G43/G27 /G47 /G48 /G61 /G45 Symbol Dimensions in inch Min. Nom. Max. A — 0.40 BSC — B — 0.29 BSC — C 0.012 — 0.020 C’ — 0.70 BSC — D — — 0.104 E — 0.00 BSC — F 0.004 — 0.012 G 0.01 — 0.00 H 0.008 — 0.013 α 0° — 8° Symbol Dimensions in mm Min. Nom. Max. A — 10.30 BSC — B — 7. BSC — C 0.31 — 0.1 C’ — 17.9 BSC — D — — 2. E — 1.27 BSC — F 0.10 — 0.30 G 0.40 — 1.27 H 0.20 — 0.33 α 0° — 8°

Rev. 1.20 222 Deee 0 201 Rev. 1.20 223 Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP 44-pin LQFP (10mm×10mm) (FP2.0mm) Outline Dimensions /G33/G34 /G31/G31 /G31 /G34/G34 /G41 /G42 /G32/G32 /G31/G32 /G45 /G46 /G47 /G48 /G49 /G4A /G4B /G61 /G33/G33 /G32/G33 /G43 /G44 Symbol Dimensions in inch Min. Nom. Max. A — 0.472 BSC — B — 0.394 BSC — C — 0.472 BSC — D — 0.394 BSC — E — 0.032 BSC — F 0.012 0.01 0.018 G 0.03 0.0 0.07 H — — 0.03 I 0.002 — 0.00 J 0.018 0.024 0.030 K 0.004 — 0.008 α 0° — 7° Symbol Dimensions in mm Min. Nom. Max. A — 12.00 BSC — B — 10.00 BSC — C — 12.00 BSC — D — 10.00 BSC — E — 0.80 BSC — F 0.30 0.37 0.4 G 1.3 1.40 1.4 H — — 1.0 I 0.0 — 0.1 J 0.4 0.0 0.7 K 0.09 — 0.20 α 0° — 7°

Rev. 1.20 224 Deee 0 201 Rev. 1.20 PB Deee 0 201 BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP BS87B12A-3/BS87C16A-3/BS87D20A-3 Touch A/D Flash MCU with OCVP Copyight© 201 y HOLTEK SEMICONDUCTOR INC. The infoation appeaing in this Data Sheet is elieved to e auate at the tie of puliation. Howeve Holtek assues no esponsi ility a ising f o the use of the specifications described. The applications mentioned herein are used solely fo the pupose of illustation and Holtek akes no waanty o epesentation that suh appliations will e suita le without fu the odifi ation no e o ends the use of its poduts fo appliation that ay pesent a isk to huan life due to alfuntion o othewise. Holtek's poduts ae not authoized fo use as itial oponents in life suppot devies o systes. Holtek eseves the ight to alte its products without prior notification. For the most up-to-date information, please visit ou we site at http://www.holtek.o.tw/en/hoe.

Product Information

BS87B12A-3 specifications and overview.

Summary

Touch A/D Flash MCU with OCVP December 05, 2016

Description

Touch A/D Flash MCU with OCVP December 05, 2016

Source title BS87B12A-3 Datasheet(PDF) - Holtek Semiconductor Inc

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