HA0082E

HT48RA0-3 HOLTEK | Alldatasheet

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Features

/c183Operating voltage: fSYS=4MHz(/c1773%) at 2.0V~3.6V, Temperature = 0/c176C ~ +50/c176C /c18310 bidirectional I/O lines /c1836 Schmitt trigger input lines (PB7 without Pull-high resistor) /c183One programmable carrier output - using 9-bit timer /c183On-chip RC oscillator - 4MHz /c1773% when VDD=2.0V~3.6V; Temperature = 0/c176C ~ +50/c176C /c183Watchdog Timer /c1831K/c18014 program memory /c18332/c1808 data RAM /c183Power-down and wake-up features reduce power consumption /c18362 powerful instructions /c183Up to 1/c109s instruction cycle with 4MHz system clock /c183All instructions executed in 1 or 2 machine cycles /c18314-bit table read instructions /c183One-level subroutine nesting /c183Bit manipulation instructions /c183Low voltage reset function /c18320-pin SOP/SSOP package General Description The HT48RA0-3/HT48CA0-3 are 8-bit high perfor- mance, RISC architecture microcontroller devices spe- cifically designed for multiple I/O control product applications. The mask version HT48CA0-3 is fully pin and functionally compatible with the OTP version HT48RA0-3 device. The advantages of low power consumption, I/O flexibil- ity, timer functions, watchdog timer, HALT and wake-up functions, as well as low cost, enhance the versatility of this device to suit a wide range of application possibili - ties such as industrial control, consumer products, and particularly suitable for use in products such as infrared remote controllers and various subsystem controllers. Technical Document /c183Tools Information /c183FAQs /c183Application Note /c45HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series /c45HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series /c45HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals /c45HA0075E MCU Reset and Oscillator Circuits Application Note /c45HA0076E HT48RAx/HT48CAx Software Application Note /c45HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing

Rev.1.10 2 October 12, 2007 /G50 /G41 /G32 /G50 /G41 /G33 /G50 /G41 /G34 /G50 /G41 /G35 /G50 /G41 /G36 /G50 /G41 /G37 /G50 /G42 /G32 /G50 /G42 /G33 /G50 /G42 /G34 /G50 /G42 /G35 /G50 /G41 /G31 /G50 /G41 /G30 /G50 /G42 /G31 /G50 /G42 /G30 /G52 /G45 /G4D /G56 /G53 /G53 /G50 /G42 /G36 /G4F /G53 /G43 /G31 /G56 /G44 /G44 /G50 /G42 /G37 /G32 /G30 /G31 /G39 /G31 /G38 /G31 /G37 /G31 /G36 /G31 /G35 /G31 /G34 /G31 /G33 /G31 /G32 /G31 /G31 /G31 /G32 /G33 /G34 /G35 /G36 /G37 /G38 /G39 /G31 /G30 /G48 /G54 /G34 /G38 /G52 /G41 /G30 /G2D /G33 /G2F /G48 /G54 /G34 /G38 /G43 /G41 /G30 /G2D /G33 /G32 /G30 /G20 /G53 /G4F /G50 /G2D /G41 /G2F /G53 /G53 /G4F /G50 /G2D /G41 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G49 /G6E /G73 /G74 /G72 /G75 /G63 /G74 /G69 /G6F /G6E /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G49 /G6E /G73 /G74 /G72 /G75 /G63 /G74 /G69 /G6F /G6E /G44 /G65 /G63 /G6F /G64 /G65 /G72 /G54 /G69 /G6D /G69 /G6E /G67 /G47 /G65 /G6E /G65 /G72 /G61 /G74 /G6F /G72 /G4F /G53 /G43 /G31 /G56 /G44 /G44 /G56 /G53 /G53 /G4D /G50 /G4D /G55 /G58 /G4D /G55 /G58 /G44 /G41 /G54 /G41 /G4D /G65 /G6D /G6F /G72 /G79 /G41 /G4C /G55 /G53 /G68 /G69 /G66 /G74 /G65 /G72 /G53 /G54 /G41 /G54 /G55 /G53 /G41 /G43 /G43 /G50 /G41 /G50 /G4F /G52 /G54 /G20 /G41 /G50 /G41 /G30 /G7E /G50 /G41 /G37 /G50 /G42 /G50 /G42 /G32 /G7E /G50 /G42 /G37 /G53 /G54 /G41 /G43 /G4B /G52 /G45 /G4D /G50 /G4F /G52 /G54 /G20 /G42 /G50 /G42 /G30 /G7E /G50 /G42 /G31 /G39 /G2D /G62 /G69 /G74 /G20 /G54 /G69 /G6D /G65 /G72 /G43 /G61 /G72 /G72 /G69 /G65 /G72 /G47 /G65 /G6E /G65 /G72 /G61 /G74 /G6F /G72 /G57 /G44 /G54 /G46 /G72 /G65 /G71 /G75 /G65 /G6E /G63 /G79 /G44 /G69 /G76 /G69 /G64 /G65 /G72 /G66 /G53 /G59 /G53 /G2F /G34

Pin Name I/O Configuration Option Description PA0~PA7 I/O /c190 Bidirectional 8-bit input/output port with pull-high resistors. Software instructions determine if the pin is an NMOS output or Schmitt Trigger input. PB0, PB1 I/O Wake-up Bidirectional 2-bit input/output lines with pull-high resistors. Each individual bit can be configured as a wake-up input by a configuration option. Software in - structions determine if the pin is an NMOS output or Schmitt Trigger input. PB2~PB6 I Wake-up 5-bit Schmitt Trigger input lines with pull-high resistors. Each individual bit can be configured as a wake-up input by a configuration option. PB7 I Wake-up 1-bit Schmitt trigger input lines without pull-high resistor. This bit can be config- ured as a wake-up input by a configuration option. REM O /c190 Carrier output pin. OSC1 I /c190 OSC1 is connected to an external resistor for the internal system clock. VDD /c190/c190 Positive power supply VSS /c190 /c190 Negative power supply, ground Absolute Maximum Ratings Note: These are stress ratings only. Stresses exceeding the range specified under/c178Absolute Maximum Ratings/c178may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. D.C. Characteristics Ta=25/c176C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VDD Operating Voltage /c190/c190 2.0 /c190 3.6 V IDD Operating Current 3V No load, fSYS=4MHz /c190 0.7 1.5 mA ISTB Standby Current 3V No load, system HALT /c190/c190 1 /c109A VIL Input Low Voltage for I/O Ports 3V /c190 0 /c1900.2VDD V VIH Input High Voltage for I/O Ports 3V /c190 0.8VDD /c190 VDD V VLVR Low Voltage Reset Voltage /c190/c190 1.8 1.9 2.0 V IOL I/O Ports Sink Current 3V VOL=0.1VDD 48 /c190 mA IOH REM Output Source Current 3V VOH=0.9VDD /c455 /c457 /c190 mA RPH Pull-high Resistance 3V /c190 100 150 200 k/c87 VPOR VDD Start Voltage to ensure Power-on Reset /c190/c190 /c190 /c190 100 mV RPOR VDD Rise Rate to ensure Power-on Reset /c190/c190 0.035 /c190/c190 V/ms HT48RA0-3/HT48CA0-3 Rev.1.10 3 October 12, 2007

A.C. Characteristics Ta=25/c176C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS System Clock 3V fSYS=4MHz(/c1773%) , Temp. = 0/c176C ~ +50/c176C 3880 4000 4120 kHz tSST System Start-up Timer Period /c190Power-up, reset or wake-up from HALT /c1901024 /c190 tSYS tLVR Low Voltage Width to Reset /c190/c190 0.25 1 2 ms tPOR Power-on Reset Low Pulse Width /c190/c190 1 /c190/c190/c109s Note: tSYS=1/fSYS HT48RA0-3/HT48CA0-3 Rev.1.10 4 October 12, 2007 Functional Description Execution Flow The HT48RA0-3/HT48CA0-3 system clock is an RC type clock which requires the connection of an external resistor for its operation. It is internally divided into four non-overlapping clocks. One instruction cycle consists of four system clock cycles. Instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. However, the pipelining scheme causes each instruc- tion to effectively execute within one cycle. If an instruc- tion changes the program counter, two cycles are required to complete the instruction. Program Counter /c45PC The 10-bit program counter (PC) controls the sequence in which the instructions stored in program memory are executed and its contents specify a maximum of 1024 addresses. After accessing a program memory word to fetch an in- struction code, the contents of the program counter are incremented by one. The program counter then points to the memory word containing the next instruction code. When executing a jump instruction, conditional skip ex- ecution, loading PCL register, subroutine call, initial re- set or return from subroutine, the PC manipulates the program transfer by loading the address corresponding to each instruction. /G54 /G31 /G54 /G32 /G54 /G33 /G54 /G34 /G54 /G31 /G54 /G32 /G54 /G33 /G54 /G34 /G54 /G31 /G54 /G32 /G54 /G33 /G54 /G34 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G4E /G53 /G54 /G20 /G28 /G50 /G43 /G29 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G4E /G53 /G54 /G20 /G28 /G50 /G43 /G2D /G31 /G29 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G4E /G53 /G54 /G20 /G28 /G50 /G43 /G2B /G31 /G29 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G4E /G53 /G54 /G20 /G28 /G50 /G43 /G29 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G4E /G53 /G54 /G20 /G28 /G50 /G43 /G2B /G32 /G29 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G4E /G53 /G54 /G20 /G28 /G50 /G43 /G2B /G31 /G29 /G50 /G43 /G50 /G43 /G2B /G31 /G50 /G43 /G2B /G32 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G43 /G6C /G6F /G63 /G6B /G49 /G6E /G73 /G74 /G72 /G75 /G63 /G74 /G69 /G6F /G6E /G20 /G43 /G79 /G63 /G6C /G65 /G50 /G43 Execution Flow Mode Program Counter Initial reset 0000000000 Skip Program Counter + 2 Return from subroutine S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: *9~*0: Program counter bits S9~S0: Stack register bits #9~#0: Instruction code bits @7~@0: PCL bits

Rev.1.10 5 October 12, 2007 The conditional skip is activated by instruction. Once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. Otherwise proceed with the next instruction. The lower byte of the program counter (PCL) is a read- able and writeable register (06H). Moving data into the PCL performs a short jump. The destination will be within 256 locations. When a control transfer takes place, an additional dummy cycle is required. Program Memory /c45ROM The program memory is used to store the program in - structions which are to be executed. It also contains data and table and is organized into 1024 /c18014 bits, ad- dressed by the program counter and table pointer. Certain locations in the program memory are reserved for special usage: /c183Location 000H This area is reserved for the initialization program. Af- ter a device reset, the program always begins execu- tion at location 000H. /c183Table location Any location in the Program Memory space can be used as a look-up table. The instructions TABRDC [m] (the current page, one page=256 words) and TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified data memory register, and the higher-order byte to TBLH (08H). Only the destination of the lower-order byte in the ta- ble is well-defined, the other bits of the table word are transferred to the lower portion of TBLH, the remain - ing 2 bits are read as/c1780/c178. The Table Higher-order byte register (TBLH) is read only. The table pointer (TBLP) is a read/write register (07H), where P indicates the table location. Before accessing the table, the location must be placed in TBLP. The TBLH is read only and cannot be restored. All table related instructions need 2 cycles to complete the operation. These areas may function as normal program memory depending upon the requirements. Stack Register /c45STACK This is a special part of the memory used to save the contents of the program counter only. The stack is orga- nized into one level and is neither part of the data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the stack pointer and is neither readable nor writeable. At a sub - routine call the contents of the program counter are pushed onto the stack. At the end of a subroutine sig - naled by a return instruction, RET, the program counter is restored to its previous value from the stack. After a chip reset, the SP will point to the top of the stack. If the stack is full and a /c178CALL/c178is subsequently exe - cuted, stack overflow occurs and the first entry will be lost and only the most recent return address is stored. Data Memory /c45RAM The data memory is divided into two functional groups: special function registers and general purpose data memory (32/c1808). Most are read/write, but some are read only. The remaining space before the 20H is reserved for fu- ture expanded usage and reading these locations will return the result 00H. The general purpose data mem - ory, addressed from 20H to 3FH, is used for data and control information under instruction command. All data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions, respec- tively. They are also indirectly accessible through memory pointer register (MP;01H). /G30 /G30 /G30 /G48 /G44 /G65 /G76 /G69 /G63 /G65 /G20 /G69 /G6E /G69 /G74 /G69 /G61 /G6C /G69 /G7A /G61 /G74 /G69 /G6F /G6E /G20 /G70 /G72 /G6F /G67 /G72 /G61 /G6D /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G31 /G34 /G20 /G62 /G69 /G74 /G73 /G4C /G6F /G6F /G6B /G2D /G75 /G70 /G20 /G74 /G61 /G62 /G6C /G65 /G20 /G28 /G32 /G35 /G36 /G20 /G77 /G6F /G72 /G64 /G73 /G29 /G6E /G30 /G30 /G48 /G4C /G6F /G6F /G6B /G2D /G75 /G70 /G20 /G74 /G61 /G62 /G6C /G65 /G20 /G28 /G32 /G35 /G36 /G20 /G77 /G6F /G72 /G64 /G73 /G29 /G33 /G46 /G46 /G48 /G6E /G46 /G46 /G48 Program Memory Instruction(s) Table Location TABRDC [m] P9 P8 @7 @6 @5 @4 @3 @2 @1 @0 Table Location Note: *9~*0: Table location bits @7~@0: Table pointer bits P9~P8: Current program counter bits

Rev.1.10 6 October 12, 2007 Indirect Addressing Register Location 00H is an indirect addressing register that is not physically implemented. Any read/write operation to [00H] accesses the data memory pointed to by MP (01H). Reading location 00H itself indirectly will return the result 00H. Writing indirectly results in no operation. The memory pointer register MP (01H) is a 7-bit register. Bit 7 of MP is undefined and reading will return the result /c1781/c178. Any writing operation to MP will only transfer the lower 7-bits of data to MP. Accumulator The accumulator closely relates to ALU operations. It is also mapped to location 05H of the data memory and is capable of carrying out immediate data operations. Data movement between two data memory locations has to pass through the accumulator. Arithmetic and Logic Unit /c45ALU This circuit performs 8-bit arithmetic and logic operation. The ALU provides the following functions. /c183Arithmetic operations (ADD, ADC, SUB, SBC, DAA) /c183Logic operations (AND, OR, XOR, CPL) /c183Rotation (RL, RR, RLC, RRC) /c183Increment and Decrement (INC, DEC) /c183Branch decision (SZ, SNZ, SIZ, SDZ ....) The ALU not only saves the results of a data operation but also changes the contents of the status register. Status Register /c45STATUS This 8-bit status register (0AH) contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF) and watchdog time-out flag (TO). It also records the status information and con- trols the operation sequence. /G53 /G70 /G65 /G63 /G69 /G61 /G6C /G20 /G50 /G75 /G72 /G70 /G6F /G73 /G65 /G44 /G61 /G74 /G61 /G20 /G4D /G65 /G6D /G6F /G72 /G79 /G49 /G41 /G52 /G4D /G50 /G41 /G43 /G43 /G50 /G43 /G4C /G54 /G42 /G4C /G50 /G54 /G42 /G4C /G48 /G53 /G54 /G41 /G54 /G55 /G53 /G50 /G41 /G50 /G42 /G54 /G53 /G52 /G30 /G54 /G53 /G52 /G31 /G43 /G41 /G52 /G4C /G30 /G43 /G41 /G52 /G4C /G31 /G43 /G41 /G52 /G48 /G30 /G43 /G41 /G52 /G48 /G31 /G47 /G65 /G6E /G65 /G72 /G61 /G6C /G20 /G50 /G75 /G72 /G70 /G6F /G73 /G65 /G44 /G61 /G74 /G61 /G20 /G4D /G65 /G6D /G6F /G72 /G79 /G28 /G33 /G32 /G20 /G42 /G79 /G74 /G65 /G73 /G29 /G3A /G20 /G55 /G6E /G75 /G73 /G65 /G64 /G52 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G30 /G22 /G32 /G30 /G48 /G30 /G30 /G48 /G30 /G31 /G48 /G30 /G32 /G48 /G30 /G33 /G48 /G30 /G34 /G48 /G30 /G35 /G48 /G30 /G36 /G48 /G30 /G37 /G48 /G30 /G38 /G48 /G30 /G39 /G48 /G30 /G41 /G48 /G30 /G42 /G48 /G30 /G43 /G48 /G30 /G44 /G48 /G30 /G45 /G48 /G30 /G46 /G48 /G31 /G30 /G48 /G31 /G31 /G48 /G31 /G32 /G48 /G31 /G33 /G48 /G31 /G34 /G48 /G31 /G35 /G48 /G31 /G36 /G48 /G31 /G37 /G48 /G31 /G38 /G48 /G31 /G39 /G48 /G31 /G41 /G48 /G31 /G42 /G48 /G31 /G43 /G48 /G31 /G44 /G48 /G31 /G45 /G48 /G31 /G46 /G48 /G33 /G46 /G48 RAM Mapping Bit No. Label Function C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C is also affected by a ro- tate through carry instruction. 1A C AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise AC is cleared. 2 Z Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared. 3O V OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. 4 PDF PDF is cleared when either a system power-up or executing the CLR WDT instruction. PDF is set by executing the HALT instruction. 5T O TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out. 6~7 /c190 Unused bit, read as /c1780/c178 Status (0AH) Register

Rev.1.10 7 October 12, 2007 With the exception of the TO and PDF flags, the other status register bits can be altered by instructions like most other register. Any data written into the status regis- ter will not change the TO or PDF flags. In addition it should be noted that operations related to the status reg- ister may give different results from those intended. The TO and PDF flags can only be changed by the Watchdog Timer overflow, device power-up, clearing the Watchdog Timer and executing the HALT instruction. The Z, OV, AC and C flags generally reflect the status of the latest operations. In addition, on executing a subroutine call, the status register will not be automatically pushed onto the stack. If the contents of the status are important and if the sub- routine can corrupt the status register, precautions must be taken to save it properly. Oscillator Configuration Only an external RC oscillator type is supported for the HT48RA0-3/HT48CA0-3. An external resistor between OSC1 and VSS in needed whose resistance must be 12k/c87for a 4MHz frequency. The RC oscillator provides /c1773% accuracy, the condi- tions are: /c183VDD= 2.0V ~ 3.6V /c183Temperature = 0/c176C ~ +50/c176C /c183fSYS= 4MHz Watchdog Timer /c45WDT The WDT clock source is implemented by the instruction clock which is the system clock divided by 4. The clock source is processed by a frequency divider and a prescaler to provide various time out periods. WDT time out period = Clock Source Where n= 8~11 selected by a configuration option. The WDT timer is designed to prevent a software mal - function or sequence jumping to an unknown location with unpredictable results. The Watchdog Timer can be disabled by configuration option. If the Watchdog Timer is disabled, all the executions related to the WDT result in no operation and the WDT will lose its protection pur- pose. In this situation the logic can only be restarted by external logic. A WDT overflow under normal operation will initialise a /c178chip reset/c178and set the status bit/c178TO/c178. To clear the con- tents of the WDT prescaler, two methods are adopted, software instructions or a HALT instruction. There are two types of software instructions. One type is the single in- struction /c178CLR WDT/c178, the other type comprises two in - structions,/c178CLR WDT1/c178and /c178CLR WDT2/c178. Of these two types of instructions, only one can be active depending on the configuration option/c45/c178CLR WDT times selection op- tion/c178.I ft h e/c178CLR WDT/c178is selected (i.e..CLR WDT times equal one), any execution ofthe CLR WDTinstruction will clear the WDT. In case/c178CLR WDT1/c178and/c178CLR WDT2/c178are chosen (i.e.. CLR WDT times equal two), these two in- structions must be executed to clear the WDT; otherwise, the WDT may reset the chip due to a time-out. /G52 /G43 /G20 /G4F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G6F /G72 /G4F /G53 /G43 /G31 /G31 /G32 /G6B /G57 System Oscillator /G32 /G6E /G43 /G6C /G6F /G63 /G6B /G20 /G53 /G6F /G75 /G72 /G63 /G65 /G28 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G43 /G6C /G6F /G63 /G6B /G2F /G34 /G29 /G33 /G2D /G62 /G69 /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G50 /G72 /G65 /G73 /G63 /G61 /G6C /G6C /G65 /G72 /G28 /G38 /G2D /G62 /G69 /G74 /G29 /G57 /G44 /G54 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G43 /G6F /G64 /G65 /G20 /G4F /G70 /G74 /G69 /G6F /G6E /G53 /G65 /G6C /G65 /G63 /G74 /G43 /G6F /G64 /G65 /G4F /G70 /G74 /G69 /G6F /G6E /G43 /G6C /G65 /G61 /G72 /G20 /G57 /G44 /G54 /G46 /G72 /G65 /G71 /G75 /G65 /G6E /G63 /G79 /G20 /G44 /G69 /G76 /G69 /G64 /G65 /G72 /G43 /G6C /G6F /G63 /G6B /G20 /G53 /G6F /G75 /G72 /G63 /G65 /G28 /G6E /G3D /G38 /G7E /G31 /G31 /G29 Watchdog Timer

Rev.1.10 8 October 12, 2007 Power Down Operation /c45HALT The Power-down mode is initialised by the HALT in - struction and results in the following: /c183The system oscillator turns off and the WDT stops. /c183The contents of the on-chip Data Memory and regis - ters remain unchanged. /c183WDT prescaler is cleared. /c183All I/O ports maintain their original status. /c183The PDF flag is set and the TO flag is cleared. The system can quit the HALT mode by means of an ex- ternal falling edge signal on port B. By examining the TO and PDF flags, the reason for chip reset can be deter - mined. The PDF flag is cleared when the system powers up or when a CLR WDT instruction is executed and is set when the HALT instruction is executed. The TO flag is set if the WDT time-out occurs during normal operation. The port B wake-up can be considered as a continuation of normal execution. Each bit in port B can be independ- ently selected to wake up the device by the code option. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. Once a wake-up event(s) occurs, it takes 1024 t SYS (system clock periods) to resume normal operation. In other words, a dummy cycle period will be inserted after the wake-up. To minimize power consumption, all I/O pins should be carefully managed before entering the HALT status. Reset There are three ways in which a reset can occur: /c183Power On reset /c183Low Voltage reset /c183WDT time-out reset during normal operation Some registers remain unchanged during reset condi - tions. Most registers are reset to the /c178initial condition/c178 when the reset conditions are met. By examining the PDF and TO flags, the program can distinguish between different chip resets. TO PDF RESET Conditions 0 0 Power-on reset during power-up u u LVR reset during normal operation 1 u WDT time-out during normal operation Note: /c178u/c178means unchanged. To guarantee that the system oscillator has started and stabilized, the SST (System Start-up Timer) provides an extra-delay of 1024 system clock pulses when the sys- tem powers up or when the system awakes from a HALT state. When a system power up occurs, an SST delay is added during the reset period. Any wake-up from HALT will en- able the SST delay. The functional unit chip reset status is shown below. Program Counter 000H WDT Prescaler Clear Input/Output ports Input mode Stack Pointer Points to the top of the stack Carrier output Low level /G57 /G44 /G54 /G43 /G6F /G6C /G64 /G20 /G52 /G65 /G73 /G65 /G74 /G48 /G41 /G4C /G54 /G50 /G6F /G77 /G65 /G72 /G2D /G6F /G6E /G20 /G44 /G65 /G74 /G65 /G63 /G74 /G69 /G6F /G6E /G53 /G53 /G54 /G31 /G30 /G2D /G73 /G74 /G61 /G67 /G65 /G52 /G69 /G70 /G70 /G6C /G65 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G4F /G53 /G43 /G31 /G4C /G56 /G52 Reset Configuration /G74 /G52 /G53 /G54 /G44 /G50 /G6F /G77 /G65 /G72 /G2D /G6F /G6E /G20 /G52 /G65 /G73 /G65 /G74 /G56 /G44 /G44 /G53 /G53 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G49 /G6E /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G20 /G52 /G65 /G73 /G65 /G74 Reset Timing Chart

Rev.1.10 9 October 12, 2007 Input/Output Ports There are an 8-bit bidirectional input/output port, a 6-bit input with 2-bit I/O port in the HT48RA0-3/HT48CA0-3, labeled PA and PB which are mapped to [12H], [14H] of the Data Memory, respectively. Each bit of PA can be se- lected as NMOS output or Schmitt trigger input with pull-high resistor by a software instruction. PB0~PB1 have the same structure as PA, while PB2~PB6 can only be used for input operation - Schmitt trigger with pull-high resistors. PB7 is used for input operation - Schmitt trigger but without pull-high resistor. When PA and PB are used for input operation, these ports are non-latched, that is, the inputs should be ready at the T2 rising edge of the instruction /c178MOV A, [m] /c178 (m=12H or 14H). For PA and PB0~PB1 output opera - tion, all data is latched and remains unchanged until the output latch is rewritten. When PA and PB0~PB1 is used for input operation, it should be noted that before reading data from the pads, a /c1781/c178should be written to the related bits to disable the NMOS device. That is, the instruction/c178SET [m].i/c178(i=0~7 for PA, i=0~1 for PB) is executed first to disable related NMOS device, and then/c178MOV A, [m]/c178to get stable data. After chip reset, PA and PB remain at a high level input line. Each bit of PA and PB0~PB1 output latches can be set or cleared by the /c178SET [m].i /c178and /c178CLR [m].i /c178 (m=12H or 14H) instructions respectively. Some instructions first input data and then follow the output operations. For example,/c178SET [m].i/c178, /c178CLR [m]/c178, /c178CPL [m]/c178, /c178CPLA [m]/c178read the entire port states into the CPU, execute the defined operations (bit-operation), and then write the results back to the latches or to the accumulator. Each line of PB has a wake-up capability selectable via a configuration option. The chip reset status of the registers is summarised in the following table: Register Power On Low Voltage Reset WDT Time-out (Normal Operation) Program Counter 000H 000H 000H MP -xxx xxxx -uuu uuuu -uuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu TBLP xxxx xxxx uuuu uuuu uuuu uuuu TBLH --xx xxxx --uu uuuu --uu uuuu STATUS --00 xxxx --uu uuuu --1u uuuu PA 1111 1111 1111 1111 1111 1111 PB 1111 1111 1111 1111 1111 1111 TSR0 0000 0000 0000 0000 0000 0000 TSR1 1000 0000 1000 0000 1000 0000 CARL0 0000 0000 0000 0000 0000 0000 CARL1 0000 0000 0000 0000 0000 0000 CARH0 0000 0000 0000 0000 0000 0000 CARH1 0000 0010 0000 0010 0000 0010 Note: /c178u/c178means unchanged /c178x/c178means unknown /c178-/c178stands for unimplemented

Rev.1.10 10 October 12, 2007 /G52 /G65 /G61 /G64 /G20 /G44 /G61 /G74 /G61 /G56 /G44 /G44 /G50 /G75 /G6C /G6C /G2D /G75 /G70 /G50 /G42 /G32 /G7E /G50 /G42 /G36 /G44 /G61 /G74 /G61 /G20 /G62 /G75 /G73 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G57 /G61 /G6B /G65 /G2D /G75 /G70 /G43 /G6F /G64 /G65 /G20 /G4F /G70 /G74 /G69 /G6F /G6E PB2~PB6 Input Lines /G44 /G61 /G74 /G61 /G20 /G42 /G75 /G73 /G52 /G65 /G61 /G64 /G20 /G44 /G61 /G74 /G61 /G50 /G42 /G37 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G57 /G61 /G6B /G65 /G2D /G75 /G70 /G43 /G6F /G64 /G65 /G20 /G4F /G70 /G74 /G69 /G6F /G6E PB7 Input Line Timer The timer is an internal unit for creating a remote control transmission pattern. As shown, it consists of a 9-bit down counter (t8 to t0), a flag (t9) permitting the 1-bit timer output, and a zero detector. No. Label Function 0~7 t0~t7 Down counter TSR0 (18H) Register No. Label Function 0 t8 Down counter 1t 9 Timer enable, initial value is /c1780/c178. 2~6 /c190Unused bit, read as /c1780/c178.

7 TOEF Timer operation end flag, initial

value is /c1781/c178. TSR1 (19H) Register Timer Operation The timer starts counting down when a value other than /c1780/c178is set for the down counter with a timer manipulation instruction. The timer manipulation instructions for mak- ing the timer start operation are shown below: MOV A,XXH ; XX = 00H ~ FFH MOV TSR0,A MOV A,XXH ; XX /c16301H, t8 MOV TSR1,A SET TSR1.1 ; The timer is started by set t9=1 Addition notes for the 9-bit timer: /c183Writing to TSR0 will only put the written data to the TSR0 register (t7~t0) and writing to TSR1 (t8) will transfer the specified data and contents of TSR0 to the Down Counter. TOEF will be cleared after the data transferred from TSR1 and TSR0 to the Down Coun- ter is completed and then wait until TSR1.1 is set by user. /c183Setting TSR1.1=1, the timer will start counting. The timer will stop when its count is equal to /c1780/c178and then TOEF is set equal to /c1781/c178. /G51 /G44 /G43 /G4B /G53 /G51 /G44 /G61 /G74 /G61 /G20 /G62 /G75 /G73 /G57 /G72 /G69 /G74 /G65 /G43 /G68 /G69 /G70 /G20 /G52 /G65 /G73 /G65 /G74 /G52 /G65 /G61 /G64 /G20 /G44 /G61 /G74 /G61 /G57 /G65 /G61 /G6B /G50 /G75 /G6C /G6C /G2D /G75 /G70 /G50 /G41 /G30 /G7E /G50 /G41 /G37 /G50 /G42 /G30 /G7E /G50 /G42 /G31 /G56 /G44 /G44 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G57 /G61 /G6B /G65 /G2D /G75 /G70 /G43 /G6F /G64 /G65 /G20 /G4F /G70 /G74 /G69 /G6F /G6E /G50 /G42 /G30 /G7E /G50 /G42 /G31 /G20 /G6F /G6E /G6C /G79 PA, PB0~PB1 Input/Output Lines

Rev.1.10 11 October 12, 2007 /c183If the TSR1.1 is cleared during the timer counting, the timer will be stopped. Once the TSR1.1 is set (1/c1740/c1741), the down counter will reload data from t8~t0, and then the down counter begins counting down with the new load data. /c183If TSR1.1 and TOEF are equal to 1 both, the timer can re-start, after new data is written to TSR0, TSR1 (t0~t8) in sequence. Note: If the contents of the Down counter is 000H, set the t9 to start the timer counting, the timer will only count 1 step. The timer output time=64/f SYS. /c174[ (0+1) /c18064/fSYS=64/fSYS ] The down counter is decremented ( /c451) in the cycle of 64/fSYS. If the value of the down counter becomes /c1780/c178, the zero detector generates the timer operation end sig- nal to stop the timer operation. At this time, TOEF will be set to /c1781/c178. The output of the timer operation end signal is continued while the down counter is/c1780/c178and the timer is stopped. The following relational expression applies be- tween the timer /c162s output time and the down counter /c162s set value. Timer output time = (Set value+1) /c18064/f SYS An example is shown below. MOV A,0FFH MOV TSR0,A MOV A,01H MOV TSR1,A SET TSR1.1 In the case above, the timer output time is as follows. (Set value+1) /c18064/f SYS = 8.192ms By setting the flag (t9) that enables the timer output to /c1781/c178, the timer can output its operation status from the REM pin. The REM pin can also output the carrier while the timer is in operation. Note: The carrier output results if bit 9 of the high-level period setting modulo register (CARH) is cleared (/c1780/c178). /G74 /G39 /G74 /G38 /G74 /G37 /G74 /G36 /G74 /G35 /G74 /G34 /G74 /G33 /G74 /G32 /G74 /G31 /G74 /G30 /G44 /G6F /G77 /G6E /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G2C /G20 /G28 /G74 /G38 /G7E /G74 /G30 /G29 /G2B /G31 /G5A /G65 /G72 /G6F /G20 /G44 /G65 /G74 /G65 /G63 /G74 /G6F /G72 /G43 /G61 /G72 /G72 /G69 /G65 /G72 /G53 /G79 /G6E /G63 /G68 /G72 /G6F /G6E /G6F /G75 /G73 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G43 /G61 /G72 /G72 /G69 /G65 /G72 /G20 /G53 /G69 /G67 /G6E /G61 /G6C /G66 /G53 /G59 /G53 /G2F /G36 /G34 /G74 /G39 /G43 /G6F /G75 /G6E /G74 /G43 /G6C /G6F /G63 /G6B /G54 /G4F /G45 /G46 /G52 /G45 /G4D /G74 /G53 /G52 /G31 /G74 /G53 /G52 /G30 Timer Configuration /G52 /G45 /G4D /G38 /G2E /G31 /G39 /G32 /G6D /G73 /G52 /G45 /G4D /G54 /G69 /G6D /G65 /G72 /G20 /G4F /G75 /G74 /G70 /G75 /G74 /G20 /G54 /G69 /G6D /G65 /G3A /G28 /G53 /G65 /G74 /G20 /G76 /G61 /G6C /G75 /G65 /G2B /G31 /G29 /G20 /G78 /G20 /G36 /G34 /G2F /G66 /G53 /G59 /G53 Timer Output when Carrier is not Output

Rev.1.10 12 October 12, 2007 Carrier Output /c183Carrier output generator The carrier generator consists of a 9-bit counter and two modulo registers for setting the high-level and low-level peri- ods - CARH and CARL respectively. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 CARL1 /c190/c190/c190/c190/c190/c190 Fix /c1780/c178CL.8 CARH1 /c190/c190/c190/c190/c190/c190 CH.9 (CARY) CH.8 CARL0 (1AH) Register, CARL1 (1BH), CARH0 (1CH) Register, CARH1 (1DH), Register Note: 1. CARH1.1 (CARY) initial value is /c1781/c178. The carrier duty ratio and carrier frequency can be determined by setting the high-level and low-level widths using the respective modulo registers. Each of these widths can be set in a range of 500ns to 64/c109sa tf SYS = 4MHz. structions. Example: MOV A,XXH ; XXH = 00H~FFH MOV CARL0,A MOV A,XXH ; XXH /c16301H, CL.8 (CARL1.0) MOV CARL1,A MOV A,XXH ; XXH = 00H~FFH MOV CARH0,A MOV A,XXH ; XXH /c17902H, CH.8 (CARH1.0) MOV CARH1,A CLR CARH1.1 ; The carrier is started by clearing CARY(CARH1.1)= /c1780/c178 /G53 /G65 /G6C /G65 /G63 /G74 /G6F /G72 /G43 /G6F /G6D /G70 /G61 /G72 /G61 /G74 /G6F /G72 /G66 /G53 /G59 /G53 /G74 /G39 /G20 /G28 /G4E /G6F /G74 /G65 /G20 /G32 /G29 /G43 /G41 /G52 /G4C /G31 /G43 /G41 /G52 /G4C /G30 /G39 /G2D /G62 /G69 /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G66 /G53 /G59 /G53 /G43 /G4C /G2E /G39 /G28 /G30 /G29 /G4E /G6F /G74 /G65 /G20 /G31 /G2E /G43 /G4C /G2E /G38 /G43 /G4C /G2E /G37 /G43 /G4C /G2E /G36 /G43 /G4C /G2E /G35 /G43 /G4C /G2E /G34 /G43 /G4C /G2E /G33 /G43 /G4C /G2E /G32 /G43 /G4C /G2E /G31 /G43 /G4C /G2E /G30 /G4D /G6F /G64 /G75 /G6C /G6F /G20 /G72 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G20 /G66 /G6F /G72 /G20 /G73 /G65 /G74 /G74 /G69 /G6E /G67 /G20 /G74 /G68 /G65 /G20 /G6C /G6F /G77 /G2D /G6C /G65 /G76 /G65 /G6C /G20 /G70 /G65 /G72 /G69 /G6F /G64 /G28 /G43 /G41 /G52 /G4C /G2E /G38 /G7E /G43 /G41 /G52 /G4C /G2E /G30 /G29 /G43 /G41 /G52 /G4C /G43 /G41 /G52 /G48 /G31 /G43 /G41 /G52 /G48 /G30 /G43 /G48 /G2E /G39 /G43 /G41 /G52 /G59 /G43 /G48 /G2E /G38 /G43 /G48 /G2E /G37 /G43 /G48 /G2E /G36 /G43 /G48 /G2E /G35 /G43 /G48 /G2E /G34 /G43 /G48 /G2E /G33 /G43 /G48 /G2E /G32 /G43 /G48 /G2E /G31 /G43 /G48 /G2E /G30 /G4D /G6F /G64 /G75 /G6C /G6F /G20 /G72 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G20 /G66 /G6F /G72 /G20 /G73 /G65 /G74 /G74 /G69 /G6E /G67 /G20 /G74 /G68 /G65 /G20 /G68 /G69 /G67 /G68 /G2D /G6C /G65 /G76 /G65 /G6C /G20 /G70 /G65 /G72 /G69 /G6F /G64 /G28 /G43 /G41 /G52 /G48 /G2E /G38 /G7E /G43 /G41 /G52 /G48 /G2E /G30 /G29 /G43 /G41 /G52 /G48 /G46 /G2F /G46 /G43 /G61 /G72 /G72 /G69 /G65 /G72 /G53 /G69 /G67 /G6E /G61 /G6C /G4D /G61 /G74 /G63 /G68 /G43 /G6C /G65 /G61 /G72 Configuration of Remote Controller Carrier Generator Note: 1. Bit 9 of the modulo register for setting the low-level period (CARL) is fixed to /c1780/c178. 2. t9: Flag that enables timer output (timer block, see Timer Configuration)

Rev.1.10 13 October 12, 2007 The values of CARH and CARL can be calculated from the following expressions. CARL (CARL1.0, CARL0.7~CARL0.0) = ( fSYS /c180(1/c45D) /c180T) /c451 CARH (CARH1.0, CARH0.7~CARH0.0) = ( f SYS /c180D /c180T) /c451 D: Carrier duty ratio (0<D<1 ) fSYS: Input clock (Mhz) T: Carrier cycle (/c109s) Ensure to input values in the range of 001H to 1FFH to CARL and CARH. Example: fSYS = 4MHz, fc = 38.1kHz, T = 1/ fc = 26.25/c109s, duty = 1/3 CARL = (4M /c180(1/c451/3) /c18026.25/c109s) /c451=6 9=4 5 H CARH = (4M /c1801/3 /c18026.25/c109s) /c451=3 4=2 2 H MOV A,045H MOV CARL0,A MOV A,022H MOV CARH0,A CLR CARH1.1 ; The carrier is started by clearing CARY(CARH1.1) = /c1780/c178 /c183Carrier output control The remote controller carrier can be output from the REM pin by clearing (0) bit 9 (CARY) of the modulo register for setting the high-level period (CARH). When performing a carrier output, be sure to set the timer operation after setting the CARH (CARH1.0, Note that a malfunction may occur if the values of CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0) are changed while the carrier is being output from the REM pin. Executing the timer manipulation instruction starts the carrier output from the low level. /G54 /G69 /G6D /G65 /G72 /G20 /G4F /G75 /G74 /G70 /G75 /G74 /G74 /G4C /G74 /G48 /G43 /G61 /G72 /G72 /G69 /G65 /G72 /G53 /G65 /G65 /G20 /G4E /G6F /G74 /G65 /G54 /G69 /G6D /G65 /G72 /G20 /G4F /G75 /G74 /G70 /G75 /G74 /G20 /G54 /G69 /G6D /G65 /G3A /G28 /G53 /G65 /G74 /G20 /G76 /G61 /G6C /G75 /G65 /G2B /G31 /G29 /G20 /G78 /G20 /G36 /G34 /G2F /G66 /G53 /G59 /G53 Timer Output when Carrier Is an Output Note: When the carrier signal is active and during the time when the signal is high, if the timer output should go low, the carrier signal will first complete its high level period before going low.

Rev.1.10 14 October 12, 2007 The output from the REM pin is as follows, in accordance with the values set to bit 9 (CARY) of CARH and the timer output enable flag (t9), and the value of the timer block/c162s 9-bit down counter (t0 to t8). CARH1.1 (CARY) Timer Output Enable Flag (t9: TSR1.1) 9-bit Down Counter (TSR0.0~TSR0.7, TSR1.0) REM Pin 00 0 Low-level output 0 0 Other than 0 0 1 0 64/fsys (with carrier output) 0 1 Other than 0 Carrier output (Note) 10 /c190 Low-level output 11 /c190 High-level output Note: Input values in the range of 001H to 1FFH to CARH (CARH1.0, CARH0.7~CARH0.0) and CARL (CARL1.0, CARL0.7~CARL0.0). REM pin is low level (t9=0o rt 0t ot 8=0 ) . CARH (CARH1.0, CARH0.7~CARH0.0) CARL (CARL1.0, CARL0.7~CARL0.0) tH (/c109s) t L (/c109s) t( /c109s) fC (kHz) Duty 01H 01H 0.5 0.5 1.0 1000 1/2 03H 05H 1.0 1.5 2.5 400 2/5 09H 09H 2.5 2.5 5.0 200 1/2 13H 13H 5.0 5.0 10.0 100 1/2 20H 20H 8.25 8.25 16.5 60.6 1/2 21H 41H 8.25 16.75 25 40 1/3 22H 44H 8.75 17.25 26.0 38.5 1/3 22H 45H 8.75 17.5 26.25 38.10 1/3 22H 46H 8.8 17.6 26.4 37.9 1/3 23H 48H 9.0 18.25 27.25 36.7 1/3 24H 49H 9.26 18.52 27.78 36.0 1/3 34H 6AH 13.33 26.66 40.0 25 1/3 3BH 3BH 15.0 15.0 30.0 33.3 1/2 63H 63H 25.0 25.0 50.0 20 1/2 7FH 7FH 32.0 32.0 64.0 15.6 1/2 Carrier Frequency Setting (fSYS=4MHz) /G74 /G4C /G74 /G43 /G61 /G72 /G72 /G69 /G65 /G72 /G20 /G53 /G69 /G67 /G6E /G61 /G6C /G74 /G48

Rev.1.10 15 October 12, 2007 /G56 /G44 /G44 /G33 /G2E /G36 /G56 /G56 /G4C /G56 /G52 /G30 /G2E /G39 /G56 /G30 /G56 /G52 /G65 /G73 /G65 /G74 /G20 /G53 /G69 /G67 /G6E /G61 /G6C /G52 /G65 /G73 /G65 /G74 /G2A /G31 /G2A /G32 /G4E /G6F /G72 /G6D /G61 /G6C /G20 /G4F /G70 /G65 /G72 /G61 /G74 /G69 /G6F /G6E /G52 /G65 /G73 /G65 /G74 /G4C /G56 /G52 /G20 /G44 /G65 /G74 /G65 /G63 /G74 /G20 /G56 /G6F /G6C /G74 /G61 /G67 /G65 Low Voltage Reset Note: /c178*1/c178To make sure that the system oscillator has stabilised, the SST provides an extra delay of 1024 system clock pulses before entering normal operation. /c178*2/c178Since low voltage has to be maintained in its original state and exceed 1ms, a 1ms delay enters the reset mode. /G33 /G2E /G36 /G56 /G31 /G2E /G39 /G56 /G30 /G2E /G39 /G56 /G56 /G44 /G44 /G56 /G4C /G56 /G52 Low Voltage Reset /c45LVR The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~V LVR, such as when changing a battery, the LVR will automatically reset the device internally. The LVR includes the following specifications: /c183The low voltage (0.9V~V LVR) has to remain in this state for a time in excess of 1ms. If the low voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function. The relationship between V DD and VLVR is shown below. Configuration Options The following table shows eight kinds of configuration options for the HT48RA0-3/HT48CA0-3. All the configuration op- tions must be defined to ensure proper system functioning. No. Code Option WDT time-out period selection Time-out period= 2 Clock Source n , where n=8~11. 2 WDT enable/disable selection. This option is to decide whether the WDT timer is enabled or disabled. CLR WDT times selection. This option defines how to clear the WDT by instruction./c178One time/c178means that the CLR WDT instruction can clear the WDT./c178Two times/c178means only if both of the CLR WDT1 and CLR WDT2 in- structions have been executed, the WDT can be cleared. 4 Wake-up selection. This option defines the wake-up activity function. External input pins (PB only) all have the capability to wake-up the device.

5 LVR function: enable or disable

Rev.1.10 16 October 12, 2007 /G4F /G53 /G43 /G31 /G4F /G53 /G43 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G48 /G54 /G34 /G38 /G52 /G41 /G30 /G2D /G33 /G2F /G48 /G54 /G34 /G38 /G43 /G41 /G30 /G2D /G33 /G4F /G53 /G43 /G20 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G52 /G43 /G20 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G4F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G6F /G72 /G52 /G4F /G53 /G43 /G3D /G31 /G32 /G6B /G57 /G56 /G44 /G44 /G52 /G4F /G53 /G43 /G4F /G53 /G43 /G31 /G34 /G37 /G30 /G70 /G46 /G50 /G42 /G30 /G7E /G50 /G42 /G31 /G50 /G41 /G30 /G7E /G50 /G41 /G37 /G52 /G45 /G4D /G50 /G42 /G32 /G7E /G50 /G42 /G37 /G50 /G42 /G32 /G50 /G42 /G33 /G50 /G42 /G34 /G50 /G42 /G35 /G50 /G42 /G36 /G50 /G42 /G37 /G50 /G41 /G37 /G50 /G41 /G36 /G50 /G41 /G35 /G50 /G41 /G34 /G50 /G41 /G30 /G50 /G41 /G31 /G50 /G41 /G32 /G50 /G41 /G33 /G50 /G42 /G30 /G50 /G42 /G31 /G48 /G54 /G34 /G38 /G52 /G41 /G30 /G2D /G33 /G2F /G48 /G54 /G34 /G38 /G43 /G41 /G30 /G2D /G33 /G56 /G44 /G44 /G52 /G45 /G4D /G32 /G32 /G30 /G57 /G7E /G31 /G6B /G57 /G31 /G30 /G30 /G6D /G46 /G33 /G33 /G57 /G31 /G57 /G4F /G53 /G43 /G31 /G4F /G53 /G43 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G56 /G62 /G61 /G74

Rev.1.10 17 October 12, 2007 Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of pro- gram instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro- gramming overheads. For easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. Instruction Timing Most instructions are implemented within one instruc - tion cycle. The exceptions to this are branch, call, or ta- ble read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5/c109s and branch or call instructions would be im- plemented within 1 /c109s. Although instructions which re - quire one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to imple- ment. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instruc- tions would be /c178CLR PCL/c178or /c178MOV PCL, A /c178. For the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific imme- diate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en - sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on pro- gram requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a sub- routine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub- routine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits.

Rev.1.10 18 October 12, 2007 Bit Operations The ability to provide single bit operations on Data Mem- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the/c178SET [m].i/c178or /c178CLR [m].i/c178instructions respectively. The fea- ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write pro - cess is taken care of automatically when these bit oper- ation instructions are used. Table Read Operations Data storage is normally implemented by using regis - ters. However, when working with large amounts of fixed data, the volume involved often makes it inconve- nient to store the fixed data in the Data Memory. To over- come this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instruc- tions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the /c178HALT/c178in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro - magnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow- ing listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Note 1Note Note 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Note 1Note 1Note Note Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory Note 1Note Z Z Z Z

Rev.1.10 19 October 12, 2007 Mnemonic Description Cycles Flag Affected Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry Note 1Note 1Note 1Note None None C C None None C C Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC Note None None None Bit Operation CLR [m].i SET [m].i Clear bit of Data Memory Set bit of Data Memory Note 1Note None None Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Note 1note 1Note 1Note 1Note 1Note 1Note 1Note None None None None None None None None None None None None None Table Read TABRDC [m] TABRDL [m] Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory Note 2Note None None Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note 1Note Note None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the /c178CLR WDT1/c178and /c178CLR WDT2/c178instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both /c178CLR WDT1/c178and /c178CLR WDT2/c178instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.

ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC /c172A C C+[ m ]+C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] /c172A C C+[ m ]+C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC /c172ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. Operation ACC /c172A C C+x Affected flag(s) OV, Z, AC, C ADDM A,[m] Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. Operation [m] /c172ACC + [m] Affected flag(s) OV, Z, AC, C AND A,[m] Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op - eration. The result is stored in the Accumulator. Operation ACC /c172ACC /c178AND/c178[m] Affected flag(s) Z AND A,x Logical AND immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. Operation ACC /c172ACC /c178AND/c178x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op - eration. The result is stored in the Data Memory. Operation [m] /c172ACC /c178AND/c178[m] Affected flag(s) Z HT48RA0-3/HT48CA0-3 Rev.1.10 20 October 12, 2007

Description Unconditionally calls a subroutine at the specified address. The Program Counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruc- tion. Operation Stack /c172Program Counter + 1 Program Counter /c172addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] /c17200H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i /c1720 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Operation WDT cleared TO /c1720 PDF /c1720 Affected flag(s) TO, PDF CLR WDT1 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT2 will have no effect. Operation WDT cleared TO /c1720 PDF /c1720 Affected flag(s) TO, PDF CLR WDT2 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc - tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO /c1720 PDF /c1720 Affected flag(s) TO, PDF HT48RA0-3/HT48CA0-3 Rev.1.10 21 October 12, 2007

CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1 /c162s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] /c172[m] Affected flag(s) Z CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1 /c162s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC /c172[m] Affected flag(s) Z DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re - sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by add- ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] /c172ACC + 00H or [m] /c172ACC + 06H or [m] /c172ACC + 60H or [m] /c172ACC + 66H Affected flag(s) C DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] /c172[m] /c451 Affected flag(s) Z DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accu - mulator. The contents of the Data Memory remain unchanged. Operation ACC /c172[m] /c451 Affected flag(s) Z HALT Enter power down mode Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO /c1720 PDF /c1721 Affected flag(s) TO, PDF HT48RA0-3/HT48CA0-3 Rev.1.10 22 October 12, 2007

INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] /c172[ m ]+1 Affected flag(s) Z INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu - lator. The contents of the Data Memory remain unchanged. Operation ACC /c172[ m ]+1 Affected flag(s) Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter /c172addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC /c172[m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC /c172x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] /c172ACC Affected flag(s) None NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper - ation. The result is stored in the Accumulator. Operation ACC /c172ACC /c178OR/c178[m] Affected flag(s) Z HT48RA0-3/HT48CA0-3 Rev.1.10 23 October 12, 2007

OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op - eration. The result is stored in the Accumulator. Operation ACC /c172ACC /c178OR/c178x Affected flag(s) Z ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper - ation. The result is stored in the Data Memory. Operation [m] /c172ACC /c178OR/c178[m] Affected flag(s) Z RET Return from subroutine Description The Program Counter is restored from the stack. Program execution continues at the re - stored address. Operation Program Counter /c172Stack Affected flag(s) None RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter /c172Stack ACC /c172x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by set- ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed be- fore returning to the main program. Operation Program Counter /c172Stack EMI /c1721 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit Operation [m].(i+1) /c172[m].i; (i = 0~6) [m].0 /c172[m].7 Affected flag(s) None RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) /c172[m].i; (i = 0~6) ACC.0 /c172[m].7 Affected flag(s) None HT48RA0-3/HT48CA0-3 Rev.1.10 24 October 12, 2007

RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) /c172[m].i; (i = 0~6) [m].0 /c172C C /c172[m].7 Affected flag(s) C RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) /c172[m].i; (i = 0~6) ACC.0 /c172C C /c172[m].7 Affected flag(s) C RR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i /c172[m].(i+1); (i = 0~6) [m].7 /c172[m].0 Affected flag(s) None RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i /c172[m].(i+1); (i = 0~6) ACC.7 /c172[m].0 Affected flag(s) None RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i /c172[m].(i+1); (i = 0~6) [m].7 /c172C C /c172[m].0 Affected flag(s) C RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re - places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i /c172[m].(i+1); (i = 0~6) ACC.7 /c172C C /c172[m].0 Affected flag(s) C HT48RA0-3/HT48CA0-3 Rev.1.10 25 October 12, 2007

SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub - tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC /c172ACC /c45[m] /c45C Affected flag(s) OV, Z, AC, C SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are sub - tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re- sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] /c172ACC /c45[m] /c45C Affected flag(s) OV, Z, AC, C SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] /c172[m] /c451 Skip if [m] = 0 Affected flag(s) None SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC /c172[m] /c451 Skip if ACC = 0 Affected flag(s) None SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] /c172FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i /c1721 Affected flag(s) None HT48RA0-3/HT48CA0-3 Rev.1.10 26 October 12, 2007

SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] /c172[ m ]+1 Skip if [m] = 0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC /c172[ m ]+1 Skip if ACC = 0 Affected flag(s) None SNZ [m].i Skip if bit i of Data Memory is not 0 Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m].i /c1850 Affected flag(s) None SUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC /c172ACC /c45[m] Affected flag(s) OV, Z, AC, C SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] /c172ACC /c45[m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumu - lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC /c172ACC /c45x Affected flag(s) OV, Z, AC, C HT48RA0-3/HT48CA0-3 Rev.1.10 27 October 12, 2007

SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 /c171[m].7 ~ [m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC.3 ~ ACC.0 /c172[m].7 ~ [m].4 ACC.7 ~ ACC.4 /c172[m].3 ~ [m].0 Affected flag(s) None SZ [m] Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruc- tion. Operation Skip if [m] = 0 Affected flag(s) None SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruc- tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC /c172[m] Skip if [m] = 0 Affected flag(s) None SZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i = 0 Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] /c172program code (low byte) TBLH /c172program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] /c172program code (low byte) TBLH /c172program code (high byte) Affected flag(s) None HT48RA0-3/HT48CA0-3 Rev.1.10 28 October 12, 2007

XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op - eration. The result is stored in the Accumulator. Operation ACC /c172ACC /c178XOR/c178[m] Affected flag(s) Z XORM A,[m] Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op - eration. The result is stored in the Data Memory. Operation [m] /c172ACC /c178XOR/c178[m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC /c172ACC /c178XOR/c178x Affected flag(s) Z HT48RA0-3/HT48CA0-3 Rev.1.10 29 October 12, 2007

Package Information

20-pin SOP (300mil) Outline Dimensions Symbol Dimensions in mil Min. Nom. Max. A 394 /c190 419 B 290 /c190 300 C1 4 /c190 20 C/c162 490 /c190 510 D9 2 /c190 104 E /c190 50 /c190 F4 /c190/c190 G3 2 /c190 38 H4 /c190 12 /c97 0/c176/c190 10/c176 HT48RA0-3/HT48CA0-3 Rev.1.10 30 October 12, 2007 /G32 /G30 /G31 /G31 /G31 /G31 /G30 /G41 /G42 /G43 /G44 /G45 /G46 /G43 /G27 /G47 /G48 /G61

20-pin SSOP (150mil) Outline Dimensions Symbol Dimensions in mil Min. Nom. Max. A 228 /c190 244 B 150 /c190 158 C8 /c190 12 C/c162 335 /c190 347 D4 9 /c190 65 E /c190 25 /c190 F4 /c190 10 G1 5 /c190 50 H7 /c190 10 /c97 0/c176/c190 8/c176 HT48RA0-3/HT48CA0-3 Rev.1.10 31 October 12, 2007 /G32 /G30 /G31 /G31 /G31 /G31 /G30 /G41 /G42 /G43 /G44 /G45 /G46 /G43 /G27 /G47 /G48 /G61

Product Tape and Reel Specifications Reel Dimensions SOP 20W Symbol Description Dimensions in mm A Reel Outer Diameter 330/c1771.0 B Reel Inner Diameter 62/c1771.5 C Spindle Hole Diameter 13.0+0.5 /c450.2 D Key Slit Width 2.0/c1770.5 T1 Space Between Flange 24.8+0.3 /c450.2 T2 Reel Thickness 30.2/c1770.2 SSOP 20S (150mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330/c1771.0 B Reel Inner Diameter 62/c1771.5 C Spindle Hole Diameter 13.0+0.5 /c450.2 D Key Slit Width 2.0/c1770.5 T1 Space Between Flange 16.8+0.3 /c450.2 T2 Reel Thickness 22.2/c1770.2 HT48RA0-3/HT48CA0-3 Rev.1.10 32 October 12, 2007 /G41 /G43 /G42 /G54 /G31 /G54 /G32 /G44

Symbol Description Dimensions in mm W Carrier Tape Width 24.0+0.3 /c450.1 P Cavity Pitch 12.0/c1770.1 E Perforation Position 1.75/c1770.1 F Cavity to Perforation (Width Direction) 11.5/c1770.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0/c1770.1 P1 Cavity to Perforation (Length Direction) 2.0/c1770.1 A0 Cavity Length 10.8/c1770.1 B0 Cavity Width 13.3/c1770.1 K0 Cavity Depth 3.2/c1770.1 t Carrier Tape Thickness 0.3/c1770.05 C Cover Tape Width 21.3 SSOP 20S (150mil) Symbol Description Dimensions in mm W Carrier Tape Width 16.0+0.3 /c450.1 P Cavity Pitch 8.0/c1770.1 E Perforation Position 1.75/c1770.1 F Cavity to Perforation (Width Direction) 7.5/c1770.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4.0/c1770.1 P1 Cavity to Perforation (Length Direction) 2.0/c1770.1 A0 Cavity Length 6.5/c1770.1 B0 Cavity Width 9.0/c1770.1 K0 Cavity Depth 2.3/c1770.1 t Carrier Tape Thickness 0.30/c1770.05 C Cover Tape Width 13.3 HT48RA0-3/HT48CA0-3 Rev.1.10 33 October 12, 2007 /G50 /G44 /G31 /G57 /G50 /G31 /G50 /G30 /G44 /G45 /G46 /G74 /G4B /G30 /G42 /G30 /G41 /G30 /G43

Rev.1.10 34 October 12, 2007 Copyright /c2112007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as - sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek/c162s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw. Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com