AM29LV652D AMD | Alldatasheet

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Publication Number 24961 Revision E Amendment 5 Issue Date May 5, 2006 Am29LV652D Data Sheet RETIRED PRODUCT This product has been retired and is not recomme nded for designs. For new designs, S29GL128N supersedes Am29LV652D. Please refer to the S29G L-N family data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 24961 Rev: A Amendment: 5 Issue Date: May 5, 2006 Refer to AMD’s Website (www.amd.com) for the latest information. Am29LV652D 128 Megabit (16 M x 8-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO™ Control DISTINCTIVE CHARACTERISTICS ■ Two 64 Megabit (Am29LV065D) in a single 63-ball 11 x 12 mm FBGA package (Note: Features will be described for each internal Am29LV065D) ■ Two Chip Enable inputs — Each CE# controls selection of one internal Am29LV065D device ■ Single power supply operation — 3.0 to 3.6 volt read, erase, and program operations ■ VersatileIO™ control — Device generates output voltages and tolerates input voltages on DQ I/Os as determined by the voltage on V IO input ■ High performance — Access times as fast as 90 ns ■ Manufactured on 0.23 µm process technology ■ CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Ultra low power consumption (typical values at 3.0 V,

5 MHz) for the part

— 9 mA typical active read current — 26 mA typical erase/program current — 400 nA typical standby mode current ■ Flexible sector architecture — Two hundred fifty-six 64 Kbyte sectors ■ Sector Protection — A hardware method to lock a sector to prevent program or erase operations within that sector — Sectors can be locked in-system or via programming equipment — Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Compatibility with JEDEC standards — Except for the added CE2#, the FBGA is pinout and software compatible with single-power supply Flash — Superior inadvertent write protection ■ Minimum 1 million erase cycle guarantee per sector ■ 63-ball FBGA Package ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences ■ Ready/Busy# output (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset input (RESET#) — Hardware method to reset the device for reading array data ■ ACC input — Accelerates programming time for higher throughput during system production ■ Program and Erase Performance (V HH not applied to the ACC input) — Byte program time: 5 µs typical — Sector erase time: 1.6 s typical for each 64 Kbyte sector ■ 20-year data retention at 125°C — Reliable operation for the life of the system This product has been retired and is not recommended for designs. For new designs, S29GL128N supersedes Am29L V652D. Please refer to the S29GL-N family data sheet for specifica- tions and ordering information. Availability of this document is retained for reference and historical purposes only.

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The Am29LV652D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory device organized as two Am29LV065D dice in a single 63-ball FBGA package. Each Am29LV065D is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory device organized as 8,388,608 bytes. Data appears on DQ0-DQ7. The device is designed to be programmed in-system with the standard system 3.0 volt V CC sup- ply. A 12.0 volt VPP is not required for program or erase operations. The Am29LV652D is equipped with two CE#s for flexible selection between the two internal 64 Mb devices. The device can also be programmed in standard EPROM programmers. The Am29LV652D offers access times of 90 and 120 ns and is offered in a 63-ball FBGA package. To elimi- nate bus contention the Am29LV652D device contains two separate chip enables (CE# and CE2#). Each chip enable (CE# or CE2#) is connected to only one of the two dice in the Am29LV652D package. To the sys- tem, this device is the same as two independent Am29LV065D on the same board. The only differ- ence is that they are now packaged together to re- duce board space. Each device requires only a single 3.0 Volt power supply (3.0 V to 3.6 V) for both read and write func- tions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the command register using standard microprocessor write timing. Register con- tents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on V IO. This allows the device to operate in a 3 V or 5 V system environment as required. For voltage levels below 3 V, contact an AMD representative for more in- formation. The host system can detect whether a program or erase operation is complete by observing RY/BY#, by reading the DQ7 (Data# Polling), or DQ6 (toggle) sta- tus bits. After a program or erase cycle is completed, the device is ready to read array data or accept an- other command. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# terminates any operation in progress and resets the internal state machine to reading array data. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory device. The device offers a standby mode as a power-saving feature. Once the system places the device into the standby mode power consumption is greatly reduced. The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to V HH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase fa ctory throughput during sys- tem production, but may also be used in the field if de- sired. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.

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Note: See “AC Characteristics” on page 39 for full specifications. Part Number Am29LV652D Speed Option Regulated Voltage Range: V CC = 3.0–3.6 V 90R 12R Max Access Time (ns) 90 120 CE# Access Time (ns) 90 120 OE# Access Time (ns) 35 50

May 5, 2006 24961A5 Am29LV652D 5 DATA SHEET BLOCK DIAGRAM Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# ACC CE# OE# STB STB DQ0–DQ7 Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address Latch VIO Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register STB STB DQ0–DQ7 Sector SwitchesRY/BY# Data Latch Y-Gating Cell Matrix Address Latch VIO A0–A22 A0–A22 A0–A22 CE#2

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Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. C2 D2 C3 D3 A3 A4 A2 A1 A0 CE# OE# V SS A7 A18 A6 A5 DQ0 NC CE2# DQ1 RY/BY# ACC NC NC DQ2 DQ3 V IO A21 WE# RESET# A22 NC DQ5 NC V CC DQ4 A9 A8 A11 A12 A19 A10 DQ6 DQ7 A14 A13 A15 A16 A17 NC A20 V SS C4 D4 E4 A1 B1 NC* NC* NC* F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7 E7 NC*NC* NC* NC* A7 B7 A8 B8 F7 G7 H7 J7 K7 NC* NC* NC* NC* L7 M7 L8 M8 NC* NC* NC* NC* * Balls are shorted together via the substrate but not connected to the die. 63-Ball FBGA Top View, Balls Facing Down

May 5, 2006 24961A5 Am29LV652D 7 DATA SHEET PIN DESCRIPTION A0–A22 = 23 Addresses inputs DQ0–DQ7 = 8 Data inputs/outputs CE# = Chip Enable input CE2# = Chip Enable input for second die OE# = Output Enable input WE# = Write Enable input ACC = Acceleration Input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL DQ0–DQ7 A0–A22 CE# CE2# OE# ACC RY/BY# WE# VIO RESET#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV652D U 90R MA I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) E = Extended (–55 °C to +125°C) F = Industrial (-40 oC to +85oC) with Pb-free Package K = Extended (-55 oC to +125oC) with Pb-free Package PACKAGE TYPE MA = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 11 x 12 mm package (FSA063) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE U = Uniform sector device DEVICE NUMBER/DESCRIPTION Am29LV652D

128 Megabit (2 x 8 M x 8-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for FBGA Packages Speed/ VIO RangeOrder Number Package Marking Am29LV652DU90R MAF , MAI L652DU90R F, I 90 ns, VIO = 3.0 V – 5.0 V Am29LV652DU12R MAI, MAE MAF , MAK L652DU12R K 120 ns, VIO = 3.0 V – 5.0 V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Am29LV652D Device Bus Operations

  1. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at
  2. Addresses are A22:A0. Sector addresses are A22:A16.

IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

  1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

  1. All sectors are unprotected when shipped from the factory.

3 V, contact an AMD representative for more informa-

from other 5 V devices on the same data bus. mand is necessary in this mode to obtain array data.

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enabled for read access until the command register contents are altered. See “VersatileIO‰ (VIO) Control” for more informa- tion. Refer to the AC “Read-Only Operations” on page 39 table for timing specifications and to Figure 13, on page 39 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# (or CE2#) to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a byte, instead of four. The “Byte Program Command Sequence” on page 26 section contains details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2, on page 11 indicates the address space that each sector occupies. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section cont ains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. If the system asserts V HH on ACC, the device automat- ically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage to reduce the time required for program operations. The system would use a two-cy- cle program command sequence as required by the Unlock Bypass mode. Removing V HH from ACC re- turns the device to normal operation. Note that ACC must not be at V HH for operations other than acceler- ated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” on page 19 and “Autoselect Command Sequence” on page 26 sections for more information. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#, CE2#, and RESET# are all held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE#, CE2#, and RESET# are held at V IH, but not within V CC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics (for two Am29LV065 de- vices) table represents the standby current specifica- tion. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, CE2#, WE#, and OE# control signals. Stan- dard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and alwa ys available to the system. I CC4 in the DC Characteristics (for two Am29LV065 de- vices) table represents the automatic sleep mode cur- rent specification. RESET#: Hardware Reset Pin RESET# provides a hardware method of resetting the device to reading array data. When RESET# is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all out- puts, and ignores all read/write commands for the du- ration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS ± 0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL, but not within VSS ± 0.3 V, the standby current is greater. RESET# may be tied to the system reset circuitry. A system reset would thus also reset the Flash memory,

tem can read data tRH after RESET# returns to VIH. Table 2. Sector Address Table for CE# (Sheet 1 of 4)

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Table 2. Sector Address Table for CE# (Sheet 2 of 4)

Table 2. Sector Address Table for CE# (Sheet 3 of 4)

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Note: All sectors are 64 Kbytes in size. Table 2. Sector Address Table for CE# (Sheet 4 of 4)

Table 3. Sector Address Table for CE2# (Sheet 1 of 4)

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Table 3. Sector Address Table for CE2# (Sheet 2 of 4)

Table 3. Sector Address Table for CE2# (Sheet 3 of 4)

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Note: All sectors are 64 Kbytes in size. Table 3. Sector Address Table for CE2# (Sheet 4 of 4)

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address A9. ing identifier code on DQ7–DQ0. command register, as shown in Table 10, on page 30. Table 4. Am29LV652D Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

  1. CE# can be replaced with CE2# when referring to the second die in the package.
  2. The device ID’s used for the Am29LV652 are the same as the Am29LV065, because the Am29LV652 uses two Am29LV065

dice and appears to the system as two Am29LV065 devices.

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implemented via two methods. to the first sector group unprotect write cycle. tact an AMD representative for details. on page 19 section for details. Table 5. Sector Group Protection/Unprotection Note: All sector groups are 256 Kbytes in size.

Figure 1. Temporary Sector Group

  1. All protected sector groups unprotected.
  2. All previously protected sector groups are protected

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Figure 2. In-System Sector Group Protect/Unprotect Algorithms

CE2#, or WE# do not initiate a write cycle. zero while OE# is a logical one. automatically reset to the read mode on power-up. interfaces for long-term compatibility. as two 64 Mbit Am29LV065 devices in the system. must write the reset command. tative for copies of these documents. Table 6. CFI Query Identification String

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Table 7. System Interface String Table 8. Device Geometry Definition

Table 9. Primary Vendor-Specific Extended Query on page 39 for timing diagrams. mands” on page 28 for more information.

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the next section, “Reset Command”, for more informa- tion. See also “VersatileIO‰ (VIO) Control” on page 9 for more information. The Read-Only Operations table provides the read parameters, and Figure 13, on page 39 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10, on page 30 shows the address and data re- quirements. This method is an alternative to that shown in Table 4, on page 19 , which is intended for PROM programmers and requires V ID on address A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: ■ A read cycle at address XX00h returns the manu- facturer code. ■ A read cycle at address XX01h returns the device code. ■ A read cycle to an address containing a sector group address (SA), and the address 02h on A7–A0 returns 01h if the sector group is protected, or 00h if it is unprotected. (Refer to Table 5, on page 20 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10, on page 30 shows the address and data requirements for the byte pro- gram command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the “Write Operation Status” on page 31 section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device returns to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un-

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When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” on page 31 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that oc- curs, the chip erase command sequence should be reinitiated once the device returns to reading array data, to ensure data integrity. Figure 4, on page 29 illustrates the algorithm for the erase operation. Refer to the “Erase and Program Op- erations” on page 41 tables in the AC Characteristics section for parameters, and Figure 17, on page 43 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 10, on page 30 shows the address and data requirements for the sec- tor erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must re- write the command sequence and any additional ad- dresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See “DQ3: Sector Erase Timer” on page 33.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Note that while the Embedded Erase operation is in progress, the system can read data from the non-erasing sector. The system can de- termine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to “Write Operation Status” on page 31 for infor- mation on these status bits. Once the sector erase operation begins, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device returns to read- ing array data, to ensure data integrity. Figure 4, on page 29 illustrates the algorithm for the erase operation. Refer to the “Erase and Program Op- erations” on page 41 tables in the AC Characteristics section for parameters, and Figure 17, on page 43 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec- tor erase operation, including the 50 µs time-out pe- riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- imum of 20 µs to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation is suspended, the device en- ters the erase-suspend-read mode. The system can read data from or program data to any sector not se- lected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status infor- mation on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is ac- tively erasing or is erase-suspended. Refer to “Write Operation Status” on page 31 for information on these status bits.

just as in the standard byte program operation. mand Sequence” on page 26 sections for details. can be written after the chip resumes erasing. Figure 4. Erase Operation

  1. See Table 10, on page 30 for erase command
  2. See the section on DQ3 for information on the sector

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Table 10. Am29LV652D Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# (or CE2#) pulse, whichever happens first. erased. Address bits A22–A16 uniquely select any sector.

  1. See Table 1, on page 9 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

  1. Unless otherwise noted, address bits A22–A12 are don’t cares.
  2. No unlock or command cycles required when device is in read
  3. The Reset command is required to return to the read mode (or to

(while the device is providing status information).

  1. The fourth cycle of the autoselect command sequence is a read
  2. The data is 00h for an unprotected sector group and 01h for a
  3. The Unlock Bypass command is required prior to the Unlock
  4. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

  1. The Erase Resume command is valid only during the Erase
  2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

3 XXX AA XXX 55 XXX 20

final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Figure 5. Data# Polling Algorithm

  1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

  1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

32 Am29LV652D 24961A5 May 5, 2006

Table 11, on page 34 shows the outputs for RY/BY#. operation is complete, DQ6 stops toggling. lected sectors that are protected. whether a sector is actively erasing or is erase-suspended. vice enters the Erase Suspend mode, DQ6 stops toggling. “DQ7: Data# Polling” on page 31). Figure 6. Toggle Bit Algorithm

May 5, 2006 24961A5 Am29LV652D 33 DATA SHEET DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may us e either OE# or CE# or CE2# to control the read cycles.) But DQ2 cannot dis- tinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are se- lected for erasure. Thus, both status bits are required for sector and mode information. Refer to Table 11, on page 34 to compare outputs for DQ2 and DQ6. Figure 6, on page 32 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” ex- plains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 19, on page 45 shows the toggle bit timing diagram. Figure 20, on page 45 shows the dif- ferences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6, on page 32 for the following discus- sion. Whenever the system initially begins reading tog- gle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typi- cally, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is th at the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 6, on page 32). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time ex- ceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit is exceeded, DQ5 produces a “1.” Under both these conditions , the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to det ermine whether or not erasure began. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also “Sector Erase Command Sequence” on page 28 After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the de- vice accepts additional sector erase commands. To ensure the command is accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11, on page 34 shows the status of DQ3 relative to the other status bits.

34 Am29LV652D 24961A5 May 5, 2006

Table 11. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

36 Am29LV652D 24961A5 May 5, 2006

(For Two Am29LV065 Devices) CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Assumes only one Am29LV065 die being programmed at the same time. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 400 nA. 7. Not 100% tested. 8. CE# can be replaced with CE2# when referring to the second device within the package. 9. Specifications in the table are for the Am29LV652 i.e. two Am29LV065 dice. Parameter Symbol Parameter Description Te st Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 70 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# (or CE2#) = VIL, OE# = VIH

5 MHz 9 16

1 MHz 2 4

VCC Active Write Current (Notes 2, 3, 4) CE# (or CE2#) = VIL, OE# = VIH 26 30 mA ICC3 VCC Standby Current (Note 2) CE#, CE2#, RESET# = V CC ± 0.3 V 0.4 10 µA ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.3 V 0.4 10 µA ICC5 Automatic Sleep Mode (Notes 2, 5) V IH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.4 10 µA IACC ACC Accelerated Program Current (Note 4) CE# = VIL, OE# = VIH ACC 5 10 mA VCC 15 30 mA VIL Input Low Voltage (Note 6) –0.5 0.8 V VIH Input High Voltage (Note 6) 0.7 x V CC VCC + 0.3 V VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage (Note 7) IOH = –2.0 mA, VCC = VCC min 0.85 V IO V VOH2 IOH = –100 µA, VCC = VCC min V IO–0.4 V VLKO Low VCC Lock-Out Voltage (Note 7) 2.3 2.5 V

38 Am29LV652D 24961A5 May 5, 2006

Table 12. Test Specifications Note: If VIO < VCC, the reference level is 0.5 VIO. Figure 11. Test Setup Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 12. Input Waveforms and Measurement Levels

May 5, 2006 24961A5 Am29LV652D 39 DATA SHEET AC CHARACTERISTICS Read-Only Operations Notes: 1. All test setups assume V IO = VCC. 2. Not 100% tested. 3. See Figure 11, on page 38 and Table 12, on page 38 for test specifications 4. CE# can be replaced with CE2# when referring to the second device within the package. Parameter

Description

(Note 1) Speed Options JEDEC Std. 90R 12R Unit tAVAV tRC Read Cycle Time (Note 2) Min 90 120 ns tAVQV tACC Address to Output Delay CE#, OE# = V IL Max 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = V IL Max 90 120 ns tGLQV tOE Output Enable to Output Delay Max 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 2) Max 30 30 ns tGHQZ tDF Output Enable to Output High Z (Note 2) Max 30 30 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns tOEH Output Enable Hold Time (Note 2) Read Min 0 ns Toggle and Data# Polling Min 10 ns tOH tCE Outputs WE# Addresses CE# or CE2# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH

0 VRY/BY#

RESET# tDF Figure 13. Read Operation Timings

40 Am29LV652D 24961A5 May 5, 2006

Figure 14. Reset Timings

May 5, 2006 24961A5 Am29LV652D 41 DATA SHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” on page 50 section for more information. 3. CE# can be replaced with CE2# when referring to the second device within the package. Parameter Speed Options JEDEC Std. Description 90R 12R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 5 µs tWHWH1 tWHWH1 Accelerated Byte Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1.6 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

42 Am29LV652D 24961A5 May 5, 2006

Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 15. Program Operation Timings Figure 16. Accelerated Program Timing Diagram

Figure 17. Chip/Sector Erase Operation Timings

44 Am29LV652D 24961A5 May 5, 2006

Figure 18. Data# Polling Timings (During Embedded Algorithms)

46 Am29LV652D 24961A5 May 5, 2006

Figure 21. Temporary Sector Group Unprotect Timing Diagram

  • For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 22. Sector Group Protect and Unprotect Timing Diagram

48 Am29LV652D 24961A5 May 5, 2006

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. CE# can be replaced with CE2# when referring to the second device within the package. Parameter Speed Options JEDEC Std Description 90R 12R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 50 ns tDVEH tDS Data Setup Time Min 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Byte Programming Operation (Note 2) Typ 5 µs tWHWH1 tWHWH1 Accelerated Byte Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1.6 sec

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data.
  3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

Figure 23. Alternate CE# Controlled Wr ite (Erase/Program) Operation Timings

50 Am29LV652D 24961A5 May 5, 2006

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10, on page 30 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all connections except VCC. Test conditions: VCC = 3.0 V, one connection at a time. INPUT/OUTPUT CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 1.6 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 205 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5)Accelerated Byte Program Time 4 120 µs Chip Program Time (Note 3) 42 126 sec Description Min Max Input voltage with respect to VSS on all device connections (including A9, OE#, and RESET#) except I/Os –1.0 V 12.5 V Input voltage with respect to VSS on all I/Os –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 12 16 pF COUT Output Capacitance V OUT = 0 12 16 pF CE/CE2 Control Pin Capacitance V IN = 0 6 8 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

May 5, 2006 24961A5 Am29LV652D 51 DATA SHEET PHYSICAL DIMENSIONS FSA063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm package

52 Am29LV652D 24961A5 May 5, 2006

Revision A (May 24, 2001) Initial release. Revision A+1 (July 31, 2001) AC Characteristics—Alternate CE# Controlled Erase and Program Table tWHWH1—Byte Programming Operation: Changed typi- cal value from 11 µs to 5 µs. tWHWH1 —Accelerated Byte Programming Operation: Changed typical value from 7 µs to 4 µs. Revision A+2 (August 14, 2001) Global Removed the speed options for 100 ns with V IO = 1.8 V – 2.9 V and 120 ns with V IO = 1.8 V – 2.9 V. Changed the speed option for 120 ns with V IO = 3.0 V – 5.0 V from 120R to 12R. General Description and Device Bus Operations Added “For voltage levels below 3 V, contact an AMD representative for more information.” to VersatileI/O™ text. Removed the Optional Processing from the order number. Revision A+3 (January 10, 2002) Global Clarified description of VersatileIO (V IO) in the follow- ing sections: Distinctive Characteristics; General De- scription; VersatileIO (V IO) Control; Operating Ranges; DC Characteristics; CMOS compatible. Revision A+4 (October 29, 2004) Global Added Spansion Cover Sheet Added reference links to page numbers Added Colophon Added two package types to temperature range. Valid Combination for FBGA Packages Added MAF and MAK to order number. Added F and K to Package Marking. Revision A5 (May 5, 2006) Added migration/obsolescence notices. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those product. Trademarks Copyright © 2000–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies