L642DU12RE

AM29LV642D_06 AMD | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 54

Technical content

Publication Number 25022 Revision A Amendment 2 Issue Date May 5, 2006 Am29LV642D Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new designs, S29GL128N supersedes Am29LV642D. Please re fer to the S29GL-N family data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions.

THIS PAGE LEFT INTENTIONALLY BLANK.

This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 25022 Rev: A Amendment: 2 Issue Date: May 5, 2006 Refer to AMD’s Website (www.amd.com) for the latest information. Am29LV642D 128 Megabit (8 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control DISTINCTIVE CHARACTERISTICS ■ Two 64 Megabit (Am29LV640D) in a single 64-ball 13 x 11 mm Fortified BGA package (Note: Features will be described for each internal Am29LV640D) ■ Two Chip Enable pins — Two CE# pins to control selection of each internal Am29LV640D devices ■ Single power supply operation — 3.0 to 3.6 volt read, erase, and program operations ■ VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the V IO pin ■ High performance — Access times as fast as 90 ns ■ Manufactured on 0.23 µm process technology ■ CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Ultra low power consumption (typical values at 3.0 V,

5 MHz) for the part

— 9 mA typical active read current — 26 mA typical erase/program current — 400 nA typical standby mode current ■ Flexible sector architecture — Two hundred fifty-six 32 Kword sectors ■ Sector Protection — A hardware method to lock a sector to prevent program or erase operations within that sector — Sectors can be locked in-system or via programming equipment — Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Compatibility with JEDEC standards — Except for the additional CE 2# pin, the Fortified BGA is pinout and software compatible with single-power supply Flash — Superior inadvertent write protection ■ Minimum 1 million erase cycle guarantee per sector ■ 64-ball Fortified BGA Package ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Data# Polling and toggle bits — Provides a software meth od of detecting program or erase operation completion ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method to reset the device for reading array data ■ ACC pin — Accelerates programming time for higher throughput during system production ■ Program and Erase Performance (VHH not applied to the ACC input pin) — Word program time: 11 µs typical — Sector erase time: 1.6 s typical for each 32 Kword sector ■ 20-year data retention at 125°C — Reliable operation for the life of the system This product has been retired and is not recommended for designs. For new designs, S29GL128N supersedes Am29L V642D. Please refer to the S29GL-N family data sheet for specifica- tions and ordering information. Availability of this document is retained for reference and historical purposes only.

2 Am29LV642D 25022A2 May 5, 2006

The Am29LV642D is a 128 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory device organized as two Am29LV640D dice in a single 64-ball Fortified BGA package. Each Am29LV640D is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory device organized as 4,194,304 words. Data appears on DQ0-DQ15. The device is designed to be pro grammed in-system with the standard system 3.0 volt V CC supply. A 12.0 volt VPP is not required for program or erase operations. The Am29LV642D is equipped with two CE# pins for flexible selection between the two internal 64 Mb devices. The device can also be programmed in standard EPROM programmers. The Am29LV642D offers access times of 90 and 120 ns and is offered in a 64-ball Fortified BGA package. To eliminate bus contention the Am29LV642D device has two separate chip enables (CE# and CE2#). Each chip enable (CE# or CE2#) is connected to only one of the two dice in the Am29LV642D package. To the sys tem, this device will be the same as two indepen - dent Am29LV640D on the same board. The only difference is that they are now packaged together to reduce board space. Each device requires only a single 3.0 Volt power supply (3.0 V to 3.6 V) for both read and write func - tions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the command register using standard microprocessor write timing. Register con tents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili - tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com - mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The VersatileI/O™ (VIO) control allows the host sys - tem to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the VIO pin. This allows the device to operate in 1.8 V, 3 V, or 5 V system environment as required. For voltage levels below 3 V, contact an AMD representative for more information. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (tog gle) status bits . After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sec - tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera - tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system micropro cessor to read boot-up firmware from the Flash mem - ory device. The device offers a standby mode as a power-saving feature. Once the system places the device into the standby mode power consumption is greatly reduced. The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to VHH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase factory throughput during sys tem production, but may also be used in the field if de- sired. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective - ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.

4 Am29LV642D 25022A2 May 5, 2006

Note: See “AC Characteristics” for full specifications. Part Number Am29LV642D Speed Option Regulated Voltage Range: VCC = 3.0–3.6 V 90R 12R Max Access Time (ns) 90 120 CE# Access Time (ns) 90 120 OE# Access Time (ns) 35 50

May 5, 2006 25022A2 Am29LV642D 5 DATA SHEET BLOCK DIAGRAM Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# ACC CE# OE# STB STB DQ0–DQ15 Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address Latch VIO Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register STB STB DQ0–DQ15 Sector SwitchesRY/BY# Data Latch Y-Gating Cell Matrix Address Latch VIO A0–A21 A0–A21 A0–A21 CE#2

6 Am29LV642D 25022A2 May 5, 2006

Special Handling Instructions for Fortified Special handling is required for Flash Memory products in Fortified BGA packages. Flash memory devices in Fortified BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 RFURFURFUVSSVIORFURFU VSSDQ15RFUA16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19A21RESET# DQ3DQ11DQ10DQ2A20A18ACC DQ1DQ9DQ8DQ0A5A6A17 RFU A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 RFUCE2#VIORFURFURFURFU RFU 64-Ball Fortified BGA Top View, Balls Facing Down

May 5, 2006 25022A2 Am29LV642D 7 DATA SHEET PIN DESCRIPTION A0–A21 = 22 Addresses inputs DQ0–DQ15 = 16 Data inputs/outputs CE# = Chip Enable input CE2# = Chip Enable input for second die OE# = Output Enable input WE# = Write Enable input ACC = Acceleration Input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VIO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL DQ0–DQ15 A0–A21 CE# CE2# OE# ACC RY/BY# WE# VIO RESET#

8 Am29LV642D 25022A2 May 5, 2006

ORDERING INFORMATION

AMD standard products are available in several packages and o perating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup - ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV642D U 90R PA I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) E = Extended (–55 °C to +125°C) PACKAGE TYPE PA = 64-Ball Fortified Ball Grid Array (Fortified BGA) 1.0 mm pitch, 13 x 11 mm package (LSA064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE U = Uniform sector device DEVICE NUMBER/DESCRIPTION Am29LV642D

128 Megabit (2 x 8 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control

3.0 Volt-only Read, Program, and Erase

Valid Combinations for Fortified BGA Packages Speed/ VIO RangeOrder Number Package Marking Am29LV642DU90R PAI L642DU90R I 90 ns, VIO = 3.0 V – 5.0 V Am29LV642DU12R PAI, PAE L642DU12R I, E 120 ns, VIO = 3.0 V – 5.0 V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Am29LV642D Device Bus Operations

1. CE# can be replaced with CE2# when referring to the second die in the package. CE# and CE2# must not both be driven at
2. Addresses are A21:A0. Sector addresses are A21:A15.
3. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
4. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

1. All sectors are unprotected wh en shipped from the factory.

from other 5 V devices on the same bus. mand is necessary in this mode to obtain array data.

10 Am29LV642D 25022A2 May 5, 2006

enabled for read access until the command register contents are altered. See “VersatileI/O™ (VIO) Control” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. ICC1 in the DC Characteristics table represents the ac - tive current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# (or CE2#) to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re - quired to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. ICC2 in the DC Characteristics table represents the ac - tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in tended to allow faster manufacturing throughput dur - ing system production. If the system asserts V HH on this pin, the device auto - matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command se - quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa - tion. Standby Mode When the system is not reading or writing to the de - vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE#, CE2#, and RESET# pins are all held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE#, CE2#, and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program - ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics (for Two Am29LV640 de- vices) table represents the standby current specifica - tion. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, CE2#, WE#, and OE# control signals. Stan - dard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics (for Two Am29LV640 de- vices) table represents the automatic sleep mode cur - rent specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re - setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en sure data integrity. Current is reduced for th e duration of the RESET# pulse. When RESET# is held at VSS ± 0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within V SS ± 0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir - cuitry. A system reset would thus also reset the Flash

rameters and to Figure 14 for the timing diagram. Table 2. Sector Address Table for CE#

12 Am29LV642D 25022A2 May 5, 2006

Table 2. Sector Address Table for CE# (Continued)

14 Am29LV642D 25022A2 May 5, 2006

Note: All sectors are 32 Kwords in size.

Table 3. Sector Address Table for CE2#

16 Am29LV642D 25022A2 May 5, 2006

Table 3. Sector Address Table for CE2# (Continued)

18 Am29LV642D 25022A2 May 5, 2006

Note: All sectors are 32 Kwords in size.

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 4. In addition, when verifying sector protection, the corresponding identifier code on DQ7–DQ0. Table 10. This method mand Sequence section for more information. Table 4. Am29LV642D Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

1. CE# can be replaced with CE2# when referring to the second die in the package.
2. The device ID’s used for the Am29LV642 are the same as the Am29LV640, because the Am29LV642 uses two Am29LV640

dice and appears to the system as two Am29LV640 devices.

20 Am29LV642D 25022A2 May 5, 2006

implemented via two methods. group unprotect write cycle. tact an AMD representative for details. Table 5. Sector Group Protection/Unprotection Note: All sector groups are 128 Kwords in size.

22 Am29LV642D 25022A2 May 5, 2006

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

and power-down transitions, or from system noise. CE2#, or WE# do not initiate a write cycle. zero while OE# is a logical one. automatically reset to the read mode on power-up. interfaces for long-term compatibility. as two 64 Mbit Am29LV640 devices in the system. 55h anytime the device is ready to read array data. the system must write the reset command. device to the autoselect mode. tative for copies of these documents. Table 6. CFI Query Identification String

24 Am29LV642D 25022A2 May 5, 2006

Table 7. System Interface String Table 8. Device Geometry Definition

Table 9. Primary Vendor-Specific Extended Query the device to reading array data. tics section for timing diagrams. Commands section for more information.

26 Am29LV642D 25022A2 May 5, 2006

See also “VersatileI/O ™ (VIO) Control” in the Device Bus Operations section for more information. The Read-Only Operations table provides the read param - eters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se - quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and re - quires V ID on address pin A9. The autoselect com - mand sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: ■ A read cycle at address XX00h returns the manu - facturer code. ■ A read cycle at address XX01h returns the device code. ■ A read cycle to an address containing a sector group address (SA), and the address 02h on A7–A0 returns 01h if the sector group is protected, or 00h if it is unprotected. (Refer to Table 5 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de vice was previously in Erase Suspend). Word Program Command Sequence Programming is a four-bus-cycle operation. The pro - gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad dresses are no longer latched. The system can deter - mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em - bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro - gram words to the device faster than using the stan - dard program command sequence. The unlock bypass command sequence is initiated by first writing two un lock cycles. This is followed by a third write cycle con - taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un lock bypass program command sequence is all that is

28 Am29LV642D 25022A2 May 5, 2006

When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im mediately terminates the erase operation. If that oc - curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase opera - tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad ditional unlock cycles are written, and are then fol - lowed by the address of the sector to be erased, and the sector erase command. Table 10 shows the ad - dress and data requirements for the sector erase com- mand sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto - matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad dress and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to en sure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must re write the command sequence and any additional ad - dresses and commands. The system can monitor DQ3 to determine if the sec - tor erase timer has timed out (See the section on DQ3: Sector Erase Timer.). The time-out begins from the ris- ing edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing sector. Refer to the Write Operation Status section for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4 illustrates the algorithm for the erase opera - tion. Refer to the Erase and Program Operations ta- bles in the AC Characteristics section for parameters, and Figure 17 section for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys - tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec tor erase operation, including the 50 µs time-out pe - riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max imum of 20 µs to suspend the erase operation. How - ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi ately terminates the time-out period and suspends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys tem can read data from or program data to any sector not selected for erasure. (The device “erase sus pends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors pro duces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for infor - mation on these status bits. After an erase-suspended program operation is com - plete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information.

can be written after the chip has resumed erasing. Figure 4. Erase Operation

1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector

30 Am29LV642D 25022A2 May 5, 2006

Table 10. Am29LV642D Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# (or CE2#) pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A21–A15 are don’t cares.
3. No unlock or command cycles required when device is in read
4. The Reset command is required to return to the read mode (or to

(while the device is providing status information).

1. The fourth cycle of the autoselect command sequence is a read
2. The data is 00h for an unprotected sector group and 01h for a
3. The Unlock Bypass command is required prior to the Unlock
4. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

32 Am29LV642D 25022A2 May 5, 2006

Table 11 shows the outputs for RY/BY#. operation is complete, DQ6 stops toggling. lected sectors that are protected. whether a sector is actively erasing or is erase-suspended. vice enters the Erase Suspend mode, DQ6 stops toggling. Table 11 shows the outputs for Toggle Bit I on DQ6. Figure 6. Toggle Bit Algorithm

34 Am29LV642D 25022A2 May 5, 2006

Table 11. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

36 Am29LV642D 25022A2 May 5, 2006

(For Two Am29LV640 Devices) CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Assumes only one Am29LV640 die being programmed at the same time. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 400 nA. 7. Not 100% tested. 8. CE# can be replaced with CE2# when referring to the second device within the package. 9. Specifications in the table are for the Am29LV64 2 i.e. two Am29LV640 dice unless otherwise noted . Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current VCC = VCC max; A9 = 12.5 V 70 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# (or CE2#) = VIL, OE# = VIH

5 MHz 9 16

1 MHz 2 4

VCC Active Write Current (Notes 2, 3, 4) CE# (or CE2#) = VIL, OE# = VIH 26 30 mA ICC3 VCC Standby Current (Note 2) CE#, CE2#, RESET# = VCC ± 0.3 V 0.4 10 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.4 10 µA ICC5 Automatic Sleep Mode (Notes 2, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.4 10 µA IACC ACC Accelerated Program Current (Note 4) CE# = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA VIL Input Low Voltage (Note 6) –0.5 0.8 V VIH Input High Voltage (Note 6) 0.7 x VCC VCC + 0.3 V VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage (Note 7) IOH = –2.0 mA, VCC = VCC min 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min VIO–0.4 V VLKO Low VCC Lock-Out Voltage (Note 7) 2.3 2.5 V

38 Am29LV642D 25022A2 May 5, 2006

Table 12. Test Specifications Note: If VIO < VCC, the reference level is 0.5 VIO. Figure 11. Test Setup Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 12. Input Waveforms and Measurement Levels

May 5, 2006 25022A2 Am29LV642D 39 DATA SHEET AC CHARACTERISTICS Read-Only Operations Notes: 1. All test setups assume V IO = VCC. 2. Not 100% tested. 3. See Figure 11 and Table 12 for test specifications 4. CE# can be replaced with CE2# when referring to the second device within the package. Parameter

Description

(Note 1) Speed Options JEDEC Std. 90R 12R Unit tAVAV tRC Read Cycle Time (Note 2) Min 90 120 ns tAVQV tACC Address to Output Delay CE#, OE# = VIL Max 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 90 120 ns tGLQV tOE Output Enable to Output Delay Max 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 2) Max 30 30 ns tGHQZ tDF Output Enable to Output High Z (Note 2) Max 30 30 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First Min 0 ns tOEH Output Enable Hold Time (Note 2) Read Min 0 ns Toggle and Data# Polling Min 10 ns tOH tCE Outputs WE# Addresses CE# or CE2# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH

0 VRY/BY#

RESET# tDF Figure 13. Read Operation Timings

40 Am29LV642D 25022A2 May 5, 2006

Figure 14. Reset Timings

May 5, 2006 25022A2 Am29LV642D 41 DATA SHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. CE# can be replaced with CE2# when referring to the second device within the package. Parameter Speed Options JEDEC Std. Description 90R 12R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 11 µs tWHWH1 tWHWH1 Accelerated Word Programming Operation (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1.6 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

42 Am29LV642D 25022A2 May 5, 2006

Note: PA = program address, PD = program data, DOUT is the true data at the program address. Figure 15. Program Operation Timings Figure 16. Accelerated Program Timing Diagram

Note: SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”. Figure 17. Chip/Sector Erase Operation Timings

44 Am29LV642D 25022A2 May 5, 2006

Figure 18. Data# Polling Timings (During Embedded Algorithms)

46 Am29LV642D 25022A2 May 5, 2006

Figure 21. Temporary Sector Group Unprotect Timing Diagram

• For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 22. Sector Group Protect and Unprotect Timing Diagram

48 Am29LV642D 25022A2 May 5, 2006

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. CE# can be replaced with CE2# when referring to the second device within the package. Parameter Speed Options JEDEC Std Description 90R 12R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 50 ns tDVEH tDS Data Setup Time Min 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 11 µs tWHWH1 tWHWH1 Accelerated Word Programming Operation (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1.6 sec

1. Figure indicates last two bus cycl es of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

Figure 23. Alternate CE# Controlled Write (Erase/Program) Operation Timings

50 Am29LV642D 25022A2 May 5, 2006

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 1.6 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 90 sec Word Program Time 11 300 µs Excludes system level overhead (Note 5)Accelerated Word Program Time 7 210 µs Chip Program Time (Note 3) 48 144 sec Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Yea r s 125°C 20 Yea r s

May 5, 2006 25022A2 Am29LV642D 51 DATA SHEET PHYSICAL DIMENSIONS LSA064—64-Ball Fortified Ball Grid Arra y (Fortified BGA) 13 x 11 mm package

52 Am29LV642D 25022A2 May 5, 2006

Revision A (August 14, 2001) Initial release. Revision A1 (January 7, 2005) Noted on the cover page and first page of data sheet that the Am29LV642D device has been superceded by the Spansion S29GL128N. Revision A2 (May 5, 2006) Updated migration/obsolescence notices. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion LLC will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those product. Trademarks Copyright © 2001–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.