L640MU11VI

AM29LV640MU_07 AMD | Alldatasheet

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Publication Number 25301 Revision C Amendment 5 Issue Date February 1, 2007 This product has been retired and is not avai lable for designs. For new and current designs, S29GL064A supersedes Am29LV640MU and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29LV640MU Data Sheet RETIRED PRODUCT

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Publication# 25301 Rev: C Amendment/5 Issue Date: February 1, 2007 DATA SHEET Am29LV640MU

64 Megabit (4 M x 16-Bit) MirrorBit™

3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control

DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Single power supply operation — 3 V for read, erase, and program operations „ VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V „ Manufactured on 0.23 µm MirrorBit process technology „ Secured Silicon Sector region — 128-word sector for permane nt, secure identification through an 8-word random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer „ Flexible sector architecture — One hundred twenty-eight 32 Kword sectors „ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection „ Minimum 100,000 erase cycle guarantee per sector „ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS „ High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 22 µs typical effective write buffer word programming time: 16-word write buffer reduces overall programming time for multiple-word/byte updates — 4-word page read buffer — 16-word write buffer „ Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current „ Package options — 63-ball Fine-Pitch BGA — 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES „ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices „ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: V ID-level method of changing code in locked sectors — ACC (high voltage) input accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29L V640M U and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

2 Am29LV640MU 25301C5 February 1, 2007

The Am29LV640MU is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words. The device has a 16-bit only data bus, and can be programmed either in the host system or in stan- dard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (V CC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Order- ing Information sections. The device is offered in a 63-ball Fine-Pitch BGA or 64-ball Fortified BGA pack- age. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to deter- mine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the V IO pin. Refer to the Ordering Information section for valid V IO options. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Secured Silicon Sector provides a 128-word area for code or data that can be permanently pro- tected. Once this sector is protected, no further changes within the sector can occur. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

February 1, 2007 25301C5 Am29LV640MU 3 DATA SHEET MIRRORBIT 64 MBIT DEVICE FAMILY RELATED DOCUMENTS To download related documents, click on the following links or go to www.amd.com →Flash Memory →Prod- uct Information→MirrorBit→Flash Information→Tech- nical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices AMD MirrorBit™ White Paper Migrating from Single-byte to Three-byte Device IDs Migration from Am29LV640DU to MirrorBit Am29LV640MU Device Bus Sector Architecture Packages V IO RY/BY# WP#, ACC WP# Protection LV065MU x8 Uniform (64 Kbyte) 48-pin TSOP (std. & rev. pinout), 63-ball FBGA Y es Y es ACC only No WP# LV640MT/B x8/x16 Boot (8 x 8 Kbyte at top & bottom) 48-pin TSOP , 63-ball Fine-pitch BGA, 64-ball Fortified BGA No Y es WP#/ACC pin 2 x 8 Kbyte top or bottom LV640MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout),

64 Fortified BGA Y es Y es WP#/ACC pin 1 x 64 Kbyte

LV641MH/L x16 Uniform (32 Kword) 48-pin TSOP (std. & rev. pinout) Y es No Separate WP# and ACC pins 1 x 32 Kword top or bottom LV640MU x16 Uniform (32 Kword) 63-ball Fine-pitch BGA, 64-ball Fortified BGA Y es Y es ACC only No WP#

4 Am29LV640MU 25301C5 February 1, 2007

Figure 2. In-System Sector Group Protect/Unprotect Algorithms ... 18 Figure 13. Input Waveforms and Figure 20. Data# Polling Timings Figure 21. Toggle Bit Timings Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 47 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 48 Figure 25. Alternate CE# Controlled Write (Erase/Program)

February 1, 2007 25301C5 Am29LV640MU 5 DATA SHEET PRODUCT SELECTOR GUIDE Notes: 1. See “AC Characteristics” for full specifications. 2. For the Am29LV640MU device, the last numeric digit in the speed option (e.g. 101 , 112, 120) is used for internal purposes only. Please use OPNs as listed when placing orders. BLOCK DIAGRAM Part Number Am29LV640MU Speed Option VCC = 3.0–3.6 V 90R (VIO = 3.0–3.6 V) 101R (VIO = 2.7–3.6 V) 112R (VIO = 1.65–3.6 V) 120R (VIO = 1.65–3.6 V) VCC = 2.7–3.6 V 101 (VIO = 2.7–3.6 V) 112 (VIO = 1.65–3.6 V) 120 (VIO = 1.65–3.6 V) Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access time (t PACC)2 5 3 0 3 0 4 0 3 0 4 0 Max. OE# Access Time (ns) 25 30 30 40 30 40 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS VIO WE# ACC CE# OE# STB STB DQ0–DQ15 Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA21–A0

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DQ4VCCDQ12DQ5A19A21RESET# DQ3DQ11DQ10DQ2A20A18ACC DQ1DQ9DQ8DQ0A5A6A17 NC A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 NCNCVIONCNCNCNC NC 64-Ball Fortified BGA Top View, Balls Facing Down

February 1, 2007 25301C5 Am29LV640MU 7 DATA SHEET CONNECTION DIAGRAMS Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP , BGA, SSOP , PDIP , PLCC). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7A7 B7 A8 B8 A1 B1 E7 F7 G7 H7 J7 K7 L7 NC* NC*NC* NC* NC* NC* NC* NC* NC* NC* NC*NC NC NC NC DQ15 VSSVIOA16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 * Balls are shorted together via the substrate but not connected to the die. 63-Ball Fine-Pitch BGA Top View, Balls Facing Down

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A21–A0 = 22 Address inputs DQ15–DQ0 = 15 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input ACC = Programming Acceleration input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL DQ15–DQ0 A21–A0 CE# OE# WE# RESET# RY/BY# ACC VIO

February 1, 2007 25301C5 Am29LV640MU 9 DATA SHEET

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Note: For the Am29LV640MU device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only. Use OPNs as listed when placing orders. Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of spe- cific valid combinations and to check on newly released combinations. Am29LV640M U 120R PC I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE PC = 64-Ball Fortified Ball Grid Array, 1.0 mm pitch, 13 x 11 mm package (LAA064) WH = 63-Ball Fine Pitch Ball Grid Array, 0.80 mm pitch, 12 x 11 mm package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE U = Uniform sector device DEVICE NUMBER/DESCRIPTION Am29LV640MU

64 Megabit (4 M x 16-Bit) MirrorBit™ Uniform Sector Flash Memory

with VersatileIO™ Control, 3.0 Volt-only Read, Program, and Erase Valid Combinations for Fortified or Fine-Pitch BGA Package Speed (ns) VIO Range VCC Range Order Number Package Marking Am29LV640MU90R WHI L640MU90R I9 0 3.0– 3.6 V 3.0–

3.6 VPCI L640MU90N

I 100 2.7– 3.6 V 2.7– 3.6 V PCI L640MU01P Am29LV640MU112 WHI L640MU11V I 110 1.65–

3.6 VPCI L640MU11P

WHI, L640MU12V I 120 1.65–

3.6 VPCI L640MU12P

WHI, L640MU01R I 100 2.7– 3.6 V 3.0– 3.6 V PCI L640MU01N Am29LV640MU112R WHI, L640MU11R I 110 1.65–

3.6 VPCI L640MU11N

WHI, L640MU12R I 120 1.65–

3.6 VPCI L640MU12N

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register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section. IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2). tion” on page 9 for VIO options on this device. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H XH i g h - Z

February 1, 2007 25301C5 Am29LV640MU 11 DATA SHEET to the DC Characteristics table for the active current specification for reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words. The appropriate page is se- lected by the higher address bits A(max)–A2. Address bits A1–A0 determine the specific word within a page. This is an asynchronous operation; the microproces- sor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word, instead of four. The Word Program Command Sequence section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Char- acteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and alwa ys available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification.

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RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for th e duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current. If RESET# is held at VIL but not within V SS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op- eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The sys- tem can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo- rithms). The system can read data t RH after the RE- SET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

Table 2. Sector Address Table

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Note: All sectors are 32 Kwords in size. Table 2. Sector Address Table (Continued)

accessed in-system through the command register. A6, A3, A2, A1, and A0 must be as shown in Table 3. mand Sequence section for more information. Table 3. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

16 Am29LV640MU 25301C5 February 1, 2007

implemented via two methods. the first sector group unprotect write cycle. tact an AMD representative for details. Table 4. Sector Group Protection/Unprotection Note: All sector groups are 128 Kwords in size.

Figure 1. Temporary Sector Group

1. All protected sector groups unprotected.
2. All previously protected sector groups are protected

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Figure 2. In-System Sector Group Protect/Unprotect Algorithms

vices that are factory locked. addresses normally occupied by the first sector (SA0). verts to sending commands to sector SA0. protected when the device is shipped from the factory. gram and protect the 128-word Secured Silicon sector. ming command sequence. See Command Definitions. ble to the Secured Silicon Sector. Table 5. Secured Silicon Sector Contents

20 Am29LV640MU 25301C5 February 1, 2007

Figure 3. Secured Silicon Sector Protect Verify and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to the read mode on power-up.

interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data. Table 6. CFI Query Identification String Table 7. System Interface String

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Table 8. Device Geometry Definition

Table 9. Primary Vendor-Specific Extended Query

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Writing specific address and data commands or se- quences into the command register initiates device op- erations. Table 10 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Command , for more informa- tion. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an aut oselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Pro- gramming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: Note: The device ID is read over three cycles. SA = Sector Address Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Identifier Code A7:A0 Manufacturer ID 00h Device ID, Cycle 1 01h Device ID, Cycle 2 0Eh Device ID, Cycle 3 0Fh Secured Silicon Sector Factory Protect 03h Sector Protect Verify (SA)02h

February 1, 2007 25301C5 Am29LV640MU 25 DATA SHEET Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing an 8-word random Electronic Se- rial Number (ESN). The system can access the Se- cured Silicon Sector region by issuing the three-cycle Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence re- turns the device to normal operation. Table 10 shows the address and data requirements for both command sequences. See also Secured Silicon Sector Flash Memory Region for further information. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Operation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Table 10 shows the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load com- mand written at the Sector Address in which program- ming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. A write-buffer-page is se- lected by address bits A MAX–A4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be

26 Am29LV640MU 25301C5 February 1, 2007

decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter dec- rements for each data load operation, not for each unique write-buffer-address location. Additionally, the last data loaded prior to the Program Buffer to Flash command will be programmed into the device. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that ad- dress will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last add ress location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is re- quired when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the ACC pin. When the system asserts V HH on the ACC pin, the device automatically enters the Un- lock Bypass mode. The system may then write the two-cycle Unlock Bypass program command se- quence. The device uses the higher voltage on the ACC pin to accelerate the operation. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may re- sult. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

1. If this flowchart location was reached because

command. if DQ5=1, write the Reset command.

1. See Table 10 for command sequences required for

28 Am29LV640MU 25301C5 February 1, 2007

Figure 5. Program Operation μs maximum (5 μs typical) and updates the status bits. quences to enter and exit this region. Autoselect Command Sequence for more information. written after the device has resume programming. Note: See Table 10 for program command sequence.

30 Am29LV640MU 25301C5 February 1, 2007

reading array data, to ensure data integrity. and Figure 18 section for timing diagrams. if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard word program operation. a longer cumulative erase time than without suspends. Figure 7. Erase Operation

1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 10. Command Definitions RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycles. All others are write cycles.
4. During unlock and command cycles, when lower address bits are

data bits higher than DQ7 are don’t care.

1. Unless otherwise noted, address bits A21–A11 are don’t cares.
2. No unlock or command cycles required when device is in read
3. The Reset command is required to return to the read mode (or to

(while the device is providing status information).

1. The fourth cycle of the autoselect command sequence is a read
2. The device ID must be read in three cycles.
3. The data is 98h for factory locked and 18h for not factory locked.
4. The data is 00h for an unprotected sector group and 01h for a
5. The total number of cycles in the command sequence is

including "Program Buffer to Flash" command.

1. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

32 Am29LV640MU 25301C5 February 1, 2007

final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 11 shows the outputs for Data# Polling on DQ7. Figure 8. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

February 1, 2007 25301C5 Am29LV640MU 33 DATA SHEET RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev- eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively eras- ing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or the device is in the erase-suspend-read mode. Table 11 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com- plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ad- dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read c ycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approxi- mately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the de- vice enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alterna- tively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 11 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

34 Am29LV640MU 25301C5 February 1, 2007

Figure 9. Toggle Bit Algorithm algorithm. See also the DQ6: Toggle Bit I subsection.

termine the status of the operation (top of Figure 8). in the erase-suspend-program mode). device will accept additional sector erase commands. last command might not have been accepted. Table 11. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

36 Am29LV640MU 25301C5 February 1, 2007

1. Minimum DC voltage on input or I/O pins is –0.5 V.

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V.

1. Minimum DC input voltage on pins A9, OE#, ACC, and

which may overshoot to +14.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability.

1. Operating ranges define those limits between which the

functionality of the device is guaranteed.

1. See Ordering Information section for valid VCC/VIO range

Figure 10. Maximum Negative Figure 11. Maximum Positive

February 1, 2007 25301C5 Am29LV640MU 37 DATA SHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. for these connections is VIO + 0.3 V 6. V CC voltage requirements. 8. Not 100% tested. 9. Includes RY/BY#. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit I LI Input Load Current (Note 1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH

5 MHz 15 20

1 MHz 15 20

VCC Initial Page Read Current (Notes 1, 2) CE# = VIL, OE# = VIH 30 50 mA ICC3 VCC Intra-Page Read Current (Notes 1, 2) CE# = VIL, OE# = VIH 10 20 mA ICC4 VCC Active Write Current (Notes 2, 3) CE# = V IL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (Note 2) CE#, RESET# = V CC ± 0.3 V 1 5 µA ICC6 VCC Reset Current (Note 2) RESET# = V SS ± 0.3 V 1 5 µA ICC7 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 15 µ A VIL1 Input Low Voltage 1(Notes 5, 6) –0.5 0.8 V VIH1 Input High Voltage 1 (Notes 5, 6) 0.7 x V CC VCC + 0.5 V VIL2 Input Low Voltage 2 (Notes 5, 7) –0.5 0.3 x V IO V VIH2 Input High Voltage 2 (Notes 5, 7) 0.7 x V IO VIO + 0.5 V VHH Voltage for ACC Program Acceleration VCC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage (Note 9) I OL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (Note 8) 2.3 2.5 V

38 Am29LV640MU 25301C5 February 1, 2007

Table 12. Test Specifications Note: If VIO < VCC, the reference level is 0.5 VIO. Figure 12. Test Setup Note: If VIO < VCC, the input measurement reference level is 0.5 VIO.

1. See Figure 11 and Table 12 for test specifications.

0 VRY/BY#

Figure 14. Read Operation Timings

40 Am29LV640MU 25301C5 February 1, 2007

Figure 15. Page Read Timings

Figure 16. Reset Timings

42 Am29LV640MU 25301C5 February 1, 2007

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. 5. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 6. AC specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101 112 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Word Program Time, using the Write Buffer (Notes 2, 4) Typ 22 µs Effective Accelerated Word Program Time, using the Write Buffer (Notes 2, 4) Typ 17.6 µs Single Word Program Operation (Note 2, 5) Typ 100 µs Accelerated Single Word Programming Operation (Note 2, 5) Typ 90 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1)M i n 2 5 0 n s tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY WE# High to RY/BY# Low Max 90 100 110 120 ns tPOLL Program Valid Before Status Polling (Note 7)M a x 4 µ s

44 Am29LV640MU 25301C5 February 1, 2007

SA= sector address (for Sector Erase), VA= Valid Address for reading status data (see “Write Operation Status”). Figure 19. Chip/Sector Erase Operation Timings

46 Am29LV640MU 25301C5 February 1, 2007

Figure 22. DQ2 vs. DQ6

Figure 23. Temporary Sector Group Unprotect Timing Diagram

48 Am29LV640MU 25301C5 February 1, 2007

• For sector group protect, A6:A0 = 0xx0010. For sector group unprotect, A6:A0 = 1xx0010.

Figure 24. Sector Group Protect and Unprotect Timing Diagram

February 1, 2007 25301C5 Am29LV640MU 49 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Write buffer program is typical per word. 3. For 1–16 words programmed. 4. Effective write buffer specification is based upon a 16-word write buffer operation. 5. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 6. AC specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101, 101R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Word Program Time, using the Write Buffer (Notes 2, 4) Typ 22 µs Effective Accelerated Word Program Time, using the Write Buffer (Notes 2, 4) Typ 17.6 µs Single Word Program (Note 2, 5)T y p 1 0 0 µ s Accelerated Single Word Programming Operation (Note 2, 5) Typ 90 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tRH RESET # High Time Before Write (Note 1) Min 50 ns tPOLL Program Valid Before Status Polling (Note 7) Max 4 µs

50 Am29LV640MU 25301C5 February 1, 2007

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

February 1, 2007 25301C5 Am29LV640MU 51 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word programming specification is based upon a single word programming operation not utilizing the write buffer. 4. For 1-16 words programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word basis for a 16-word write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Table 10 for further information on command definitions. 8. The device has a minimum erase and pr ogram cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 15 sec Excludes 00h programming prior to erasure (Note 6)Chip Erase Time 64 128 sec Single Word Program Time (Note 3) 100 800 µs Excludes system level overhead (Note 7) Accelerated Single Word Program Time (Note 3) 90 720 µs Total Write Buffer Program Time (Note 4) 352 1800 µs Effective Word Program Time, using the Write Buffer (Note 5) 22 113 µs Total Accelerated Write Buffer Program Time (Note 4) 282 1560 µs Effective Accelerated Word Program Time, using the Write Buffer (Note 4) 17.6 98 µs Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA

52 Am29LV640MU 25301C5 February 1, 2007

TSOP PIN AND FINE-PITCH BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Symbol Parameter Desc ription Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF COUT Output Capacitance V OUT = 0 TSOP 8.5 12 pF Fine-pitch BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 pF Fine-pitch BGA 3.9 4.7 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

February 1, 2007 25301C5 Am29LV640MU 53 DATA SHEET PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FBGA) 13 x 11 mm Package

54 Am29LV640MU 25301C5 February 1, 2007

FBE063—63-Ball Fine-Pitch Ball Gr id Array (FBGA) 12 x 11 mm Package Dwg rev AF; 10/99

56 Am29LV640MU 25301C5 February 1, 2007

Revision B+4 (February 16, 2003) Distinctive Characteristics Corrected performance characteristics. Product Selector Guide Added note 2. Corrected Valid Combination to reflect speed option changes. Added Note. AC Characteristics Removed 90R speed option. Added Note Input values in the t WHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previ- ously TBD. Also added notes 5 and 6. Input values in the t WHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Op- tions table that were previously TBD. Also added notes 5 and 6. Erase and Programming Performance Input values into table that were previously TBD. Added note 4. Revision C (March 11, 2003) Product Selector Guide and AC Characteristics, Read Only Operations Table Added separate values for the 112 and 120 ns speed options in the Page access times and OE# access time. Removed note from sector architecture. tion and Secured Silicon Sector Indicator Bit. Updated second bullet in Customer Lockable section. voltage range title for remaining VCC. Updated ICC parameter symbol. Added 90R speed grade, modified note. Erase and Programming Performance Modified table, inserted values for Typical. Revision C+2 (February 13, 2004) Writing Commands/Command Sequence Removed byte reference. Word/Byte Program Command Sequence Removed byte reference. Erase Suspend/Erase Resume Commands Added note on flash device performance during suspend/erase mode. Table 10: Command Definitions Replaced the Addr information for Program/Erase Suspend and Program/Erase Resume from BA to XXX. AC Characteristics - Erase and Program Operations, and Alternate CE# Controlled Erase and Program Operations Added t POLL information. AC Characteristics Figures - Program Operation Timings, Data# Polling Timings (During Embedded Algorithms, and Alternate CE# Controlled Write (Erase/Program) Operation Timings Updated figures with t POLL information. Erase and Programming Performance Removed byte reference. Incorporated comments 6 & 7 to table. Trademarks Updated. Revision C + 3 (August 23, 2004) Added Max programming specifications. Added notation referencing superseding documenta- tion.

February 1, 2007 25301C5 Am29LV640MU 57 DATA SHEET Revision C + 4 (December 13, 2005) Global This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M U and is the factory-recom- mended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Revision C5 (February 1, 2007) Global Changed SecSi Sector to Secured Silicon Sector. AC Characteristics Erase and Program Operations table: Changed t BUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2001–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.