L640ML11NI

AM29LV640MH AMD | Alldatasheet

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Publication Number 26191 Revision F Amendment +3 Issue Date December 14, 2005 Am29LV640MH/L Data Sheet RETIRED PRODUCT This product has been retired and is not avai lable for designs. For new and current designs, S29GL064A supersedes Am29LV640M H/L and is th e factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. April 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 26191 Rev: F Amendment/3 Issue Date: December 14, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. Am29LV640MH/L

64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™

3.0 Volt-only Uniform Sector Flash Memory

with VersatileI/O™ Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Single power supply operation — 3 V for read, erase, and program operations „ VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages on the DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V „ Manufactured on 0.23 µm MirrorBit process technology „ SecSi™ (Secured Silicon) Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer „ Flexible sector architecture — One hundred twenty-eight 32 Kword/64-Kbyte sectors „ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection „ Minimum 100,000 erase cycle guarantee per sector „ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS „ High performance — 90 ns access time — 25 ns page read times — 0.5 s typical sector erase time — 22 µs typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word/byte updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer „ Low power consumption (typical values at 3.0 V, 5 MHz) — 30 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current „ Package options — 56-pin TSOP — 64-ball Fortified BGA SOFTWARE FEATURES — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resu me: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices HARDWARE FEATURES — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Unprotect: V ID-level method of changing code in locked sectors — WP#/ACC input: Write Protect input (WP#) protects first or last sector regardless of sector protection settings ACC (high voltage) accelerates programming time for higher throughput during system production — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) indicates program or erase cycle completion This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29L V640M H/L and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

2 Am29LV640MH/L December 14, 2005

The Am29LV640MH/L is a 64 Mbit, 3.0 volt single power supply flash memory device organized as 4,194,304 words or 8,388,608 bytes. The device has an 8-bit/16-bit bus and can be programmed either in the host system or in standard EPROM programmers. An access time of 90, 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (V CC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Order- ing Information sections. The device is offered in a 56-pin TSOP or 64-ball Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (ACC) feature provides shorter programming times through increased current on the WP#/ACC input. This feature is intended to facili tate factory throughput dur- ing system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to deter- mine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the V IO pin. Refer to the Ordering Information section for valid V IO options. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP#/ACC pin. The protected sector will still be protected even during accelerated programming. The SecSi ™ (Secured Silicon) Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. Spansion MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection.

December 14, 2005 Am29LV640MH/L 3 DATASHEET MIRRORBIT 64 MBIT DEVICE FAMILY Related Documents To download related documents, click on the following links or go to www.amd.com →Flash Memory →Prod- uct Information→MirrorBit→Flash Information→Tech- nical Documentation. MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs AMD MirrorBit™ White Paper Device Bus Sector Architecture Packages V IO RY/BY# WP#, ACC WP# Protection LV065MU x8 Uniform (64 Kbyte) 48-pin TSOP (std. & rev. pinout), 63-ball FBGA Y es Y es ACC only No WP# LV640MT/B x8/x16 Boot (8 x 8 Kbyte at top & bottom) 48-pin TSOP , 63-ball Fine-pitch BGA, 64-ball Fortified BGA No Y es WP#/ACC pin 2 x 8 Kbyte top or bottom LV640MH/L x8/x16 Uniform (64 Kbyte) 56-pin TSOP (std. & rev. pinout), 64-ball Fortified BGA Y es Y es WP#/ACC pin 1 x 64 Kbyte high or low LV641MH/L x16 Uniform (32 Kword) 48-pin TSOP (std. & rev. pinout) Y es No Separate WP# and ACC pins 1 x 32 Kword top or bottom LV640MU x16 Uniform (32 Kword) 64-ball Fortified BGA, 64-Ball Fine-Pitch BGA Y es Y es ACC only No WP#

4 Am29LV640MH/L December 14, 2005

Figure 2. In-System Sector Group Figure 11. Maximum Positive Figure 13. Input Waveforms and Figure 20. Data# Polling Timings Figure 23. Temporary Sector Group Unprotect Timing Diagram ... 52 Figure 24. Sector Group Protect and Unprotect Timing Diagram .. 53 Figure 25. Alternate CE# Controlled Write (Erase/Program)

December 14, 2005 26191F3 Am29LV640MH/L 5 DATASHEET PRODUCT SELECTOR GUIDE Notes: 1. See “AC Characteristics” for full specifications. 2. For the Am29LV640MH-L device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only. Please use OPNs as listed on p. 9 when placing orders. BLOCK DIAGRAM Part Number Am29LV640MH/L Speed Option VCC = 3.0–3.6 V 90R (VIO = 3.0– 3.6 V) 101R (VIO = 2.7– 3.6 V) 112R (VIO = 1.65– 3.6 V) 120R (VIO = 1.65 –3.6 V) VCC = 2.7–3.6 V 101 (VIO = 2.7– 3.6 V) 112 (VIO = 1.65 –3.6 V) 120 (VIO = 1.65– 3.6 V) Max. Access Time (ns) 90 100 110 120 Max. CE# Access Time (ns) 90 100 110 120 Max. Page access time PACC) 25 30 30 40 30 40 Max. OE# Access Time (ns) 25 30 30 40 30 40 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WP#/ACC BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA21–A0 VIO

6 Am29LV640MH/L 26191F3 December 14, 2005

V IO A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# V SS CE# DQ5 DQ12 DQ4 V CC DQ11 DQ3 DQ10 56-Pin Standard TSOP NC NC A15 A14 A13 A12 A11 A10 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 NC NC A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 NC NC OE# V SS CE# NC VIO 56-Pin Reverse TSOP

December 14, 2005 Am29LV640MH/L 7 DATASHEET CONNECTION DIAGRAMS Special Package Handling Instructions Special handling is required for Flash Memory prod- ucts in molded packages (TSOP and BGA). The pack- age and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 NCNCNCVSSVIONCNC VSSDQ15/A-1BYTE#A16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19A21RESET# DQ3DQ11DQ10DQ2A20A18WP#/ACC DQ1DQ9DQ8DQ0A5A6A17 NC A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 NCNCVIONCNCNCNC NC 64-Ball Fortified BGA Top View, Balls Facing Down

8 Am29LV640MH/L December 14, 2005

A21–A0 = 22 Address inputs DQ14–DQ0 = 15 Data inputs/outputs DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect input/Pro- gramming Acceleration input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output BYTE# = Selects 8-bit or 16-bit mode V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally Logic Symbol 16 or 8 DQ15–DQ0 (A-1) A21–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO BYTE#

December 14, 2005 Am29LV640MH/L 9 DATASHEET

ORDERING INFORMATION

Standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Notes: 1. For the Am29LV640MH-L device, the last numeric digit in the speed option (e.g. 101, 112, 120) is used for internal purposes only. 2. To select product with ESN factory-locked into the SecSi Sector: 1) select order number from the valid combinations given above, 2) add designator “N” at the end of the order number, and 3) modify the speed option indicator as follows [101R = 10R, 112R = 11R, 120R = 12R, 90R, 101, 112, 120 = no change] Example: Am29LV640MH12RPCIN. For Fortified BGA packages, the designator “N” will also appear at the end of the package marking. Example: L640MH12NIN. Am29LV640M H 120R PC I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056) F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056) PC = 64-Ball Fortified Ball Grid Array, 1.0 mm pitch, 13 x 11 mm package (LAA064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND WP# PROTECTION (WP# = V IL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV640MH/L

64 Megabit (4 M x 16-Bit/8 M x 8-Bit) MirrorBit™ Uniform Sector Flash Memory

with VersatileIO™ Control, 3.0 Volt-only Read, Program, and Erase Valid Combinations for Speed (ns) VIO Range (V) VCC Range (V) Am29LV640MH90R Am29LV640ML90R EI, FI 90 3.0–3.6 3.0–3.6 Am29LV640MH112 Am29LV640ML112 110 1.65–3.6 2.7–3.6Am29LV640MH120 Am29LV640ML120 120 1.65–3.6 Am29LV640MH101R Am29LV640ML101R 100 2.7–3.6 3.0–3.6Am29LV640MH112R Am29LV640ML112R 110 1.65–3.6 Am29LV640MH120R Am29LV640ML120R 120 1.65–3.6 Valid Combinations for Fortified BGA Package (Note 2) Speed (ns) VIO Range (V) VCC Range (V)Order Number Package Marking Am29LV640MH90R Am29LV640ML90R PCI L640MH90NI L640ML90NI 90 3.0– 3.6 3.0– 3.6 Am29LV640MH101 Am29LV640ML101 L640MH01PI L640ML01PI 100 2.7– 3.6 2.7– 3.6 Am29LV640MH112 Am29LV640ML112 L640MH11PI L640ML11PI 110 1.65– 3.6 Am29LV640MH120 Am29LV640ML120 L640MH12PI L640ML12PI 120 1.65– 3.6 Am29LV640MH101R Am29LV640ML101R L640MH01NI L640ML01NI 100 2.7– 3.0– 3.6 Am29LV640MH112R Am29LV640ML112R L640MH11NI L640ML11NI 110 1.65– 3.6 Am29LV640MH120R Am29LV640ML120R L640MH12NI L640ML12NI 120 1.65– 3.6

10 Am29LV640MH/L December 14, 2005

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A21:A0 in word mode; A21:A-1 in byte

mode. Sector addresses are A21:A15 in both modes.

1. The sector protect and sector unprotect functions may also

“Sector Group Protection and Unprotection” section.

1. If WP# = V IL, the first or last sector remains protected. If

polling, or sector protect algorithm (see Figure 2).

0.3 V XX VCC ±

0.3 V X H X High-Z High-Z High-Z

December 14, 2005 Am29LV640MH/L 11 DATASHEET Word/Byte Configuration The BYTE# pin controls whether the device data I/O pins operate in the byte or word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con- figuration, DQ0–DQ15 are active and controlled by CE# and OE#. If the BYTE# pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. VersatileIO™ (VIO) Control The VersatileIO™ (VIO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on V IO. See “Ordering Informa- tion” on page 9 for VIO options on this device. For example, a V I/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing speci- fications and to Figure 14 for the timing diagram. Refer to the DC Characteristics ta ble for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Ad- dress bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteri stics table for the active current specification for the write mode. The AC Char- acteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system to write a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be

12 Am29LV640MH/L December 14, 2005

at VHH for operations other than accelerated program- ming, or device damage may result. In addition, no ex- ternal pullup is necessary since the WP#/ACC pin has internal pullup to V CC. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for th e duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 16 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

December 14, 2005 Am29LV640MH/L 13 DATASHEET Sector A21–A15 Sector Size (Kbytes/Kwords) 8-bit Address Range (in hexadecimal) 16-bit Address Range (in hexadecimal) SA0 0 0 0 0 0 0 0 64/32 000000–00FFFF 000000–007FFF SA1 0 0 0 0 0 0 1 64/32 010000–01FFFF 008000–00FFFF SA2 0 0 0 0 0 1 0 64/32 020000–02FFFF 010000–017FFF SA3 0 0 0 0 0 1 1 64/32 030000–03FFFF 018000–01FFFF SA4 0 0 0 0 1 0 0 64/32 040000–04FFFF 020000–027FFF SA5 0 0 0 0 1 0 1 64/32 050000–05FFFF 028000–02FFFF SA6 0 0 0 0 1 1 0 64/32 060000–06FFFF 030000–037FFF SA7 0 0 0 0 1 1 1 64/32 070000–07FFFF 038000–03FFFF SA8 0 0 0 1 0 0 0 64/32 080000–08FFFF 040000–047FFF SA9 0 0 0 1 0 0 1 64/32 090000–09FFFF 048000–04FFFF SA10 0 0 0 1 0 1 0 64/32 0A0000–0AFFFF 050000–057FFF SA11 0 0 0 1 0 1 1 64/32 0B0000–0BFFFF 058000–05FFFF SA12 0 0 0 1 1 0 0 64/32 0C0000–0CFFFF 060000–067FFF SA13 0 0 0 1 1 0 1 64/32 0D0000–0DFFFF 068000–06FFFF SA14 0 0 0 1 1 1 0 64/32 0E0000–0EFFFF 070000–077FFF SA15 0 0 0 1 1 1 1 64/32 0F0000–0FFFFF 078000–07FFFF SA16 0 0 1 0 0 0 0 64/32 100000–10FFFF 080000–087FFF SA17 0 0 1 0 0 0 1 64/32 110000–11FFFF 088000–08FFFF SA18 0 0 1 0 0 1 0 64/32 120000–12FFFF 090000–097FFF SA19 0 0 1 0 0 1 1 64/32 130000–13FFFF 098000–09FFFF SA20 0 0 1 0 1 0 0 64/32 140000–14FFFF 0A0000–0A7FFF SA21 0 0 1 0 1 0 1 64/32 150000–15FFFF 0A8000–0AFFFF SA22 0 0 1 0 1 1 0 64/32 160000–16FFFF 0B0000–0B7FFF SA23 0 0 1 0 1 1 1 64/32 170000–17FFFF 0B8000–0BFFFF SA24 0 0 1 1 0 0 0 64/32 180000–18FFFF 0C0000–0C7FFF SA25 0 0 1 1 0 0 1 64/32 190000–19FFFF 0C8000–0CFFFF SA26 0 0 1 1 0 1 0 64/32 1A0000–1AFFFF 0D0000–0D7FFF SA27 0 0 1 1 0 1 1 64/32 1B0000–1BFFFF 0D8000–0DFFFF SA28 0 0 1 1 1 0 0 64/32 1C0000–1CFFFF 0E0000–0E7FFF SA29 0 0 1 1 1 0 1 64/32 1D0000–1DFFFF 0E8000–0EFFFF SA30 0 0 1 1 1 1 0 64/32 1E0000–1EFFFF 0F0000–0F7FFF SA31 0 0 1 1 1 1 1 64/32 1F0000–1FFFFF 0F8000–0FFFFF SA32 0 1 0 0 0 0 0 64/32 200000–20FFFF 100000–107FFF SA33 0 1 0 0 0 0 1 64/32 210000–21FFFF 108000–10FFFF SA34 0 1 0 0 0 1 0 64/32 220000–22FFFF 110000–117FFF SA35 0 1 0 0 0 1 1 64/32 230000–23FFFF 118000–11FFFF SA36 0 1 0 0 1 0 0 64/32 240000–24FFFF 120000–127FFF SA37 0 1 0 0 1 0 1 64/32 250000–25FFFF 128000–12FFFF SA38 0 1 0 0 1 1 0 64/32 260000–26FFFF 130000–137FFF SA39 0 1 0 0 1 1 1 64/32 270000–27FFFF 138000–13FFFF SA40 0 1 0 1 0 0 0 64/32 280000–28FFFF 140000–147FFF SA41 0 1 0 1 0 0 1 64/32 290000–29FFFF 148000–14FFFF SA42 0 1 0 1 0 1 0 64/32 2A0000–2AFFFF 150000–157FFF SA43 0 1 0 1 0 1 1 64/32 2B0000–2BFFFF 158000–15FFFF SA44 0 1 0 1 1 0 0 64/32 2C0000–2CFFFF 160000–167FFF SA45 0 1 0 1 1 0 1 64/32 2D0000–2DFFFF 168000–16FFFF SA46 0 1 0 1 1 1 0 64/32 2E0000–2EFFFF 170000–177FFF SA47 0 1 0 1 1 1 1 64/32 2F0000–2FFFFF 178000–17FFFF SA48 0 1 1 0 0 0 0 64/32 300000–30FFFF 180000–187FFF SA49 0 1 1 0 0 0 1 64/32 310000–31FFFF 188000–18FFFF SA50 0 1 1 0 0 1 0 64/32 320000–32FFFF 190000–197FFF SA51 0 1 1 0 0 1 1 64/32 330000–33FFFF 198000–19FFFF SA52 0 1 1 0 1 0 0 64/32 340000–34FFFF 1A0000–1A7FFF SA53 0 1 1 0 1 0 1 64/32 350000–35FFFF 1A8000–1AFFFF SA54 0 1 1 0 1 1 0 64/32 360000–36FFFF 1B0000–1B7FFF SA55 0 1 1 0 1 1 1 64/32 370000–37FFFF 1B8000–1BFFFF

14 Am29LV640MH/L December 14, 2005

SA56 0 1 1 1 0 0 0 64/32 380000–38FFFF 1C0000–1C7FFF SA57 0 1 1 1 0 0 1 64/32 390000–39FFFF 1C8000–1CFFFF SA58 0 1 1 1 0 1 0 64/32 3A0000–3AFFFF 1D0000–1D7FFF SA59 0 1 1 1 0 1 1 64/32 3B0000–3BFFFF 1D8000–1DFFFF SA60 0 1 1 1 1 0 0 64/32 3C0000–3CFFFF 1E0000–1E7FFF SA61 0 1 1 1 1 0 1 64/32 3D0000–3DFFFF 1E8000–1EFFFF SA62 0 1 1 1 1 1 0 64/32 3E0000–3EFFFF 1F0000–1F7FFF SA63 0 1 1 1 1 1 1 64/32 3F0000–3FFFFF 1F8000–1FFFFF SA64 1 0 0 0 0 0 0 64/32 400000–40FFFF 200000–207FFF SA65 1 0 0 0 0 0 1 64/32 410000–41FFFF 208000–20FFFF SA66 1 0 0 0 0 1 0 64/32 420000–42FFFF 210000–217FFF SA67 1 0 0 0 0 1 1 64/32 430000–43FFFF 218000–21FFFF SA68 1 0 0 0 1 0 0 64/32 440000–44FFFF 220000–227FFF SA69 1 0 0 0 1 0 1 64/32 450000–45FFFF 228000–22FFFF SA70 1 0 0 0 1 1 0 64/32 460000–46FFFF 230000–237FFF SA71 1 0 0 0 1 1 1 64/32 470000–47FFFF 238000–23FFFF SA72 1 0 0 1 0 0 0 64/32 480000–48FFFF 240000–247FFF SA73 1 0 0 1 0 0 1 64/32 490000–49FFFF 248000–24FFFF SA74 1 0 0 1 0 1 0 64/32 4A0000–4AFFFF 250000–257FFF SA75 1 0 0 1 0 1 1 64/32 4B0000–4BFFFF 258000–25FFFF SA76 1 0 0 1 1 0 0 64/32 4C0000–4CFFFF 260000–267FFF SA77 1 0 0 1 1 0 1 64/32 4D0000–4DFFFF 268000–26FFFF SA78 1 0 0 1 1 1 0 64/32 4E0000–4EFFFF 270000–277FFF SA79 1 0 0 1 1 1 1 64/32 4F0000–4FFFFF 278000–27FFFF SA80 1 0 1 0 0 0 0 64/32 500000–50FFFF 280000–287FFF SA81 1 0 1 0 0 0 1 64/32 510000–51FFFF 288000–28FFFF SA82 1 0 1 0 0 1 0 64/32 520000–52FFFF 290000–297FFF SA83 1 0 1 0 0 1 1 64/32 530000–53FFFF 298000–29FFFF SA84 1 0 1 0 1 0 0 64/32 540000–54FFFF 2A0000–2A7FFF SA85 1 0 1 0 1 0 1 64/32 550000–55FFFF 2A8000–2AFFFF SA86 1 0 1 0 1 1 0 64/32 560000–56FFFF 2B0000–2B7FFF SA87 1 0 1 0 1 1 1 64/32 570000–57FFFF 2B8000–2BFFFF SA88 1 0 1 1 0 0 0 64/32 580000–58FFFF 2C0000–2C7FFF SA89 1 0 1 1 0 0 1 64/32 590000–59FFFF 2C8000–2CFFFF SA90 1 0 1 1 0 1 0 64/32 5A0000–5AFFFF 2D0000–2D7FFF SA91 1 0 1 1 0 1 1 64/32 5B0000–5BFFFF 2D8000–2DFFFF SA92 1 0 1 1 1 0 0 64/32 5C0000–5CFFFF 2E0000–2E7FFF SA93 1 0 1 1 1 0 1 64/32 5D0000–5DFFFF 2E8000–2EFFFF SA94 1 0 1 1 1 1 0 64/32 5E0000–5EFFFF 2F0000–2F7FFF SA95 1 0 1 1 1 1 1 64/32 5F0000–5FFFFF 2F8000–2FFFFF SA96 1 1 0 0 0 0 0 64/32 600000–60FFFF 300000–307FFF SA97 1 1 0 0 0 0 1 64/32 610000–61FFFF 308000–30FFFF SA98 1 1 0 0 0 1 0 64/32 620000–62FFFF 310000–317FFF SA99 1 1 0 0 0 1 1 64/32 630000–63FFFF 318000–31FFFF SA100 1 1 0 0 1 0 0 64/32 640000–64FFFF 320000–327FFF SA101 1 1 0 0 1 0 1 64/32 650000–65FFFF 328000–32FFFF SA102 1 1 0 0 1 1 0 64/32 660000–66FFFF 330000–337FFF SA103 1 1 0 0 1 1 1 64/32 670000–67FFFF 338000–33FFFF SA104 1 1 0 1 0 0 0 64/32 680000–68FFFF 340000–347FFF SA105 1 1 0 1 0 0 1 64/32 690000–69FFFF 348000–34FFFF SA106 1 1 0 1 0 1 0 64/32 6A0000–6AFFFF 350000–357FFF SA107 1 1 0 1 0 1 1 64/32 6B0000–6BFFFF 358000–35FFFF SA108 1 1 0 1 1 0 0 64/32 6C0000–6CFFFF 360000–367FFF SA109 1 1 0 1 1 0 1 64/32 6D0000–6DFFFF 368000–36FFFF SA110 1 1 0 1 1 1 0 64/32 6E0000–6EFFFF 370000–377FFF SA111 1 1 0 1 1 1 1 64/32 6F0000–6FFFFF 378000–37FFFF Sector A21–A15 Sector Size (Kbytes/Kwords) 8-bit Address Range (in hexadecimal) 16-bit Address Range (in hexadecimal)

December 14, 2005 Am29LV640MH/L 15 DATASHEET Note: The address range is A21:A-1 in byte mode (BYTE# = VIL) or A21:A0 in word mode (BYTE# = VIH). SA112 1 1 1 0 0 0 0 64/32 700000–70FFFF 380000–387FFF SA113 1 1 1 0 0 0 1 64/32 710000–71FFFF 388000–38FFFF SA114 1 1 1 0 0 1 0 64/32 720000–72FFFF 390000–397FFF SA115 1 1 1 0 0 1 1 64/32 730000–73FFFF 398000–39FFFF SA116 1 1 1 0 1 0 0 64/32 740000–74FFFF 3A0000–3A7FFF SA117 1 1 1 0 1 0 1 64/32 750000–75FFFF 3A8000–3AFFFF SA118 1 1 1 0 1 1 0 64/32 760000–76FFFF 3B0000–3B7FFF SA119 1 1 1 0 1 1 1 64/32 770000–77FFFF 3B8000–3BFFFF SA120 1 1 1 1 0 0 0 64/32 780000–78FFFF 3C0000–3C7FFF SA121 1 1 1 1 0 0 1 64/32 790000–79FFFF 3C8000–3CFFFF SA122 1 1 1 1 0 1 0 64/32 7A0000–7AFFFF 3D0000–3D7FFF SA123 1 1 1 1 0 1 1 64/32 7B0000–7BFFFF 3D8000–3DFFFF SA124 1 1 1 1 1 0 0 64/32 7C0000–7CFFFF 3E0000–3E7FFF SA125 1 1 1 1 1 0 1 64/32 7D0000–7DFFFF 3E8000–3EFFFF SA126 1 1 1 1 1 1 0 64/32 7E0000–7EFFFF 3F0000–3F7FFF SA127 1 1 1 1 1 1 1 64/32 7F0000–7FFFFF 3F8000–3FFFFF Sector A21–A15 Sector Size (Kbytes/Kwords) 8-bit Address Range (in hexadecimal) 16-bit Address Range (in hexadecimal)

16 Am29LV640MH/L December 14, 2005

accessed in-system through the command register. A6, A3, A2, A1, and A0 must be as shown in Table 3. Command Sequence section for more information. Table 2. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. implemented via two methods. the first sector group unprotect write cycle. tact an AMD representative for details. Table 3. Sector Group Protection/Unprotection Address Table

18 Am29LV640MH/L December 14, 2005

scribed in “Sector Group Protection and Unprotection”. increased. See the table in “DC Characteristics”.

1. All protected sector groups unprotected (If WP# = V IL, the first or last sector will remain protected).
2. All previously protected sector groups are protected once again.

Figure 1. Temporary Sector Group Unprotect Operation

20 Am29LV640MH/L December 14, 2005

SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 128 words/256 bytes in length, and uses a SecSi Sector Indicator Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which pre- vents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sec- tor unprotected, allowing customers to program the sector after receiving the device. The customer-lock- able version also has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indi- cator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The SecSi sector address space in this device is allo- cated as follows: The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the ad- dresses normally occupied by the first sector (SA0). This mode of operation continues until the system is- sues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending commands to sector SA0. Factory Locked: SecSi Sector Programmed and Protected At the Factory In devices with an ESN, the SecSi Sector is protected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. See Table 5 for SecSi Sector addressing. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. The de- vices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s Express- Flash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory As an alternative to the factory-locked version, the de- vice may be ordered such that the customer may pro- gram and protect the 128-word/256 bytes SecSi sector. See Table 5 for SecSi Sector addressing. The system may program the SecSi Sector using the write-buffer, accelerated and/or unlock bypass meth- ods, in addition to the standard programming com- mand sequence. See Command Definitions. Programming and protecting the SecSi Sector must be used with caution since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. ■ To verify the protect/unprotect status of the SecSi Sector, follow the algorithm shown in Figure 3. Once the SecSi Sector is programmed, locked and verified, the system must write the Exit SecSi Sector Region command sequence to return to reading and writing within the remainder of the array. SecSi Sector Address Range Standard Factory Locked ExpressFlash Factory Locked Customer Lockablex16 x8 000000h– 000007h 000000h– 00000Fh ESN ESN or determined by customer Determined by customer000008h– 00007Fh 000010h– 0000FFh Unavailable Determined by customer

Figure 3. SecSi Sector Protect Verify or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data.

22 Am29LV640MH/L December 14, 2005

Table 4. CFI Query Identification String Table 5. System Interface String

Table 6. Device Geometry Definition

24 Am29LV640MH/L December 14, 2005

Table 7. Primary Vendor-Specific Extended Query Commands section for more information. Device Bus Operations section for more information.

December 14, 2005 Am29LV640MH/L 25 DATASHEET The Read-Only Operations table provides the read pa- rameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Pro- gramming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to read several identifier codes at specific ad- dresses: Note: The device ID is read over three cycles. SA = Sector Address Tables 10 and 11 show the address requirements and codes. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 10 and 11 show the address and data requirements for both command sequences. See also “SecSi (Secured Sili- con) Sector Flash Memory Region” for further informa- tion. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is en- abled. Word/Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word/byte pro- gram command sequence, respectively. Identifier Code A7:A0 (x16) A6:A-1 (x8) Manufacturer ID 00h 00h Device ID, Cycle 1 01h 02h Device ID, Cycle 2 0Eh 1Ch Device ID, Cycle 3 0Fh 1Eh SecSi Sector Factory Protect 03h 06h Sector Protect Verify (SA)02h (SA)04h

26 Am29LV640MH/L December 14, 2005

When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status sec- tion for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is enabled. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Tables 10 and 11 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 90h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi- ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which pro- gramming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is se- lected by address bits A MAX–A4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the addre ss/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter decrements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways:

December 14, 2005 Am29LV640MH/L 27 DATASHEET ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is re- quired when using Write-Buffer-Programming features in Unlock Bypass mode. Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device dam- age may result. In addition, no external pullup is nec- essary since the WP#/ACC pin has internal pullup to V CC. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 17 for timing diagrams.

28 Am29LV640MH/L December 14, 2005

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

1. If this flowchart location was reached because

command. if DQ5=1, write the Reset command.

1. See Table 11 for command sequences required for

Note: See Table 11 for program command sequence. Figure 5. Program Operation μs maximum (5 μs typical) and updates the status bits. program operation is in progress. Autoselect Command Sequence for more information. written after the device has resume programming.

30 Am29LV640MH/L December 14, 2005

Figure 6. Program Suspend/Program Resume chip erase command sequence. of the erase operation by using DQ7, DQ6, or DQ2. mation on these status bits. available when an erase operation is in progress. and Figure 19 section for timing diagrams.

32 Am29LV640MH/L December 14, 2005

Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec- tor erase operation, including the 50 µs time-out pe- riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- imum of 20 (typical 5 µs) to suspend the erase opera- tion. However, when the Erase Suspend command is written during the sector erase time-out, the device im- mediately terminates the time-out period and sus- pends the erase operation. After the erase operation has been suspended, the device enters the erase-suspend-read mode. The sys- tem can read data from or program data to any sector not selected for erasure. (The device “erase sus- pends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors pro- duces status information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. Refer to the Write Operation Status section for infor- mation on these status bits. After an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. The system can determine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard word program operation. Refer to the Write Operation Status section for more information. In the erase-suspend-read mode, the system can also issue the autoselect command sequence. Refer to the Autoselect Mode and Autoselect Command Sequence sections for details. To resume the sector erase operation, the system must write the Erase Resume command. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the chip has resumed erasing. Note: During an erase operation, this flash device per- forms multiple internal operations which are invisible to the system. When an erase operation is suspended, any of the internal operations that were not fully com- pleted must be restarted. As such, if this flash device is continually issued suspend/resume commands in rapid succession, erase progress will be impeded as a function of the number of suspends. The result will be a longer cumulative erase time than without suspends. Note that the additional suspends do not affect device reliability or future performance. In most systems rapid erase/suspend activity occurs only briefly. In such cases, erase performance will not be significantly im- pacted.

Table 8. Command Definitions (x16 Mode, BYTE# = V IH) RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycl es. All others are write cycles.
4. During unlock and command cycles, when lower address bits are

bits above DQ7 are don’t care.

1. No unlock or command cycles re quired when device is in read
2. Reset command is required to return to read mode (or to

providing status information.

1. Fourth cycle of the autoselect command sequence is a read
2. Device ID must be read in three cycles.
3. If WP# protects highest address sector, data is 98h for factory
4. Data is 00h for an unprotected sector group and 01h for a
5. Total number of cycles in command sequence is determined by
6. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. Unlock Bypass command is required prior to Unlock Bypass
2. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

1. System may read and program in non-erasing sectors, or enter

command is valid only during a sector erase operation.

1. Erase Resume command is valid only during Erase Suspend

34 Am29LV640MH/L December 14, 2005

Table 9. Command Definitions (x8 Mode, BYTE# = V IL) RA = Read Address of memory location to be read. RD = Read Data read from location RA during read operation. CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector. BC = Byte Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Shaded cells indicate read cycl es. All others are write cycles.
4. During unlock and command cycles, when lower address bits are
5. Unless otherwise noted, address bits A21–A11 are don’t cares.
6. No unlock or command cycles re quired when device is in read
7. Reset command is required to return to read mode (or to

providing status information.

1. Fourth cycle of autoselect comma nd sequence is a read cycle.

Sequence section or more information.

1. Device ID must be read in three cycles.
2. If WP# protects highest address sector, data is 98h for factory
3. Data is 00h for an unprotected sector group and 01h for a
4. Total number of cycles in command sequence is determined by
5. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. Unlock Bypass command is required prior to Unlock Bypass
2. Unlock Bypass Reset command is required to return to read

mode when device is in unlock bypass mode.

1. System may read and program in non-erasing sectors, or enter

command is valid only during a sector erase operation.

1. Erase Resume command is valid only during Erase Suspend

December 14, 2005 Am29LV640MH/L 35 DATASHEET WRITE OPERATION STATUS The device provides several bits to determine the sta- tus of a program or erase operation: DQ2, DQ3, DQ5, DQ6, and DQ7. Table 12 and the following subsec- tions describe the function of these bits. DQ7 and DQ6 each offer a method for determining whether a pro- gram or erase operation is complete or in progress. The device also provides a hardware-based output signal, RY/BY#, to determine whether an Embedded Program or Erase operation is in progress or has been completed. DQ7: Data# Polling The Data# Polling bit, DQ7, indicates to the host sys- tem whether an Embedded Program or Erase algo- rithm is in progress or completed, or whether the device is in Erase Suspend. Data# Polling is valid after the rising edge of the final WE# pulse in the command sequence. During the Embedded Program algorithm, the device outputs on DQ7 the complement of the datum pro- grammed to DQ7. This DQ7 status also applies to pro- gramming during Erase Suspend. When the Embedded Program algorithm is complete, the device outputs the datum programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, Data# Polling on DQ7 is active for approximately 1 µs, then the device returns to the read mode. During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7. When the Embedded Erase algorithm is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide an address within any of the sectors selected for erasure to read valid status infor- mation on DQ7. After an erase command sequence is written, if all sectors selected for erasing are protected, Data# Poll- ing on DQ7 is active for approximately 100 µs, then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. However, if the sys- tem reads DQ7 at an address within a protected sector, the status may not be valid. Just prior to the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0–DQ6 while Output Enable (OE#) is asserted low. That is, the device may change from providing status information to valid data on DQ7. Depending on when the system samples the DQ7 output, it may read the status or valid data. Even if the device has com- pleted the program or erase operation and DQ7 has valid data, the data output s on DQ0–DQ6 may be still invalid. Valid data on DQ0–DQ7 will appear on suc- cessive read cycles. Table 12 shows the outputs for Data# Polling on DQ7. Figure 8 shows the Data# Polling algorithm. Figure 20 in the AC Characteristics section shows the Data# Polling timing diagram.

36 Am29LV640MH/L December 14, 2005

1. VA = Valid address for programming. Duri ng a sector erase operation, a valid

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ 5 = “1” because DQ7 may change simulta-

Figure 8. Data# Polling Algorithm

December 14, 2005 Am29LV640MH/L 37 DATASHEET RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev- eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively eras- ing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 12 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com- plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ad- dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read cycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 tog- gles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are pro- tected. The system can use DQ6 and DQ2 together to deter- mine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Sus- pend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Poll- ing). If a program address falls within a protected sector, DQ6 toggles for approximately 1 μs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 12 shows the outputs for Toggle Bit I on DQ6. Figure 9 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

38 Am29LV640MH/L December 14, 2005

Figure 9. Toggle Bit Algorithm section. Figure 21 shows the toggle bit timing diagram.

December 14, 2005 Am29LV640MH/L 39 DATASHEET Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 9 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 9). DQ5: Exceeded Timing Limits DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 pro- duces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 12 shows the status of DQ3 relative to the other status bits. DQ1: Write-to-Buffer Abort DQ1 indicates whether a Write-to-Buffer operation was aborted. Under these conditions DQ1 produces a “1”. The system must issue the Write-to-Buffer-Abort-Reset command sequence to re- turn the device to reading array data. See Write Buffer Programming section for more details.

40 Am29LV640MH/L December 14, 2005

Table 10. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

42 Am29LV640MH/L December 14, 2005

Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 6. If V IO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. If VIO < VCC, minimum VIH for CE# and DQ I/Os is 0.7 VIO. Maximum VIH for these connections is VIO + 0.3 V. 7. V CC voltage requirements. 8. V IO voltage requirements. 9. Includes RY/BY# 10. Not 100% tested. Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (2, 3) CE# = V IL, OE# = VIH,

5 MHz 15 20

1 MHz 15 20

ICC2 VCC Initial Page Read Current (2, 3) CE# = V IL, OE# = VIH 30 50 mA ICC3 VCC Intra-Page Read Current (2, 3) CE# = V IL, OE# = VIH 10 20 mA ICC4 VCC Active Write Current (3, 4) CE# = V IL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 15 µ A ICC6 VCC Reset Current (3) RESET# = V SS ± 0.3 V, WP# = VIH 15 µ A ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 15 µ A VIL1 Input Low Voltage 1(6, 7) –0.5 0.8 V VIH1 Input High Voltage 1 (6, 7) 1.9 VCC + 0.5 V VIL2 Input Low Voltage 2 (6, 8) –0.5 0.3 x VIO V VIH2 Input High Voltage 2 (6, 8) 1.9 VIO + 0.5 V VHH Voltage for ACC Program Acceleration V CC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage (9) I OL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (10) 2.3 2.5 V

44 Am29LV640MH/L December 14, 2005

1. See Figure 12 and Table 13 for test specifications.
2. AC Specifications listed are tested with V IO = VCC. Contact AMD for

information on AC operation with VIO ≠ VCC. Figure 14. Read Operation Timings

0 VRY/BY#

• Figure shows device in word mode. Addresses are A1–A-1 for byte mode.

Figure 15. Page Read Timings

46 Am29LV640MH/L December 14, 2005

1. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Figure 16. Reset Timings Description All Speed Options UnitJEDEC Std.

December 14, 2005 Am29LV640MH/L 47 DATASHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer spec ification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101, 101R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 11 µs Per Word Typ 22 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 8.8 µs Per Word Typ 17.6 µs Single Word/Byte Program Operation (Note 2, 5) Byte Typ 100 µs Word 100 µs Single Word/Byte Accelerated Programming Operation (Note 2, 5) Byte Typ 90 µs Word 90 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tBUSY WE# High to RY/BY# Low Min 90 100 110 120 ns tPOLL Program Valid Before Status Polling (Note 7) Max 4 µs

48 Am29LV640MH/L December 14, 2005

1. PA = program address, PD = program data, D OUT is the true data at the program address.

ILLUSTRATION SHOWS DEVICE IN WORD MODE. Figure 17. Program Operation Timings Figure 18. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. Illustration shows device in word mode.

Figure 19. Chip/Sector Erase Operation Timings

50 Am29LV640MH/L December 14, 2005

52 Am29LV640MH/L December 14, 2005

1. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC.

Figure 23. Temporary Sector Group Unprotect Timing Diagram

Figure 24. Sector Group Protect and Unprotect Timing Diagram

54 Am29LV640MH/L December 14, 2005

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC Specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 90R 101, 101R 112, 112R 120, 120R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 352 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 11 µs Per Word Typ 22 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 8.8 µs Per Word Typ 17.6 µs Single Word/Byte Program Operation (Note 2, 5) Byte Typ 100 µs Word 100 µs Single Word/Byte Accelerated Programming Operation (Note 2, Byte Typ 90 µs Word 90 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 7) Typ 0.5 sec tRH RESET# High Time Before Write Min 50 ns tPOLL Program Valid Before Status Polling (Note 7) Max 4 µs

1. Figure indicates last two bus cycle s of a program or erase operation.
2. PA = program address, SA = sector address, PD = program
3. DQ7# is the complement of the data written to the device.

DOUT is the data written to the device.

1. Illustration shows device in word mode.

56 Am29LV640MH/L December 14, 2005

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is calculated on a per-word/per-byte basis for a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the command sequence(s) for the program command. See Tables 8 and 9 for further information on command definitions. 8. The device has a minimum erase and program cycle endurance of 100,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP PIN AND BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 15 sec Excludes 00h programming prior to erasure (Note 6)Chip Erase Time 64 128 sec Single Word/Byte Program Time (Note 3) Byte 100 800 µs Excludes system level overhead (Note 7) Word 100 800 µs Accelerated Single Word/Byte Program Time (Note 3) Byte 90 720 µs Word 90 720 µs Total Write Buffer Program Time (Note 4) 352 1800 µs Effective Write Buffer Program Time (Note 5) Per Byte 11 57 µs Per Word 22 113 µs Total Accelerated Effective Write Buffer Program Time (Note 4) 282 1560 µs Effective Accelerated Write Buffer Program Time (Note 4) Per Byte 8.8 49 µs Per Word 17.6 98 µs Chip Program Time, using the Write Buffer 92 170 sec Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP 6 7.5 pF Fine-pitch BGA 4.2 5.0 pF COUT Output Capacitance V OUT = 0 TSOP 8.5 12 pF Fine-pitch BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 pF Fine-pitch BGA 3.9 4.7 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

December 14, 2005 Am29LV640MH/L 57 DATASHEET PHYSICAL DIMENSIONS TS056/TSR056—56-Pin Standard and Reverse Pinout Thin Small Outline Package (TSOP) NOTES: 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) 2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15 mm PER SIDE. 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP. 8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 3160\\38.10A MO-142 (B) EC TS/TSR 56 NOM. --- --- 1.00 1.20 0.15 1.05 MAX. --- MIN. 0.95 0.20 0.230.17 0.22 0.270.17 --- 0.160.10 --- 0.210.10 20.00 20.2019.90 14.00 14.1013.90 0.60 0.700.50 3˚ 5˚0˚ --- 0.200.08 18.40 18.5018.30 0.05

0.50 BASIC

E R JEDEC PACKAGE SYMBOL A D c b e L N O

58 Am29LV640MH/L December 14, 2005

LAA064—64-Ball Fortified Ball Grid Array ( FBGA) 13 x 11 mm Package

December 14, 2005 Am29LV640MH/L 59 DATASHEET REVISION SUMMARY Revision A (March 19, 2002) Initial release as abbreviated Advance Information data sheet. This document contains information that was previously released in publication number 25301. The package marking for the Fortified BGA option has been updated. Physical Dimensions Added drawing that shows both TS056 and TSR056 specifications. Revision B (April 26, 2002) Expanded data sheet to full specification version. Revision C (May 23, 2002) Changed packaging from 63-ball FBGA to 64-ball For- tified BGA. Changed Block Diagram: Moved V IO from RY/BY# to Input/Output Buffers. Changed note about WP#/ACC pin to indicate internal pullup to V CC. Modi- fied Table 4: Sector Group Protection/Unprotection Ad- dress Table. Changed 47h Address data from 0004h to 0001h in Table 9. Revision D (August 8, 2002) Alternate CE# Controlled Erase and Program Operations Added t RH parameter to table. Erase and Program Operations Added tBUSY parameter to table. TSOP and BGA PIN Capacitance Added the FBGA package. Program Suspend/Program Resume Command Sequence Changed 15 μs typical to maximum and added 5 μs typical. Erase Suspend/Erase Resume Commands Changed typical from 20 μs to 5 μs and added a maxi- mum of 20 μs. Special package handling instructions Modified the special handling wording. DC Characteristics table Deleted the Iacc specification row. CFI Changed text in the third paragraph of CFI to read “reading array data.” Revision D+1 (September 10, 2002) Product Selector Guide Added Note 2. Added Note 1. Sector Erase Command Sequence Deleted statement that describes the outcome of when the Embedded Erase operation is in progress. Revision E (December 5, 2002) Product Selector Guide and Read-Only Characteristics Added a 30 ns option to t PACC and tOE standard for the 112R and 120R speed options. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Com- mand Sequence Noted that the SecSi Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Common Flash Memory Interface (CFI) Changed CFI website address mum to 1.9. Removed typos in notes. Corrected performance characteristics.

60 Am29LV640MH/L December 14, 2005

Added note 2. Corrected Valid Combinations table. Added Note. AC Characteristics Removed 90, 90R speed option. Added Note Input values in the t WHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previ- ously TBD. Also, added note 5. Input values in the t WHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Op- tions table that were previously TBD. Also, added note Erase and Programming Performance Input values into table that were previously TBD. Added notes 3 and 4. Revision E+2 (June 11, 2003) Added 90R speed grade, modified note. Erase and Programming Performance Modified table, supplied values for Typical. Revision F (August 14, 2003) Global Converted document to new Spansion template. Added note for ordering and marking information re- lated to “N” (factory-protected SecSi Sector) devices. Command Definitions Corrected Program Erase/Suspend addressing from BA to don’t care. DC Characteristics table Corrected note reference number on VOL specification. Hardware Reset (RESET#) Added tRB specification to table. Revision F+1 (February 17, 2004) Erase Suspend/Erase Resume Commands Added note (last paragraph) in reference to erase op- eration. AC Characteristics - Erase and Program Operations, and Alternate CE# Controlled Erase and Program Operations Added t POLL information. AC Characteristics - Program Operation Timings, Data# Polling Timings, and Alternate CE# Controlled Write (Erase/Program) Operation Timings Updated figures to show t POLL information. Trademarks Updated. Revision F+2 (August 23, 2004) Added Max programming specifications. Added notation referencing superseding documenta- tion. Revision F+3 (December 14, 2005) Global This product has been retired and is not available for designs. For new and current designs, S29GL064A supersedes Am29LV640M H/L and is the factory-rec- ommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Trademarks Copyright © 2002-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.