L640GU53RI

AM29LV641G AMD | Alldatasheet

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Publication Number 25295 Revision A Amendment +3 Issue Date June 14, 2005 Am29LV641G Data Sheet RETIRED PRODUCT This product has been retired and is not recommended for designs. For new and current designs, S29GL064A supersedes Am29LV641G and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this docu- ment is retained for reference and historical purposes only. June 2005 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro- priate, and changes will be noted in a revision summary. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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This document contains information on a product under development at Advance Micro Devices. The information is intended to help you evaluate this product. Do not design in the product without contacting the factory. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 25295 Rev: A Amendment/+3 Issue Date: June 14, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. Am29LV641G 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Single power supply operation — 2.7 to 3.6 volt read, erase, and program operations ■ SecSi™ (Secured Silicon) Sector region — 128-word sector for permanent, secure identification through an 8-word random Electronic Serial Number — May be programmed and locked at the factory or by the customer — Accessible through a command sequence ■ VersatileI/O™ control — Device generates data output voltages and tolerates data input voltages as determined by the voltage on the V IO pin ■ Manufactured on 0.18 µm process technology ■ Flexible sector architecture — One hundred twenty-eight 32 Kword sectors ■ Compatibility with JEDEC standards — Pinout and software compatible with single-power supply Flash standard ■ Package options — 48-pin TSOP and Reverse TSOP (LV641GH/L only) — 63-ball Fine-Pitch BGA (LV640GU only) — 64-ball Fortified BGA (LV640GU only) ■ Minimum 1 million erase cycle guarantee per sector ■ 20-year data retention at 125 PERFORMANCE CHARCTERISTICS ■ High performance — Access time ratings as fast as 55 ns ■ Ultra low power consumption (typical values at 3.0 V,

5 MHz)

— 9 mA typical active read current — 26 mA typical erase/program current — 200 nA typical standby mode current ■ Program and erase performance (VHH not applied to the ACC input pin) — Word program time: 7 µs typical — Sector erase time: 0.6 s typical for each 32 Kword sector SOFTWARE AND HARDWARE FEATURES ■ Hardware features — Hardware reset input (RESET#): resets device for new operation — WP# input: protects first or last 32 Kword sector regardless of sector protection settings (LV641GH/L only) — ACC input: Accelerates programming time for higher throughput during system production ■ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Sector Group Protection: V CC-level method of preventing program or erase operations within a sector — Temporary Sector Group Unprotect: V ID-level method of changing in previously locked sectors — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices — Erase Suspend/Erase Resume: read/program other sectors before an erase operation is complete — Data# Polling and toggle bits provide erase and programming operation status — Unlock Bypass Program command reduces overall multiple-word programming time This product has been retired and is not recommended for designs. For new and current designs, S29GL064A supersedes Am29LV641G and is the factory-recommended migration path. Please refer to the S29GL064A datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

5 Am29LV641G June 14, 2005

The Am29LV641G are 64 Mbit, 3.0 volt (3.0 V to 3.6 V) single power supply flash memory devices organized as 4,194,304 words. Data appears on DQ15–DQ0. These devices are designed to be programmed in-sys- tem with the standard system 3.0 volt V CC supply. A 12.0 volt VPP is not required for program or erase oper- ations. The device can also be programmed in stan- dard EPROM programmers. Access times of 55 regulated volage and 70 ns full voltage range are available for applications where V IO ≥ V CC . The Am29LV641GH/L is offered in 48-pin TSOP and reverse TSOP packages. The Am29LV640GU is offered in a 63-ball Fine-pitch BGA package, and a 64-ball Fortified BGA. To eliminate bus contention each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply (2.7 V to 3.6 V) for both read and write func- tions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the command register using standard microprocessor write timing. Register con- tents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already pro- grammed) before executing the erase operation. Dur- ing erase, the device automatically times the erase pulse widths and verifies proper cell margin. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates at its data outputs and the voltages tolerated at its data inputs to the same voltage level that is asserted on the V IO pin. This allows the device to operate in 1.8 V or 3 V system environment as required. The host system can detect whether a program or erase operation is complete by reading the DQ7 (Data# Polling) or DQ6 (toggle) status bits . After a program or erase cycle has been completed, the de- vice is ready to read array data or accept another command. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The Program Suspend/Program Resume feature enables the host system to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system micropro- cessor to read boot-up firmware from the Flash mem- ory device. The device offers a standby mode as a power-saving feature. Once the system places the device into the standby mode power consumption is greatly reduced. The SecSi ™ (Secured Silicon) Sector provides an minimum 128-word area for code or data that can be permanently protected. Once this sector is protected, no further programming or erasing within the sector can occur. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP# pin. The protected sector will still be protected even during accelerated programming. (Am29LV641GH/L only) The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to V HH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase factory throughput during sys- tem production, but may also be used in the field if de- sired. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.

7 Am29LV641G June 14, 2005

Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Part Number Am29LV641G Speed Option Regulated Voltage Range VCC = 3.0–3.6 V 55R Standard Voltage Range VCC = 2.7–3.6 V 70 Max Access Time (ns) 55 70 CE# Access Time (ns) 55 70 OE# Access Time (ns) 35 35 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WP# ACC RY/BY# CE# OE# STB STB DQ15–DQ0 Sector Switches RESET# Data Latch Y-Gating Cell Matrix Address LatchA21–A0 VIO

June 14, 2005 Am29LV641G 8 ADVANCE INFORMATION CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A21 A20 WE# RESET# ACC WP# A19 A17 A16 DQ2 V IO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 A15 A18 A14 A13 A12 A11 A10 A21 A20 WE# RESET# ACC WP# A19 A17 A16 DQ2 V IO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP 48-Pin Reverse TSOP

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NC* NC*NC* NC* NC* NC* NC* NC* NC* NC* NC*NC NC NC NC DQ15 VSSVIOA16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 * Balls are shorted together via the substrate but not connected to the die. 63-Ball FBGA Top View, Balls Facing Down

June 14, 2005 Am29LV641G 10 ADVANCE INFORMATION CONNECTION DIAGRAMS B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 RFURFURFUVSSVIORFURFU VSSDQ15BYTE#A16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19A21RESET# DQ3DQ11DQ10DQ2A20A18WP#/ACC DQ1DQ9DQ8DQ0A5A6A17 RFU A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 RFURFUVIORFURFURFURFU RFU 64-Ball Fortified BGA Top View, Balls Facing Down Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP and BGA) The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for pro- longed periods of time.

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A21–A0 = 22 Addresses inputs DQ15–DQ0 = 16 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP# = Hardware Write Protect input ACC = Acceleration Input RY/BY# = Ready/Busy output RESET# = Hardware Reset Pin input VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally Note:WP#/ACC functionality is multiplexed for Am29LV641GH/L devices. RY/BY# available only for Am29LV640GU devices. LOGIC SYMBOL DQ15–DQ0 A21–A0 CE# OE# WE# RESET# ACC WP# VIO RY/BY#

June 14, 2005 Am29LV641G 12 ADVANCE INFORMATION

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV641G H 55R WH I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) WH = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 11 x 12 mm package (FBE063) PC = 64-Ball Fine-Pitch Ball Grid Array (Fortified BGA) 1.0 mm pitch, 13 x 11 mm package (LAA064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV641G

64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO ™ Control

3.0 Volt-only Read, Program, and Erase

TSOP and SSOP Packages Speed/V IO Range Am29LV641GH73, Am29LV641GL73 EI, FI 70 ns VIO = 2.7 V – 3.6 V Am29LV641GH53R, Am29LV641GL53R 55 ns VIO = 3.0 V – 3.6 V Valid Combinations for FBGA Packages Speed/ VIO RangeOrder Number Package Marking Am29LV640GU53R WHI L640GU53R I 55ns VIO = 3.0V – 3.6 V Am29LV640GU73 L640GU73V 70 ns VIO = 2.7 V – 3.6 V Am29LV640GU53R PCI L640GU53N 55 ns VIO = 3.0 V – 3.6 V Am29LV640GU73 L640GU73P 70 ns VIO = 2.7 V – 3.6 V Marking Converstion For the Am29LV641GH/L/AmLV640GU Enhanced-VIO device, the last digit of the speed indicator specifies VIO range. Speed grades ending in 3 (e.g. 93, 103, etc.) indicate a 3 Volt V IO range; speed grades ending in 8 (e.g. 98, 108, etc.) indicate a

1.8 V V

IO range.

13 Am29LV641G June 14, 2005

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

1. All sectors are unprotected when shipped from the factory (The SecSi Sector may be factory protected depending on version
2. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

V system environment as required. from other 3 V devices on the same bus. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H X High-Z

June 14, 2005 Am29LV641G 14 ADVANCE INFORMATION enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facil- itate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word, instead of four. The “Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V , the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V , the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory.

15 Am29LV641G June 14, 2005

rameters and to Figure 15 for the timing diagram. Table 2. Sector Address Table

Table 2. Sector Address Table (Continued)

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Note: All sectors are 32 Kwords in size.

19 Am29LV641G June 14, 2005

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 3. In addition, when verifying sector protection, shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. mand Sequence section for more information. Table 3. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: SecSi™ Sector Indicator Bit (DQ7) exist only in the Am29LV641GH/L devices.

implemented via two methods. group unprotect write cycle. ID on address pin A9 and OE#. written for earlier 3.0 volt-only AMD flash devices. contact an AMD representative to request a copy. the device through AMD’s ExpressFlash™ Service. Contact an AMD representative for details. Table 4. Sector Group Protection/Unprotection Note: All sector groups are 128 Kwords in size.

21 Am29LV641G June 14, 2005

scribed in “Sector Group Protection and Unprotection”. creased. See the table in “DC Characteristics”. Figure 22 shows the timing diagrams, for this feature. Figure 1. Temporary Sector Group

1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector will remain protected).

1. All previously protected sector groups are protected

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

23 Am29LV641G June 14, 2005

rity of the ESN once the product is shipped to the field. being used to replace devices that are factory locked. has its Sector starting at address 0. dresses normally occupied by the first sector (SA0). sending commands to sector SA0. gram and protect the 128-word SecSi sector. space can be modified in any way. without raising any device pin to a high voltage. Group Protection and Unprotection” section. writing within the remainder of the array. Table 5. SecSi Sector Contents

Figure 3. SecSi Sector Protect Verify and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data.

25 Am29LV641G June 14, 2005

Table 6. CFI Query Identification String Table 7. System Interface String Table 8. Device Geometry Definition

June 14, 2005 Am29LV641G 26 ADVANCE INFORMATION 31h 32h 33h 34h 007Eh 0000h 0000h 0001h Erase Block Region 2 Information (refer to CFI publication 100) 35h 36h 37h 38h 0000h 0000h 0000h 0000h Erase Block Region 3 Information (refer to CFI publication 100) 39h 3Ah 3Bh 3Ch 0000h 0000h 0000h 0000h Erase Block Region 4 Information (refer to CFI publication 100)

27 Am29LV641G June 14, 2005

Table 9. Primary Vendor-S pecific Extended Query Commands section for more information. operation, or if the device is in the autoselect mode.

June 14, 2005 Am29LV641G 28 ADVANCE INFORMATION See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: ■ A read cycle at address XX00h returns the manu- facturer code. ■ A read cycle at address XX01h returns the device code. ■ A read cycle to an address containing a sector group address (SA), and the address 02h on A7–A0 in word mode returns 01h if the sector group is pro- tected, or 00h if it is unprotected. (Refer to Table 4 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word random Electronic Serial Num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. Table 10 shows the address and data requirements for both command sequences. See also “SecSi ™ (Secured Silicon) Sector Flash Memory Region” for further information. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 10 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status sec- tion for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed

29 Am29LV641G June 14, 2005

cycle containing the unlock bypass command, 20h. ments for the command sequence. device then returns to the read mode. and Figure 16 for timing diagrams. Figure 4. Program Operation Note: See Table 10 for program command sequence.

31 Am29LV641G June 14, 2005

can be written after the chip has resumed erasing. Figure 5. Erase Operation

1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 10. Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A21–A15 are don’t cares.
3. No unlock or command cycles required when device is in read
4. The Reset command is required to return to the read mode (or to

(while the device is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence section for more information.

1. If WP# protects the highest address sector, the data is 98h for
2. The data is 00h for an unprotected sector group and 01h for a
3. The Unlock Bypass command is required prior to the Unlock
4. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or

when device is in autoselect mode.

1. Bottom boot = 2200 and top boot = 2201.

33 Am29LV641G June 14, 2005

final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 11 shows the outputs for Data# Polling on DQ7. Figure 6. Data# Polling Algorithm

1. VA = Valid address for programming. During a secto r

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” becaus e

DQ7 may change simultaneously with DQ5.

35 Am29LV641G June 14, 2005

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to con- trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 11 to compare out- puts for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 7 for the following discussion. When- ever the system initially begins reading toggle bit sta- tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 11 shows the status of DQ3 relative to the other status bits.

Table 11. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

37 Am29LV641G June 14, 2005

1. Minimum DC voltage on input or I/O pins is –0.5 V.

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V .

1. Minimum DC input voltage on pins A9, OE#, ACC, and

which may overshoot to +14.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. functionality of the device is guaranteed. Figure 8. Maximum Negative Figure 9. Maximum Positive

June 14, 2005 Am29LV641G 38 ADVANCE INFORMATION DC CHARACTERISTICS CMOS Compatible Notes: 1. On the WP# pin only, the maximum input load current when WP# = V IL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 7. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current (Note 1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 2, 3) CE# = VIL, OE# = VIH

5 MHz 9 16

1 MHz 2 4

ICC2 VCC Active Write Current (Notes 3, 4) CE# = V IL, OE# = VIH, WE# = VIL 15 26 mA ICC3 VCC Standby Current (Note 3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 0.2 5 µA ICC4 VCC Reset Current (Note 3) RESET# = V SS ± 0.3 V, WP# = VIH 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V , WP# = VIH 0.2 5 µA VIL Input Low Voltage (Note 6) –0.5 0.8 V VIH Input High Voltage (Note 6) 0.7 x V CC VCC + 0.3 V VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage (Note 7) IOH = –2.0 mA, VCC = VCC min 0.85 x V IO V VOH2 IOH = –100 µA, VCC = VCC min V IO–0.4 V VLKO Low VCC Lock-Out Voltage (Note 7) 2.3 2.5 V

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Figure 10. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 11. Typical I CC1 vs. Frequency

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1. See Figure 12 and Table 12 for test specifications.

Figure 14. Read Operation Timings

Figure 15. Reset Timings

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Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std. Description 55R 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 40 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 40 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 ns tWHDL tWPH Write Pulse Width High Min 25 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 7 µs tWHWH1 tWHWH1 Accelerated Word Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.6 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs

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1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.

Figure 18. Chip/Sector Erase Operation Timings

Figure 19. Data# Polling Timings

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Figure 20. Toggle Bit Timings Figure 21. DQ2 vs. DQ6

Figure 22. Temporary Sector Group Unprotect Timing Diagram

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• For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Group Protect and Unprotect Timing Diagram

June 14, 2005 Am29LV641G 50 ADVANCE INFORMATION AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 55R 70 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 40 ns tDVEH tDS Data Setup Time Min 40 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 7 µs tWHWH1 tWHWH1 Accelerated Word Programming Operation (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.6 sec

51 Am29LV641G June 14, 2005

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 24. Alternate CE# Controlled Write (Erase/Program) Operation Timings

June 14, 2005 Am29LV641G 52 ADVANCE INFORMATION ERASE AND PROGRAMMING PERFORMANCE Notes: 1. T ypical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90 °C, VCC = 3.0 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP & FBGA PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. T est conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.6 4 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 50 sec Word Program Time 7 210 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 4 120 µs Chip Program Time (Note 3) 18 54 sec Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 TSOP 6 7.5 Fine-pitch BGA 4.2 5.0 COUT Output Capacitance V OUT = 0 TSOP 8.5 12 Fine-pitch BGA 5.4 6.5 CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 Fine-pitch BGA 3.9 4.7 Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

53 Am29LV641G June 14, 2005

FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 11 x 12 mm package Dwg rev AF; 10/99

54 Am29LV641G June 14, 2005

LAA064–64-Ball Fortified Ball Grid Array (Fortified BGA) 13 x 11 mm package

June 14, 2005 Am29LV641G 55 ADVANCE INFORMATION PHYSICAL DIMENSIONS TS 048—48-Pin Standard TSOP Note: For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

56 Am29LV641G June 14, 2005

Revision A (August 9, 2002) Initial Release. Revision A+1 (August 28, 2002) Corrected order numbers and package markings. Added Marking Convention explanation about En- hanced-VIO markings. Revision A+2 (October 18, 2002) Global Added 55R speed grade and removed 90 and 100 speed grade throughout datasheet. Connection Diagram Removed the 56–pin SSOP package diagram. Special Package Handling Instructions Modified wording. Changed the VIO for 55R to equal 3.0 V–3.6 V and added 55 ns to Valid Combinations table. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. Common Flash Memory Interface (CFI) Changed wording in last sentence of third paragraph data.” Changed CFI website address. Command Definitions Changed wording in last sentence of first paragraph from, “...resets the device to reading array data.” to ...”may place the device to an unknown state. A reset command is then required to return the device to read- ing array data.” TSOP Pin Capacitance Added fine-pitch BGA capacitance. Revision A+3 (June 14, 2005) Cover Page / Title Page Added Spansion EOL cover page and EOL disclaimer to AMD title page. Trademarks Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification pur poses only and may be trademarks of their respective companies .