L640DU12NF

AM29LV640D_07 AMD | Alldatasheet

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Publication Number 22366 Revision C Amendment 6 Issue Date January 22, 2007 The following document contains information on Spansion memory produc ts. Although the docis marked with the name of the company that originally developed the specification, Spansion will con- tinue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29LV640D/Am29LV641D Data Sheet

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22366 Rev: C Amendment 6 Issue Date: January 22, 2007 Am29LV640D/Am29LV641D 64 Megabit (4 M x 16-Bit) CMOS 3.0 Volt-only Uniform Sector Flash Memory with VersatileIO™ Control DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 3.0 to 3.6 volt read, erase, and program operations ■ VersatileIO™ control — Device generates output voltages and tolerates data input voltages on the DQ input/outputs as determined by the voltage on VIO ■ High performance — Access times as fast as 90 ns ■ Manufactured on 0.23 µm process technology ■ CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ SecSi (Secured Silicon) Sector region — 128-word sector for permane nt, secure identification through an 8-word random Electronic Serial Number — May be programmed and locked at the factory or by the customer — Accessible through a command sequence ■ Ultra low power consumption (typical values at 3.0 V,

5 MHz)

— 9 mA typical active read current — 26 mA typical erase/program current — 200 nA typical standby mode current ■ Flexible sector architecture — One hundred twenty-eight 32 Kword sectors ■ Sector Protection — A hardware method to lock a sector to prevent program or erase operations within that sector — Sectors can be locked in-system or via programming equipment — Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Compatibility with JEDEC standards — Pinout and software compatible with single-power supply Flash — Superior inadvertent write protection ■ Minimum 1 million erase cycle guarantee per sector ■ Package options — 48-pin TSOP (Am29LV641DH/DL only) — 56-pin SSOP (Am29LV640DH/DL only) — 63-ball Fine-Pitch BGA (Am29LV640DU only) — 64-ball Fortified BGA (Am29LV640DU only) ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sect27 — or that is not being erased, then resumes the erase operation ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences ■ Ready/Busy# pin (RY/BY#) (Am29LV640DU in FBGA package only) — Provides a hardware method of detecting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method to reset the device for reading array data ■ WP# pin (Am29LV641DH/DL in TSOP, Am29LV640DH/DL in SSOP only) —A t V IL, protects the first or last 32 Kword sector, regardless of sector protect/unprotect status —A t V IH, allows removal of sector protection — An internal pull up to V CC is provided ■ ACC pin — Accelerates programming time for higher throughput during system production ■ Program and Erase Performance (VHH not applied to the ACC input pin) — Word program time: 11 µs typical — Sector erase time: 0.9 s typical for each 32 Kword sector

2 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

The Am29LV640DU/Am29LV641DU is a 64 Mbit, 3.0 Volt (3.0 V to 3.6 V) single power supply flash memory device organized as 4,194,304 words. Data appears on DQ0-DQ15. The device is designed to be pro- grammed in-system with t he standard system 3.0 volt V CC supply. A 12.0 volt VPP is not required for program or erase operations. Y ou can also program this device in standard EPROM programmers. Access times of 90 and 120 ns are available for appli- cations where V IO ≥ VCC. An access time 120 ns are available for applications where VIO < VCC. The device is offered in 48-pin TSOP , 56-pin SSOP , 63-ball Fine-Pitch BGA and 64-ball Fortified BGA packages. To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#), and output en- able (OE#) controls. Each device requires only a single 3.0 Volt power supply (3.0 V to 3.6 V) for both read and write func- tions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the command register using standard microprocessor write timing. Register con- tents serve as inputs to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm — an internal algorithm that auto- matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili- tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com- mand sequence. This initiates the Embedded Erase algorithm — an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The VersatileIO™ (V IO) control allows the host system to set the voltage levels that the device generates and tolerates on CE# and DQ I/Os to the same voltage level that is asserted on V IO. VIO is available in two configurations (1.8–2.9 V and 3.0–5.0 V) for operation in various system environments. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, by reading the DQ7 (Data# Polling), or DQ6 (tog- gle) status bits. After a program or erase cycle com- pletes, the device is ready to read array data or accept another command. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of sectors of memory. This is achieved in-system or via programming equip- ment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin can be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system microprocessor to read boot-up firmware from the Flash memory de- vice. The device offers a standby mode as a power-saving feature. Once the system places the device into the standby mode, power consumption is greatly reduced. The SecSi (Secured Silicon) Sector provides an minimum 128-word area for code or data that can be permanently protected. Once this sector is protected, no further programming or erasing within the sector can occur. The Write Protect (WP#) feature protects the first or last sector by asserting a logic low on the WP# pin. The protected sector is still protected even during ac- celerated programming. The accelerated program (ACC) feature allows the system to program the device at a much faster rate. When ACC is pulled high to V HH, the device enters the Unlock Bypass mode, enabling the user to reduce the time needed to do the program operation. This feature is intended to increase fa ctory throughput during sys- tem production, but may also be used in the field if de- sired. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective- ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.

4 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Notes: 1. RY/BY# is only available in the FBGA package. 2. WP# is only available in the TSOP and SSOP packages. Part Number Am29LV640D/Am29LV641D Speed Option VCC = 3.0–3.6 V, VIO = 3.0–5.0 V 90R 120R VCC = 3.0–3.6 V, VIO = 1.8–2.9 V 121R Max Access Time (ns) 90 120 CE# Access Time (ns) 90 120 OE# Access Time (ns) 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WP# (Note 2) ACC CE# OE# STB STB DQ0–DQ15 Sector Switches RY/BY# (Note 1) RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A21 VIO

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 5 DATA SHEET CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A21 A20 WE# RESET# ACC WP# A19 A17 A16 DQ2 V IO VSS DQ15 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP (Am29LV641DH/DL only) ACC WP# A19 A18 A17 NC NC NC NC CE# V SS OE# DQ0 DQ8 RESET# WE# A20 A21 A10 A11 A12 A13 A14 A15 NC NC NC NC A16 V IO VSS DQ15 DQ7 DQ14 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 DQ6 DQ13 DQ5 DQ12 DQ4 V CC 56-Pin SSOP (Am29LV640DH/DL only)

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NC* NC*NC* NC* NC* NC* NC* NC* NC* NC* NC*NC NC NC NC DQ15 VSSVIOA16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 * Balls are shorted together via the substrate but not connected to the die. 63-Ball Fine-Pitch BGA (FBGA) Top View, Balls Facing Down (Am29LV640DU only)

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 7 DATA SHEET CONNECTION DIAGRAMS Special Handling Instructions for FBGA/fBGA Packages Special handling is required for Flash Memory products in BGA packages. Flash memory devices in BGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. B3 C3 D3 E3 F3 G3 H3 B4 C4 D4 E4 F4 G4 H4 B5 C5 D5 E5 F5 G5 H5 B6 C6 D6 E6 F6 G6 H6 B7 C7 D7 E7 F7 G7 H7 B8 C8 D8 E8 F8 G8 H8 RFURFURFUVSSVIORFURFU VSSDQ15NCA16A15A14A12 DQ6DQ13DQ14DQ7A11A10A8 DQ4VCCDQ12DQ5A19A21RESET# DQ3DQ11DQ10DQ2A20A18ACC DQ1DQ9DQ8DQ0A5A6A17 RFU A13 WE# RY/BY# B2 C2 D2 E2 F2 G2 H2 VSSOE#CE#A0A1A2A4 B1 C1 D1 E1 F1 G1 H1 RFURFUVIORFURFURFURFU RFU 64-Ball Fortified BGA (FBGA) Top View, Balls Facing Down (Am29LV640DU only)

8 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

A0–A21 = 22 Addresses inputs DQ0–DQ15 = 16 Data inputs/outputs CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP# = Hardware Write Protect input (N/A on FBGA) ACC = Acceleration Input RESET# = Hardware Reset Pin input RY/BY# = Ready/Busy output (FBGA only) V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally RFU = Reserved for Future Use LOGIC SYMBOL Note: WP# is not available on the FBGA package. RY/BY# is not available on the TSOP and SSOP packages. DQ0–DQ15 A0–A21 CE# OE# WE# RESET# RY/BY# ACC WP# VIO

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 9 DATA SHEET

ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in vol- ume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. Note: Reverse pinout TSOP (TSR048) packages are not Note: offered for new designs. For 128 Mb requirements, the S29GL128N product is recommended as a single-device substitute for the 64 Mb + 64 Mb clamshell design; please refer to the S29GL128N data sheet for specifications and ordering information. Am29LV640D Am29LV641D H 90R E I N OPTIONAL PROCESSING Blank = Standard Processing N = 32-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-Free Package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) Z = 56-Pin Shrink Small Outline Package (SSO056) PC = 64-Ball Fortified Ball Grid Array 1.0 mm pitch, 13 x 11 mm package (LAA064) WH = 63-Ball Fine-Pitch Ball Grid Array 0.80 mm pitch, 11 x 12 mm package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = 0) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected U = Uniform sector device (WP# not available) DEVICE NUMBER/DESCRIPTION Am29LV640DU/DH/DL, Am29LV641DH/DL

64 Megabit (4 M x 16-Bit) CMOS Uniform Sector Flash Memory with VersatileIO™ Control

3.0 Volt-only Read, Program, and Erase

TSOP and SSOP Packages Speed/V IO Range AM29LV640DH90R, AM29LV640DL90R ZI, ZF 90 ns, VIO = 3.0 V – 5.0 VAM29LV641DH90R, AM29LV641DL90R EI, FI, EF AM29LV640DH120R, AM29LV640DL120R ZI, ZF 120 ns, VIO = 3.0 V – 5.0 VAM29LV641DH120R, AM29LV641DL120R EI, FI, EF AM29LV640DH121R, AM29LV640DL121R ZI, ZF 120 ns, VIO = 1.8 V – 2.9 VAM29LV641DH121R, AM29LV641DL121R EI, FI, EF Note: LV640/641DH & DL have WP#, but no RY/BY#. U designator in base part number replaced by H or L. Valid Combinations for BGA Packages Speed/ VIO RangeOrder Number Package Marking AM29LV640DU90R PCI, PCF L640DU90N I, F 90 ns, VIO = 3.0 V – 5.0 VWHI, WHF L640DU90R AM29LV640DU120R PCI, PCF L640DU12N I, F 120 ns, VIO = 3.0 V – 5.0 VWHI, WHF L640DU12R AM29LV640DU121R PCI, PCF L640DU21N 120 ns, VIO = 1.8 V – 2.9 VWHI, WHF L640DU21R Note: LV640DU has RY/BY#, but no WP#.

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register serve as inputs to the internal state machine. Table 1. Device Bus Operations

1. Addresses are A21:A0. Sector addresses are A21:A15.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group

Protection and Unprotection” section.

1. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2, on page 19).

in various system environments. other 5 V devices on the same data bus. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V XH X High-Z

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 11 DATA SHEET data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” on page 10 for more information. Refer to the AC “Read-Only Operations” on page 37 table for timing specifications and to Figure 13, on page 37 for the tim- ing diagram. I CC1 in the “DC Characteristics” on page 34 table represents the active current specifica- tion for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word instead of four. The “Word Program Command Sequence” on page 24 has de- tails on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 on page 12 indicates the address space that each sector occupies. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This function is primarily in- tended to allow faster manufacturing throughput dur- ing system production. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the ACC pin returns the device to normal op- eration. Note that the ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” on page 16 and “Autoselect Command Sequence” on page 24 for more information. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires stan- dard access time (t CE) for read access when the de- vice is in either of these standby modes before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the table “DC Characteristics” on page 34 rep- resents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and alwa ys available to the system. I CC4 in the table “DC Characteristics” on page 34 rep- resents the automatic sleep mode current specifica- tion. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. To ensure data integrity, the operation that was interrupted should be reinitiated once the device is ready to accept another command sequence. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within V SS±0.3 V, the standby current is greater.

12 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Table 2. Sector Address Table (Sheet 1 of 4)

Table 2. Sector Address Table (Sheet 2 of 4)

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Table 2. Sector Address Table (Sheet 3 of 4)

Note: All sectors are 32 Kwords in size. Table 2. Sector Address Table (Sheet 4 of 4)

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accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 3. In addition, when verifying sector protection, highest order address bits (see Table 2 on page 12 ). corresponding identifier code on DQ7–DQ0. command register, as shown in Table 10 on page 28. Table 3. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

tact an AMD representative for details. Table 4. Sector Group Protection/Unprotection Note: All sector groups are 128 Kwords in size.

18 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

mode, the maximum input load current is increased. See the table in “DC Characteristics” on page 34. Figure 1. Temporary Sector Group

1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector remains protected).

1. All previously protected sector groups are protected

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

20 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

rity of the ESN once the product is shipped to the field. being used to replace devices that are factory locked. addresses normally occupied by the first sector (SA0). sending commands to sector SA0. gram and protect the 128-word SecSi sector. space can be modified in any way. Protection and Unprotection” on page 17. writing within the remainder of the array. Table 5. SecSi Sector Contents

or WE#, do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. command to return the device to the autoselect mode. tative for copies of these documents. Table 6. CFI Query Identification String

22 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Table 7. System Interface String Table 8. Device Geometry Definition

Table 9. Primary Vendor-Specific Extended Query mands” on page 26, for more information.

24 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Command , for more informa- tion. See also “Requirements for Reading Array Data” on page 10 in the Device Bus Operations section for more information. The “Read-Only Operations” on page 37 table provides the read parameters, and Fig- ure 13, on page 37 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 10 on page 28 shows the address and data re- quirements. This method is an alternative to that shown in Table 3 on page 16 , which is intended for PROM programmers and requires V ID on address pin A9. The autoselect command sequence may be writ- ten to an address that is either in the read or erase-suspend-read mode. The autoselect command cannot be written while the device is actively program- ming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: ■ A read cycle at address XX00h returns the manu- facturer code. ■ A read cycle at address XX01h returns the device code. ■ A read cycle to an address containing a sector group address (SA), and the address 02h on A7–A0 returns 01h if the sector group is protected, or 00h if it is unprotected. (Refer to Table 4 on page 17 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word random Electronic Serial Num- ber (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the de- vice to normal operation. Table 10 on page 28 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” on page 20 for further informa- tion. Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. The “Command Definitions” on page 28 shows the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system determines the sta- tus of the program operation by using DQ7, DQ6, or RY/BY#. Refer to “Write Operation Status” on page 29 for information on these status bits.

26 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

When the Embedded Erase algorithm is complete, the device returns to the read mode and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” on page 29 for information on these status bits. Any commands written during the chip erase operation are ignored. However, note that a hardware reset im- mediately terminates the erase operation. If that oc- curs, the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. Figure 4, on page 27 illustrates the algorithm for the erase operation. Refer to the table “Erase and Pro- gram Operations” on page 39 in the AC Characteris- tics section for parameters, and Figure 17, on page 41 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad- ditional unlock cycles are written, and are then fol- lowed by the address of the sector to be erased, and the sector erase command. Table 10 on page 28 shows the address and data requirements for the sec- tor erase command sequence. The device does not require the system to preprogram prior to erase. The Embedded Erase algorithm auto- matically programs and verifies the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim- ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs occurs. During the time-out period, additional sector addresses and sector erase com- mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec- tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise erasure may begin. Any sector erase ad- dress and command following the exceeded time-out may or may not be accepted. It is recommended that processor interrupts be disabled during this time to en- sure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to the read mode. The system must re- write the command sequence and any additional ad- dresses and commands. The system can monitor DQ3 to determine if the sec- tor erase timer has timed out (See the section “DQ3: Sector Erase Timer” on page 31 .). The time-out be- gins from the rising edge of the final WE# pulse in the command sequence. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by reading DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” on page 29 for information on these status bits. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com- mands are ignored. However, note that a hardware reset immediately terminates the erase operation. If that occurs, the sector erase command sequence should be reinitiated once the device returns to read- ing array data, to ensure data integrity. Figure 4, on page 27 illustrates the algorithm for the erase operation. Refer to the table “Erase and Pro- gram Operations” on page 39 in the AC Characteris- tics section for parameters, and Figure 17, on page 41 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command, B0h, allows the sys- tem to interrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sec- tor erase operation, including the 50 µs time-out pe- riod during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algorithm. When the Erase Suspend command is written during the sector erase operation, the device requires a max- imum of 20 µs to suspend the erase operation. How- ever, when the Erase Suspend command is written during the sector erase time-out, the device immedi- ately terminates the time-out period and suspends the erase operation. After the erase operation is suspended, the device en- ters the erase-suspend-read mode. The system can read data from or program data to any sector not se- lected for erasure. (The device “erase suspends” all sectors selected for erasure.) Reading at any address within erase-suspended sectors produces status infor- mation on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is ac- tively erasing or is erase-suspended. Refer to “Write Operation Status” on page 29 for information on these status bits. After an erase-suspended program operation is com- plete, the device returns to the erase-suspend-read mode. The system determines the status of the pro- gram operation using the DQ7 or DQ6 status bits, just

mand Sequence” on page 24 for details. Figure 4. Erase Operation

1. See Table 10 for erase command sequence.
2. See the section on DQ3 for information on the sector

28 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Table 10. Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A21–A15 uniquely select any sector.

1. See Table 1 on page 10 for a description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. During unlock cycles, (when lower address bits are 555 or 2AAh

is required) and data bits higher than DQ7 are don’t cares.

1. No unlock or command cycles required when device is in read
2. The Reset command is required to return to the read mode (or to

(while the device is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence” on page 24 section for more information.

1. If WP# protects the highest address sector (or if WP# is not

data is 88h for factory locked and 08h for not factor locked.

1. The data is 00h for an unprotected sector group and 01h for a
2. The Unlock Bypass command is required prior to the Unlock
3. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Figure 5. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

30 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Table 11 on page 32 shows the outputs for RY/BY#. complete, DQ6 stops toggling. lected sectors that are protected. whether a sector is actively erasing or is erase-suspended. vice enters the Erase Suspend mode, DQ6 stops toggling. tics” section shows the toggle bit timing diagrams. tion “DQ2: Toggle Bit II” on page 31. Figure 6. Toggle Bit Algorithm

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 31 DATA SHEET DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that were selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6, by comparison, indicates whether the device is ac- tively erasing, or is in Erase Suspend, but cannot dis- tinguish which sectors are selected for erasure. Thus, both status bits are required for sector and mode infor- mation. Refer to Table 11 on page 32 to compare out- puts for DQ2 and DQ6. Figure 6, on page 30 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” ex- plains the algorithm. See also the “DQ6: Toggle Bit I” on page 30 subsection. Figure 19, on page 43 shows the toggle bit timing diagram. Figure 20, on page 43 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6, on page 30 for the following discus- sion. Whenever the system initially begins reading tog- gle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typi- cally, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the sub-section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog- gling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to re- turn to reading array data. The remaining scenario is th at the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previ- ous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to de- termine the status of the operation (top of Figure 6, on page 30). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit is exceeded, DQ5 produces a “1.” Under both these conditions , the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if the device was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to det ermine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also “Sector Erase Command Se- quence” on page 26. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command was accepted, the system soft- ware should check the status of DQ3 prior to and fol- lowing each subsequent sector erase command. If DQ3 is high on the second status check, the last com- mand might not have been accepted. Table 11 on page 32 shows the status of DQ3 relative to the other status bits.

32 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Table 11. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. RY/BY# is only available on the FBGA package.

34 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Notes: 1. On the WP# pin only, the maximum input load current when WP# = V IL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. for these connections is VIO + 0.3 V 7. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current (Note 1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 2, 3) CE# = VIL, OE# = VIH

5 MHz 9 16

1 MHz 2 4

ICC2 VCC Active Write Current (Notes 3, 4) CE# = V IL, OE# = VIH, WE# = VIL 26 30 mA ICC3 VCC Standby Current (Note 3) CE#, RESET# = VCC ± 0.3 V, WP# = VIH 0.2 5 µA ICC4 VCC Reset Current (Note 3) RESET# = V SS ± 0.3 V, WP# = VIH 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 0.2 5 µA IACC ACC Accelerated Program Current CE# = V IL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA VIL Input Low Voltage (Note 6) –0.5 0.8 V VIH Input High Voltage (Note 6) 0.7 x V CC VCC + 0.3 V VHH Voltage for ACC Program Acceleration VCC = 3.0 V ± 10% 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.8 V IO V VOH2 IOH = –100 µA, VCC = VCC min V IO–0.4 V VLKO Low VCC Lock-Out Voltage (Note 7)2 . 3 2 . 5 V

36 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Table 12. Test Specifications Note: If VIO < VCC, the reference level is 0.5 VIO. Figure 11. Test Setup Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 12. Input Waveforms and

1. See Figure 11 and Table 12 for test specifications.

0 VRY/BY#

Figure 13. Read Operation Timings

38 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Figure 14. Reset Timings

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 39 DATA SHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std. Description 90R 120R, 121R Unit tAVAV tWC Write Cycle Time (Note 1)M i n 9 0 1 2 0 n s tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2)T y p 1 1 µ s tWHWH1 tWHWH1 Accelerated Word Programming Operation (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.9 sec tVHH VHH Rise and Fall Time (Note 1)M i n 2 5 0 n s tVCS VCC Setup Time (Note 1)M i n 5 0 µ s tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

40 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 15. Program Operation Timings Figure 16. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.

Figure 17. Chip/Sector Erase Operation Timings

42 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Figure 18. Data# Polling Timings

44 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Figure 21. Temporary Sector Group Unprotect Timing Diagram

• For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 22. Sector Group Protect and Unprotect Timing Diagram

46 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 90R 120R, 121R Unit tAVAV tWC Write Cycle Time (Note 1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 50 ns tDVEH tDS Data Setup Time Min 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Word Programming Operation (Note 2) Typ 11 µs tWHWH1 tWHWH1 Accelerated Word Programming Operation (Note 2) Typ 7 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2)T y p 0 . 9 s e c

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 23. Alternate CE# Controlled Wr ite (Erase/Program) Operation Timings

48 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 3.0 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most words program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 10 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ ( Note 1)M a x ( Note 2) Unit Comments Sector Erase Time 0.9 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 115 sec Word Program Time 11 300 µs Excludes system level overhead (Note 5) Accelerated Word Program Time 7 210 µs Chip Program Time (Note 3) 48 144 sec Description Min Max Input voltage with respect to V SS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance V OUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 49 DATA SHEET PHYSICAL DIMENSIONS SSO056—56-Pin Shrink Small Outline Package (SSOP) Dwg rev AB; 10/99

50 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package Dwg rev AF; 10/99

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 51 DATA SHEET PHYSICAL DIMENSIONS LAA064—64-Ball Fortified Ball Grid Array (FB G A )1 3x1 1m mp a c k a g e

52 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

TS 048—48-Pin Standard TSOP Note: For reference only. BSC is an ANSI standard for Basic Space Centering. * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 53 DATA SHEET REVISION SUMMARY Revision A (April 26, 1999) Initial release. Revision A+1 (May 4, 1999) Global Deleted references to the 4-word unique ESN. Re- placed references to VCCQ with VIO. Connection Diagrams 63-ball FBGA: Corrected signal for ball H7 to VIO. Added “U” designator description. SecSi (Secured Silicon) Sector Flash Memory Region In the third paragraph, replaced references to boot sectors with SA0. Added table to show SecSi sector contents. DC Characteristics table Added V IO = VCC as a test condition for I CC1 and ICC2. Changed V HH minimum specification from 8.5 V to 11.5 V. Revision A+2 (May 14, 1999) Clarified the differences between the H, L, and U designators. Revision A+3 (June 7, 1999) Product Selector Guide Added note under table. Deleted the “0” from the 120 and 150 ns part numbers. Corrected the FBGA package marking for the 150 ns speed option. Revision A+4 (June 25, 1999) Global Information on the 56-pin SSOP package has been added: pinout information and physical dimension drawings. Command Definitions Corrected the data for SecSi Sector protection in Note 9. Added device ID data to the table. Revision A+5 (August 2, 1999) Block Diagram Separated WP# and ACC. Added the valid combinations for the SSOP package. Revision A+6 (September 28, 1999) Connection Diagrams Clarified which packages are available for a particular part number. Device Bus Operations VersatileIO Control: Added comment to contact AMD for more information on this feature. DC Characteristics CMOS Compatible table: Added notes (1 and 2) for I LI and test conditions column. Test Conditions In Test Specifications table and Input Waveforms and Measurement Levels figure, changed the output mea- surement level to V IO/2. AC Characteristics Read-only Operations table: Added note for test setup column. Revision B (June 20, 2000) Global Deleted references to 150 ns speed option. Added more information and specifications on V IO feature, in- cluding part number distinctions. At V IO < V CC, the available speed options are 100 ns and 120 ns. At V IO ≥ VCC, the available speed options are 90 ns and 120 ns. Changed data sheet status to “Preliminary.” Distinctive Characteristics Clarified on which devices RY/BY# and WP# are avail- able. Clarified package options for devices. Clarified on which devices RY/BY# and WP# are avail- able. Clarified package options for devices. Reinstated “0” into the 120 ns speed part number for V IO = 3.0 V to 5.0 V; added part numbers for VIO = 1.8 V to 2.9 V. Device Bus Operations table In the legend, corrected the VHH voltage range. SecSi Sector Contents table Corrected ending address in second row to 7Fh. DC Characteristics table Redefined VOH1 and VOH2 in terms of V IO. Added note relative to V IO for VIH and VIL. Deleted note regarding test condition assumption of VIO = VCC.

54 Am29LV640D/Am29LV641D 22366C6 January 22, 2007

Test Conditions table: Redefined output timing mea- surement reference level as 0.5 VIO. Added note to table and figure. Erase and Program Operations table, Alternate CE# Controlled Erase and Program Operations table, Erase and Programming Performance table Changed the typical sector erase time to 1.6 s. AC Characteristics—Figure 15. Program Operations Timing and Figure 17. Chip/Sector Erase Operations Deleted t GHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision B+1 (August 4, 2000) Global Added trademarks for SecSi Sector. Accelerated Program Operation (page 11), Unlock Bypass Command Sequence (page 25) Added caution note regarding ACC pin. Absolute Maximum Ratings Corrected the maximum voltage on VIO to +5.5V. DC Characteristics table Added WP# = V IH to test conditions for standby cur- rents ICC3, ICC4, ICC5. Revision B+2 (October 18, 2000) Distinctive Characteristics Corrected package options for 56-pin SSOP as being available on Am29LV640DH/DL only. Revision B+3 (January 18, 2001) Global Deleted “Preliminary” status from document. General Description In the second paragraph, corrected references to V IO voltage ranges. The 90 and 120 speeds are available where VIO ≥ VCC, and 100 and 120 ns speeds are avail- able where VIO < VCC. Revision B+4 (March 8, 2001) Table 4, Sector Group Protection/Unprotection Address Table Corrected the sector group address bits for sectors 64–127. Revision B+5 (October 11, 2001) Connection Diagrams, Ordering Information, Physical Dimensions Added 64-ball Fortified BGA package information. Revision B+6 (January 10, 2002) Global Clarified description of VersatileIO (V IO) in the follow- ing sections: Distinctive Characteristics; General De- scription; VersatileIO (V IO) Control; Operating Ranges; DC Characteristics; CMOS compatible. Reduced typical sector erase time from 1.6 s to 0.9 s. DC Characteristics Changed minimum V OH1 from 0.85V IO to 0.8V IO. De- leted reference to Note 6 for both VOH1 and VOH2. Erase and Program Performance table Reduced typical sector erase time from 1.6 s to 0.9 s. Changed typical chip program time from 90 s to 115 s. Revision B+7 (April 15, 2002) Added N designator for Fortified BGA package mark- ings. Common Flash Interface (CFI) Revised data value at address 44h. Clarified descrip- tion of data for addresses 45–47h, 49, 4A, 4D–4Fh. Table 10, Command Definitions Clarified and combined Notes 4 and 5 into Note 4. Revision B+8 (September 20, 2002) Sector Erase Command Sequence Changed sentence arrangement in fourth paragraph. Revision B+9 (March 3, 2004) Table 10, Command Definitions Revised SecSi Sector Factory Protect (note 8) com- mand definitions. Revision B+10 (April 5, 2004) Command Definitions Changed first Address data for Erase Suspend/Re- sume from BA to XXX. Revision C (June 4, 2004) Added Pb-free OPNs.

January 22, 2007 22366C6 Am29LV640D/Am29LV641D 55 DATA SHEET Revision C + 1 (October 14, 2004) Added tRH reference line to Figure 14. Corrected description of Sector Erase Command Se- quence on page 30. Added Colophon Revision C + 2 (January 7, 2005) Valid Combinations Updated table to include a note regarding product of- ferings for new designs. Revision C + 3 (February 9, 2005) Pin Description Added RFU to the list of pins. Global Removed references to byte mode. Revision C + 4 (September 13, 2005) Valid Combinations New option FF added on TSOP and SSOP packages. Revision C5 (December 23, 2005) Global Deleted reverse TSOP package option and 100 ns speed option. Revision C6 (January 22, 2007) AC Characteristics Erase and Program Operations table: Changed t BUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 1999–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006–2007 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.