L256ML113RI

AM29LV256M_05 AMD | Alldatasheet

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Publication Number 25263 Revision C Amendment +6 Issue Date December 16, 2005 Am29LV256M Data Sheet RETIRED PRODUCT This product has been retired and is not ava ilable for designs. For new and current designs, S29GL256N supersedes Am29LV256M and is the factory-recommended migration path. Please refer to the S29GL256N datasheet for specifications and or dering information. Availability of this docu- ment is retained for reference and historical purposes only. July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Althou gh the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Fu ture routine revisions will occur when appro- priate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 25263 Rev: C Amendment/+6 Issue Date: December 16, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. Am29LV256M

256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit

3.0 Volt-only

Uniform Sector Flash Memory with VersatileI/O TM Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Single power supply operation — 3 volt read, erase, and program operations „ VersatileI/OTM control — Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the VIO pin; operates from 1.65 to 3.6 V „ Manufactured on 0.23 µm MirrorBit process technology „ SecSi TM (Secured Silicon) Sector region — 128-word/256-byte sector for permanent, secure identification through an 8-word/16-byte random Electronic Serial Number, accessible through a command sequence — May be programmed and locked at the factory or by the customer „ Flexible sector architecture — Five hundred twelve 32 Kword (64 Kbyte) sectors „ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection „ Minimum 100,000 erase cycle guarantee per sector „ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS „ High performance — 100 ns access time — 30 ns page read times — 0.5 s typical sector erase time — 15 µs typical effective write buffer word programming time: 16-word/32-byte write buffer reduces overall programming time for multiple-word updates — 4-word/8-byte page read buffer — 16-word/32-byte write buffer „ Low power consumption (typical values at 3.0 V, 5 MHz) — 13 mA typical active read current — 50 mA typical erase/program current — 1 µA typical standby mode current „ Package options — 56-pin TSOP — 64-ball Fortified BGA SOFTWARE & HARDWARE FEATURES „ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word or byte programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices „ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Group Unprotect: V ID-level method of changing code in locked sector groups — WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) detects program or erase cycle completion This product has been retired and is not available for designs. For new and current designs, S29GL256N supersedes Am29LV256M and is the factory-recommended migration path. Please refer to the S29GL256N datasheet for specifications and ordering information. Availability of this document is retained for reference and his- torical purposes only.

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The Am29LV256M is a 256 Mbit, 3.0 volt single power supply flash memory devices organized as 16,777,216 words or 33,554,432 bytes. The device has a 16-bit wide data bus that can also function as an 8-bit wide data bus by using the BYTE# input. The device can be programmed either in the host system or in standard EPROM programmers. An access time of 100, 110, or 120 ns is available. Note that each access time has a specific operating voltage range (V CC) and an I/O voltage range (VIO), as specified in the Product Selector Guide and the Order- ing Information sections. The device is offered in a 56-pin TSOP or Fortified BGA package. Each device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 (Data# Polling) or DQ6 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) output to deter- mine whether the operation is complete. To facilitate programming, an Unlock Bypass mode reduces com- mand sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the V IO pin. Refer to the Ordering Information section for valid V IO options. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector group protection feature disables both program and erase operations in any combination of sector groups of memory. This can be achieved in-system or via pro- gramming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or when addresses have been stable for a specified period of time. The SecSi TM (Secured Silicon) Sector provides a 128-word/256-byte area for code or data that can be permanently protected. Once this sector is protected, no further changes within the sector can occur. The Write Protect (WP# /ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. AMD MirrorBit flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. RELATED DOCUMENTS For a comprehensive information on MirrorBit prod- ucts, including migration information, data sheets, ap- plication notes, and software drivers, please see www.amd.com →Flash Memory →Product Informa- tion→MirrorBit→Flash Information →Technical Docu- mentation. The following is a partial list of documents closely related to this product: MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs

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Notes: 1. See “AC Characteristics” for full specifications. 2. Contact factory for availability and ordering information. BLOCK DIAGRAM Part Number Am29LV256M Speed/ Voltage Option Regulated Voltage Range VCC = 3.0–3.6 V 103R (Note 2) (VIO = 2.7–3.6) 113R (VIO = 1.65–3.6) 123R (VIO = 1.65–3.6) Full Voltage Range VCC = 2.7–3.6 V 103 (Note 2) (VIO = 2.7–3.6) 113 (Note 2) (VIO = 1.65–3.6) 123 (Note 2) (VIO = 1.65–3.6) Max. Access Time (ns) 100 110 120 Max. CE# Access Time (ns) 100 110 120 Max. Page access time (tPACC) 3 03 04 03 0 4 0 Max. OE# Access Time (ns) 30 30 40 30 40 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WP#/ACC BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA23–A0 VIO

December 16, 2005 Am29LV256M 5 DATASHEET CONNECTION DIAGRAMS A23 A22 A15 A14 A13 A12 A11 A10 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 NC NC A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 NC NC OE# V SS CE# NC V IO A23 A22 A15 A14 A13 A12 A11 A10 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 NC NC A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 NC NC OE# V SS CE# NC VIO 56-Pin Standard TSOP 56-Pin Reverse TSOP

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Special handling is required for Flash Memory products in molded packages (TSOP and BGA). The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A2 C2 D2 E2 F2 G2 H2 A3 C3 D3 E3 F3 G3 H3 A4 C4 D4 E4 F4 G4 H4 A5 C5 D5 E5 F5 G5 H5 A6 C6 D6 E6 F6 G6 H6 A7 C7 D7 E7 F7 G7 H7 DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A211RESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 A1 C1 D1 E1 F1 G1 H1 NC NCVIONCNCNCNCNC A8 C8 B8 D8 E8 F8 G8 H8 NC NCNCVSSVIOA233A222NC Fortified BGA Top View, Balls Facing Down

December 16, 2005 Am29LV256M 7 DATASHEET PIN DESCRIPTION A23–A0 = 24 Address inputs DQ14–DQ0 = 15 Data inputs/outputs DQ15/A-1 = DQ15 (Data input/output, word mode), A-1 (LSB Address input, byte mode) CE# = Chip Enable input OE# = Output Enable input WE# = Write Enable input WP#/ACC = Hardware Write Protect input; Acceleration input RESET# = Hardware Reset Pin input BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V IO = Output Buffer power VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ15–DQ0 (A-1) A23–A0 CE# OE# WE# RESET# RY/BY# WP#/ACC VIO BYTE#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Note:For 103, 103R, 110, and 120 speed option shown in product selector guide, contact AMD for availability and ordering information. Notes: 1. To select the product with ESN factory-locked into the SecSi Se ctor: 1) select the order number from the valid combinations given above, 2)add designator “N” at the end of the order number, and 3) modify the speed option indicator as follows [113R = 11R; 123R = 12R; 113, 123 = no change] Example: Am29LV256MH12RPGIN. For fortified BGA packages, the designator “N” will also appear at the end of the package marking. Example: L256MH12RIN. Am29LV256M H 123R PG I TEMPERATURE RANGE I = Industrial (–40°C to +85°C) F = Industrial (–40°C to +85°C) with Lead (Pb)-free package PACKAGE TYPE E = 56-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 056) F = 56-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR056) PG = 64-Ball Fortified Ball Grid Array, 1.0 mm pitch, 18 x 12 mm package (LAC064) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = V IL) H = Uniform sector device, highest address sector protected L = Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV256MH/L

256 Megabit (16 M x 16-Bit/32 M x 8-Bit) MirrorBit Uniform Sector Flash Memory with VersatileIO

3.0 Volt-only Read, Program, and Erase

(ns) VIO Range VCC Range Am29LV256MH113R Am29LV256ML113R EI, FI, EF 110 1.65–3.6 V 3.0–3.6 V Am29LV256MH123R Am29LV256ML123R 120 1.65–3.6 V Valid Combinations for Fortified BGA Package Speed (ns) VIO Range VCC Range Order Number Package Marking Am29LV256MH113R Am29LV256ML113R PGI, PGF L256MH113R L256ML113R I, F 110 1.65– 3.6 V 3.0–

3.6 VAm29LV256MH123R

L256ML123R 120 1.65– 3.6 V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A23:A0 in word mode; A23:A-1 in byte mode. Sector addresses are A23:A15 in both modes.
2. The sector group protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Group Protection and Unprotection” section.

1. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

used as an input for the LSB (A-1) address function. for VIO options on this device.

0.3 V XX VCC ±

0.3 V XH X High-Z High-Z High-Z

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For example, a V I/O of 1.65–3.6 volts allows for I/O at the 1.8 or 3 volt levels, driving and receiving signals to and from other 1.8 or 3 V devices on the same data bus. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing speci- fications and to Figure 13 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 words/8 bytes. The appropriate page is selected by the higher address bits A(max)–A2. Ad- dress bits A1–A0 in word mode (A1–A-1 in byte mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Char- acteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to re- duce the time required for program operations. The system would use a two-cycle program command se- quence as required by the Unlock Bypass mode. Re- moving V HH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at V IH. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not read ing or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced,

December 16, 2005 Am29LV256M 11 DATASHEET and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V IO ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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Table 2. Sector Address Table

Table 2. Sector Address Table (Continued)

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tion, through identifier codes output on DQ7–DQ0. accessed in-system through the command register. A6, A3, A2, A1, and A0 must be as shown in Table 3. Command Sequence section for more information. Table 3. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

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groups must be individually re-protected. tact an AMD representative for details. Table 4. Sector Group Protection/Unprotection

December 16, 2005 Am29LV256M 25 DATASHEET SA248–SA251 0111110xx SA252–SA255 0111111xx SA256–SA259 1000000xx SA260–SA263 1000001xx SA264–SA267 1000010xx SA268–SA271 1000011xx SA272–SA275 1000100xx SA276–SA279 1000101xx SA280–SA283 1000110xx SA284–SA287 1000111xx SA288–SA291 1001000xx SA292–SA295 1001001xx SA296–SA299 1001010xx SA300–SA303 1001011xx SA304–SA307 1001100xx SA308–SA311 1001101xx SA312–SA315 1001110xx SA316–SA319 1001111xx SA320–SA323 1010000xx SA324–SA327 1010001xx SA328–SA331 1010010xx SA332–SA335 1010011xx SA336–SA339 1010100xx SA340–SA343 1010101xx SA344–SA347 1010110xx SA348–SA351 1010111xx SA352–SA355 1011000xx SA356–SA359 1011001xx SA360–SA363 1011010xx SA364–SA367 1011011xx SA368–SA371 1011100xx SA372–SA375 1011101xx SA376–SA379 1011110xx SA380–SA383 1011111xx SA384–SA387 1100000xx SA388–SA391 1100001xx SA392–SA395 1100010xx SA396–SA399 1100011xx SA400–SA403 1100100xx SA404–SA407 1100101xx SA408–SA411 1100110xx SA412–SA415 1100111xx SA416–SA419 1101000xx SA420–SA423 1101001xx SA424–SA427 1101010xx Sector Group A23–A15 SA428–SA431 1101011xx SA432–SA435 1101100xx SA436–SA439 1101101xx SA440–SA443 1101110xx SA444–SA447 1101111xx SA448–SA451 1110000xx SA452–SA455 1110001xx SA456–SA459 1110010xx SA460–SA463 1110011xx SA464–SA467 1110100xx SA468–SA471 1110101xx SA472–SA475 1110110xx SA476–SA479 1110111xx SA480–SA483 1111000xx SA484–SA487 1111001xx SA488–SA491 1111010xx SA492–SA495 1111011xx SA496–SA499 1111100xx SA500–SA503 1111101xx SA504–SA507 1111110xx SA508 111111100 SA509 111111101 SA510 111111110 SA511 111111111 Sector Group A23–A15

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scribed in “Sector Group Protection and Unprotection”. increased. See the table in “DC Characteristics”. Figure 1. Temporary Sector

1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector will remain protected).

1. All previously protected sector groups are protected

Figure 2. In-System Sector Group Protect/Unprotect Algorithms

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rity of the ESN once the product is shipped to the field. when the SecSi Sector is enabled. dresses normally occupied by the first sector (SA0). sending commands to sector SA0. mand sequence. See Command Definitions. space can be modified in any way. without raising any device pin to a high voltage. Sector, follow the algorithm shown in Figure 3. writing within the remainder of the array. using AMD’s ExpressFlash service. Table 5. SecSi Sector Contents

Figure 3. SecSi Sector Protect Verify or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data.

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Table 6. CFI Query Identification String Table 7. System Interface String

Table 8. Device Geometry Definition

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Table 9. Primary Vendor-Specific Extended Query

December 16, 2005 Am29LV256M 33 DATASHEET non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase op- eration, or if the device is in the autoselect mode. See the next section, Reset Command , for more informa- tion. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a pr ogram command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the device to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 goes high during a Write Buffer Pro- gramming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: „ A read cycle at address XX00h returns the manu- facturer code. „ Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code. „ A read cycle to an address containing a sector ad- dress (SA), and the address 02h on A7–A0 in word mode returns 01h if the sector is protected, or 00h if it is unprotected. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend). Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-word/16-byte random Electronic Serial Number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command se- quence. The Exit SecSi Sector command sequence returns the device to normal operation. Tables 11 and 12 show the address and data requirements for both command sequences. See also “SecSi (Secured Sili- con) Sector Flash Memory Region” for further informa- tion. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is en- abled. Word/Byte Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 11 and 12 show the

34 Am29LV256M December 16, 2005

address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 or DQ6. Refer to the Write Operation Status sec- tion for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that the SecSi Sector, autoselect, and CFI functions are un- available when a program operation is in progress. Note that a hardware reset immediately terminates the program operation. The program command se- quence should be reinitiated once the device has re- turned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 20h. The device then enters the unlock bypass mode. A two-cycle un- lock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program com- mand, A0h; the second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispenses with the initial two unlock cycles required in the standard program command sequence, resulting in faster total program- ming time. Tables 11 and 12 show the requirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. (See Table 9). Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 words/32 bytes in one programming operation. This results in faster effective programming time than the standard programming algorithms. The Write Buffer Programming command sequence is initi- ated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Address in which pro- gramming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For example, if the system will pro- gram 6 unique address locations, then 05h should be written to the device. This tells the device how many write buffer addresses will be loaded with data and therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is se- lected by address bits A MAX–A4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter dec- rements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7, DQ6, DQ5, and DQ1 should be monitored to determine the device status during Write Buffer Programming. The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways:

December 16, 2005 Am29LV256M 35 DATASHEET „ Load a value that is greater than the page buffer size during the Number of Locations to Program step. „ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. „ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. „ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 = 1, DQ7 = DATA# (for the last address location loaded), DQ6 = toggle, and DQ5=0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the de- vice for the next operation. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is re- quired when using Write-Buffer-Programming features in Unlock Bypass mode. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was suc- cessful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device dam- age may result. WP# has an internal pullup; when un- connected, WP# is at V IH. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.

36 Am29LV256M December 16, 2005

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 may change simultaneously with DQ5.

Therefore, DQ7 should be verified.

1. If this flowchart location was reached because

command. if DQ5=1, write the Reset command.

1. See Tables 11 and 12 for command sequences

required for write buffer programming.

Figure 5. Program Operation μs maximum (5μs typical) and updates the status bits. Autoselect Command Sequence for more information.

38 Am29LV256M December 16, 2005

Figure 6. Program Suspend/Program Resume chip erase command sequence. of the erase operation by using DQ7, DQ6, or DQ2. mation on these status bits. array data, to ensure data integrity. and Figure 18 section for timing diagrams. ings during these operations. erase operation in is progress.

tion Status section for information on these status bits. reading array data, to ensure data integrity. and Figure 18 section for timing diagrams. Table 10. Erase Operation suspends the erase operation. if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard word program operation. a longer cumulative erase time than without suspends.

1. See Tables 11 and 12 for program command sequence.
2. See the section on DQ3 for information on the sector

40 Am29LV256M December 16, 2005

Table 11. Command Definitions (x16 Mode, BYTE# = V IH) RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A23–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A23–A11 are don’t cares.
3. No unlock or command cycles required when device is in read
4. The Reset command is required to return to the read mode (or to

while the device is providing status information.

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence section for more information.

1. The device ID must be read in three cycles.
2. If WP# protects the highest address sector, the data is 98h for
3. The total number of cycles in the command sequence is

maximum number of cycles in the command sequence is 21.

1. The data is 00h for an unprotected sector and 01h for a protected
2. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

Table 12. Command Definitions (x8 Mode, BYTE# = V IL) RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A23–A15 uniquely select any sector. BC = Byte Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A22–A11 are don’t cares.
3. No unlock or command cycles required when device is in read
4. The Reset command is required to return to the read mode (or to

while the device is providing status information.

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence section for more information.

1. The device ID must be read in three cycles.
2. If WP# protects the highest address sector, the data is 98h for
3. The total number of cycles in the command sequence is

maximum number of cycles in the command sequence is 37.

1. The data is 00h for an unprotected sector group and 01h for a
2. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

42 Am29LV256M December 16, 2005

in progress or has been completed. final WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 13 shows the outputs for Data# Polling on DQ7. Figure 7. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

December 16, 2005 Am29LV256M 43 DATASHEET RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev- eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively eras- ing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is in the read mode, the standby mode, or in the erase-suspend-read mode. Table 13 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com- plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ad- dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op- eration, successive read c ycles to any address cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for approxi- mately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algo- rithm erases the unprotected sectors, and ignores the se- lected sectors that are protected. The system can use DQ6 and DQ2 together to determine whether a sector is actively erasing or is erase-suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the de- vice enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alterna- tively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro- gram algorithm is complete. Table 13 shows the outputs for Toggle Bit I on DQ6. Figure 8 shows the toggle bit algorithm. Figure 20 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 21 shows the differences be- tween DQ2 and DQ6 in graphical form. See also the subsection on DQ2: Toggle Bit II.

44 Am29LV256M December 16, 2005

Figure 8. Toggle Bit Algorithm section. Figure 20 shows the toggle bit timing diagram.

termine the status of the operation (top of Figure 8). in the erase-suspend-program mode). device will accept additional sector erase commands. last command might not have been accepted. Table 13. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 switches to ‘1’ when the device has aborted the write-to-buffer operation.

46 Am29LV256M December 16, 2005

1. Minimum DC voltage on input or I/O pins is –0.5 V.

SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V.

1. Minimum DC input voltage on pins A9, OE#, ACC, and

which may overshoot to +14.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability.

1. Operating ranges define those limits between which the

functionality of the device is guaranteed.

1. See Ordering Information section for valid VCC/VIO range

Figure 9. Maximum Negative Figure 10. Maximum Positive

December 16, 2005 Am29LV256M 47 DATASHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 2. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 6. If V IO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. Maximum VIH for these connections is VIO + 0.3 V 7. V CC voltage requirements. 8. V IO voltage requirements. 9. Not 100% tested 10. Includes RY/BY# Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ICC1 VCC Active Read Current (2, 3) CE# = VIL, OE# = VIH,

1 MHz 3 34

5 MHz 13 43

ICC2 VCC Initial Page Read Current (2, 3) CE# = V IL, OE# = VIH

1 MHz 4 50

10 MHz 40 80

ICC3 VCC Intra-Page Read Current (2, 3) CE# = V IL, OE# = VIH

10 MHz 3 20

33 MHz 6 40

ICC4 VCC Active Write Current (3, 4) CE# = V IL, OE# = VIH 50 60 mA ICC5 VCC Standby Current (3) CE#, RESET# = V CC ± 0.3 V, WP# = VIH 15 µ A ICC6 VCC Reset Current (3) RESET# = V SS ± 0.3 V, WP# = VIH 15 µ A ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 15 µ A VIL1 Input Low Voltage 1(6, 7) –0.5 0.8 V VIH1 Input High Voltage 1 (6, 7) 1.9 V CC + 0.5 V VIL2 Input Low Voltage 2 (6, 8) –0.5 0.3 x V IO V VIH2 Input High Voltage 2 (6, 8) 1.9 V IO + 0.5 V VHH Voltage for ACC Program Acceleration V CC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOL Output Low Voltage (10) I OL = 4.0 mA, VCC = VCC min = VIO 0.15 x VIO V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (9) 2.3 2.5 V

48 Am29LV256M December 16, 2005

Table 14. Test Specifications Note: If VIO < VCC, the reference level is 0.5 VIO. Note: Diodes are IN3064 or equivalent. Figure 11. Test Setup Note: If VIO < VCC, the input measurement reference level is 0.5 VIO. Figure 12. Input Waveforms and

1. See Figure 11 and Table 14 for test specifications.
2. AC specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC

0 VRY/BY#

Figure 13. Read Operation Timings

50 Am29LV256M December 16, 2005

• Figure shows word mode. Addresses are A1–A-1 for byte mode.

Figure 14. Page Read Timings

1. AC specifications listed are tested with V

IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. Description All Speed Options UnitJEDEC Std. Figure 15. Reset Timings

52 Am29LV256M December 16, 2005

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Byte/Word programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within t POLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 103, 103R 113, 113R 123, 123R Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 7.5 µs Per Word Typ 15 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 6.25 µs Per Word Typ 12.5 µs Single Byte/Word Program Operation (Note 2, 5) Byte Typ 60 µs Word Typ 60 µs Accelerated Single Byte/Word Programming Operation (Note 2, 5) Byte Typ 54 µs Word Typ 54 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs tBUSY Erase/Program Valid to RY/BY# Delay Max 100 110 120 ns tPOLL Program Valid Before Status Polling (Note 7) Max 4µ s

54 Am29LV256M December 16, 2005

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.

Figure 18. Chip/Sector Erase Operation Timings

Figure 19. Data# Polling Timings (During Embedded Algorithms)

56 Am29LV256M December 16, 2005

Figure 20. Toggle Bit Timings (During Embedded Algorithms) Figure 21. DQ2 vs. DQ6

Figure 22. Temporary Sector Group Unprotect Timing Diagram

58 Am29LV256M December 16, 2005

• For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Group Protect and Unprotect Timing Diagram

December 16, 2005 Am29LV256M 59 DATASHEET AC CHARACTERISTICS Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 words/1–32 bytes programmed. 4. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 5. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 6. AC listed are tested with V IO = VCC. Contact AMD for information on AC operation with VIO ≠ VCC. 7. When using the program suspend/resume feature, if the suspend command is issued within tPOLL, tPOLL must be fully re-applied upon resuming the programming operation. If the suspend command is issued after tPOLL, tPOLL is not required again prior to reading the status bits upon resuming. Parameter Speed Options JEDEC Std. Description 103, 103R 113, 113R 123, 123R Unit tAVAV tWC Write Cycle Time (Note 1) Min 100 110 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 7.5 µs Per Word Typ 15 µs Effective Accelerated Write Buffer Program Operation (Notes 2, 4) Per Byte Typ 6.25 µs Per Word Typ 12.5 µs Single Byte/Word Program Operation (Note 2, 5) Byte Typ 60 µs Word Typ 60 µs Accelerated Single Byte/Word Programming Operation (Note 2, 5) Byte Typ 54 µs Word Typ 54 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tPOLL Program Valid before Status Polling (Note 7) Max 4 µs

60 Am29LV256M December 16, 2005

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 24. Alternate CE# Controlled Write (Erase/Program)

December 16, 2005 Am29LV256M 61 DATASHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC. Programming specifications assume that all bits are programmed to 00h. 2. Maximum values are measured at VCC = 3.0, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. For 1-16 words or 1-32 bytes programmed in a single write buffer programming operation. 5. Effective write buffer specification is based upon a 16-word/32-byte write buffer operation. 6. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 7. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 11 for further information on command definitions. 8. The device has a minimum erase and pr ogram cycle endurance of 100,000 cycles. TSOP PIN AND BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 3.5 sec Excludes 00h programming prior to erasure (Note 6)Chip Erase Time 256 512 sec Single Byte/Word Program Time (Note 3) Byte 60 600 µs Excludes system level overhead (Note 7) Word 60 600 µs Accelerated Single Byte/Word Program Time (Note 3) Byte 54 540 µs Word 54 540 µs Total Write Buffer Program Time (Note 4) 240 1200 µs Effective Write Buffer Program Time (Note 5) Per Byte 7.5 38 µs Per Word 15 75 µs Total Accelerated Write Buffer Program Time (Note 4) 200 1040 µs Effective Accelerated Write Buffer Program Time (Note 5) Per Byte 6.25 33 µs Per Word 12.5 65 µs Chip Program Time 252 584 sec Parameter Symbol Parameter Desc ription Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 TSOP 6 7.5 pF BGA 4.2 5 pF COUT Output Capacitance V OUT = 0 TSOP 8.5 12 pF BGA 5.4 6.5 pF CIN2 Control Pin Capacitance V IN = 0 TSOP 7.5 9 pF BGA 3.9 4.7 pF

62 Am29LV256M December 16, 2005

Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

December 16, 2005 Am29LV256M 63 DATASHEET PHYSICAL DIMENSIONS TS056/TSR056—56-Pin Standard/Reverse Thin Small Outline Package (TSOP) NOTES: 1 CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm). (DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982.) 2 PIN 1 IDENTIFIER FOR STANDARD PIN OUT (DIE UP). 3 PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK. 4 TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT HORIZONTAL SURFACE. 5 DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS 0.15 mm PER SIDE. 6 DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE 0.08 mm TOTAL IN EXCESS OF b DIMENSION AT MAX MATERIAL CONDITION. MINIMUM SPACE BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 mm.

7 THESE DIMESIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN

0.10 mm AND 0.25 mm FROM THE LEAD TIP. 8. LEAD COPLANARITY SHALL BE WITHIN 0.10 mm AS MEASURED FROM THE SEATING PLANE. 9 DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS. 3160\\38.10A MO-142 (B) EC TS/TSR 56 NOM. --- --- 1.00 1.20 0.15 1.05 MAX. --- MIN. 0.95 0.20 0.230.17 0.22 0.270.17 --- 0.160.10 --- 0.210.10 20.00 20.2019.90 14.00 14.1013.90 0.60 0.700.50 3˚ 5˚0˚ --- 0.200.08 18.40 18.5018.30 0.05

0.50 BASIC

E R JEDEC PACKAGE SYMBOL A D c b e L N O

64 Am29LV256M December 16, 2005

LAC064—64-Ball Fortified Ball Grid Array 18 x 12 mm Package 3243 \\ 16-038.12d PACKAGE LAC 064 JEDEC N/A 18.00 mm x 12.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.40 PROFILE HEIGHT A1 0.40 --- --- STANDOFF A2 0.60 --- --- BODY THICKNESS D 18.00 BSC. BODY SIZE E 12.00 BSC. BODY SIZE D1 7.00 BSC. MATRIX FOOTPRINT E1 7.00 BSC. MATRIX FOOTPRINT MD 8 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION N 64 BALL COUNT φb 0.50 0.60 0.70 BALL DIAMETER eD 1.00 BSC. BALL PITCH - D DIRECTION eE 1.00 BSC. BALL PITCH - E DIRECTION SD / SE 0.50 BSC. SOLDER BALL PLACEMENT NONE DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010 (EXCEPT AS NOTED). 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL ROW MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL COLUMN MATRIX SIZE IN THE "E" DIRECTION. N IS THE TOTAL NUMBER OF SOLDER BALLS.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS

A AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW PARALLEL TO THE D OR E DIMENSION, RESPECTIVELY, SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. NOT USED. 9. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. BOTTOM VIEW SIDE VIEW TOP VIEW C0.20 C0.20 6 7 A M M C Cφ 0.10 φ 0.25 B C0.25 0.15 C A B CSEATING PLANE eD (INK OR LASER) CORNER D E φ0.50 A1 CORNER ID. 1.00±0.5 1.00±0.5 A CORNER NXφb SD SE eE ACBDFEGH

December 16, 2005 Am29LV256M 65 DATASHEET REVISION SUMMARY Revision A (August 3, 2001) Initial release as abbreviated Advance Information data sheet. Revision A+1 (September 12, 2001) Changed package part number designation from WH to PC. Physical Dimensions Added the TS056 and LAA064 packages. Revision A+2 (October 3, 2001) Global Corrected title from 64 Mbit to 256 Mbit. Added 120 ns speed option. Distinctive Characteristics SecSi TM (Secured Silicon) Sector region : Corrected 64-byte to 256-byte. Connection Diagram Modified Fortified BGA ball grid to an 8 x 8 ball matrix. Changed RFU (reserved for future use) balls to NC (No Connection). Changed operating voltage range on 90 ns speed op- tion to 3.0–3.6 V. Pin Description Added A-1 description. Revision A+3 (March 25, 2002) Distinctive Characteristics Clarified description of Enhanced VersatileIO control. Physical Dimensions Added drawing that shows both TS056 and TSR056 specifications. Revision B (July 1, 2002) Expanded data sheet to full specification version. Revision B+1 (July 10, 2002) Ordering Information, Physical Dimensions Corrected package description to LAC064, 18 x 12 mm Fortified BGA. DC Characteristics table Deleted IACC specification. Revision B+2 (September 9, 2002) Product Selector Guide, Ordering Information, Read-Only Operations, Erase and Program Operations, and Alternate CE# Controlled Erase and Program Operations Added regulated OPNs. Changed all OPNs that end with 4 or 9 to end with 3 or Changed all package markings that contain combina- tions that end with 4 or 9 to end with 3 or 8. CFI Modified wording of last paragraph to read: “reading array data.” Program Suspend/Program Resume Command Sequence Changed 15 µs typical to maximum and added 5 µs typical. Erase Suspend/Erase Resume Commands Changed typical from 20 µs to 5 µs and added a maxi- mum of 20 µs. LAC064—64-Ball Fortified Ball Grid Array Added final package drawing. Revision B+3 (October 23, 2002) SecSi (Secured Silicon) Sector Flash Memory Region Added x8 address range. Physical Dimensions Modified drawing to show the actual number of balls on device package. Revision B+4 (November 6, 2002) Global Removed the Enhanced VI/O option and changed it to VI/O only. Product Selector Guide Removed the 98R, 108, 108R, 118, 118R, 128, and 128R Speed Options. Modified Note #2. Moved V IO from far left side of the block diagram and moved it to Input/Output Buffers. Modified Order numbers and package markings to re- flect the removal of speed options.

66 Am29LV256M December 16, 2005

Table 4. SecSi Sector Contents Changed the VIO supply range to 1.65–3.6 V. Programmed or Protected at the factory. Table 7. Device Geometry Definition Changed the x16 data for 2Dh to 00FFh. are not available when the SecSi sector is enabled. Changed CFI website address. Access time to the 113R and 123R Speed Options. Added Sector Group Protection and added Table 4. Corrected typos in VIO ranges. Removed Note. Corrected typos in VIO ranges. Changed VIH1 and VIH2 minimum to 1.9. Corrected performance characteristics. Corrected Valid Combination to reflect speed option changes. Added Note. AC Characteristics Removed 93, 93R speed option. Added Note Input values in the t WHWH1 and tWHWH2 parameters in the Erase and Program Options table that were previ- ously TBD. Also added notes 5 and 6. Input values in the t WHWH1 and tWHWH2 parameters in the Alternate CE# Controlled Erase and Program Op- tions table that were previously TBD. Also added notes Erase and Programming Performance Input values into table that were previously TBD. Added note 4.

December 16, 2005 Am29LV256M 67 DATASHEET Revision C+1 (May 28, 2003) Global Converted to full datasheet version. Modified SecSi Sector Flash Memory Region section to include ESN references. Erase and Programming Performance Input values into table that were previously TBD. Modified notes. CMOS Compatible Corrected typos in table. Erase and Program Operations and Alternate CE# Controlled Erase and Program Operations Changed the typical for the Accelerated Effective Write Buffer Program Operation for Byte and Word to 6.25 and 12.5. Revision C+2 (June 11, 2003) Global Modified speed grades available. Revision C+3 (September 15, 2003) Added OPN note for ESN feature. Tables 11 & 12 Command Definitions Changed definition BA to XXX for Program/Erase Sus- pend (Note 16) and for Program/Erase Resume (Note 17). Program Suspend/Program Resume Command Sequence Removed - program suspended sector is required when writing this command. AC Characteristics - Hardware Reset Added information for tRB. AC Characteristics - Erase and Program Operations Added information for tBUSY. Revision C + 4 (February 9, 2004) Table 1 Device Bus Operations Modified ACC column to replace instances of X to L/H. Customer Lockable: SecSi Sector NOT Programmed or Protected at the Factory Removed second paragraph. Enter SecSi Sector/Exit SecSi Sector Command Sequence Added (write buffer) to last sentence of first paragraph. Write Buffer Programming Removed last paragraph. Table 10 & Table 12: Command Definitions Replaced the Addr information Program/Erase Sus- pend and Program/Erase Resume from BA to XXX. Erase Suspend/Erase Resume Commands Added note on flash device performance during suspend/erase mode. AC Characteristics - Erase and Program Operations Added tPOLL information. AC Characteristics - Operation Timings Figures Updated Figure 16: Program Operation Timings, Figure 19: Data# Polling Timings (During Embedded Algorithms, and Figure 24: Alternate CE# Controlled Write (Erase/Program) Operation Timings. Trademarks Updated information. Cover page and Title sheet Added notation referencing superseding documenta- tion. Revision C + 5 (October 27, 2004) Ordering Information Table Added Pb-free ordering option Revision C + 6 (December 16, 2005) This product has been retired and is not available for designs. For new and current designs, S29GL256N supersedes Am29LV256M and is the factory-recom- mended migration path. Please refer to the S29GL256N datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. Trademarks Copyright © 2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.