L2562MH12RI

AM29LV2562M AMD | Alldatasheet

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Publication Number 26494 Revision B Amendment +2 Issue Date December 16, 2005 Am29LV2562M Data Sheet RETIRED PRODUCT This product has been retired and is not available for de signs. For new and current designs, S29GL512N supersedes Am29LV2562M and is the factory-recommended migration path. Please refer to the S29GL512N Data Sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only. July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 26494 Rev: B Amendment/+2 Issue Date: December 16, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. Am29LV2562M

512 Megabit (16 M x 32-Bit/32 M x 16-Bit)

MirrorBit™ 3.0 Volt-only Uniform Sector Flash Memory with VersatileI/O™ Control DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Single power supply operation — 3 volt read, erase, and program operations „ VersatileI/OTM control — Device generates data output voltages and tolerates data input voltages on the CE# and DQ inputs/outputs as determined by the voltage on the V IO pin; operates from 1.65 to 3.6 V „ Manufactured on 0.23 µm MirrorBitTM process technology „ SecSi™ (Secured Silicon) Sector region — 128-doubleword/256-word sector for permanent, secure identification through an 8-doubleword/16-word random Electronic Serial Number, accessible through a command sequence — May be programmed and lock ed at the factory or by the customer „ Flexible sector architecture — Five hundred twelve 32 Kdoubleword (64 Kword) sectors „ Compatibility with JEDEC standards — Provides pinout and software compatibility for single-power supply flash, and superior inadvertent write protection „ 100,000 erase cycles per sector „ 20-year data retention at 125°C PERFORMANCE CHARACTERISTICS „ High performance — 120 ns access time — 30 ns page read times — 0.5 s typical sector erase time — 15 µs typical write buffer doubleword programming time: 16-doubleword/32-word write buffer reduces overall programming time for multiple-word updates — 4-doubleword/8-word page read buffer — 16-doubleword/32-word write buffer „ Low power consumption (typical values at 3.0 V, 5 MHz) — 26 mA typical active read current — 100 mA typical erase/program current — 2 µA typical standby mode current „ Package options — 80-ball Fortified BGA SOFTWARE & HARDWARE FEATURES „ Software features — Program Suspend & Resume: read other sectors before programming operation is completed — Erase Suspend & Resume: read/program other sectors before an erase operation is completed — Data# polling & toggle bits provide status — Unlock Bypass Program command reduces overall multiple-word or byte programming time — CFI (Common Flash Interface) compliant: allows host system to identify and accommodate multiple flash devices „ Hardware features — Sector Group Protection: hardware-level method of preventing write operations within a sector group — Temporary Sector Group Unprotect: V ID-level method of changing code in locked sector groups — WP#/ACC input accelerates programming time (when high voltage is applied) for greater throughput during system production. Protects first or last sector regardless of sector protection settings — Hardware reset input (RESET#) resets device — Ready/Busy# output (RY/BY#) detects program or erase cycle completion This product has been retired and is not available for designs. For new and current designs, S29GL512N supersedes Am29LV2562M and is the factory-recommended migration path. Please refer to the S29GL512N Data Sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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The Am29LV2562M consists of two 256 Mbit, 3.0 volt single power supply flash memory devices and is or- ganized as 16,777,216 doublewords or 33,554,432 words. The device has a 32-bit wide data bus that can also function as an 16-bit wide data bus by using the WORD# input. The device can be programmed either in the host system or in standard EPROM program- mers. An access time of 120 ns is available. Note that each access time has a specific operating voltage range CC) as specified in the Product Selector Guide and the Ordering Information sections. The device is of- fered in an 80-ball Fortified BGA package. Each de- vice has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. Each device requires only a single 3.0 volt power supply for both read and write functions. In addition to a V CC input, a high-voltage accelerated program (WP#/ACC) input provides shorter programming times through increased current. This feature is intended to facilitate factory throughput during system production, but may also be used in the field if desired. The device is entirely command set compatible with the JEDEC single-power-su pply Flash standard . Commands are written to the device using standard microprocessor write timing. Write cycles also inter- nally latch addresses and data needed for the pro- gramming and erase operations. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Device programming and erasure are initiated through command sequences. Once a program or erase oper- ation has begun, the host system need only poll the DQ7 and DQ15 (Data# Polling) or DQ6 and DQ14 (toggle) status bits or monitor the Ready/Busy# (RY/BY#) outputs to determine whether the operation is complete. To facilitate programming, an Unlock By- pass mode reduces command sequence overhead by requiring only two write cycles to program data instead of four. The VersatileI/O™ (V IO) control allows the host sys- tem to set the voltage levels that the device generates and tolerates on the CE# control input and DQ I/Os to the same voltage level that is asserted on the V IO pin. Refer to the Ordering Information section for valid V IO options. Hardware data protection measures include a low VCC detector that automatically inhibits write opera- tions during power transitions. The hardware sector group protection feature disables both program and erase operations in any combination of sector groups of memory. This can be achieved in-system or via pro- gramming equipment. The Erase Suspend/Erase Resume feature allows the host system to pause an erase operation in a given sector to read or program any other sector and then complete the erase operation. The Program Sus- pend/Program Resume feature enables the host sys- tem to pause a program operation in a given sector to read any other sector and then complete the program operation. The hardware RESET# pin terminates any operation in progress and resets the device, after which it is then ready for a new operation. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the host system to read boot-up firmware from the Flash memory device. The device reduces power consumption in the standby mode when it detects specific voltage levels on CE# and RESET#, or wh en addresses have been stable for a specified period of time. The SecSi ™ (Secured Silicon) Sector provides a 128-doubleword/256-word area for code or data that can be permanently protected. Once this sector is pro- tected, no further changes within the sector can occur. The Write Protect (WP# /ACC) feature protects the first or last sector by asserting a logic low on the WP# pin. AMD MirrorBit TM flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effec- tiveness. The device electrically erases all bits within a sector simultaneously via hot-hole assisted erase. The data is programmed using hot electron injection. RELATED DOCUMENTS For a comprehensive information on MirrorBit prod- ucts, including migration information, data sheets, ap- plication notes, and software drivers, please see www.amd.com →Flash Memory →Product Informa- tion→MirrorBit→Flash Information →Technical Docu- mentation. The following is a partial list of documents closely related to this product: MirrorBit™ Flash Memory Write Buffer Programming and Page Buffer Read Implementing a Common Layout for AMD MirrorBit and Intel StrataFlash Memory Devices Migrating from Single-byte to Three-byte Device IDs

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Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board. Part Number Am29LV2562M Speed Option VCC = 3.0–3.6 V , VIO = 1.65–3.6V 120R Max. Access Time (ns) 120 Max. CE# Access Time (ns) 120 Max. Page access time (t PACC)3 0 Max. OE# Access Time (ns) 30 OE# WE# CE#

256 Mbit

#1 DQ23/A-1 to DQ16; DQ7-DQ0 DQ32/A-1 to DQ24; DQ15 TO DQ8 DQ31 to DQ0 A23 to A0 RY/BY# RESET# X16 X16 X32 WORD# WP#/ACC

December 16, 2005 Am29LV2562M 5 DATASHEET FLASH MEMORY BLOCK DIAGRAM Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board. Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# WP#/ACC WORD# CE# OE# STB VIO DQ31–DQ0 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA23–A0 STB

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Note: The FBGA package pinout configuration shown is preliminary. The ball count and package physical dimensions have not yet been determined. Contact AMD for further information. Special Package Handling Instructions Special handling is required for Flash Memory products in molded packages (BGA). The package and/or data integrity may be compromise d if the package body is exposed to temperatures above 150°C for prolonged periods of time. 80-ball Fortified BGA Top View, Balls Facing Down A2 C2 D2 E2 F2 G2 H2 A3 C3 D3 E3 F3 G3 H3 A4 C4 D4 E4 F4 G4 H4 A5 C5 D5 E5 F5 G5 H5 A6 C6 D6 E6 F6 G6 H6 A7 C7 D7 E7 F7 G7 H7 WORD# DQ15A16A15A14A12A13DQ23/A-1 DQ14 DQ13DQ7A11A10A8A9DQ30 DQ12 V CCDQ5A19A21RESET#WE#VSS DQ10 DQ11DQ2A20A18WP#/ACCRY/BY# VCC DQ8 DQ9DQ0A5A6A17A7DQ31/A-1 CE# OE#A0A1A2A4A3DQ18 A1 C1 D1 E1 F1 G1 H1 VIO RFURFURFURFUVCCDQ16RFU A8 C8 B8 D8 E8 F8 G8 H8 RFU RFU V SS DQ6 DQ4 DQ3 DQ1 V SS DQ24 DQ29 DQ20 DQ27 DQ26 DQ19 DQ17 VCC DQ25 DQ22VSSVIOA23A22DQ28DQ21

December 16, 2005 Am29LV2562M 7 DATASHEET PIN CONFIGURATION A–1 = Least significant address bit for the 16-bit data bus, and selects between the high and low word. A –1 is not used for the 32-bit mode (WORD# = V IH). A23–A0 = 24-bit address bus for 512 Mb device. DQ31–DQ0 = 32-bit data inputs/outputs/float WORD# = Selects 16-bit or 32-bit mode. When WORD# = VIH, data is output on DQ31–DQ0. When WORD# = VIL, data is output on DQ15–DQ0. CE# = Chip Enable Input. OE# = Output Enable Input. WE# = Write enable. VSS = Device ground RY/BY# = Ready/Busy output and open drain. When RY/BY# = VOH, the device is ready to ac- cept read operations and commands. When RY/BY# = VOL, the device is either executing an embedded algorithm or the device is executing a hardware reset oper- ation. WP#/ACC = Write Protect input/Acceleration input. V CC = Power Supply (2.7 V to 3.6 V) RESET# = Hardware reset input NC = Pin not connected internally LOGIC SYMBOLS x16 Mode x32 Mode Note:In x16 Mode, DQ31 and DQ23 must be connected together on the board. DQ15–DQ0 A23 to A-1 RY/BY# CE# OE# WE# WP#/ACC RESET# WORD# V IO DQ31–DQ0 A23–A0 RY/BY# CE# OE# WE# WP#/ACC RESET# WORD# V IO

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list conf igurations planned to be sup- ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV2562M H 120R PI I TEMPERATURE RANGE I = Industrial (–40 °C to +85°C) PACKAGE TYPE PI =80-Ball Fortified Ball Grid Array (FBGA), 18 x 12 mm, (LSC080) SPEED OPTION See Product Selector Guide and Valid Combinations SECTOR ARCHITECTURE AND SECTOR WRITE PROTECTION (WP# = VIL) H =Uniform sector device, highest address sector protected L =Uniform sector device, lowest address sector protected DEVICE NUMBER/DESCRIPTION Am29LV2562MH/L 2 x 256 Megabit (16 M x 32-Bit/32 M x 16-Bit) MirrorBitTM Uniform Sector Flash Memory

3.0 Volt-only Read, Program, and Erase

d (ns) VCC Range VIO RangeOrder Number Package Marking Am29LV2562MH120 Am29LV2562ML120 R PII L2562MH12RI L2562ML12RI 120 3.0– 3.6 V 1.65– 3.6 V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A23:A0 in doubleword mode; A23:A-1 in word mode. Sector addresses are A23:A15 in both modes.
2. The sector group protect and sector group unprotect functions may also be implemented via programming equipment. See the

“Sector Group Protection and Unprotection” section.

1. If WP# = V IL, the first or last sector group remains protected. If WP# = VIH, the first or last sector will be protected or unprotected as
2. D IN or DOUT as required by command sequence, data polling, or sector protect algorithm (see Figure 2).

pins operate in the word or doubleword configuration. for VIO options on this device.

0.3 V XX VCC ±

0.3 V XH X High-Z High-Z High-Z

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Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE# and OE# pins to V IL. CE# is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. The device remains enabled for read access until the command register contents are altered. See “Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing speci- fications and to Figure 13 for the timing diagram. Refer to the DC Characteristics table for the active current specification on reading array data. Page Mode Read The device is capable of fast page mode read and is compatible with the page mode Mask ROM read oper- ation. This mode provides faster read access speed for random locations within a page. The page size of the device is 4 doublewords/8 words. The appropriate page is selected by the higher address bits A(max)–A2. Address bits A1–A0 in doubleword mode (A1–A-1 in word mode) determine the specific word within a page. This is an asynchronous operation; the microprocessor supplies the specific word location. The random or initial page access is equal to t ACC or tCE and subsequent page read accesses (as long as the locations specified by the microprocessor falls within that page) is equivalent to t PACC. When CE# is deasserted and reasserted for a subsequent access, the access time is t ACC or t CE. Fast page mode ac- cesses are obtained by keeping the “read-page ad- dresses” constant and changing the “intra-read page” addresses. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Doubleword/Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command se- quences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. Refer to the DC Characteristics table for the active current specification for the write mode. The AC Char- acteristics section contains timing specification tables and timing diagrams for write operations. Write Buffer Write Buffer Programming allows the system write to a maximum of 16 doublewords/32 words in one pro- gramming operation. This results in faster effective programming time than the standard programming al- gorithms. See “Write Buffer” for more information. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sector groups, and uses the higher voltage on the pin to re- duce the time required for program operations. The system would use a two-cycle program command se- quence as required by the Unlock Bypass mode. Re- moving V HH from the WP#/ACC pin returns the device to normal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated programming, or device damage may result. WP# has an internal pullup; when unconnected, WP# is at V IH. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more informa- tion. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than

December 16, 2005 Am29LV2562M 11 DATASHEET VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. Refer to the DC Characteristics table for the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard ad- dress access timings provide new data when ad- dresses are changed. While in sleep mode, output data is latched and always available to the system. Refer to the DC Characteristics table for the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re- setting the device to reading array data. When the RE- SET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state ma- chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to en- sure data integrity. Current is reduced for th e duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir- cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 15 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high impedance state.

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Table 2. Sector Address Table

Table 2. Sector Address Table (Continued)

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tion, through identifier codes output on DQ7–DQ0. accessed in-system through the command register. A6, A3, A2, A1, and A0 must be as shown in Table 3. Command Sequence section for more information. Table 3. Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

groups must be individually re-protected. tact an AMD representative for details. Table 4. Sector Group Protection/Unprotection

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SA248–SA251 0111110xx SA252–SA255 0111111xx SA256–SA259 1000000xx SA260–SA263 1000001xx SA264–SA267 1000010xx SA268–SA271 1000011xx SA272–SA275 1000100xx SA276–SA279 1000101xx SA280–SA283 1000110xx SA284–SA287 1000111xx SA288–SA291 1001000xx SA292–SA295 1001001xx SA296–SA299 1001010xx SA300–SA303 1001011xx SA304–SA307 1001100xx SA308–SA311 1001101xx SA312–SA315 1001110xx SA316–SA319 1001111xx SA320–SA323 1010000xx SA324–SA327 1010001xx SA328–SA331 1010010xx SA332–SA335 1010011xx SA336–SA339 1010100xx SA340–SA343 1010101xx SA344–SA347 1010110xx SA348–SA351 1010111xx SA352–SA355 1011000xx SA356–SA359 1011001xx SA360–SA363 1011010xx SA364–SA367 1011011xx SA368–SA371 1011100xx SA372–SA375 1011101xx SA376–SA379 1011110xx SA380–SA383 1011111xx SA384–SA387 1100000xx SA388–SA391 1100001xx SA392–SA395 1100010xx SA396–SA399 1100011xx SA400–SA403 1100100xx SA404–SA407 1100101xx SA408–SA411 1100110xx SA412–SA415 1100111xx SA416–SA419 1101000xx SA420–SA423 1101001xx SA424–SA427 1101010xx Sector Group A23–A15 SA428–SA431 1101011xx SA432–SA435 1101100xx SA436–SA439 1101101xx SA440–SA443 1101110xx SA444–SA447 1101111xx SA448–SA451 1110000xx SA452–SA455 1110001xx SA456–SA459 1110010xx SA460–SA463 1110011xx SA464–SA467 1110100xx SA468–SA471 1110101xx SA472–SA475 1110110xx SA476–SA479 1110111xx SA480–SA483 1111000xx SA484–SA487 1111001xx SA488–SA491 1111010xx SA492–SA495 1111011xx SA496–SA499 1111100xx SA500–SA503 1111101xx SA504–SA507 1111110xx SA508 111111100 SA509 111111101 SA510 111111110 SA511 111111111 Sector Group A23–A15

scribed in “Sector Group Protection and Unprotection”. increased. See the table in “DC Characteristics”. Figure 1. Temporary Sector Group

1. All protected sector groups unprotected (If WP# = V IL,

the first or last sector will remain protected).

1. All previously protected sector groups are protected

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Figure 2. In-System Sector Group Protect/Unprotect Algorithms

product is shipped to the field. being used to replace devices that are factory locked. Table 5. SecSi Sector Contents dresses normally occupied by the first sector (SA0). sending commands to sector SA0. space can be modified in any way. without raising any device pin to a high voltage. Sector, follow the algorithm shown in Figure 3. writing within the remainder of the array.

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Figure 3. SecSi Sector Protect Verify or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. 55h, any time the device is ready to read array data. the system must write the reset command. device to reading array data.

Table 6. CFI Query Identification String Table 7. System Interface String

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Table 8. Device Geometry Definition

Table 9. Primary Vendor-Specific Extended Query Note:To reduce power consumption read Lower Byte only.

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Writing specific address and data commands or se- quences into the command register initiates device op- erations. Tables 10 and 11 define the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence may place the device in an unknown state. A reset command is then required to return the device to read- ing array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the erase-suspend-read mode, after which the system can read data from any non-erase-suspended sector. After completing a pro- gramming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return the device to the read (or erase-suspend-read) mode if DQ5 or DQ13 goes high during an active program or erase operation, or if the device is in the autoselect mode. See the next section, Reset Command , for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the device to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the device to the read mode. Once erasure begins, however, the device ig- nores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to the read mode. If the program command sequence is written while the device is in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. Once programming be- gins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If the de- vice entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns the device to the erase-suspend-read mode. If DQ5 or DQ13 goes high during a program or erase operation, writing the reset command returns the de- vice to the read mode (or erase-suspend-read mode if the device was in Erase Suspend). Note that if DQ1 or DQ9 goes high during a Write Buffer Programming operation, the system must write the Write-to-Buffer-Abort Reset command sequence to reset the device for the next operation. Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 11 shows the address and data requirements. This method is an alternative to that shown in Table 3, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect com- mand sequence may be written to an address that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the de- vice is actively programming or erasing. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the autoselect command. The device then enters the autoselect mode. The system may read at any address any number of times without initiating another autoselect command sequence: ■ A read cycle at address XX00h returns the manu- facturer code. ■ Three read cycles at addresses 01h, 0Eh, and 0Fh return the device code. ■ A read cycle to an address containing a sector ad- dress (SA), and the address 02h on A7–A0 in dou- bleword mode returns 0101h if the sector is protected, or 0000h if it is unprotected. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the de- vice was previously in Erase Suspend).

December 16, 2005 Am29LV2562M 35 DATASHEET Enter SecSi Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing an 8-doubleword/16-word random Elec- tronic Serial Number (ESN ). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector com- mand sequence. The Exit SecSi Sector command se- quence returns the device to normal operation. Tables 10 and 11 show the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Region” for further infor- mation. Note that the ACC function and unlock bypass modes are not available when the SecSi Sector is en- abled. Doubleword/Word Program Command Sequence Programming is a four-bus-cycle operation. The pro- gram command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program al- gorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Tables 10 and 11 show the address and data requirements for the word program command sequence. When the Embedded Program algorithm is complete, the device then returns to the read mode and ad- dresses are no longer latched. The system can deter- mine the status of the program operation by using DQ7 and DQ15 or DQ6 and DQ14. Refer to the Write Operation Status section for information on these sta- tus bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once the device has returned to the read mode, to ensure data integrity. Note that the SecSi Sector, autoselect, and CFI functions are unavailable when a program operation is in progress Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 and/or DQ13 = 1, or cause the DQ7 and/or DQ15, and DQ6 and/or DQ14 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram words to the device faster than using the stan- dard program command sequence. The unlock bypass command sequence is initiated by first writing two un- lock cycles. This is followed by a third write cycle con- taining the unlock bypass command, 2020h. The device then enters the unlock bypass mode. A two-cy- cle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass program command, A0A0h; the second cycle contains the pro- gram address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Tables 10 and 11 show the re- quirements for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the data 9090h. The second cycle must contain the data 00h. The device then returns to the read mode. Write Buffer Programming Write Buffer Programming allows the system write to a maximum of 16 doublewords/32 words in one pro- gramming operation. This results in faster effective programming time than the standard programming al- gorithms. The Write Buffer Programming command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the Write Buffer Load command written at the Sector Ad- dress in which programming will occur. The fourth cycle writes the sector address and the number of word locations, minus one, to be programmed. For ex- ample, if the system will program 6 unique address lo- cations, then 0505h should be written to the device. This tells the device how many write buffer addresses will be loaded with data an d therefore when to expect the Program Buffer to Flash command. The number of locations to program cannot exceed the size of the write buffer or the operation will abort. The fifth cycle writes the first address location and data to be programmed. The write-buffer-page is se- lected by address bits A23–A4. All subsequent ad- dress/data pairs must fall within the selected-write-buffer-page. The system then writes the remaining address/data pairs into the write buffer. Write buffer locations may be loaded in any order. The write-buffer-page address must be the same for all address/data pairs loaded into the write buffer. (This means Write Buffer Programming cannot be per- formed across multiple write-buffer pages. This also

36 Am29LV2562M December 16, 2005

means that Write Buffer Programming cannot be per- formed across multiple sectors. If the system attempts to load programming data outside of the selected write-buffer page, the operation will abort. Note that if a Write Buffer address location is loaded multiple times, the address/data pair counter will be decremented for every data load operation. The host system must therefore account for loading a write-buffer location more than once. The counter dec- rements for each data load operation, not for each unique write-buffer-address location. Note also that if an address location is loaded more than once into the buffer, the final data loaded for that address will be programmed. Once the specified number of write buffer locations have been loaded, the system must then write the Pro- gram Buffer to Flash command at the sector address. Any other address and data combination aborts the Write Buffer Programming operation. The device then begins programming. Data polling should be used while monitoring the last address location loaded into the write buffer. DQ7 and DQ15, DQ6 and DQ14, DQ5 and DQ13, and DQ1 and DQ9 should be monitored to determine the device status during Write Buffer Pro- gramming. The write-buffer programming operation can be sus- pended using the standard program suspend/resume commands. Upon successful completion of the Write Buffer Programming operation, the device is ready to execute the next command. The Write Buffer Programming Sequence can be aborted in the following ways: ■ Load a value that is greater than the page buffer size during the Number of Locations to Program step. ■ Write to an address in a sector different than the one specified during the Write-Buffer-Load com- mand. ■ Write an Address/Data pair to a different write-buffer-page than the one selected by the Starting Address during the write buffer data load- ing stage of the operation. ■ Write data other than the Confirm Command after the specified number of data load cycles. The abort condition is indicated by DQ1 and DQ9 = 1, DQ7 and DQ15 = DATA# (for the last address location loaded), DQ6 and DQ14 = toggle, and DQ5 and DQ13 =0. A Write-to-Buffer-Abort Reset command sequence must be written to reset the device for the next opera- tion. Note that the full 3-cycle Write-to-Buffer-Abort Reset command sequence is required when using Write-Buffer-Programming features in Unlock Bypass mode. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause the device to set DQ5 and/or DQ13= 1, or cause the DQ7 and/or DQ15 and DQ6 and/or DQ14 status bits to indicate the operation was successful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Accelerated Program The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated prog ramming, or device dam- age may result. WP# has an internal pullup; when un- connected, WP# is at V IH. Figure 5 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 16 for timing diagrams.

Figure 4. Write Buffer Programming Operation

1. When Sector Address is specified, any address in
2. DQ7 and DQ15 may change simultaneously with
3. If this flowchart location was reached because
4. See Tables 10 and 11 for command sequences

required for write buffer programming.

38 Am29LV2562M December 16, 2005

Figure 5. Program Operation Autoselect Command Sequence for more information. tion Status for more information. written after the device has resume programming.

Figure 6. Program Suspend/Program Resume chip erase command sequence. when an erase operation in is progress. and Figure 18 section for timing diagrams. ings during these operations. erase operation in is progress.

40 Am29LV2562M December 16, 2005

section for information on these status bits. reading array data, to ensure data integrity. and Figure 18 section for timing diagrams. suspends the erase operation. section for more information.

1. See Tables 10 and 11 for program command sequence.
2. See the section on DQ3 and DQ10 for information on

Figure 7. Erase Operation

Table 10. Command Definitions (x32 Mode, WORD# = V IH) RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A23–A15 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ31–DQ16 are don’t care in command sequences,
2. Unless otherwise noted, address bits A23–A11 are don’t cares.
3. No unlock or command cycles required when device is in read
4. The Reset command is required to return to the read mode (or to

goes high while the device is providing status information.

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence section for more information.

1. The device ID must be read in three cycles.
2. If WP# protects the highest address sector, the data is 9898h for

and 0808h for not factor locked.

1. The total number of cycles in the command sequence is
2. The data is 0000h for an unprotected sector and 0101h for a
3. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

1212 X0F 2222

42 Am29LV2562M December 16, 2005

Table 11. Command Definitions (x16 Mode, WORD# = V IL) RA = Read Address of the memory location to be read. RD = Read Data read from location RA during read operation. or CE# pulse, whichever happens later. WE# or CE# pulse, whichever happens first. erased. Address bits A23–A15 uniquely select any sector. WC = Word Count. Number of write buffer locations to load minus 1.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ31–DQ15 are don’t care in command sequences.
2. Unless otherwise noted, address bits A23–A11 are don’t cares.
3. No unlock or command cycles required when device is in read
4. The Reset command is required to return to the read mode (or to

DQ13goes high while the device is providing status information.

1. The fourth cycle of the autoselect command sequence is a read

Command Sequence section for more information.

1. The device ID must be read in three cycles.
2. If WP# protects the highest address sector, the data is 9898h for

and 0808h for not factor locked.

1. The total number of cycles in the command sequence is

maximum number of cycles in the command sequence is 37.

1. The data is 0000h for an unprotected sector group and 0101h for
2. Command sequence resets device for next command after

aborted write-to-buffer operation.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the device is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase
2. Command is valid when device is ready to read array data or when

device is in autoselect mode.

of the final WE# pulse in the command sequence. to read valid status information on DQ7 and DQ15. protected sector, the status may not be valid. DQ15–DQ0 will appear on successive read cycles. shows the Data# Polling timing diagram. Figure 7. Data# Polling Algorithm

1. VA = Valid address for programming. During a sector

valid address is any non-protected sector address.

1. DQ7 and DQ15 should be rechecked even if DQ5

change simultaneously with DQ5 and DQ13.

44 Am29LV2562M December 16, 2005

shows the outputs for RY/BY#. ation is complete, DQ6 and DQ14 stops toggling. for approximately 100 µs, then returns to reading array data. nores the selected sectors that are protected. DQ7 and DQ15: Data# Polling). bedded Program algorithm is complete. and DQ14. Figure 8 shows the toggle bit algorithm. Figure 8. Toggle Bit Algorithm

December 16, 2005 Am29LV2562M 45 DATASHEET DQ2 and DQ10: Toggle Bits II The “Toggle Bits II” on DQ2 and DQ10, when used with DQ6 and DQ14, indicate whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bits II are valid after the ris- ing edge of the final WE# pulse in the command se- quence. DQ2 and DQ10 toggle when the system reads at ad- dresses within those sectors that have been selected for erasure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 and DQ10 cannot distinguish whether the sector is actively erasing or is erase-suspended. DQ6 and DQ14, by comparison, in- dicate whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for erasure. Thus, both status bits are re- quired for sector and mode information. Refer to Table 12 to compare outputs for DQ2 and DQ10 and DQ6 and DQ14. Figure 8 shows the toggle bit algorithm in flowchart form, and the section “DQ2 and DQ10: Toggle Bits II” explains the algorithm. See also the RY/BY#: Ready/Busy# subsection. Figure 20 shows the toggle bit timing diagram. Figure 21 shows the differences between DQ2 and DQ10 and DQ6 and DQ14 in graphical form. Reading Toggle Bits DQ6 and DQ14/DQ2 and DQ10 Refer to Figure 8 for the following discussion. When- ever the system initially begins reading toggle bits sta- tus, it must read DQ15–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bits are not toggling, the de- vice has completed the program or erase operation. The system can read array data on DQ15–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that one of the toggle bits are still toggling, the system also should note whether the value of DQ5 and DQ13 is high (see the section on DQ5 and DQ13). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 and/or DQ13 went high. If the toggle bits are no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 and/or DQ13 has not gone high. The system may continue to monitor the toggle bits and DQ5 and DQ13 through successive read cycles, determining the status as de- scribed in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it returns to determine the status of the opera- tion (top of Figure 8). DQ5 and DQ13: Exceeded Timing Limits DQ5 indicates whether the program, erase, or write-to-buffer time has exceeded a specified internal pulse count limit. Under these conditions DQ5 and DQ13 produce a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 and/or DQ13 if the system tries to program a “1” to a location that was previously programmed to “0.” Only an erase opera- tion can change a “0” back to a “1.” Under this con- dition, the device halts the operation, and when the timing limit has been exceeded, DQ5 and/or DQ13 produces a “1.” In all these cases, the system must write the reset command to return the device to the reading the array (or to erase-suspend-read if the device was previously in the erase-suspend-program mode). DQ3 and DQ11: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 and DQ11 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase command. When the time-out period is com- plete, DQ3 and DQ11 switch from a “0” to a “1.” If the time between additional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3 and DQ11. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 and DQ15 (Data# Poll- ing) or DQ6 and DQ14 (Toggle Bits I) to ensure that the device has accepted the command sequence, and then read DQ3 and DQ11. If DQ3 and DQ11 are “1,” the Embedded Erase algorithm has begun; all further commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 and DQ11 are “0,” the device will accept additional sector erase com- mands. To ensure the command has been accepted, the system software should check the status of DQ3 and DQ11 prior to and following each subsequent sec- tor erase command. If DQ3 and DQ11 are high on the

46 Am29LV2562M December 16, 2005

Programming section for more details. Table 12. Write Operation Status

1. DQ5 and DQ13 switch to ‘1’ when an Embedded Program, Embedded Erase, or Write-to-Buffer operation has exceeded the

maximum timing limits. Refer to the section on DQ5 and DQ13 for more information.

1. DQ7 and DQ15 and DQ2 and DQ10 require a valid address when reading status information. Refer to the appropriate subsection
2. The Data# Polling algorithm should be used to monitor the last loaded write-buffer address location.
3. DQ1 and DQ9 switch to ‘1’ when the device has aborted the write-to-buffer operation.

48 Am29LV2562M December 16, 2005

Notes: 1. On the WP#/ACC pin only, the maximum input load current when WP# = VIL is ± 5.0 µA. 2. The I CC current listed is typically less than 4 mA/MHz, with OE# at VIH. 3. Maximum I CC specifications are tested with VCC = VCCmax. 4. I CC active while Embedded Erase or Embedded Program is in progress. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. 6. If V IO < VCC, maximum VIL for CE# and DQ I/Os is 0.3 VIO. Maximum VIH for these connections is VIO + 0.3 V 7. V CC voltage requirements. 8. V IO voltage requirements. 9. Not 100% tested Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ILI Input Load Current (1) VIN = VSS to VCC, VCC = VCC max ±2.0 µA ILIT A9, ACC Input Load Current V CC = VCC max; A9 = 12.5 V 70 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±2.0 µA ILR Reset Leakage Current V CC = VCC max; RESET# = 12.5 V 35 µA ICC1 VCC Active Read Current (2, 3) CE# = V IL, OE# = VIH,

1 MHz 6 68

5 MHz 26 86

1 MHz 8 100 mA

ICC2 VCC Initial Page Read Current (2, 3) CE# = V IL, OE# = VIH

10 MHz 80 160 mA

10 MHz 6 40 mA

ICC3 VCC Intra-Page Read Current (2, 3) CE# = V IL, OE# = VIH 33 MHz 12 80 mA ICC4 VCC Active Write Current (3, 4) CE# = V IL, OE# = VIH 100 120 mA ICC5 VCC Standby Current (3) CE#, RESET# = V CC ± 0.3 V, WP# = VIH 21 0 µ A ICC6 VCC Reset Current (3) RESET# = V SS ± 0.3 V, WP# = VIH 21 0 µ A ICC7 Automatic Sleep Mode (3, 5) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V, WP# = VIH 21 0 µ A VIL1 Input Low Voltage 1(6, 7) –0.5 0.8 V VIH1 Input High Voltage 1 (6, 7) 1.9 V CC + 0.5 V VIL2 Input Low Voltage 2 (6, 8) –0.5 0.3 x V IO V VIH2 Input High Voltage 2 (6, 8) 1.9 V IO + 0.5 V VHH Voltage for ACC Program Acceleration V CC = 2.7 –3.6 V 11.5 12.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 2.7 –3.6 V 11.5 12.5 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min = VIO 0.85 VIO V VOH2 IOH = –100 µA, VCC = VCC min = VIO VIO–0.4 V VLKO Low VCC Lock-Out Voltage (9) 2.3 2.5 V

50 Am29LV2562M December 16, 2005

1. See Figure 11 and Table 13 for test specifications.
2. AC specifications listed are tested with V

IO = VCC. Contact AMD for information on AC operation when VIO ≠ VCC.

0 VRY/BY#

Figure 13. Read Operation Timings

• Figure shows doubleword mode. Addresses are A1–A-1 for word mode.

Figure 14. Page Read Timings

52 Am29LV2562M December 16, 2005

1. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO ≠ VCC

Description All Speed Options UnitJEDEC Std. Figure 15. Reset Timings

December 16, 2005 Am29LV2562M 53 DATASHEET AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 doublewords/1–32 words programmed. 4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 5. AC specifications listed are tested with V IO = VCC. Contact AMD for information on AC operation when VIO ≠ VCC Parameter 120RJEDEC Std. Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 ns tWHDL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 7.5 µs Per Doubleword Typ 15 µs Accelerated Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 6.25 µs Per Doubleword Typ 12.5 µs Single Doubleword/Word Program Operation (Note 2) Word Typ 60 µs Doubleword Typ 60 µs Accelerated Single Doubleword/Word Programming Operation (Note 2) Word Typ 54 µs Doubleword Typ 54 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec tVHH VHH Rise and Fall Time (Note 1) Min 250 ns tVCS VCC Setup Time (Note 1) Min 50 µs

54 Am29LV2562M December 16, 2005

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 16. Program Operation Timings Figure 17. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. These waveforms are for the doubleword mode.

Figure 18. Chip/Sector Erase Operation Timings

56 Am29LV2562M December 16, 2005

Figure 19. Data# Polling Timings (During Embedded Algorithms)

58 Am29LV2562M December 16, 2005

1. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO ≠ VCC

Figure 22. Temporary Sector Group Unprotect Timing Diagram

• For sector group protect, A6 = 0, A1 = 1, A0 = 0. For sector group unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 23. Sector Group Protect and Unprotect Timing Diagram

60 Am29LV2562M December 16, 2005

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. 3. For 1–16 doublewords/1–32 words programmed. 4. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 5. AC specifications listed are tested with VIO = VCC. Contact AMD for information on AC operation when VIO ≠ VCC. Parameter 120RJEDEC Std. Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 ns tDVEH tDS Data Setup Time Min 45 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Write Buffer Program Operation (Notes 2, 3) Typ 240 µs Effective Write Buffer Program Operation (Notes 2, 4) Per Word Typ 7.5 µs Per Doubleword Typ 15 µs Effective Accelerated Write Buffer Program Operation (Notes 2, 4) Per Word Typ 6.25 µs Per Doubleword Typ 12.5 µs Program Operation (Note 2) Word Typ 60 µs Doubleword Typ 60 µs Accelerated Programming Operation (Note 2) Word Typ 54 µs Doubleword Typ 54 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.5 sec

Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

1. Figure indicates last two bus cycl es of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# and DQ15# are the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 24. Alternate CE# Cont rolled Write (Erase/Program)

62 Am29LV2562M December 16, 2005

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V CC, 10,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles. 3. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation. 4. For 1–16 doublewords or 1-32 words programmed in a single write buffer programming operation. 5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure. 6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables 10 and 11 for further information on command definitions. TSOP PIN AND BGA PACKAGE CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.5 3.5 sec Excludes 00h programming prior to erasure (Note 5)Chip Erase Time 256 512 sec Single Doubleword/Word Program Time (Note 3) Word 60 600 µs Excludes system level overhead (Note 6) Doubleword 60 600 µs Accelerated Single Doubleword/ Word Program Time Word 54 540 µs Doubleword 54 540 µs Total Write Buffer Program Time (Note 4) 240 1200 µs Effective Write Buffer Program Time (Note 3) Per Word 7.5 38 µs Per Doubleword 15 75 µs Total Accelerated Write Buffer Program Time (Note 4) 200 1040 µs Effective Write Buffer Accelerated Program Time (Note 3) Per Word 6.25 33 µs Per Doubleword 12.5 65 µs Chip Program Time 252 584 sec Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 BGA TBD TBD pF COUT Output Capacitance V OUT = 0 BGA TBD TBD pF CIN2 Control Pin Capacitance V IN = 0 BGA TBD TBD pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

December 16, 2005 Am29LV2562M 63 DATASHEET PHYSICAL DIMENSIONS LSC080–80-Ball Fortified Ball Grid Array 18 x 12 mm Package 3266 \\ 16-038.15a PACKAGE LSC 080 JEDEC N/A D x E 18.00 mm x 12.00 mm PACKAGE SYMBOL MIN NOM MAX NOTE A --- --- 1.60 PROFILE A1 0.40 --- --- BALL HEIGHT A2 1.00 --- 1.11 BODY THICKNESS D 18.00 BSC. BODY SIZE E 12.00 BSC. BODY SIZE D1 9.00 BSC. MATRIX FOOTPRINT E1 7.00 BSC. MATRIX FOOTPRINT MD 10 MATRIX SIZE D DIRECTION ME 8 MATRIX SIZE E DIRECTION n 80 BALL COUNT φb 0.50 0.60 0.70 BALL DIAMETER eE 1.00 BSC. BALL PITCH eD 1.00 BSC BALL PITCH SD / SE 0.50 BSC. SOLDER BALL PLACEMENT DEPOPULATED SOLDER BALLS NOTES: 1. DIMENSIONING AND TOLERANCING METHODS PER ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. BALL POSITION DESIGNATION PER JESD 95-1, SPP-010. 4. e REPRESENTS THE SOLDER BALL GRID PITCH. 5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION. SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION. n IS THE NUMBER OF POPULTED SOLDER BALL POSITIONS FOR MATRIX SIZE MD X ME.

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

DIAMETER IN A PLANE PARALLEL TO DATUM C.

7 SD AND SE ARE MEASURED WITH RESPECT TO DATUMS A

AND B AND DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW. WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW SD OR SE = 0.000. WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW, SD OR SE = e/2 8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED BALLS. 9. N/A

10 A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK

MARK, METALLIZED MARK INDENTATION OR OTHER MEANS. KJ 80X eD CORNER C0.20 (2X) (2X) C0.20 7SE B A D1 ABDCEFHG eE SD BOTTOM VIEW b 0.25 C C

0.25 M C

0.10 PIN A17 D E C TOP VIEW SIDE VIEW A 0.20 INDEX MARK CORNER PIN A1

64 Am29LV2562M December 16, 2005

Revision A (November 19, 2002) Initial release. Revision A+1 (January 22, 2003) Distinctive Characteristics Corrected the access and page read times. Global Added Sector Group Protection throughout datasheet and added Table 4. Product Selector Guide Added VIOs to table and removed Note #2. Added reg- ulated speed option. Connection Diagrams In the BGA package D8 is A23 and A1 is RFU. Corrected typos in VIO ranges. Removed Note. Added LSC080 package. SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Command Sequence Noted that the SecSi Sector, autoselect, and CFI func- tions are unavailable when a program or erase opera- tion is in progress. Common Flash Memory Interface (CFI) Changed wording in last sentence of third paragraph data.” Changed CFI website address. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. DC Characteristics Changed V IH1 and V IH2 minimum to 1.9. Removed typos in notes. Removed V IL, VIH, VOL, and VOH from table and added V IL1, VIH1, VIL2, VIH2, VOL, VOH1, and VOH2 from the CMOS table in the Am29LV640MH/L datasheet. Operating Ranges Added VCC voltage range. AC Characteristics Read-only Operations: Added note #3. Hardware Reset, Erase and Program Operations, Temporary Sector Unprotect, and Alternate CE# Controlled Erase and Program Operations Added Note. Revision A+2 (February 3, 2003) Corrected OPNs. Revision B (September 17, 2003) Global Changed data sheet status from Advance Information to Preliminary. Distinctive Characteristics Changed description of device erase cycle endurance. Changed typical sector erase time, typical write buffer programming time, and typical active read current specification. Connection Diagrams Corrected signal name for ball D8. Erase Suspend/Erase Resume Commands Deleted reference to erase-suspended sector address requirement for commands. Tables 10 and 11, Command Definitions Corrected addresses for Erase Suspend and Erase Resume to “XXX” (don’t care). DC Characteristics Changed typical and maximum values for I CC1, ICC2, and ICC3. Values for different frequencies were added to ICC2 and ICC3. AC Characteristics Erase and Program Operations table; Alternate CE# Controlled Erase and Program Operations table. Changed values for the following parameters: Write Buffer Program Operation, Effective Write Buffer Pro- gram Operation, Accelerated Effective Write Buffer Program Operation, Sector Erase Operation, Single Doubleword/Word Program Operation, Accelerated Single Doubleword/Word Program Operation (the phrase “Single Doubleword/Word” was added to the last two parameter titles).

December 16, 2005 Am29LV2562M 65 DATASHEET Erase and Programming Performance Changed typical and maximum sector erase time. Changed typical values and entered maximum values for chip erase time and added maximum erase time. Replaced TBDs for all typical and maximum specifica- tions with actual values. Added phrase “Single Double- word/Word” to Program Time and Accelerated Program Time parameters titles. Added Total Write Buffer Program Time and Total Accelerated Write Buffer Program Time parameters to table. Changed device endurance in Note 1 to 10,000 cycles. Changed write buffer operation size in Note 3. Note 4 now refers to write buffer programming instead of chip programming. Deleted Note 7. Revision B+1 (October 9, 2003) Connection Diagrams Reverted entire pinout to that shown in Revision A+2. Table 1, Device Bus Operations Corrected requirement for ACC column from “X” to “L/H”. Revision B+2 (December 16, 2005) This product has been retired and is not available for designs. For new and current designs, S29GL512N supersedes Am29LV2562M and is the factory-recom- mended migration path. Please refer to the S29GL512N Data Sheet for specifications and order- ing information. Availability of this document is re- tained for reference and historical purposes only. Trademarks Copyright © 2002–2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies .