L200BB12VD

AM29LV200B_06 AMD | Alldatasheet

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Technical content

The Am29LV200B is not offered for new designs. Please contact a Spansion representative for alter- nates. The following document contains information on Spansion memory products. Although the document is marked with the name of the company that orig inally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appro and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29LV200B Data Sheet Publication Number 21521 Revision D Amendment 6 Issue Date October 10, 2006

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This Data Sheet states AMD’s current technical specifications regarding the Products described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21521 Rev: D Amendment: 6 Issue Date: October 10, 2006 Am29LV200B

2 Megabit (256 K x 8-Bit/128 K x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 2.7 to 3.6 volt read and write operations for battery-powered applications ■ Manufactured on 0.32 µm process technology — Compatible with 0.5 µm Am29LV200 device ■ High performance — Full voltage range: access times as fast as 70 ns — Regulated voltage range: access times as fast as 55 ns ■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 7 mA read current — 15 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and three 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and three 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1 million erase cycle guarantee per sector ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ Package option — 48-pin TSOP — 44-pin SO — 48-ball FBGA ■ Compatibility with JEDEC standards — Pinout and software compatible with single- power supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data The Am29L V200B is not offered for new designs. Please contact a Spansion representative for alternates.

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The Am29LV200B is a 2 Mbit, 3.0 volt-only Flash memory organized as 262,144 bytes or 131,072 words. The device is offered in 44-pin SO, 48-pin TSOP , and 48- ball FBGA packages. The word-wide data (x16) appears on DQ15-DQ0; the byte-wide (x8) data appears on DQ7-DQ0. This device is designed to be programmed in-system using only a single 3.0 volt V CC supply. No VPP is required for write or erase operations. The device can also be programmed in standard EPROM programmers. This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and ben efits of the Am29LV200, which was manufactured using 0.5 µm process technology. In addition, the Am29LV200B features unlock bypass programming and in-system sector protection/unprotection. The standard device offers access times of 55, 70, 90 and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Com mands are written to the command register using standard microprocessor write timings. Register con - tents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili - tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase command sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera - tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of memory. This can be achi eved in-system or via pro gramming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A sys tem reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

4 Am29LV200B 21521D6 October 10, 2006

Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29LV200B Speed Options Regulated Voltage Range: VCC = 3.0–3.6 V 55R Full Voltage Range: VCC = 2.7–3.6 V 70 90 120 Max access time, ns (tACC) 55 70 90 120 Max CE# access time, ns (tCE) 55 70 90 120 Max OE# access time, ns (tOE) 30 30 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A16

October 10, 2006 21521D6 Am29LV200B 5 DATA SHEET CONNECTION DIAGRAMS A15 NC A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# NC A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 Standard TSOP

6 Am29LV200B 21521D6 October 10, 2006

Special Handling Instructions Special handling is required for Flash Memory products in molded packages (TSOP , BGA, SSOP , PLCC, PDIP). The package and/or data integrity may be com promised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. NC RY/BY# NC CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCNCNCRY/BY# DQ9 DQ1DQ8DQ0A5A6NCA7 OE# V SSCE#A0A1A2A4A3 SO 48-ball FBGA Top View, Balls Facing Down

October 10, 2006 21521D6 Am29LV200B 7 DATA SHEET PIN CONFIGURATION A0–A16 = 17 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device ground NC = Pin not connected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A16 CE# OE# WE# RESET# BYTE# RY/BY#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi - nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup - ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV200B T -55R E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-free package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-free package E = Extended (–55 °C to +125°C) K = Extended (–55 °C to +125°C) with Pb-free package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) S = 44-Pin Small Outline Package (SO 044) WA = 48-ball Fine-pitch Ball Grid Array (FBGA), 0.80 mm ball pitch, 6 x 8 mm package (FBA048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29LV200B

2 Megabit (256 K x 8-Bit/128 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

AM29LV200BT -55R, AM29LV200BB-55R EC, EI, SC, SI ED, EF , SD, SFAM29LV200BT -70, AM29LV200BB-70 AM29LV200BT -90, AM29LV200BB-90 EC, EI, EE, ED, EF , EK SC, SI, SE, SD, SF , SKAM29LV200BT -120, AM29LV200BB-120 Valid Combinations for FBGA Packages Order Number Package Marking AM29LV200BT55R, AM29LV200BB55R WAC, WAI, WAD, WAF L200BT55R, L200BB55R C, I, D, F AM29LV200BT70, AM29LV200BB70 WAC, WAI, WAE, WAD, WAF, WAK L200BT70V, L200BB70V C, I, E, D, F, K AM29LV200BT90, AM29LV200BB90 L200BT90V, L200BB90V AM29LV200BT120, AM29LV200BB120 L200BT12V, L200BB12V

describe each of these operations in further detail. Table 1. Am29LV200B Device Bus Operations

1. Addresses are A16:A0 in word mode (BYTE# = V IH), A16:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. used as an input for the LSB (A-1) address function. register contents are altered. specification for reading array data.

0.3 V X X VCC ±

0.3 V X High-Z High-Z High-Z

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sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are required to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Am29LV200B Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command sequence, the device enters the autoselect mode. The system can then read autoselect codes from the internal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose lect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the active current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to “AC Characteris tics” for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program - ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Char- acteristics table represents the automatic sleep mode current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the RESET# pin is driven low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write com- mands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be rein itiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within V SS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir - cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory.

parameters and to Figure 14 for the timing diagram. Table 2. Am29LV200BT Top Boot Block Sector Address Table Table 3. Am29LV200BB Bottom Boot Block Sector Address Table through the command register. Table 4. In addition, when verifying sector protection, 4 shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. Definitions” for details on using the autoselect mode.

12 Am29LV200B 21521D6 October 10, 2006

Table 4. Am29LV200B Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. ID on address pin A9 and OE#. an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD representative for details. or unprotected. See “Autoselect Mode” for details.

Figure 1. In-System Sector Protect/Unprotect Algorithms

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Figure 2. Temporary Sector Unprotect Operation tional writes when VCC is greater than VLKO. WE# do not initiate a write cycle. reset to reading array data on power-up.

1. All protected sectors unprotected.
2. All previously protected sectors are protected once

October 10, 2006 21521D6 Am29LV200B 15 DATA SHEET COMMAND DEFINITIONS Writing specific address and data commands or sequences into the command register initiates device operations. Table 5 defines the valid register command sequences. Writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more infor mation on this mode. The system must issue the reset command to re- enable the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame ters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the sequence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to reading array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is protected. Table 5 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM programmers and requires V ID on address bit A9. The autoselect command sequence is initiated by writing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufacturer code. A read cycle at address XX01h in word mode (or 02h in byte mode) returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program - ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or tim ings. The device automatically generates the program pulses and verifies the programmed cell margin. Table 5 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. The system can determine the status of the program operation by using

16 Am29LV200B 21521D6 October 10, 2006

for information on these status bits. reset to reading array data, to ensure data integrity. returns to reading array data. Note: See Table 5 for program command sequence. Figure 3. Program Operation

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1. See Table 5 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

Table 5. Am29LV200B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A16–A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all bus cycles
4. Data bits DQ15–DQ8 are don’t cares for unlock and
5. Address bits A16–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

1. No unlock or command cycles required when reading array
2. The Reset command is required to return to reading array

high (while the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a
2. The data is 00h for an unprotected sector and 01h for a
3. The Unlock Bypass command is required prior to the Unlock
4. The Unlock Bypass Reset command is required to return to
5. The system may read and program in non-erasing sectors, or
6. The Erase Resume command is valid only during the Erase

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progress. These three bits are discussed first. Suspend mode, Data# Polling produces a “1” on DQ7. the selected sectors that are protected. “AC Characteristics” section illustrates this. Table 6 shows the outputs for Data# Polling on DQ7. Figure 5 shows the Data# Polling algorithm.

1. VA = Valid address for programming. During a sector

address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5. Figure 5. Data# Polling Algorithm

22 Am29LV200B 21521D6 October 10, 2006

determine the status of the operation (top of Figure 6). be less than 50 µs, the system need not monitor DQ3. accepted the command sequence, and then read DQ3. pend) are ignored until the erase operation is complete. accepted. Table 6 shows the outputs for DQ3.

1. Read toggle bit twice to determine whether or not it is
2. Recheck toggle bit because it may stop toggling as DQ5

Figure 6. Toggle Bit Algorithm

Table 6. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

24 Am29LV200B 21521D6 October 10, 2006

1. Minimum DC voltage on input or I/O pins is –0.5 V. During

up to 20 ns. See Figure 7 and Figure 8.

1. Minimum DC input voltage on pins A9, OE#, and RESET#
2. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. functionality of the device is guaranteed. Figure 7. Maximum Negative Figure 8. Maximum Positive

October 10, 2006 21521D6 Am29LV200B 25 DATA SHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. 5. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 7 12

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode (Notes 2, 3, and 5) CE# = VIL, OE# = VIH 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = VCC±0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

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Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical ICC1 vs. Frequency

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Notes: 1. Not 100% tested. 2. See Figure 11 and Table 7 for test specifications. Parameter

Description

JEDEC Std Test Setup -55R -70 -90 -120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 55 70 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 15 25 30 30 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 15 25 30 30 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH Figure 13. Read Operations Timings

Figure 14. RESET# Timings

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Figure 15. BYTE# Timings for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations

October 10, 2006 21521D6 Am29LV200B 31 DATA SHEET AC CHARACTERISTICS Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -55R -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns tWLAX tAH Address Hold Time Min 45 45 45 50 ns tDVWH tDS Data Setup Time Min 20 35 45 50 ns tWLWH tWP Write Pulse Width Min 30 35 35 50 ns tAVWL tAS Address Setup Time Min 0 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWHWL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

32 Am29LV200B 21521D6 October 10, 2006

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

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Figure 19. Data# Polling Timings (During Embedded Algorithms) cycle, and array data read cycle. Figure 20. Toggle Bit Timings (During Embedded Algorithms)

36 Am29LV200B 21521D6 October 10, 2006

Figure 23. Sector Protect/Unprotect Timing Diagram

October 10, 2006 21521D6 Am29LV200B 37 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -55R -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns tELAX tAH Address Hold Time Min 45 45 45 50 ns tDVEH tDS Data Setup Time Min 35 35 45 50 ns tELEH tCP CE# Pulse Width Min 35 35 35 50 ns tAVEL tAS Address Setup Time Min 0 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

38 Am29LV200B 21521D6 October 10, 2006

1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the device.
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

October 10, 2006 21521D6 Am29LV200B 39 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 2.7 V (3.0 V for regulated speed options), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 5 s Byte Programming Time 9 300 µs Excludes system level overhead (Note 5) Word Programming Time 11 360 µs Chip Programming Time (Note 3) Byte Mode 2.3 6.9 s Word Mode 1.5 4.5 s Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Ye a r s 125°C 20 Ye a r s

40 Am29LV200B 21521D6 October 10, 2006

PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

October 10, 2006 21521D6 Am29LV200B 41 DATA SHEET PHYSICAL DIMENSIONS SO 044—44-Pin Smal l Outline Package Dwg rev AC; 10/99

42 Am29LV200B 21521D6 October 10, 2006

FBA048—48-Ball Fine-Pitch Ball Grid Array, 0.80 mm pitch, 6 x 8 mm package Dwg rev AF; 10/99

October 10, 2006 21521D6 Am29LV200B 43 DATA SHEET REVISION SUMMARY Revision A (January 1998) Initial release. Revision B (July 1998) Global Expanded data sheet from Advanced Information to Preliminary version. Distinctive Characteristics Changed “Manufactured on 0.35 µm process technology” to “Manufactured on 0.32 µm process technology”. General Description Second paragraph: Changed “This device is manufac- tured using AMD’s 0.35 µm process technology” to “This device is manufactured using AMD’s 0.32 µm process technology”. Revision C (January 1999) Global Deleted the 80 ns speed option. Added the -50R and -55R speed options. Distinctive Characteristics Added 20-year data retention subbullet. Connection Diagrams Reverse TSOP: Moved the circle marking to upper right corner from the upper left corner, added an upside down triangle marking to the upper left corner. Package Type: Added “S = 44-Pin Small Outline Package (SO 044)”. DC Characteristics— CMOS Compatible ICC1, ICC2, ICC3, ICC4: Added Note “Maximum ICC spec- ifications are tested with VCC = VCCmax. AC Characteristics—Alternate CE# Controlled Erase/Program Operations Corrected speed options. Erase and Programming Performance Chip Erase Time : Changed Typical value to 5 s from 7 s. Chip Programming Time: Changed Max value for Byte Mode to 6.9 s from 6.8 s. Changed Max value for Word Mode to 4.5 s from 4.3 s. Note 2: Added “(3.0 V for regulated speed options)”. Revision C+1 (March 27, 1999) Corrected the example part number to include the “R” after “-50.” Operating Ranges The VCC supply voltage for regulated devices is 3.0– 3.6 V. The V CC supply voltage for full voltage range devices is 2.7–3.6 V. Revision C+2 (May 17, 1999) Boot Code Sector Architecture : Added “B = Bottom Sector”. Revision C+3 (June 1, 1999) Physical Dimensions TS 048: The drawing previously showed the TSR 048 package; now shows the proper package. Revision C+4 (July 2, 1999) Global Deleted references to the 50R speed option. Revision C+5 (August 25, 1999) Valid Combinations: Restored package options for Am29LV200BT -70 and Am29LV200BB-70. Revision D (November 18, 1999) AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision D+1 (November 13, 2000) Global Added table of contents. Deleted burn-in option from Ordering Information section. Revision D+2 (April 12, 2002) Global Added FBA048 package. Revision D+3 (June 11, 2004) Added Pb-free packages. Revision D+4 (September 20, 2005) Corrected Valid Combinations table. Revision D+5 (January 4, 2006) Removed TSR048 48-pin Reverse TSOP option.

44 Am29LV200B 21521D6 October 10, 2006

Revision D6 (October 10, 2006) Global Added notice on product availability to cover sheet and first page of data sheet. Erase and Program Operations table Changed t BUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable ( i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 1998-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.