L160DB120VC

AM29LV160D_06 AMD | Alldatasheet

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Publication Number 22358 Revision B Amendment 7 Issue Date May 5, 2006 Am29LV160D Data Sheet RETIRED PRODUCT This product has been retired and is not recomme nded for designs. For new and current designs, S29AL016D supersedes Am29LV160D and is the fa ctory-recommended migration path for this device. Please refer to the S29AL016D data sheet for specifications and ordering information. Avail- ability of this document is retained for reference and historical purposes only. The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 22358 Rev: B Amendment: 7 Issue Date: May 5, 2006 Am29LV160D

16 Megabit (2 M x 8-Bit/1 M x 16-Bit)

CMOS 3.0 Volt-only Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications — Regulated voltage range: 3.0 to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors ■ Manufactured on 0.23 µm process technology — Fully compatible with 0.32 µm Am29LV160B device ■ High performance — Access times as fast as 70 ns ■ Ultra low power consumption (typical values at

5 MHz)

— 200 nA Automatic Sleep mode current — 200 nA standby mode current — 9 mA read current — 20 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: — A hardware method of locking a sector to prevent any program or erase operations within that sector — Sectors can be locked in-system or via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1,000,000 write cycle guarantee per sector ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ Package option — 48-ball FBGA — 48-pin TSOP — 44-pin SO ■ CFI (Common Flash Interface) compliant — Provides device-specific information to the system, allowing host software to easily reconfigure for different Flash devices ■ Compatibility with JEDEC standards — Pinout and software compatible with single- power supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion (not available on 44-pin SO) ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data This product has been retired and is not recommended for designs. For new and current designs, S29AL016D supersedes Am29L V160D and is the factory-recommended migration path for this device. Please refer to the S29AL016D data sheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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The Am29LV160D is a 16 Mbit, 3.0 Volt-only Flash memory organized as 2,097,152 bytes or 1,048,576 words. The device is offered in 48-ball FBGA, 44-pin SO, and 48-pin TSOP packages. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the standard system 3.0 volt V CC supply. A 12.0 V V PP or 5.0 V CC are not re - quired for write or erase operations. The device can also be programmed in standard EPROM programmers. The device offers access times of 70, 90, and 120 ns, allowing high speed microprocessors to operate with out wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. The Am29LV160D is entirely command set compatible with the JEDEC single-power-supply Flash stan dard. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili - tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com - mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits . After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sec - tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera - tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem - ory. This can be achieved in-system or via programming equipment. The Erase Suspend/Erase Resume feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system micropro cessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re duced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunnel ing. The data is programmed using hot electron injection.

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Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29LV160D Speed Option Voltage Range: VCC = 2.7–3.6 V -70 -90 -120 Max access time, ns (tACC) 70 90 120 Max CE# access time, ns (tCE) 70 90 120 Max OE# access time, ns (tOE) 30 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A19

22358B7 May 5, 2006 Am29LV160D 5 DATA SHEET CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A19 NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 A15 A18 A14 A13 A12 A11 A10 A19 NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 Reverse TSOP Standard TSOP

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Special Handling Instructions Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. RESET# A18 A17 CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 WE# A19 A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC SO A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2NCA18NCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 FBGA Top View, Balls Facing Down

22358B7 May 5, 2006 Am29LV160D 7 DATA SHEET PIN CONFIGURATION A0–A19 =20 addresses DQ0–DQ14 =15 data inputs/outputs DQ15/A-1 =DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# =Selects 8-bit or 16-bit mode CE# =Chip enable OE# = Output enable WE# =Write enable RESET# =Hardware reset pin RY/BY# = Ready/Busy output (N/A SO 044) VCC =3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS =Device ground NC =Pin not connected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A19 CE# OE# WE# RESET# BYTE# RY/BY# (N/A SO 044)

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi - nation) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup - ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29LV160D T -70 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-Free Package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-Free Package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) F = 48-Pin Thin Small Outline Package (TSOP) Reverse Pinout (TSR048) S = 44-Pin Small Outline Package (SO 044) WC = 48-ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 9 mm package (FBC048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29LV160D

16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations For TSOP and SO Packages Am29LV160DT -70, Am29LV160DB-70 EC, EI, ED, EF FC, FI SC, SI, SD, SF Am29LV160DT -90, Am29LV160DB-90 Am29LV160DT -120, Am29LV160DB-120 Valid Combinations for FBGA Packages Order Number Package Marking Am29LV160DT -70, Am29LV160DB-70 WCC, WCI, WCD, WCF L160DT70V, L160DB70V C, I, D, F Am29LV160DT -90, Am29LV160DB-90 L160DT90V, L160DB90V Am29LV160DT -120, Am29LV160DB-120 L160DT12V, L160DB12V

each of these operations in further detail. Table 1. Am29LV160D Device Bus Operations

1. Addresses are A19:A0 in word mode (BYTE# = V IH), A19:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. used as an input for the LSB (A-1) address function. device outputs array data in words or bytes. memory content occurs during the power transition. command register contents are altered. rent specification for reading array data.

0.3 V X X VCC ±

0.3 V X High-Z High-Z High-Z

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sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once the device enters the Unlock Bypass mode, only two write cycles are re - quired to program a word or byte, instead of four. The “Word/Byte Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. A “sector address” consists of the address bits required to uniquely select a sector. The “Command Definitions” section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. After the system writes the autoselect command se - quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Au- toselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Op- eration Status” for more information, and to “AC Characteristics” for timing diagrams. Standby Mode When the system is not reading or writing to the de - vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at V IH, but not within V CC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The de - vice requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program - ming, the device draws active current until the operation is completed. In the DC Characteristics table, I CC3 and ICC4 repre- sents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device energy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.

22358B7 May 5, 2006 Am29LV160D 11 DATA SHEET RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of re - setting the device to reading array data. When the system drives the RESET# pin to V IL for at least a pe- riod of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the de vice is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V SS±0.3 V, the device draws CMOS standby current (I CC4 ). If RESET# is held at V IL but not within V SS±0.3 V, the standby cur - rent will be greater. The RESET# pin may be tied to the system reset cir - cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase op - eration, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monito r RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embed - ded Algorithms). The system can read data t RH after the RESET# pin returns to V IH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high im - pedance state.

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Table 2. Sector Address Tables (Am29LV160DT) Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See “Word/Byte Configuration” section.

Table 3. Sector Address Tables (Am29LV160DB) Note: Address range is A19:A-1 in byte mode and A19:A0 in word mode. See the “Word/Byte Configuration” section.

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accessed in-system through the command register. Table 4. In addition, when verifying sector protection, corresponding identifier code on DQ7-DQ0. Table 9. This method details on using the autoselect mode. Table 4. Am29LV160D Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. Note: The autoselect codes may also be accessed in-system via command sequences. See Table 9. The device is shipped with all sectors unprotected. AMD representative for details. ID on address pin A9 and OE#.

ure 22 shows the timing diagrams, for this feature. Figure 1. Temporary Sector Unprotect Operation

1. All protected se ctors unprotected.
2. All previously protected sectors are protected once

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Figure 2. In-System Sector Protect/Unprotect Algorithms

interfaces for long-term compatibility. data, the system must write the reset command. device to the autoselect mode. representative for copies of these documents. Table 5. CFI Query Identification String

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Table 6. System Interface String Table 7. Device Geometry Definition

and power-down transitions, or from system noise. unintentional writes when VCC is greater than VLKO. or WE# do not initiate a write cycle. cally reset to reading array data on power-up. Table 8. Primary Vendor-Specific Extended Query

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Writing specific address and data commands or se - quences into the command register initiates device operations. Table 9 defines the valid register command sequences. Writing incorrect address and data val - ues or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em bedded Erase algorithm. After the device accepts an Erase Suspend com - mand, the device enters the Erase Suspend mode. The system can read array data using the standard read timings, except that if it reads at an address within erase-suspended sectors, the device outputs status data. After completing a programming opera tion in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Suspend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-en - able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Command” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more informa- tion. The Read Operations table provides the read parameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command to the device resets the device to reading array data. Address bits are don’t care for this command. The reset command may be written between the se - quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig nores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in a program command sequence before programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read ing array data (also applies during Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not a sector is pro tected. Table 9 shows the address and data requirements. This method is an alternative to that shown in Table 4, which is intended for PROM pro - grammers and requires VID on address bit A9. The autoselect command sequence is initiated by writ- ing two unlock cycles, followed by the autoselect command. The device then enters the autoselect mode, and the system may read at any address any number of times, without initiating another command sequence. A read cycle at address XX00h retrieves the manufac- turer code. A read cycle at address XX01h returns the device code. A read cycle containing a sector address (SA) and the address 02h in word mode (or 04h in byte mode) returns 01h if that sector is protected, or 00h if it is unprotected. Refer to Tables 2 and 3 for valid sector addresses. The system must write the reset command to exit the autoselect mode and return to reading array data. Word/Byte Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com mand. The program address and data are written next, which in turn initiate the Embedded Program al gorithm. The system is not required to provide further controls or timings. The device automatically gener - ates the program pulses and verifies the programmed cell margin. Table 9 shows the address and data re - quirements for the byte program command sequence. When the Embedded Program algorithm is complete, the device then returns to reading array data and ad dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. See “Write Operation Status” for information on these status bits.

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Figure 4 illustrates the algorithm for the erase opera - tion. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to Figure 18 for timing diagrams. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two unlock cycles, followed by a set-up command. Two ad ditional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. Table 9 shows the address and data requirements for the sector erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase al - gorithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase com mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec tors may be from one sector to all sectors. The time between these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recom mended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between addi tional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the de vice to reading array data. The system must rewrite the command sequence and any additional sector ad - dresses and commands. The system can monitor DQ3 to determine if the sec - tor erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other com mands are ignored. Note that a hardware reset during the sector erase operation immediately termi - nates the operation. The Sector Erase command sequence should be reinitiated once the device has re turned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. (Refer to “Write Operation Status” for information on these status bits.) Figure 4 illustrates the algorithm for the erase opera - tion. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to Figure 18 for timing diagrams. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Ad dresses are “don’t-cares” when writing the Erase Suspend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maxi mum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is writ ten during the sector erase time-out, the device immediately terminates the time-out period and sus pends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sec tors produces status data on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is com - plete, the system can once again read array data within non-suspended sectors. The system can deter mine the status of the program operation using the DQ7 or DQ6 status bits, just as in the standard pro gram operation. See “Write Operation Status” for more information. The system may also write the autoselect command sequence when the device is in the Erase Suspend mode. The device allows reading autoselect codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the device exits the autoselect mode, the device reverts to the Erase Suspend mode, and is ready for another

pend mode and continue the sector erase operation. Further writes of the Resume command are ignored. the device has resumed erasing.

1. See Table 9 for erase command sequence.
2. See “DQ3: Sector Erase Timer” for more information.

Figure 4. Erase Operation

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Table 9. Am29LV160D Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A19–A12 uniquely select any sector.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t cares for unlock and command
2. Address bits A19–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

1. No unlock or command cycles required when reading array
2. The Reset command is required to return to reading array data

(while the device is providing status data).

1. The fourth cycle of the autoselect command sequence is a
2. The data is 00h for an unprotected sector and 01h for a
3. Command is valid when device is ready to read array data or

when device is in autoselect mode.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to
3. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

1. The Erase Resume command is valid only during the Erase Suspend mode.

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RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. (The RY/BY# pin is not avail - able on the 44-pin SO package.) If the output is low (Busy), the device is actively eras - ing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (includ ing during the Erase Suspend mode), or is in the standby mode. Table 10 shows the outputs for RY/BY#. Figures 13, 14, 17 and 18 shows RY/BY# for read, reset, program, and erase operations, respectively. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or com plete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any ad dress, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op - eration, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 tog gles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter - mine whether a sector is actively erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro gram algorithm is complete. Table 10 shows the outputs for Toggle Bit I on DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. Figure 20 in the “AC Character- istics” section shows the toggle bit timing diagrams. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era sure. Thus, both status bits are required for sector and mode information. Refer to Table 10 to compare out - puts for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 20 shows the toggle bit timing dia - gram. Figure 21 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When - ever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a togg le bit is toggling. Typi cally, the system would note and store the value of the toggle bit after the first read. After the second read, the system would com pare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase oper ation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bi t is still toggling, the sys tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer

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was not successfully completed. Table 10 shows the outputs for DQ3. Table 10. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

1. DQ7 and DQ2 require a valid address when reading status info rmation. Refer to the appropriate subsection for further

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –2.0 V

input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 8.

1. Minimum DC input voltage on pins A9, OE#, and RESET#

Figure 7. Maximum DC input voltage on pin A9 is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

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Operating ranges define those limits between which the functionality of the device is guaranteed. Figure 7. Maximum Negative Figure 8. Maximum Positive

22358B7 May 5, 2006 Am29LV160D 31 DATA SHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. At extended temperature range (>+85°C), typical current is 5 µA and maximum current is 10 µA. 5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 6. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 9 16

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode (Notes 2, 3, 5) CE# = VIL, OE# = VIH 20 30 mA ICC3 VCC Standby Current (Notes 2, 4) CE#, RESET# = VCC±0.3 V 0.2 5 µA ICC4 VCC Standby Current During Reset (Notes 2, 4) RESET# = VSS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4, 6) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = -2.0 mA, VCC = VCC min 0.85 x VCC V VOH2 IOH = -100 µA, VCC = VCC min VCC–0.4 VLKO Low VCC Lock-Out Voltage (Note 4) 2.3 2.5 V

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Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical ICC1 vs. Frequency

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Notes: 1. Not 100% tested. 2. See Figure 11 and Table 11 for test specifications. Parameter

Description

JEDEC Std Test Setup -70 -90 -120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 70 90 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 70 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 70 90 120 ns tGLQV tOE Output Enable to Output Delay Max 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 25 30 30 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 25 30 30 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH Figure 13. Read Operations Timings

Figure 14. RESET# Timings

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Figure 15. BYTE# Timings for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations

22358B7 May 5, 2006 Am29LV160D 37 DATA SHEET AC CHARACTERISTICS Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 45 45 50 ns tDVWH tDS Data Setup Time Min 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 35 50 ns tWHWL tWPH Write Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

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1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings

1. SA = sector address (for Sector Erase), VA = Valid Addr ess for reading status data (see “Write Operation Status”).
2. Illustration shows device in word mode.

Figure 18. Chip/Sector Erase Operation Timings

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Figure 19. Data# Polling Timings (During Embedded Algorithms) cycle, and array data read cycle. Figure 20. Toggle Bit Timings (During Embedded Algorithms)

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Note: For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0. Figure 23. Sector Protect/Unprotect Timing Diagram

22358B7 May 5, 2006 Am29LV160D 43 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 50 ns tDVEH tDS Data Setup Time Min 35 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 35 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

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1. PA = program address, PD = program data, DQ7# = complement of the data written to the device, DOUT = data written to the
2. Figure indicates the last two bus cycles of the command sequence.
3. Word mode address used as an example.

Figure 24. Alternate CE# Controlled Write Operation Timings

22358B7 May 5, 2006 Am29LV160D 45 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 9 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 25 s Byte Programming Time 5 150 µs Excludes system level overhead (Note 5) Word Programming Time 7 210 µs Chip Programming Time (Note 3) Byte Mode 11 33 s Word Mode 7.2 21.6 s Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

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PHYSICAL DIMENSIONS* TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

22358B7 May 5, 2006 Am29LV160D 47 DATA SHEET PHYSICAL DIMENSIONS TSR048—48-Pin Reverse TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering. Dwg rev AA; 10/99

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FBC048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 8 x 9 mm Dwg rev AF; 10/99

22358B7 May 5, 2006 Am29LV160D 49 DATA SHEET PHYSICAL DIMENSIONS SO 044—44-Pin Small Outline Package Dwg rev AC; 10/99

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Revision A (January 1999) The Am29LV160D is fully form, fit, and function com - patible with the Am29LV160B device, with the following differences: A 70 ns device at full voltage range is now available. The 80 ns speed option has been deleted. Byte and word programming times, and byte- and word-mode chip programming times are now reduced. At extended temperatures (>+85 °C), sleep and standby currents increase. Revision A+1 (April 19, 1999) Global Reclassified the document from advance information to preliminary. The 70 ns speed option is now also available with the industrial and extended temperature range ratings. Revision B (November 23, 1999) AC Characteristics—Figure 17. Program Operations Timing and Figure 18. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision B+1 (February 22, 2000) Global Added dash to speed options. Added dash to OPN. Revision B+2 (November 7, 2000) Global Deleted Preliminary status from data sheet. Deleted burn-in option. Added table of contents. Revision B+3 (November 10, 2000) Command Definitions Reset Command: Deleted reference to Figure 14, RE- SET# Timings, which applies only to hardware reset. Revision B+4 (April 5, 2004) Erase/Program Operations Changed standard parameter tBUSY from Min to Max. Revision B+5 (June 4, 2004) Added Pb-Free OPNs. Revision B+6 (October 7, 2004) Cover Sheet and Title Page Added notation to superseding document. Revision B7 (May 5, 2006) Updated migration and obsolescence statement on cover page and first page of data sheet. Updated trademarks. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 1999–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.