J175 INTERFET | Alldatasheet
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J174, J175 P-Channel Silicon Junction Field-Effect Transistor ¥ Choppers ¥ Commutators ¥ Analog Switches Absolute maximum ratings at TA = 25¡C Reverse Gate Source & Reverse Gate Drain Voltage – 30 V Continuous Forward Gate Current 50 mA Continuous Device Power Dissipation 360 mW Power Derating 3.27 mW/°C TOÐ226AA Package Dimensions in Inches (mm) Pin Configuration
1 Drain, 2 Gate, 3 Source
SMPJ174, SMPJ175 At 25°C free air temperature: J174 J175 Process PJ99 Static Electrical Characteristics Min Max Min Max Unit Test Conditions Gate Source Breakdown Voltage V(BR)GSS 30 30 V IG = 1 µA, VDS = Ø V Gate Reverse Current IGSS 1 1 nA VGS = 20V, VDS = Ø V Gate Source Cutoff Voltage VGS(OFF) 5 10 3 6 V VDS = – 15V, ID = – 10 nA Drain Saturation Current (Pulsed) IDSS – 20 – 125 – 7 – 70 mA VDS = – 15V, VGS = Ø V Drain Cutoff Current ID(OFF) – 1 – 1 nA VDS = – 15V, VGS = 10V Dynamic Electrical Characteristics Max Max Drain Source ON Resistance rds(on) 85 85 Ω VGS = Ø, VDS < = 0.1V f = 1 kHz Dynamic Electrical Characteristics Typ Typ Drain Gate Capacitance Cgd 5.5 5.5 pF VDS = Ø V, VGS = 10V f = 1 MHz Source Gate Capacitance Cgs 5.5 5.5 pF VDS = Ø V, VGS = 10V f = 1 MHz Drain Gate + Source Gate Capacitance Cgd + Cgs 32 32 pF VDS = VGS = Ø V f = 1 MHz Switching Characteristics J174 J175Turn ON Delay Time td(on) 2 5 ns VDD – 10 – 6 VRise Time tr 5 10 ns VGS(OFF) 12 8 V Turn OFF Delay Time td(off) 5 10 ns RL 560 1.2 k Ω Fall Time tf 10 20 ns VGS(ON) Ø Ø V 1000 N. Shiloh Road, Garland, TX 75042 (972) 487-1287 FAX (972) 276-3375 www.interfet.com Databook.fxp 1/13/99 2:09 PM Page B-52