AM9157A AMD | Alldatasheet
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Am9517A/8237A‘ Multimode DMA Controller FINAL DISTINCTIVE CHARACTERISTICS © Four independent DMA channels, each with separate © End of Process input for terminating transfers registers for Mode Control, Current Address, Base © Software DMA requests Address, Current Word Count and Base Word Count @ Independent polarity control for DREQ and DACK @ Transfer modes: Block, Demand, Single Word, Cascade signals @ Independent Autoinitialization of all channels © Compressed timing option speeds transfers —up to © Memory-io-memory traraters 25M bytos/socond ‘© Memory block initialization © +5 volt power supply @ Address increment or decrement @ N-channel silicon gate MOS technology © Master system disable © 40-pin Hermetic DIP package, 44-pin PLCC package @ Enable/disable control of individual DMA requests @ 9517A-5 5 MHz version for higher speed CPU compati- © Directly expandable to any number of channels bility GENERAL DESCRIPTION The Am9517A/8237A Multimode Direct Memory Access Am74LS373. It contains four independent channels and (OMA) Controlier is @ peripheral interface circuit for micro- may be expanded to any number of channels by cascading Processor systems. It is designed to improve system additional controlier chips. Periormancs by allowing external devices to directly trans- ‘The three basic transter allow programmability of r information to or from the system memory. Memory-to- the types of DMA service by the user. Each channel can be memory transfer capability is also provided. The Am9517A/ pti iets individually programmed to Autoinitialize to its original 8297A offers a wide variety of programmable control Onion following an End of Process (EOP) features to enhance data throughput and system optimiza- "a 7 tion and to allow dynamic reconfiguration under program Each channel has a full 64K address and word count control. capability. An external EOP signal can terminate a DMA or memory-to-memory transfer. This is useful for block search The Am9517A/8237A is designed to be used in conjunc- —_or compare operations using external comparators or for tion with an external 8-bit address register such as the intelligent peripherals to abort erroneous services. BLOCK DIAGRAM = | 403, = ee) ey [st >> ae 4 4 | aS $ omsoe? =) RSS 0003284 “The 8237A is an AMD-invented device more commonly referred to as the Am9517A. Issue Date: 1909 Am9517A/8237A 1-227
CONNECTION DIAGRAMS | Top View } DIPs PLec oR cfre oh ” Eg on >]? 2» a8 i : see wows <3 =p gERESez2226 aw =a 7 s tatatatatatatatatat= esa 52 Tae 2 * wore 1) cs 3/5 er Ba As ReaDy Se =e me “wore 17 O 39 Pc Nac o> “ee q reaoy 8 a8 Plas Apsre Cs af at Hack 9 a7 Paz nen ay nf 10 aostaq] 10 36 Pat wea eat) ap vee (8vi eng] 11 38 Pao & i 2 80 Head] 12 34 Bvco cu C2 29 81 age 33 JD 080 Reser 3 2 ps2 ax 32 Poa pack? Fu a=, oss reser] 15 or baz packs Cs 2 one oackaY] 16 30 fi oa orca? is 3 aco ne] 17 20 fi oae Oncor ae a once 18 19 20 21 22 29 24 25 26 27 28 oreo! is af as SON eon BBLS oneao C1 22 = 088 PTET LLLLES (ono) vss <2 ne oe? SEEBE as ‘0008072 0009911 Note: Pin 1 is marked for orientation. *See Note 11 under DC Characteristics table. 1-228 Am9517A/8237A
ORDERING INFORMATION
AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by. a combination of: a. Device Number b. Speed Option (it applicable) c. Package Type d. Temperature Range . Optional Processing AMSBIZA 28 2 8 [ ©. OPTIONAL PROCESSING Blank = Standaro processing 8 = Buin 4. TEMPERATURE RANGE* = Commercial (0 19 + 70°C) 1S industrial (49 10 + 85°C), ©. PACKAGE TYPE P= 40.81 Plaste DIP (PO 040) = 40.Pm Ceramic DIP (CD 040) 32 4:Pin Paste Leaded Chip Carer ous) . SPEED OPTION wena ME vereue 4 | 1. DEVICE NUMBER/DESCRIPTION amost7A Multimode OMA Contoter Valid Combinations Valid Combinations list configurations planned to be Valid Combinations supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid [_amesi7as | 00, 08. PCC | combinations, to check on newly released combinations, and to obtain additional data on AMD's standard mititary grade Products. Am9517A/8237A 1-229
ORDERING INFORMATION (continued) 82370 ‘AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of: a. Temperature Range b. Package Type . Device Number . Speed Option €. Optional Processing L 2 B2978 =6 a L_ ©. OPTIONAL PROCESSING Blank = Standard Processing B= Bunn 4, SPEED OPTION wernt
2525 MHz
©. DEVICE NUMBER/DESCRIPTION 82374 Mullmode DMA Controtier b. PACKAGE TYPE P= 40-Pin Plastic DIP (PD 040) D= 40:Pin Ceramic DIP (CD 040) a, TEMPERATURE RANGE Blank = Commercial (0 to +70°C) Valid Combinations Valid Combinations Valid Combinations list configurations planned to be ee ee supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid ‘combinations, to check on newly released valid combinations, and to obtain additional data on AMD's standard military grade products. 1-230 Am9517A/8237A,
ORDERING INFORMATION (continued) Standard Milltary Drawing (SMD)/DESC Products AMD standard products for Aerospace and Defense applications are available in several packages and operating ranges. Standard Military Drawing (SMD)/DESC products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for SMD/DESC products is formed by a combination of: a. Mititary Drawing Part Number b. Device Type . ¢. Case Outline d. Lead Finish 7 i Q x L___4 cero rust X= Any Lead Finish Acceptable ‘¢. CASE OUTLINE = 40 pin Ceramic DIP (CD 040) b. MILITARY DEVICE TYPE 01 = 3 MHz (9517A) 02= 4 MHz (951704) ‘a, MILITARY DRAWING NO./DESCRIPTION 5962-87575 Multimode DMA Controller Valid Combinations Valid Combinations Valid Combinations list configurations planned to be ‘supported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations, to check on newly released combinations. Group A Tests 4 | Group A tests consist of Subgroups ‘Am9517A/8237A 4-231
ORDERING INFORMATION (continued) APL Products AMD products for Aerospace and Defense applications are available in several packages and operating ranges. APL (Approved Products List) products are fully compliant with MIL-STD-883C requirements. The order number (Valid Combination) for APL products is formed by a combination of: a. Device Number 'b. Speed Option (if applicable) c. Device Class d. Package Type @. Lead Finish L_. LEAD FINISH KeRot Solder Dp 4. PACKAGE TYPE Oi torn Corame O (CO 040) €. DEVICE CLASS 75 =Cess B 'b. SPEED OPTION Bork = S re mc ne 1. DEVICE NUMBER/DESCRIPTION nSt7A Matmode OMA Controller Valid Combinations Valid Combinations list configurations planned to be [AMesi7a sd ‘supported in volume for this device. Consult the local AMD ee ee | sales office to confirm availability of specific valid combinations or to check for newly released valid combinations Group A Tests Group A tests consist of Subgroups: 1-232 Am9517A/8237A
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|reknquished control of the system buses. TAEDA nan Regist The BUA Rogan esas ol papers Send oan Eps aay Frees seo ena ue gone oy scoring te DAEO be on) Feiler ten ene tt reel Ren open rt Oe er aca caine oreeeare tack es an 7D [BATE Bik Te Ons Bn Ro oo Wreclrl Uavosia yah Gamo she me la Be re a es hi aga tena ing he VO oests coma econcns Bp eer toto teeta gl ere LE oe a oe i ort a a reed ete ari Fe eee eae ee eae See acne etree Se a ee ncn ne Se ae a Nee tas Fedo eeepc
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Loan at he a reat ne rae toeiee hie Ree nee he ane Ce ee a ee a eae ee Tang Ds we Pest Oe oO nese Sob ea hauaey Fo naan VEIT he hte se eapelatleee nto erties tee tu oarpeaary anaes To end of amas End Bes © See Tw icine ops Bah Sonal Hlaraton [concerning the completion of DMA service ts available at the bidirectional EOP pin. The Am9517A/ |8237A allows an external signal to terminate an active DMA service. This is accomplished by puling ithe EOP input low with an external EOP signal. The Am9517A/8237A aiso.generates 2 pulse when Pale dtr et nalicorupy a pparearenri ‘through the EOP Line. The reception of EOP, either internal or external, will cause the Am9517A/ ee teed nent peer prot octnpetmrg tiara od Heal aberdeen caper netted set for the currently active channel by EOP unless the channel is programmed for Autoinitialize. in jthat case, the mask bit remains: unchanged, During memory-to-memory transfers, EOP will be a ee eet nel ara tt est ml ae oaeoas rene 7am Oreos Tre Toor et aigca adress tos ne recone oo Sale gash he lo Re Taste chaos cael a Do ae Se ee ote aia el nee |Actwe cycle, they are outputs and provide the lower 4 bits of the output address. a anes To Tae most Ga elves: Ren we voosions capuls ord pe 4 oT Raseae Thos tar te St co sea aa one Tad Hemet Tiss he Tod equa the GPU ands od gue Goma a he aan Seat eye ecto ior hoa dey el ec pene See ena raat Soo a a cos re tc cyan eM mus act bos aa see me Re oO iene Ra ee on ay a ee en gee Palas ry acions Erae Tiara Erste obi he Bich colig oper 6 adios Bs a Ne a ee eee ae saa Bak regen ero ae aa atone Seone Th babe igh AGToas Saba Wad To SEG supper Saabs Blo ah Menory Read Te Momo Read sgl an sive ow tocol aug! ued oaccae [repel ery riety aeenrenveree ery anor Wile Toe asnny Vins Sips nah ave iw roo ae cpt ood rhe Soa a ee a aut ek ike ova tocar eonay beta “Applies to. DIPs only. Am9517A/8237A 1-233
fume _]__sie_| number] nen no chamalisequesting sree, the AmdS174/8287A [Base Adsross Registers [6 bts | 4} will enter the Idle cycle and perform SI states. In this cycle [Base Word Count Registers [16 bis | ¢| the Am9517A/8237A will sample the DREQ lines every clock [Current Address Registers | v6 bts | «| _cycle to determine if any channel is requesting a DMA service. [Curent Word Count Registers | 16 bts_| 4 |_—‘The device will also sample CS, looking for an attempt by the [Temporary Adress Regsie: | ve bis | 1 | Me"OPFOCEEEDY Lo wate or rad the internal rqitrs of the ‘Am9517A/8237A. When CS is LOW and HACK is LOW, the now establish, change or inspect the internal definition of the [Command Register |e bts [| part by reading from or writing to the internal registers. ‘Address lines AO-A3 are inputs to the device and select [Mose Registers ~~~ bis | | _which registers will be read or written. The [OR and IOW lines [Mask Register —~—~=S*«d~SC*«<‘ (te ~~] ~~ +|SC_ arsed to select and time reads or writes. Due to the number [Request Regsior | bis] 1] «Cand size of the internal registers, an internal fip/flop is used to = generate an additional bit of address. This bit is used to Am9517/8237A Internal Registers. determine the upper or lower byte of the 16-bit Address and Word Count registers. The flip/flop is reset by Master Clear or DETAILED DESCRIPTION Reset. A separate software command can also reset this flip/ ‘The Am9517A/8237A block diagram includes the major logic HOP. blocks and all of the internal registers. The data interconnec- Special software commands can be executed by the tion paths are also shown. Not shown are the various control. _Am9517A/8237A in the Program Condition. These commands signals between the blocks. The Am9517A/8237A contains —_are decoded as sets of addresses when both CS and IOW are 344 bits of internal memory in the form of registers. The table active and do not make use of the data bus. Functions include shown above lists these registers by name and shows the size Clear First/Last Flip/Flop and Master Clear. of each. A detailed description of the registers and their functions can be found under Register Description. Active Cycle ) _ When the Am9517A/8237A is in the idle cycle and a channel external control signals for the Am9517A/8237A. The Pro- Microprocessor and enter the Active cycle. It is in this cycle gram Command Control block decodes the various commands _that the OMA service will take place in one of four modes: given to the Am9517A/8237A by the microprocessor prior to Single Transfer Mode: In Single Transfer mode, the servicing a DMA Request. It also decodes each channel's _Am9517A/8237A will make a one-byte transfer during each Mode Control word. The Priority Encoder biock resolves HREQ/HACK handshake. When DREQ goes active, HREQ priority contention among DMA channels requesting service —_will go active. After the CPU responds by driving HACK active, simultaneously. a one-byte transfer will take place. Following the transfer, i HREQ will go inactive, the word count will be decremented ies aa aertant tne te ea wil eval be the ae and the address will be either incremented or decremented. Fee ook fom an Anva024, However any appropnate system When the word count goes to zero, a Terminal Count (TC) will . any appropriate sy‘ cause an Autoinitialize if the channel has been programmed to clock will suffice. So'se. DMA Operation To perform a single transfer, DREQ must be held active only ITAIB2I7A is rate in two m until the corresponding DACK goes active. If DREQ is held The AMQSITA/GER7A is deiged to opto wo major Sine ann TRE wl go nace tomy each cycle is made up of a number of states. The Am9517A/8237A Transfer and then will go aclive again and a new one. byte can assume seven separate slates, each composed of one ansfer will be made following each rising edge of HACK. In full clock period, State | (Si) is the inactive state. It is entered 8080A/AmBOBOA systems, this will ensure one full machine when the Am9517A/8237A has no valid DMA requests cele of execution between DMA transfers. Details of timing pending. While in SI, the DMA controller is inactive but maybe between the Am9517A/6237A and other bus control proto~ in the Program Condition, being programmed by the proces. 0018 will depend upon the characteristics of the microproces- sor. State 0 (S0) is the first state of a DMA service. The $0 involved. ‘Am9517A/8237A has requested a hold but the processorhas = Block Transfer Mode: In Block Transfer mode, the rot yet returned an acknowledge, An acknowledge from the Am9517A/8237A will continue making transfers until a TC CPU will signal that transfers may begin. $1, S2, $3, and S4 (caused by the word count going to zero) or an external End of are the working states of the DMA service. If more time is Process (EOP) is encountered. OREQ need be held active needed to complete a transfer than is available with normal —_ only until DACK becomes active. An Autoinitialize will occur at timing, wait states (SW) can be inserted before S4 by the use _—_the end of the service if the channel has been programmed of the Ready line on the Am9517A/8237A. for it. Memory-to-memory transfers require a read-trom and a write- Demand Transfer Mode: In Demand Transfer mode the to-memory to complete each transfer. The states, which device will continue making transfers until a TC or external resemble the normal working states, use two digit numbers for EOP is encountered or until REQ goes inactive. Thus, the identification. Eight states are required for each complete _device requesting service may discontinue transfers by bring- transfer. The first four states (S11, $12, $13, $14) are used for _ing DREQ inactive. Service may be resumed by asserting an the read-rom-memory haif and the last four states (S21, S22, active DREQ once again. During the time between services $23 and $24) for the write-to-memory half of the transfer. The __ when the microprocessor is allowed to operate, the intermedi- Temporary Data register is used for intermediate storage of ale values of address and word count may be read from the the memory byte. ‘Am9517A/8237A Current Address and Current Word Count 1-234 ‘Am9517A/8237A,
‘Address Generation: To reduce pin count, the Am9517A/ 8237A multiplexes the eight higher order address bits onthe 7 6 5 4 3 2 1 0 ~—BitNumber data lines. State S1 is used to output the higher order address bits to an external latch from which they may be placed on the address bus. The falling edge of Address Strobe (ADSTB) is 0 Memory-to-memary disable Used to load these bits from the data lines to the latch. 1 Memory-to-memory enable ‘Address Enable (AEN) is usod to enable the bits onto the address bus through a three-state enable. The lower order (© Channel O address hold disable address bits are output by the Am9517A/8237A directly. Lines 1 Channel O addeess hold enable ‘AQ-A7 should be connected to the address bus. Timing X itbito=0 Diagram 1 shows the time relationships between CLK, AEN, ADSTB, 0B0~DB7 and A0-A7. © Controter enable
1 Controller disable
During Block and Demand Transfer mode services which include multiple transfers, the addresses generated will be sequential. For many transfers the data held in the external (© Notmat timing address latch will remain the same. This data need only 1 Compressed timing ‘change when a carry or borrow from A7 to A8 takos place in X WbitO=t the normal sequence of addresses. To save time and speed transfers, the Am9517A/8237A executes St states only when 0 Fixes Priority updating of A8 - A15 in the latch is necessary. This means for 1 Rotating Priority long services that S1 states may occur only once every 256 transfers, a savings of 255 clock cycles for each 256 transfers. ©. Late write selection Register Description 1 Extended write seletion Current Address Register: Each channel has a 16-bit X bidet Current Address register. This register holds the value of the address used during DMA transfers. The address is automati- © DREQ sense active high cally incremented or decremented after each transfer and the 1 DREQ sense active tow intermediate values of the address are stored in the Current ‘Address register during the transfer. This register is written or 0 DACK sense active low read by the microprocessor in successive 8-bit bytes. It may 1 DACK sense active high also be reinitialized by an Autoinitialize back to its original F000970 value. Autointialzation takes place only after an EOP. Current Word Count Register: Each channel has a 16-bit Mode Register: Each channel has a 6-bit Mode register ‘associated with it. When the register is being written to by the Current Word Count register. This register should be pro- Fen i roprocessor in the Program Condition, bits O and 1 grammed with, and will return on a CPU tead, avalue one les Getermine, which channol Modo register is to be writen to than the number of words to be transferred. The word count is 7 dacremented after each transfer. The intermediate value of the word count is stored in the register during the transfer. 76 5 4 3 2 1 _0 + —8it Number When the value in the register goes to zero, a TC will be generated. This register is loaded or read in successive 8-bit bytes by the microprocessor in the Program Condition. Follow- 00. Channel O select ing the end of a DMA service, it may also be reinitialized by an 01 Channel 1 select Autoinitialize back to its original value. Autoinitialize can occur 10 Channel 2 select ‘only when an EOP occurs. Note that the contents of the Word 11. Channel 3 select Count register will be FFF (nex) folowing on intomaly GO Verity wanster
01 Write transter
Base Address and Base Word Count Registers: Each 10. Reed tsaneter channel has a pair of Base Address and Base Word Count 11 tegat registers. These 16-bit registers store the original values of XX tte 6and7=11 their associated current registers. During Autoinitiaize these values are used to restore the current registers to their original © Autoiitistize disable values. The base registers are written simultaneously with 1 Autoinitisize enable their corresponding current register in 8-bit bytes during DMA, programming by the microprocessor. Accordingly, writing to these registers when intermediate values are in the Current © Address increment select registers will overwrite the intermediate values. The Base 1) Address decrement select registers cannot be read by the microprocessor. ‘Command Register: This 8.bit register controls the operation or Sige mode sect of the Am9517A/8297A. It is programmed by the microproces- sor in the Program Condition and is cleared by Reset. The 10 Block mode select following table lists the function of the command bits, See 11 Coscade sacle anlect Figure 2 tor address coding. DFo00980 Request Register: The Am9517A/8237A can respond to requests for DMA service which are initiated by software as well as by a DREQ. Each channel has a request bit associated with it in the 4-bit Request register. These are nonmaskable and subject to prioritization by the Priority Encoder network 1-236 ‘Am9517A/8237A
Each register bit is set or reset separately under software Status Register: The Status registers may be read out of the contol ois cleared upon generation of a TC or external EOP. Am9517A/B237A by the microprocessor, It indicates which ‘The entire register is cleared by a Reset. To set or reset abit, channels have reached a terminal count and which channels the software loads the proper form of the data word. See have pending DMA requests. Bits 0- 3 are set each time a TC Figure 2 for address coding is reached by that channel, including after each Autoinitializa- tion. These bits are cleared by Reset and each Status Read. 7.6 5 4 3 2 1 0 ——BitNumber Bits 4-7 are set whenever their corresponding channel is requesting service. ae 00 Select channel 0 76 5 4 3.2 1 0 ——BitNumber
1 Select channel 1
- Select channel 2 11. Select channel 3
0 Reset request bit 1 Channel 0 has reached TC
1 Set request bit 1. Channel 1 has reached TC r000800 1 Channet 2 has reached TC
1 Channel 3 has reached TC
Software requests will be serviced only if the channel is in Block mode. When initiating a memory-to-memory transfer, the software request for channel 0 should be set. 1 Channel O request Mask Register: Each channel has associated with it a mask 1 Channel 1 request bit which can be set to disable the incoming DREQ, Each 1 Channel 2 request ‘mask bit is set when its associated channel produces an EOP 1 Channel 3 request it the channel is not programmed for Autoinitialize. Each bit of oFoot020 the 4-bit Mask register may also be set or cleared separately under software control. The entire register is also set by a Reset. This disables all DMA requests until a clear Mask Temporary Register: The Temporary register is used to hold fegistor instruction allows them to occur. The instruction to data during memory-o-memory transfers. Following the com Separately set or clear the mask bits is similar inform to that pletion of the transfers, the last word moved can be read by used with the Request register. See Figure 2 for instruction the microprocessor in the Program Condition. The Temporary addressing register always contains the last byte transferred in the previous memory-to-memory operation, unless cleared by a 7 6 5 4 3 2 1 0 ——~BitNumber Reset Software Commands: There are three special software me 00 Select channel O mask bit. Commands which can be executed in the Program Condition. Don't Care ‘Ot Select channel t mask bit ‘They do not depend on any specific bit pattern on the data 10 Select channel 2mask bit ‘BUS. The three software commands are. 11. Select channel 3 mask bit Clear First/Last Flip/Flop: This command may be issued © Clear mask bit prior to writing or reading Am9517A/8237A address or word 1 Set mask bit count information. This initializes the Flip/Flop to a known state so that subsequent accesses to register contents by 001000 the microprocessor will address lower and upper bytes in All four bits of the Mask Flegister may also be written with the correct sequence. When the Flip/Flop is cleared it single command. addresses the lower byte and when set it addresses the upper byte. 7.6 5 4 3.2 1 0 ——BitNumber Master Clear: This software instruction has the same effect as the hardware Reset. The Command, Status, Request, —— 0 Clear Chennel 0 ask bit Temporary and Internal First/Last Flip/Flop registers are Don't Care + Ser Channel mast bit cleared and the Mask register is sot. The Am9517A/8237A will enter the idle cycle. (0 Giese Cnannel 1 mask bit 1 Sot Chonnat ? med bit Clear Mask Rogister: This command clears the mask bits of all four channels, enabling them to accept DMA requests.
0 Clear Channel 2 mask bit
1 Set Channet 2 mask bit
1 Set Channel 3 mask bit
‘Am9517A/8237A 1-237
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES All Signal Voltages with Respect Supply Voltage (VoO) oes. 5 V 25%
10 V6 crscsstsseeeneineinenerseiie 05 VIO +70 V Industrial (l) Devices
Stresses above those listed under ABSOLUTE MAXIMUM Supply Voltage (Voc) -.-.+.--. cnS V 210% RATINGS may cause permanent device failure, Functionality at or above these limits is not implied. Exposure to absolute Operating ranges define those limits between which the maximum ratings for extended periods may affect device functionality of the device is guaranteed. reliability. DC CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified. (Note 1) vor | Output HIGH Vonage 1H = 200 uA [24 [ f vos HOH==100 4A, REG Oy [33 TT [vor] Oupst Low vowtage [toes azma oso Tons [7 vin [input HIGH Votage ao voor os Tvons | [vn [input Low vottage os oT vos Input Load Curent VSS <VIS VCC re ee [10z [output Leakage Curent VOC K VO <VSS + 0.40 re ee EZ ie Noe Supply Curent Ls es BC uiput Capacitance (Note 14) re ee f= 1.0 MHz, Inputs = 0 V a | a A | CORREO |" Output Capictance (HREO) [ re= to MHz Inputs= vig 20 or Notes 1. Typical values are for Ta= 25°C, nominal supply voltage and nominal processing parameters. 2. Input tming parameters assume Wansiion times of 20 ns or less. Wavelorm measurement points for both input and output signals are 20 Vifor HIGH and 0.8 V for LOW. unless otherwise noted 3. Output loading is 1 Standard TTL gate plus 50 pF capacitance unless noted otherwise The new TOW or HEMW pulse wh for normal wnte wil be TCY-100 ns and for extended write wil be ZTCY-100 ns. The net TOR or EWA pulse width for normal read will be 2TCY-50 ns and for compressed read will be TCY-50 ns. 5. TDQ is specilied for two diferent output HIGH levels, TOO! is measured at 20 V. TDO2 is measured at 3.3 V. The value for TOG2 assumes an external 3:3 KO pullup resistor connected from HREQ to VCC. 6. DEQ should be hold actwe unti DACK is returned 7. DREO and DACK signals may be actve high or active low. Ting diagrams assume the acive high mode 18 Output loading on the data bus s 1 Standard TTL gate plus 15 pF Yor the minimum value and 1 Standard TTL gate plus 100 pF for the maximum valve 8. Successive read and/or write operations by the externs! processor to program or examine the controller must be tmed to allow at least 450 ns for the AmQ517A.4/6237A-4, and 400 ns for the AmO517A-5/8237A-5 as recovery ime between ace read oF write uses 10. Parameters are listed in alphabetical order 11. Pin 5 is.an input that should always Bo at a logic high tevel {An internal pul-up resistor will establish a logic high when the pin is lett Nloating. Alternatively, pin 5 may be ted to VEC. 12 Says HEAD ana WRITE for to TOR ono MEMW roopectvely for perbhorattememory OWA operations and 19 NEMA and TOW respectively for memory to-perpheral OMA operations. 13. WEN wai states are added during the wrtesto-memory halt of a memory-l-memory transfer, this parameter wil increase by N (TOY)
14 A ouput gins xcept HREO
15 Because high from clock high is load dependent, users wishing to test these parameters should use a 2k pull-up resistor and a tester with 50 pF or less load capacitance. Time constant AC = 120 ns is added to the spectied number in the data sheet for testing SWITCHING TEST INPUT WAVEFORM wr003310 4-240 ‘Am9517A/8237A
ABSOLUTE MAXIMUM RATINGS OPERATING RANGES Stresses above those listed under ABSOLUTE MAXIMUM functionality of the device is guaranteed. RATINGS may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability DC CHARACTERISTICS over MILITARY operating range (for SMD/DESC and APL Products, Group A, Subgroups 1, 2, 3 are tested unless otherwise noted) Parameter
Description
lon = =200 WA Voo=45 V a “ Output HIGH Vok v on “se low == 100 4A (AEG Oniy) [sa Output LOW Voliage [io =32 mA Voo=ssv [| easy Pv [Vm | Input WIGH Vote | Voce as visév [aa | vocvoss |v Input HIGH Voltage Voo=asvissv com [235 | vocsos [VT Voo= 45 Vv. 55 V [os [oy [tx | tnt Load Current Ves Wi Veo. Vec=ssv Uf =10 TT sio aa Voc Supply Current [Note so a [Co + | urput Capacitance (Note 12) a a fe=1.0 MHz, Inputs «0 V ee ae a * Guaranteed by design + Not included in Group A tests, Notes: 1. icc iS measured in a dynamic condition with outputs in a worst-case stato having no loads applied 2 Input liming parameters assume transition times of 20 ns oF less. Wavelorm measurement poinis for both input and output signals are
20 V for HIGH and 08 V for LOW, unless otherwise noted
- The new [OW or MEMW pulse width for normal write wil be TCY-100 ns and for extended write wil be 2TCY-100 ns. The net 'OF or EWR pulse width for normal read wil be 2TCY-50 ns and for compressed read will be TCY-50 ns. assumes an external 33 KE pull-up resisior connected from HREQ 10 Voc. 5, DREQ should be held active until OACK is returned & OREO and DACK signals may be active HIGH or active LOW. Timing diagrams assume the actwe-HIGH mode. 7. Successive read and/or wrte operations by the external processor to program or examine the controller must be timed to allow at Jeast 600 ns for the AMOBI7A, at least 450 ns for the AMOSITA-6 as recovery bme between active read oF write pulses, 2, Parameters ara listed in alphabetical ordor 8. Pin 5 is an mput that should aways be at a logic-HIGH level. An internal pull-up resistor will establish a loge HIGH when the pin is left floating, Alternatively pin § may 0 tied to V. 10. Signale READ ang WAITE refer to [OR and MENW respectvoly for pensheralto-memory OMA operations and to NEMA and iOW respectively for memory-to-peripheral DMA operations. 11. IPN wait states are added during the wnte.to-memary half of @ memory-to-memory transfer, this parameter will increase by N (TCY)
12 Ai ouput ns except HRE
- Because EOP HIGH from clock HIGH is load-dependent, users wishing fo test these parameters should use a 2k pull-up resistor and a tester with 50 pF of less load capacitance. Time constant A = 120 ns 1S added to the speciied number in the data sheet for testing. ‘Am9517A/8237A 4-241
SWITCHING CHARACTERISTICS over COMMERCIAL operating ranges unless otherwise specified ACTIVE CYCLE (Notes 2, 3, 10, 11, and 12) Description |i | won| in| won| [_TAgL [AEN HIGH from CLK LOW (81) Delay Time [as 200s [TAT [AEN LOW tom CLK HIGH ($1) Oolay Time | 180 tgs [“TAFAB [ADA Actvo to Float Oolay trom CK AIGH [|| 0 [ir | | Tarc [READ or WAITE Float trom CuK HIGH T2020 ns [“TAFDa [08 Aiwa to Foat Delay from CUX HIGH P| | 190 70 rs [Tan [AA trom REAB HIGH Wold Tme SS YevO | revo || rs | [_TAHS [08 from ADSTE LOW Hold Time 9090s [DACK Vake rom CLK LOW Geiey Tiwi) | Oe TAK [EOP FIGH trom CLK HIGH Delay Time J | oof 70 re | EOF LOW to CLK HIGH Delay Time 0900s [TASH [ADR Stable tom CLK HGH S90 0 rs | [TASS | D8 to ADSTB LOW Setup Time 0000 es [ton Giock igh Time (Transitons ©1006) [00 0s) [Tot | “Geek tow Time (Transitons < 10ns) P08 rr [rey | otk Cyto Time co 00s [ roc. [CLK HIGH to EAB or WAITE LOW Delay (Note 4) [200190 ns [_roctr | Read HiGH trom GLK HIGH (S4) Delay Time (Note 4) [aio PT t90 ns [“Toctw | “WRITE HIGH trom CLK HIGH (Si) Detey Time Wore 4) [| _190_ [|] 90 [rs] [ Toor | {120 | [ar ——] eo a om cic oye 9 Ff psf — if [eps [EOP LOW trom CLK LOW Setup Time Pasa [_Tepw | EOP Putso with ees es | TrAAB | ADA Float to Active Delay from CLK HIGH [| te 70 ns | TkAG [READ or WRITE Actwo trom CLK HIGH e000 ns | TFADe [08 Float to Active Delay trom CLK HIGH aa 200 ne [THs [HACK Valid to CLK HIGH Setup Time 75 Pens [Tow | input Data trom WENA HIGH Hold Time Ps [tins | input Data to WENA HIGH Setup Time [90 Paros [_TODH [Output Data trom WEMW HIGH Hold Tmo P20 Pt ns] [Toov | Out Data Vets to WEMW HIGH (Note Ya) ts Psp ns T [Tas [BRED te CLK LOW (1, $4) Setup Time [TRH | CAK to READY LOW Hold Tine 00 ao 0s [tas [READY to CLK LOW Setup Time eo eos [rstt[AOSTB HIGH trom CL HIGH Delay Time P80 190 os) [_tstr | ADSTS LOW from CLK HIGH Delay Time to 90s [ran [OREO from DACK Valid Hold Time Ps [TROHA™ | HREQ to HACK Delay Time ae PROGRAM CONDITION (Idle Cycle) (Notes 2, 3, 10, and 11) [TART ADR Valid or G5 Low to READ LOW soso [raw [ADA Valid to WRITE HIGH Setup Timo 7 [sso ts [row | GS Low to WRITE HIGH Setup Tomo got ns | row | Data Vad to WRITE HIGH Setup Time aso [a0 es J TRA | ADR oF CS Hold trom READ HIGH os [ADE [bata Accwss trom READ LOW (Nowe ey TT a0 ao ns [tRoF [08 Float Delay tom READ HGH [a0 too Poo | Taso ____| "Power Supply HIGH to RESET LOW Setup Time [500 [500 [ns | tasts [Reset to Fret OWA are PP arcy es [_tastw [RESET Puteo wath 00 00s [raw ReaD wa e800 eT [twa [ADR trom WRITE HIGH oid Time aoa pte [CS HIGH trom WAITE HIGH Hold Time [2020s [two [Data trom WRITE HIGH Hold Time T9030 es [rwws | weito with, 200 Ts 1-242 ‘Am9517A/8237A
SWITCHING CHARACTERISTICS over MILITARY operating range (for SMD/DESC and APL Products, | Group A, Subgroups 9, 10, 11 are tested unless otherwise noted) ACTIVE CYCLE (Notes 2, 8, 9, and 10) Description [min [won | win | wax_| [TAEL | AEN HIGH Wom GLK LOW (St) Delay Tme || goa [TAET___|_AEN LOW rom GLK HIGH (St) Dolay Time TT ao so [TAFAB | ADA Active to Float Osiy rom Gu HIGH Tso ao ns [Taro [READ or WRITE Fioat tom GiK GH [tgs [taF08 | 08 ‘Active to Foat Delay from Gix HGH Paso 00 [TAHR | ADR trom READ HIGH Hold Time Tews || rovsoo [| [Tans |B trom ADSTE LOW Hod Time To = [Takw [ADA irom WRITE HIGH Hold Time rovso [| rovs0 | [os | [DACK Vat trom CuK LOW Delay Time || amo 220 TAK [EOP HIGH tom GLK HIGH Doty Time Taste ["EOB LOW to CLK HIGH Doty Tmo Taso 90s [“TASM [TAA Stable rom CuK HIGH aso oo Ys [Tass [08 to ADSTB LOW Soup Time too Poo ns [Tox [Gock High Time (Transtions < rons) Pao oo [Tor | Giook Low Time (Transttons <t0ns) so fo as [tov aK Gee time CY seo so [ “root | 60x HIGH to READ or WHITE LOW Delay (Note 3) [aro 00 ns [Tooth [Raa HIGH trom CLK HIGH ($8) Delay Time Note g) [| ao a0 fs 4 | [footw] "WATE HIGH fom GLK HIGH ($0) Datay Time (Weie [Tao sos a [Toaa | HREO Val trom CU HIGH Delsy Tine (vole 9 | ferov esol ferev + vaof ns | [tes [EOF LOW tom GLK LOW Setup Time [go [as [teew | EOP Pus wan mo es [“TrAAa | ADA Float to Actwe Doay rom cu HIGH [esos [TRAC | READ or WRITE Active trom UK HIGH [ao fon [“TFADB | 0 Float to Active Delay ftom GUX HIGH | 00 aes [THs TRAGK Vals 10 GLK HIGH Soup Time too Ps ns [Ton [put Oata tom WEWR HIGH Hog Time | Pes ce [took [“outout Data from MEMW HIGH Hold Time | 2a [Toov | “output Data Vato to WEMW HIGH Woie vi) 200 Pass [Tas J DREG to CLK LOW (1. 54) Setup Time Po ns [tan | CuK Wo READY LOW Hog Time Pea [tes | READY to CLK LOW Sewp Time Sf too | wes [TST] ADSTB HIGH fom CLK HIGH Delay Time goof isos [tert [“ADSTB LOW Wom CLK HIGH Delay Time ao one [Ton [oR fom OAK Vaid Ho Time | Te [TROHA | HREQ 10 HACK Detay Time Pt Po AC Device Test Conditions: Voc = 4.5 V. 5.5 V Vit = 045 V, Vin 24 V Vou = 08 V, Vou 20 V ToL 82 mA, lon = 200 HA CL = 100 pF #20 pF Notes: See notes following DC Characteristics ‘Am9517A/8237A 1-243
SWITCHING CHARACTERISTICS over MILITARY operating range (continued) PROGRAM CONDITION (Idle Cycle) (Notes 2, 3, 10, and 11) | —aa Descrtption | wn | mex | min | max_| [TAR [ADR Vaid or TS tow w READ LOW Tso Tso Ts [Taw | ADR Valid to WRITE HIGH Seup Time zoo fT gos) [ row [GS tow to WRITE HIGH Sewp Time [200 Tasos [Tow [Data Vaid to WRITE HIGH Setup Time [200 Tso ns [TRA [ADA or CS Hold trom READ HIGH os [TRE | "Data Access trom FEAD LOW (Note @) P00 200 ns | TROF | 08 Float Delay tom READ WGH a0 as0 0 t00 ns | TRsTo "|" Power Supply HIGH to RESET LOW Setup Time [600 [soo Js | tasts "| RESET 0 Fst WR arc aroy Ps [tastw | RESET Putse wenn 0g 200s [aw TREAD Wim mos [twa | ADR trom WRITE HIGH Hold Tne To To [two [cS HIGH rom WAITE HIGH Hold Time oT ao Ps [two | Dota tom WRITE HIGH Hold Tne oP [twws | wike wen a0 00 Lv | tosantmen iow Te Pe Ts (TAD = TAR + TROE) ‘Notes: See notes following DC Characteristics. 1-244 Am9517A/8237A
Timing Diagram 1. Active Cycle Timing Diagram | met TESS [=F | | —F eH TL i | “ a “) | WTA - oa Pre nn ae || | Tl wae] = | reer aa] 2; | rocre| 4-1 are S| a _— tte = = ee SXNNXNNNNANNN SS //////////// Note: EOP must precede AEN in single transfer mode. | ‘Am9517A/8237A 1-245
SWITCHING WAVEFORMS (continued) Timing Diagram 2. Memory-to-Memory cue ii A mal oe SL f won i | { h i i rana| Foms = fee [rane re C aim omer ——— 0006 SM ore CO =_ | wd all reel = rote. = — | 5 TT, = von ere wnt ey . | ents | TAK: TAK | _ Timing Diagram 3. Ready Timing Timing Diagram 4. Compressed Timing ne . AAA |. : = ~ ee ~ = ‘oe. wee rverw- = | | were Pe sre i> ‘rat df we 4 Ace ae I wor eH HE wos | EG EY OG 'WF003340 Timing Diagram 5. Reset Timing <=. ae 1-246 ‘Am9517A/8237A
SWITCHING WAVEFORMS (continued) Timing Diagram 6. Program Condition Write Timing mee THs, ony ee - =p wo RRR mre vacio XK Tow ™e ono-oe7 ARQ meer vaio ROX ve Timing Diagram 7. Program Condition Read Cycle 01s RK aconessmesrarvanig XXKKKKXYD Am9517A/8237A 1-247