Z9972 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

  • Output frequency up to 125 MHz  12 clock outputs: frequency configurable  350 ps max output-to-output skew  Configurable output disable  Two reference clock inputs for dynamic toggling  Oscillator or crystal reference input  Spread Spectrum-compatible  Glitch-free output clocks transitioning  3.3V power supply  Pin-compatible with MPC972  Industrial temperature range: –40°C to +85°C  52-pin TQFP package

Table 1. Frequency Table[1]

  1. x = the reference input frequency, 200 MHz < FVCO < 480 MHz.

Document #: 38-07088 Rev. *D Page 2 of 9 Pin Descriptions Pin Name PWR I/O Type Description 11 XIN I Oscillator Input. Connect to a crystal. 12 XOUT O Oscillator Output. Connect to a crystal. 9T C L K 0 I P U External Reference/Test Clock Input. 10 TCLK1 I PU External Reference/Test Clock Input. 44, 46, 48, 50 QA(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 32, 34, 36, 38 QB(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 16, 18, 21, 23 QC(3:0) VDDC O Clock Outputs. See Table 2 for frequency selections. 29 FB_OUT VDDC O Feedback Clock Output. Connect to FB_IN for normal operation. The divider ratio for this output is set by FB_SEL(0:2). See Table 1. A bypass delay capacitor at this output will control Input Reference/ Output Banks phase relationships. 25 SYNC VDDC O Synchronous Pulse Output. This output is used for system synchroni- zation. The rising edge of the output pulse is in sync with both the rising edges of QA (0:3) and QC(0:3) output clocks regardless of the divider ratios selected. 42, 43 SELA(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QA(0:3) outputs. See Table 2. 40, 41 SELB(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QB(0:3) outputs. See Table 2. 19, 20 SELC(1,0) I PU Frequency Select Inputs. These inputs select the divider ratio at QC(0:3) outputs. See Table 2. 5, 26, 27 FB_SEL(2:0) I PU Feedback Select Inputs. These inputs select the divide ratio at FB_OUT output. See Table 2. 52 VCO_SEL I PU VCO Divider Select Input. When set LOW, the VCO output is divided by 2. When set HIGH, the divider is bypassed. See Table 1. 31 FB_IN I PU Feedback Clock Input. Connect to FB_OUT for accessing the PLL. 6 PLL_EN I PU PLL Enable Input. When asserted HIGH, PLL is enabled. And when LOW, the phase-lock loop (PLL) is bypassed. 7 REF_SEL I PU Reference Select Input. When HIGH, the crystal oscillator is selected. And when LOW, TCLK (0,1) is the reference clock. 8 TCLK_SEL I PU TCLK Select Input. When LOW, TCLK0 is selected and when HIGH TCLK1 is selected. 2M R # / O E I P U Master Reset/Output Enable Input. When asserted LOW, resets all of the internal flip-flops and also disables all of the outputs. When pulled HIGH, releases the internal flip-flops from reset and enables all of the outputs. 14 INV_CLK I PU Inverted Clock Input. When set HIGH, QC(2,3) outputs are inverted. When set LOW, the inverter is bypassed. 3S C L K I P U Serial Clock Input. Clocks data at SDATA into the internal register. 4S D A T A I P U Serial Data Input. Input data is clocked to the internal register to enable/disable individual outputs. This provides flexibility in power management. 17, 22, 28, 33,37, 45, 49 VDDC [2] 3.3V Power Supply for Output Clock Buffers. 13 VDD [2] 3.3V Supply for PLL. 1, 15, 24, 30, 35, 39, 47, 51 VSS Common Ground . Note: 2. A bypass capacitor (0.1 µF) should be placed as close as possible to each positive power (< 0.2”). If these bypass capacitors are not close to the pins their high-frequency filtering characteristics will be cancelled by the lead inductance of the traces.

Document #: 38-07088 Rev. *D Page 3 of 9

Description

The Z9972 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide excep- tional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz. The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs (see Table 1). The VCO frequency is then divided to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs (see Table 2). For situations in which the VCO needs to run at relatively low frequencies and therefore might not be stable, assert VCO_SEL LOW to divide the VCO frequency by 2. This will maintain the desired output relationships, but will provide an enhanced PLL lock range. The Z9972 is also capable of providing inverted output clocks. When INV_CLK is asserted HIGH, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the Z9972 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output-to-output skew. Glitch-Free Output Frequency Transitions Customarily when output buffers have their internal counter’s changed “on the fly’ their output clock periods will: 1. contain short or “runt” clock periods. These are clock cycles in which the cycle(s) are shorter in period than either the old or new frequency to which they are being transitioned. 2. contain stretched clock periods. These are clock cycles in which the cycle(s) are longer in period than either the old or new frequency to which they are being transitioned. This device specifically includes logic to guarantee that runt and stretched clock pulses do not occur if the device logic levels of any or all of the following pins changed “on the fly” while it is operating: SELA, SELB, SELC, and VCO_SEL. SYNC Output [3] In situations where output frequency relationships are not integer multiples of each other the SYNC output provides a signal for system synchronization. The Z9972 monitors the relationship between the QA and the QC output clocks. It provides a low going pulse, one period in duration, one period prior to the coincident rising edges of the QA and QC outputs. The duration and the placement of the pulse depend on the higher of the QA and QC output frequencies. The following timing diagram illustrates various waveforms for the SYNC output. Note:. 3. The SYNC output is defined for all possible combinations of the QA and QC outputs even though under some relationships the lower frequency clock could be used as a synchronizing signal. Table 2. Frequency Select Inputs

Figure 1. Sync Output Waveforms

the possibility of partial “runt” clocks. Figure 2. SDATA Input Register

Document #: 38-07088 Rev. *D Page 6 of 9 Maximum Ratings [4] This device contains circuitry to protect the inputs against damage due to high static voltages or electric field; however, precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. For proper operation, V IN and VOUT should be constrained to the range: VSS < (VIN or VOUT ) < VDD . Unused inputs must always be tied to an appropriate logic voltage level (either VSS or VDD ). DC Parameters VDD = 2.9V to 3.6V, VDDC = 3.3V ±10%, TA = –40°C to +85°C Parameters Description Conditions Min. Typ. Max. Unit VIL Input LOW Voltage V SS 0.8 V VIH Input HIGH Voltage 2.0 V DD V IIL Input LOW Current[5] –120 µA IIH Input HIGH Current 10 µA VOL Output LOW Voltage[6] IOL = 20 mA 0.5 V VOH Output HIGH Voltage[6] IOH = –20 mA 2.4 V IDDQ Quiescent Supply Current 10 15 mA IDDA PLL Supply Current V DD only 15 20 mA IDD Dynamic Supply Current QA and QB @ 60 MHz QC @ 120 MHz, CL = 30pF 225 mA QA and QB @ 25 MHz QC @ 50 MHz, CL = 30pF 125 C IN Input Pin Capacitance 4 pF Notes: 4. The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required. 5. Inputs have pull-up/pull-down resistors that effect input current. 6. Driving series or parallel terminated 50Ω (or 50Ω to VDD /2) transmission lines.

Table 3. Crystal Oscillator Frequency TA Aging (first 3 years @ 25 °C)[12] 5P P M / Y r .

  1. Parameters are guaranteed by design and characterization. Not 100% tested in production.
  2. Maximum and minimum input reference is limited by VC0 lock range.
  3. Outputs loaded with 30 pF each.
  4. 50Ω transmission line terminated into VDD/2.
  5. Tpd is specified for a 50 MHz input reference. Tpd does not include jitter.
  6. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these
  7. Larger values may cause this device to exhibit oscillator startup problems.

Document #: 38-07088 Rev. *D Page 8 of 9 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Drawing and Dimensions All product and company names mentioned in this document are the trademarks of their respective holders.

Ordering Information

Part Number Package Type Production Flow IMIZ9972BA 52-pin TQFP Industrial, –40°C to +85°C IMIZ9972BAT 52-pin TQFP - Tape and Reel Industrial, –40°C to +85°C 52-lead Thin Plastic Quad Flat Pack(10 × 10 × 1.4 mm) A52 51-85131-**

Document #: 38-07088 Rev. *D Page 9 of 9 Document Title: Z9972 3.3V, 125 MHz Multi-Output Zero Delay Buffer Document Number: 38-07088 Rev. ECN No. Issue Date Orig. of Change Description of Change ** 107124 06/12/01 IKA Convert from IMI to Cypress *A 108066 07/03/01 NDP Changed Commercial to Industrial *B 111798 02/06/02 BRK Convert from Word doc to Adobe Framemaker Cypress format Changed the Timing Diagram and the operating voltage condition *C 116451 08/16/02 HWT Corrected the Ordering Information to match the Dev Master. Changed Pin Configuration diagram label from CY29972 to IMIZ9972. *D 122773 12/21/02 RBI Add power up requirements to maximum ratings information.