CYIFS781BSXC CYPRESS | Alldatasheet

Document overview

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Technical content

Features

  • Spread Spectrum clock generator (SSCG) with 1×, 2×, and 4× outputs
  • 6- to 82-MHz operating frequency range
  • Modulates external clocks including crystals, crystal oscillators, or ceramic resonators
  • Programmable modulation with simple R-C external loop filter (LF)
  • Center spread modulation
  • 3V-5V power supply
  • TTL-/CMOS-compatible outputs
  • Low short-term jitter
  • Low-power Dissipation — 3.3 VDC = 37 mW – typical — 5.0 VDC = 115 mW – typical
  • Available in 8-pin SOIC and TSSOP packages

Applications

  • Desktop/notebook computers
  • Printers, copiers, and MFP
  • Scanners and fax
  • LCD displays and monitors
  • CD-ROM, VCD, and DVD
  • Automotive and embedded systems
  • Networking, LAN/WAN
  • Digital cameras and camcorders
  • M o d e m s Benefits
  • Programmable EMI reduction
  • Fast time to market
  • Lower cost of compliance
  • No degradation in rise/fall times
  • Lower component and PCB layer count Functional Description The Cypress FS781/82/84 are Spread Spectrum clock generator ICs (SSCG) designed for the purpose of reducing electromagnetic interference (EMI) found in today’s high-speed digital systems. The FS781/82/84 SSCG clocks use a Cypress-proprietary technology to modulate the input clock frequency, XIN, by modulating the frequency of the digital clock. By modulating the reference clock the measured EMI at the fundamental and harmonic frequencies of FSOUT is greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory requirements without degrading digital waveforms. The Cypress FS781/82/84 cl ocks are very simple and versatile devices to use. By programming the two range select lines, S0 and S1, any frequency from 6- to 82-MHz operating range can be selected. T he FS781/2/4 are designed to operate over a very wide range of input frequencies and provides 1×, 2×, and 4× modulated clock outputs. The FS78x devices have a simple frequency selection table that allows operation from 6 MHz to 82 MHz in four separate ranges. The bandwidth of the frequency spread at FSOUT is determined by the values of th e loop filter components. The modulation rate is determined internally by the input frequency and the selected input frequency range. The Bandwidth of these products can be programmed from as little as 1.0% up to as much as 4.0% by selecting the proper loop filter value. Refer to the Loop Filter Selection chart in Table 2 and Table 3 for the recommended values. Due to a wide range of application requirements, an external loop filter (LF) is used on the FS78x products. The user can select the exact amount of frequency modulation suitable for the appli- cation. Using a fixed internal loop filter would severely limit the use of a wide range of modulation bandwidths (Spread %) to a few discrete values. Refer to FS791/2/4 products for appli- cations requiring 80- to 140-MHz frequency range. [+] Feedback

other than crystal, leave XOUT (pin 2) unconnected. pull-down. S1 has internal pull-up. passive loop filter is connected to LF. and 4× for FS782 and FS784, respectively. DD P Power Positive Power Supply. SS P Power Power Supply Ground. Table 1. FSOUT SSCG (Modulated Output Clock) Product Selection

8 Pin SOIC Package

8 Pin TSSOP Package

Table 2. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +3.3 VDC ±5% (R6 = 3.3K)[1, 2, 3, 4]

  1. If the value selected from the above chart is not a standard, use the next available larger value.
  2. If C8 is not listed in the chart for a particular ba ndwidth and frequency, it is not used in the loop filter.
  3. Contact Cypress for LF values less than 1.0% bandwidth.

Table 3. FS781/82/84 Recommended Loop Filter Values C7 (pF) @ +5.0 VDC ±5% (R6 = 3.3K)[1, 2, 3, 4]

modulation divider number in Table 4. discussed in the following sections. All clocks generate unwanted energy in their harmonics. lowering the Q of the clock. consider that we have a 20-MHz clock with a 50% duty cycle. Clock Frequency = Fc = 20 MHz. Clock Period = Tc = 1/20 MHz = 50 ns. bandwidth spread of 2%. Refer to Figure 2. Table 4. Modulation Rate Divider Ratios Figure 1. Frequency Profile in Time Domain[5]

  1. With the correct loop filter connected to Pin 4, the following profile will provide the best EMI reduction. This profile can be seen on a Time Domain Analyzer.

sweeping symmetrically around a center frequency of 20 MHz. small and accumulate to achieve the total period deviation. minimum extreme back to the high extreme. the bandwidth of the third harmonic will be 3 × 200, or 600 kHz. greater the energy reduction of the clock. reduction at the higher harmonics, due to a modulated clock. lated clock, by as much as 12 to 18 dB. the loop filter connected to pin 4. Figure 2. 20-MHz Unmodulated Clock

19.8 MHz

20.2 MHz

Figure 3. Spectrum Analysis of 19.8–20.2 MHz Clock Figure 4. Period Comparison Chart

close to LF pin as possible. with 18 pF load capacitance.

20 MHz

Figure 5. FS781 Schematic

fications for operating supply range. Table 5. Absolute Maximum Ratings Table 6. DC Electrical Characteristics VDD = 3.3V and 5.0V ±10%, XIN = 48 MHz, TA = 0°C to 70°C Table 7. Timing Electrical Characteristics VDD = 3.3V and 5.0V ±10%, TA = 0°C to 70°C, CL = 15 pF, XIN = 48 MHz

  1. Single Power Supply: The Voltage on any input or /O pin cannot exceed the power pin during power-up.
  2. Percentage variations from the bandwidth % values given in Table 2 and Table 3.

Table 7. Timing Electrical Characteristics VDD = 3.3V and 5.0V ±10%, TA = 0°C to 70°C, CL = 15 pF, XIN = 48 MHz (continued) Table 8. Range Selection Table

  1. The ordering part number differs from the marking on the actual device.

Document #: 38-07029 Rev. *F Page 10 of 12 Marking Example Package Drawing and Dimensions Cypress FS781BS Date Code, Lot # Cypress FS781BT Date Code, Lot # FS781 B S Cypress Device Driver Revision Package S = SOIC T = TSSOP SEATING PLANE P I N1I D 0.230[5.842] 0.244[6.197] 0.157[3.987] 0.150[3.810] 0.189[4.800] 0.196[4.978] 0.050[1.270] BSC 0.061[1.549] 0.068[1.727] 0.004[0.102] 0.0098[0.249] 0.0138[0.350] 0.0192[0.487] 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249] 1. DIMENSIONS IN INCHES[MM] MIN. MAX. 0° ~8° 0.016[0.406] 0.010[0.254] X 45° 2 . P I N1I DI SO P T I O N A L , ROUND ON SINGLE LEADFRAME RECTANGULAR ON MATRIX LEADFRAME 0.004[0.102]

8 Lead (150 Mil) SOIC S08

  1. REFERENCE JEDEC MS-012 PART # S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG. 4. PACKAGE WEIGHT 0.07gms 8-lead (150-Mil) SOIC S8 51-85066-*C [+] Feedback

Document #: 38-07029 Rev. *F Page 11 of 12 © Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. All product and company names mentioned in this document may be the trademarks of their respective holders. Package Drawing and Dimensions (continued) P I N1I D SEATING PLANE BSC. BSC 0° -8° PLANE GAUGE 2.90[0.114] 1.10[0.043] MAX. 0.65[0.025] 0.20[0.008] 0.05[0.002] 6.50[0.256] 0.076[0.003] 6.25[0.246] 4.50[0.177] 4.30[0.169] 3.10[0.122] 0.15[0.006] 0.19[0.007] 0.30[0.012] 0.09[[0.003] 0.25[0.010] 0.70[0.027] 0.85[0.033] DIMENSIONS IN MM[INCHES] MIN. MAX. 8-Lead Thin Shrunk Small Outline Package (4.40 MM Body) Z8 51-85093-*A [+] Feedback

Document #: 38-07029 Rev. *F Page 12 of 12 Document History Page Document Title: FS781/82/84 Low EMI Spectrum Spread Clock Document Number: 38-07029 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 106948 06/07/01 IKA Convert from IMI to Cypress *A 111654 02/27/02 IKL Add new marking suffix for SOIC packages. Converted to FrameMaker. *B 118355 08/30/02 RGL Swap the location of S0 and S1 in tables 2 and 3 in pages 2,3 and 4. *C 122679 12/14/02 RBI Add power up requirements to operating conditions information. *D 277189 See ECN RGL Added Lead-free Devices *E 314274 See ECN RGL Fixed the Ordering Information to match the DevMaster *F 417662 See ECN RGL Added Maximum Junction Temperature in Absolute Maximum Ratings table [+] Feedback