C9835 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

  • Meets Intel’s Mobile 133.3MHz Chipset  Three CPU Clocks (66.6/100/133.3 MHz, 2.5V)  Six SDRAM Clocks, 1-DCLK (100/133.3 MHz, 3.3V)  Seven PCI Clocks (33MHz, 3.3V), one free running  Two IOAPIC clocks, synchronous to CPU clock (33.3 MHz, 2.5V)  One REF Clock  Two 48-MHz fixed non-SSCG clocks (USB and DOT)  Three 3V66 clocks (66.6 MHz, 3.3V) ICH, HUBLINK, and AGP memory  One selectable frequency for VCH video channel clock (48-MHz non-SSCG, 66.6-MHz CPU-SSCG, 3.3V)  Power management using power-down, CPU stop, and PCI stop pins  Three function select pins (include test-mode select)  Cypress Spread Spectrum for best electromagnetic interference (EMI) reduction  SMBUS support with readback  56-pin SSOP and TSSOP packages Note: 1. These are the frequencies that are selectable after power up using the SEL1 and SEL0 hardware pins. Other frequencies may be chosen using the devices SMBUS interface. See the expanded frequency for a complete listing of all of the availible frequencies. 2. Will be set to 133MHz, when SMBUS Byte3, Bit 0 is set to logic 1.

Table 1. Function Table[1]

0 X 0 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z

0 X 1 TCLK/2 TCLK/2 TCLK/3 TCLK/6 TCLK/2 TCLK TCLK/6

Document #: 38-07303 Rev. ** Page 2 of 18 Note: 3. A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin. If these bypass capacitors are not close to the pins their high-frequency filtering characteristic will be cancelled by the lead inductance of the traces. Pin Description[3] Pin Name PWR Description 1 REF VDD 3.3V 14.318 MHz clock output 3X I N V D D Oscillator buffer input. Connect to a crystal or to an external clock. 4X O U T V D D Oscillator buffer output. Connect to a crystal. Do not connect when an external clock is applied at XIN. 49, 50, 52 CPU(0:2) VDDC 2.5V Host bus clock outputs 7, 8, 9 3V66(0:2) VDD 3.3V Fixed 66.6 MHz clock outputs 12 PCI_F VDDP 3.3V PCI clock output. This clock continues to run when PCI_STP# is at a logic low level. 13, 15, 16, 18, 19, 20 PCI (1:6) VDDP 3.3V PCI clock outputs. These clocks synchronously stop in a low state when PCI_STP# is brought to a logic low level. They synchronously resume running when PCI_STP# is brought to a logic high state. 25, 26 48M(0,1) VDD 3.3V Fixed 48 MHz clock outputs 36 VCH_CLK VDD 3.3V selectable 66.6 MHz or 48 MHz clock output to VCH. Spread spectrum applies only when 66.6 MHz is selected. Select via SMBUS, byte 4 bit7.

34 CPU_STP# VDD

CPU0 stop clock control input. Stops only CPU0 in a low state when asserted low. Using this pin to start and stop CPU0 clock insures synchronous (no short or long clocks) transitioning of this clock.

11 PCI_STP# VDD

PCI stop clock control input. When this signal is at a logic low level (0), all PCI clocks (except PCI_F) stop at a logic low level. Using this pin to start and stop PCI clocks insures synchronous (no short or long clocks) transitioning of these clocks. This pin has no effect on the PCI_F clock. 28, 29 SEL(0,1) VDD 3.3V LVTTL inputs for logic selection. These pins have Internal pull-ups, typically 250k (range 200k to 800k).

30 SDATA VDD

Serial data input pin. Conforms to the SMBUS specification of a Slave Receive/Transmit device. This pin is an input when receiving data. It is an open drain output when acknowledging or transmitting data. See 2-Wire SMBUS Control Interface on page 7. 31 SCLK VDD Serial clock input pin. Conforms to the SMBUS specification. See 2-Wire SMBUS Control Interface on page 7.

32 PD# VDD

3.3V LVTTL-compatible input. When held LOW, the device enters a power down mode. This pin has an Internal Pull-Up. See Power Management Functions on page 3. 33 TEST# VDD 3.3V LVTTL compatible input for selecting test mode. See Table 1. 38 DCLK VDDS 3.3V SDRAM feedback clock output. See Table 1 for frequency selection. See Figure 4 for timing relationship. 39, 40, 42, 43, 45, 46 SDRAM(0:5) VDDS 3.3V SDRAM clock outputs 54, 55 IOAPIC(0,1) VDDI 2.5V IOAPIC clock outputs. See Figure 4 for timing relationships. 37, 44 VDDS 3.3V Power for SDRAM and DCLK clock output buffers 17 VDDP 3.3V Power for PCI clock output buffers 53 VDDI 2.5V Power for IOAPIC clock output buffers 51 VDDC 2.5V Power for CPU clock output buffers 2, 10, 27, 35 VDD 3.3V Common power supply

22 AVDD Analog power

23 AVSS Analog ground

5, 6, 14, 21, 24, 41, 47, 48, 56VSS Common ground pins

the device is in normal running mode and all signals are active. USB clocks are stopped in a low state as soon as possible.

  1. Extended frequencies are only available via SMBUS interface. They are accessable via SMBUS Byte 5 bits 0,1.
  2. 48M(0,1) clocks are constant at 48 MHz and REF is constant at 14.31818 MHz for all table selections.
  3. Will be set to 133 MHz and boosted accordingly, when Byte3,Bit 0 is set to logic 1.

Table 2. Expanded Frequency Selection (MHz)[4, 5, 6]

  1. All internal timing is referenced to the CPU clock.
  2. CPU_STP# signal is an input signal that is made synchronous to free-running PCI_F.
  3. Diagrams shown with respect to 133 MHz. Similar operation when CPU is 100 MHz.

Table 3. Power Management Current

Table 4. Group Timing Relationships and Tolerances

(standard mode) data transfer is supported. when the SCLK signal is low, and is stable when SCLK is high. an 8-bit address. The LSB address Byte = 0 in write mode. The device will respond to transfers of 10 bytes (max) of data. previously set control registers are retained. down, the device retains all SMBUS programming information. Table 4. Group Timing Relationships and Tolerances (continued)

1 BYTE N

1 ACK

Figure 5. SMBus Communications Waveforms

Document #: 38-07303 Rev. ** Page 8 of 18 Serial Control Registers Following the acknowledge of the Address Byte, two additional bytes must be sent: 1) “Command Code “ byte 2) “Byte Count” byte. Although the data (bits) in these two bytes are considered “don’t care,” they must be sent and will be acknowledged. After the Command Code and the Byte Count have been acknowl- edged, the sequence (Byte 0, Byte 1, and Byte 2) described below will be valid and acknowledged. Byte 0 : CPU Clock Register (1 = Enable, 0 = Disable) Bit @Pup [15] Pin#[16] Description 7 1 36 VCH_CLK 6 1 49 CPU2 5 1 50 CPU1 4 1 52 CPU0 30 – Spread Spectrum ( 1 = enabled) 2 1 26 48M1(DOT) 1 1 25 48M0(USB) 00 – Reserved. Set to 0 Byte 1 : SDRAM Clock Register (1 = Enable, 0 = Disable) Bit @Pup [15] Pin#[16] Description 7 0 – Reserved. Set to 0 6 0 – Reserved. Set to 0 5 1 39 SDRAM5 4 1 40 SDRAM4 3 1 42 SDRAM3 2 1 43 SDRAM2 1 1 45 SDRAM1 0 1 46 SDRAM0 Byte 2: 3C66 Clock Register (1 = Enable, 0 = Disable) Bit @Pup [15] Pin#[16] Description 7 1 9 3V66_2 (AGP) 6 1 8 3V66_1 5 1 7 3V66_0 40 – Reserved. Set to 0 3 0 – Reserved. Set to 0 2 0 – Reserved. Set to 0 1 0 – Reserved. Set to 0 0 0 – Reserved. Set to 0 Byte 3: PCI Register (1 = Enable, 0 = Disable) Bit @Pup [17] Pin#[18] Description 7 0 – Reserved. Set to 0 6 12 0 P C I 6 5 11 9 P C I 5 4 11 8 P C I 4 3 11 6 P C I 3 21 1 5 P C I 2 1 11 3 P C I 1 0 0 – SDRAM 133- MHz Mode Enable. Default is disabled = “0,” enabled = “1” Notes: 15. The @Pup column gives the default state at power-up. 16. The Pin# column lists the relevant pin number where applicable.

Byte 5, bits 5, 6, and 7 . See Table 7 below.

  1. The @Pup column gives the default state at power-up
  2. The Pin# column lists the relevant pin number where applicable.

6 0 – Selects spread bandwidth. See Table 5. 50 – Selects spread bandwidth. See Table 5. 1 0 – ESEL1 Expanded Freq. Selection MSB, See Table 2. 0 0 – ESEL0 Expanded Freq. Selection LSB, See Table 2.

2.2 K Device under

Figure 6. SMBUS Test Circuitry[19]

  1. Buffer is 7407 with VCC @ 5.0V.

Figure 7. Spread Spectrum

voltage higher than the maximum rated voltages to this circuit. VSS < (VIN or VOUT ) < VDD . voltage level (either VSS or VDD ).

  1. All outputs loaded per Table 7.
  2. Applicable to input signals : SEL(0:1), PD# (pull-up).
  3. Applicable to SDATA and SCLK.
  4. Internal pull-up and pull-down resistors affect this current.
  5. See Applications data that is presented later in this datasheet on crystal interfacing.

Table 7. Maximum Output Load

Document #: 38-07303 Rev. ** Page 12 of 18 AC Parameters CPU THIGH CPU(0:2) high time [30] 1.87 3.0 5.2 ns TLOW CPU(0:2) low time [31] 1.67 2.8 5.0 ns TSKEW CPU0 to any CPU Skew [26,29] 150 150 150 ps TCCJ CPU(0:2) Cycle to Cycle Jitter[26,29] 250 250 250 ps SDRAM TPeriod SDRAM(0:5) 100 MHz and DCLK THIGH SDRAM(0:5) 100 MHz and DCLK high time[30] 3.0 3.0 3.0 ns TLOW SDRAM(0:5) 100 MHz and DCLK low time[31] 2.8 2.8 2.8 ns Tr / Tf SDRAM(0:5) 100 MHz and DCLK rise and TSKEW SDRAM(0:5) 100 MHzand DCLK Skew [26,29] 250 250 250 ps TCCJ SDRAM(0:5) 100 MHz, DCLK Cycle to Cycle Jitter[26,29] 250 250 250 ps IOAPIC TPeriod IOAPIC(0,1) period[25,26] 30.0 30.0 30.0 ns THIGH IOAPIC(0,1) high time [30] 12.0 12.0 12.0 ns TLOW IOAPIC(0,1) low time [31] 12.0 12.0 N/S 12.0 ns TSKEW IOAPIC(0,1) Skew [26,29] 250 250 250 ps TCCJ IOAPIC(0,1) Cycle to Cycle Jitter[26,29] 500 500 500 ps 3V66 THIGH 3V66-(0:2) high time [30] 5.25 5.25 5.25 ns TLOW 3V66-(0:2) low time [31] 5.05 5.05 5.05 ns TSKEW (Any 3V66) to (any 3V66) Skew [26,29] 175 175 175 ps TCCJ 3V66-(0:2) Cycle to Cycle Jitter[26,29] 500 500 500 ps PCI_F TPeriod PCI(_F,1:6) period[25,26] 30.0 30.0 30.0 ns THIGH PCI(_F, 1:6) high time[30] 12.0 12.0 12.0 ns Notes: 25. This parameter is measured as an average over 1us duration, with a crystal center frequency of 14.31818 MHz. Figure 8). 28. Measured from when both SEL1 and SEL0 are switched to high (enable). 29. This measurement is applicable with Spread ON or Spread OFF. 31. Probes are placed on the pins, and measurements are acquired at 0.4V.

Document #: 38-07303 Rev. ** Page 13 of 18 Notes: 32. The time specified is measured from when all VDD ’s reach their respective supply rail (3.3V and 2.5V) till the frequency output is stable and operating within the specifications. 33. Measured from when both SEL1 and SEL0 are switched to low (disable). 34. Device designed for Typical Duty Cycle of 50%. TLOW PCI(_F, 1:6) low time [31] 12.0 12.0 12.0 ns TSKEW (Any PCI) to (Any PCI) Skew[26,29] 500 500 500 ps TCCJ PCI(_F, 1:6) Cycle to Cycle Jitter[26,29] 500 500 500 ps DOT and USB TPeriod DOT and USB (48M[0,1]) period (conforms to +167 ppm max) [25,26] TCCJ DOT and USB Cycle to Cycle Jitter[26,29] 500 500 500 ps TCCJ VCH_CLK Cycle to Cycle Jitter [26] 250 250 250 ps REF TCCJ REF Cycle to Cycle Jitter[26] 1000 1000 1000 ps tstable All clock stabilization from power-up[32] 333 m s Tduty Duty cycle for all outputs[34] 45 55 45 55 45 55 % AC Parameters (continued)

Table 8. CPU, IOAPIC Table 9. PCI, 3V66, VCH Table 10. 48M0(USB), 481(DOT), REF Table 11. SDRAM (VDD = VDDS = 3.3V ± 5%, VDDC = VDDI = 2.5V ± 5%, TA = 0°C to 70°C)

of the loading specification of a crystal (CXTAL ) for a design. C XTAL = the load rating of the crystal. internal capacitance to ground. internal capacitance to ground.

  1. For best performance and accurate frequencies from this device, it is recommended but not mandatory that the chosen crystal meets or exceeds these
  2. Larger values may cause this device to to exhibit oscillator startup problems.

Table 12. Suggested Oscillator Crystal Parameters

Document #: 38-07303 Rev. ** Page 16 of 18 Therefore, to obtain output frequencies that are as close to this datasheets specified values as possible, in this design example, you should specify a parallel cut crystal that is designed to work into a load of 20pF. Package Diagrams CXINPCB CXOUTPCB CXOUTDISC CXINDISC CXINFTG CXOUTFTG XIN XOUT Clock Generator Figure 9.

Ordering Information

Part Number Package Type Product Flow IMIC9835CY 56-pin Shrunk Small Outlie package (SSOP) Commercial, 0 ° to 70°C IMIC9835CYT 56-pin Shrunk Small Outlie package (SSOP) –Tape and Reel Commercial, 0 ° to 70°C IMIC9835CT 56-pin Thin Shrunk Small Outlie package (TSSOP) Commercial, 0 ° to 70°C IMIC9835CTT 56-pin Thin Shrunk Small Outlie package (TSSOP) –Tape and Reel Commercial, 0° to 70°C 51-85060-B 56-lead Thin Shrunk Small Outline Package, Type II (6 mm x 12 mm) Z56

Document #: 38-07303 Rev. ** Page 17 of 18 © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Package Diagrams (continued) Purchase of I2C components from Cypress, or one of its sublicensed Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Intel is a registered trademark of Intel Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. 56-lead Shrunk Small Outline Package O56 51-85062-C

Document #: 38-07303 Rev. Page 18 of 18 Document Title: C9835 Low-EMI Clock Generator for Intel® Mobile 133-MHz/3 SO-DIMM Chipset Systems Document Number: 38-07373 REV. ECN NO. Issue Date Orig. of Change Description of Change 113556 05/28/02 DMG New Data Sheet (converted from IMI format)