IL800T NVE | Alldatasheet
Document overview
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- PDF pages: 23
Technical content
Features
- DC-correct
- −40 ºC to 125 ºC operating temperature
- 110 Mbps
- 10 ns propagation delay
- 1.3 mA/channel typical quiescent current
- 50 kV/ μs typ.; 30 kV/ μs min. common mode transient immunity
- 44000 year barrier life
- 3 V to 5 V power supplies
- Low EMC footprint
- IEC 60747-17 (VDE 0884-17):2021-10 certified; UL 1577 recognized
- 8-pin MSOP and SOIC packages for one and two channels
- 16-pin QSOP, 0.15" SOIC, and 0.3" True 8™ SOIC for 3, 4, and 5 channels
Applications
- ADCs and DACs
- Digital Fieldbus
- RS-485 and RS-422
- Multiplexed data transmission
- Data interfaces
- Board-to-board communication
- Digital noise reduction
- Ground loop elimination
- Peripheral interfaces
- Parallel bus
- Logic level shifting
Description
IL800-Series isolators are high-speed, high temperature dc-correct isolators. An internal refresh clock ensures the outputs respond to dc states on inputs within a maximum of 9 µs. The devices use NVE’s patented* spintronic Giant Magnetoresistive (GMR) technology. A unique ceramic/polymer composite barrier provides excellent isolation and virtually unlimited barrier life. IL810 IL814 IL821 IL815 IL816 IL811 IL817 IL860
Absolute Maximum Ratings (1) Parameters Symbol Min. Typ. Max. Units Test Conditions Storage Temperature TS −55 150 °C Junction Temperature TJ −55 150 °C Supply Voltage VDD 1, V DD 2 −0.5 7 V Input Voltage VI −0.5 VDD +0.5 V Output Voltage VO −0.5 VDD +0.5 V Output Current Drive IO 10 mA Lead Solder Temperature 260 °C 10 sec. ESD 2 kV HBM Recommended Operating Conditions Parameters Symbol Min. Typ. Max. Units Test Conditions Operating Ambient Temperature TA −40 125 * °C Operating Junction Temperature TJ −40 125 * °C Supply Voltage VDD 1, V DD 2 3.0 5.5 V Logic High Input Voltage VIH 2.4 VDD V Logic Low Input Voltage VIL 0 0.8 V Input Signal Rise and Fall Times (10) tIR , t IF DC -Correct *IL860-1 max. operating ambient and junction temperature is 100 °C; all other part types are 125 °C.
IEC 60747-17 (VDE 0884-17):2021-10 (Basic Isolation; VDE File Number 5016933-4880-0001):
- Isolation voltage (V ISO ): 2500 VRMS
- Transient overvoltage (V IOTM ): 4000 VPK
- Surge rating 4000 V
- Each part tested at 1590 VPK for 1 second, 5 pC partial discharge limit
- Samples tested at 4000 VPK for 60 sec.; then 1358 VPK for 10 sec. with 5 pC partial discharge limit
- Working Voltage (V IORM ; pollution degree 2): Package Part No. Suffix Working Voltage MSOP8 -1 800 V RMS SOIC8 -3 700 V RMS QSOP16 -1 600 V RMS Narrow -body SOIC16 -3 700 V RMS Wide -body SOIC16/True 8 ™ None 600 V RMS Safety-Limiting Values Symbol Value Units Safety rating ambient temperature TS 180 °C Safety rating power (180°C) PS 270 mW Supply current safety rating (total of supplies) IS 54 mA UL 1577 (Component Recognition Program File Number E207481)
- 2500 V rating for all types other than MSOP
- Each part other than MSOP tested at 3000 V RMS (4240 VPK ) for 1 second; each lot sample tested at 2500 VRMS (3530 VPK ) for 1 minute
- MSOP rating 1000 V; tested at 1200 VRMS (1768 VPK ) for 1 second; each lot sample tested at 1500 VRMS (2121 VPK ) for 1 minute Soldering Profile Per JEDEC J-STD-020C, MSL 1
IL810-1/IL810-3 Pin Connections
1 VDD1 Supply voltage
2 IN Data in
3 SYNC
Internal refresh clock disable (normally enabled and internally held low with 10 kΩ)
4 GND 1 Ground return for V DD1
5 GND 2 Ground return for V DD2
6 OUT Data out
(internally held low with 100 kΩ)
8 VDD2 Supply voltage
IL811-1/IL811-3 Pin Connections
2 IN 1 Data in, channel 1
3 IN 2 Data in, channel 2
6 OUT 2 Data out, channel 2
7 OUT 1 Data out, channel 1
2 OUT 1 Data out, channel 1
7 IN 1 Data in, channel 1
IL814-1/IL814-3/IL814 Pin Connections
1 VDD1 Supply voltage 1
2 GND 1
(pin 2 internally connected to pin 8)
3 IN 1 Data in, channel 1
4 IN 2 Data in, channel 2
5 OUT 3 Data out, channel 3
6 NC No connection
Output enable, channel 3 (internally held low with 100 k Ω)
8 GND 1
(pin 8 internally connected to pin 2)
9 GND 2
(pin 9 internally connected to pin 15)
10 NC No connection
11 NC No connection
12 IN 3 Data in, channel 3
13 OUT 2 Data out, channel 2
14 OUT 1 Data out, channel 1
15 GND 2
(pin 15 internally connected to pin 9)
16 VDD2 Supply voltage
IL815-1/IL815-3/IL815 Pin Connections
2 GND 1 Ground return for V DD 1
(pin 2 internally connected to pin 8)
5 IN 3 Data in, channel 3
6 IN 4 Data in, channel 4
7 DNC Do Not Connect (test pin)
8 GND 1 Ground return for V DD 1
(pin 8 internally connected to pin 2)
9 GND 2 Ground return for V DD 2
(pin 9 internally connected to pin 15)
10 DNC Do Not Connect (test pin)
11 OUT 4 Data out, channel 4
12 OUT 3 Data out, channel 3
15 GND 2 Ground return for V DD 2
(pin 15 internally connected to pin 9)
IL816-1/IL816-3/IL816 Pin Connections (pin 2 internally connected to pin 8)
6 OUT 4 Data out, channel 4
Output enable, channels 3 and 4 (internally held low with 100 k Ω) (pin 8 internally connected to pin 2) (pin 9 internally connected to pin 15)
11 IN 4 Data in, channel 4
(pin 15 internally connected to pin 9) IL817-3/IL817 Pin Connections (pin 2 internally connected to pin 8) Output enable, channel 4 (internally held low with 100 k Ω) (pin 8 internally connected to pin 2) (pin 9 internally connected to pin 15) (pin 15 internally connected to pin 9)
2 GND 1 Ground return for V DD1
(pins 1, 2, 7, and 8 internally connected)
3 VDD1 Supply voltage
4 OUT 1 Data out, channel 1
5 IN 2 Data in, channel 2
8 GND 1 Ground return for V DD1
(pins 1, 2, 7, and 8 internally connected)
10 GND 2 Ground return for V DD2
(pins 9, 10, 15, and 16 internally connected)
12 OUT 2 Data out, channel 2
13 IN 1 Data in, channel 1
14 VDD2 Supply voltage
16 GND 2 Ground return for V DD2
(pins 9, 10, 15, and 16 internally connected) IL821 IL860-1 Pin Connections
1 IN 1 Data in, channel 1
(pin 2 internally connected to pin 8)
4 IN 3 Data in, channel 3
5 IN 4 Data in, channel 4
6 VDD1 Supply voltage
7 IN 5 Data in, channel 5
(pin 8 internally connected to pin 2) (pin 9 internally connected to pin 15)
10 OUT 5 Data out, channel 5
(pin 15 internally connected to pin 9) /K49/K4E /K31 /K56 /K44/K44/K32 /K47/K4E/K44 /K31 /K47/K4E/K44 /K32 /K49/K4E /K32 /K4F/K55/K54 /K31 /K49/K4E /K33 /K4F/K55/K54 /K32 /K49/K4E /K34 /K4F/K55/K54 /K33 /K56 /K44/K44/K31 /K49/K4E /K35 /K4F/K55/K54 /K34 /K4F/K55/K54 /K35 /K47/K4E/K44 /K31 /K47/K4E/K44 /K32
tPLH Propagation Delay, Low to High tPHL Propagation Delay, High to Low tPW Minimum Pulse Width tPLZ Propagation Delay, Low to High Impedance tPZH Propagation Delay, High Impedance to High tPHZ Propagation Delay, High to High Impedance tPZL Propagation Delay, High Impedance to Low tR Rise Time tF Fall Time Truth Tables Output Enable VI VOE VO L L L H L H L H Z H H Z SYNC SYNC Internal Refresh Clock
0 Enabled
1 Disabled
Note: SYNC should be left open or connected to GND to enable the internal refresh clock, or connected to V DD to disable the internal clock.
3.3 Volt Electrical Specifications (T min to T max unless otherwise stated)
Parameters Symbol Min. Typ. Max. Units Test Conditions Input Quiescent Supply Current IL810 IDD1 0.06 0.1 mA IL811 0.09 0.15 IL815 , IL860 0.15 0.25 IL812, IL814, IL817, IL821 1.3 1.8 IL816 2.6 3.6 Output Quiescent Supply Current IL810, IL812, IL821 IDD2 1.3 1.8 mA IL811, IL814, IL816 2.6 3.6 IL815 5.2 7.2 IL817 3.9 5.4 IL860 6.8 9 Logic Input Current II − 10 10 µA Logic High Output Voltage VOH VDD − 0.1 VDD V IO = − 20 µA, V I = V IH 0.8 x V DD 0.9 x V DD IO = − 4 mA, V I = V IH Logic Low Output Voltage V OL 0 0.1 V IO = 20 µA, V I = V IL 0.5 0.8 IO = 4 mA, V I = V IL Switching Specifications (V DD = 3.3 V ) Maximum Data Rate 100 110 Mbps CL = 15 pF Pulse Width (7) PW 10 ns VO 50% points; Propagation Delay Input to Output (High to Low) tPHL 12 18 ns C L = 15 pF Propagation Delay Input to Output (Low to High) tPLH 12 18 ns C L = 15 pF Propagation Delay Enable to Output (High to High Impedance) tPHZ 5 ns C L = 15 pF Propagation Delay Enable to Output (Low to High Impedance) tPLZ 5 ns C L = 15 pF Propagation Delay Enable to Output (High Impedance to High) tPZH 5 ns C L = 15 pF Propagation Delay Enable to Output (High Impedance to Low) tPZL 5 ns C L = 15 pF Pulse Width Distortion (2) PWD 2 3 ns CL = 15 pF Propagation Delay Skew (3) tPSK 4 6 ns CL = 15 pF Output Rise Time (10% −90%) tR 2 4 ns CL = 15 pF Output Fall Time (10% −90%) tF 2 4 ns CL = 15 pF Common Mode Transient Immunity (Output Logic High or Logic Low) (4) |CM H|,|CM L| 30 50 kV/µs VCM = 1500 V DC tTRANSIENT = 25 ns Channel -to -Channel Skew tCSK 2 3 ns CL = 15 pF SYNC Internal Clock Off Time (11) tOFF 5 ns Dynamic Power Consumption (6) 140 240 μA/Mbps per channel Magnetic Field Immunity (8) (V DD2 = 3V, 3V<V DD1 <5.5V) Power Frequency Magnetic Immunity HPF 1500 A/m 50Hz/60Hz Pulse Magnetic Field Immunity HPM 2000 A/m tp = 8µs Damped Oscillatory Magnetic Field HOSC 2000 A/m 0.1Hz – 1MHz Cross -axis Immunity Multiplier (9) KX 2.5
5 Volt Electrical Specifications (T min to T max unless otherwise stated)
Parameters Symbol Min. Typ. Max. Units Test Conditions Input Quiescent Supply Current IL810 IDD1 0.1 0.15 mA IL811 0.15 0.25 mA IL815, IL860 0.25 0.35 mA IL814, IL817, IL821 1.8 2.5 mA IL816 3.6 5 mA Output Quiescent Supply Current IL810, IL821 IDD2 1.8 2.5 mA IL811, IL814, IL816 3.6 5 mA IL815 7.2 10 mA IL817 5.4 7.5 mA IL860 9 12.5 Logic Input Current II −10 10 µA Logic High Output Voltage VOH VDD − 0.1 VDD V IO = − 20 µA, V I = V IH 0.8 x V DD 0.9 x V DD IO = − 4 mA, V I = V IH Logic Low Output Voltage V OL 0 0.1 V IO = 20 µA, V I = V IL 0.5 0.8 IO = 4 mA, V I = V IL Switching Specifications (V DD = 5.5 V) Maximum Data Rate 100 110 Mbps CL = 15 pF Pulse Width (7) PW 10 ns VO 50% points Propagation Delay Input to Output (High to Low) tPHL 10 15 ns C L = 15 pF Propagation Delay Input to Output (Low to High) tPLH 10 15 ns C L = 15 pF Propagation Delay Enable to Output (High to High Impedance) tPHZ 5 ns C L = 15 pF Propagation Delay Enable to Output (Low to High Impedance) tPLZ 5 ns C L = 15 pF Propagation Delay Enable to Output (High Impedance to High) tPZH 5 ns C L = 15 pF Propagation Delay Enable to Output (High Impedance to Low) tPZL 5 ns C L = 15 pF Pulse Width Distortion (2) PWD 2 3 ns CL = 15 pF Propagation Delay Skew (3) tPSK 4 6 ns CL = 15 pF Output Rise Time (10% − 90%) tR 1 3 ns CL = 15 pF Output Fall Time (10% −90%) tF 1 3 ns CL = 15 pF Common Mode Transient Immunity (Output Logic High or Logic Low) (4) |CM H|,|CM L| 30 50 kV/µs VCM = 1500 V DC tTRANSIENT = 25 ns Channel -to -Channel Skew tCSK 3 5 ns CL = 15 pF SYNC Internal Clock Off Time (11) tOFF 5 ns Dynamic Power Consumption (6) 200 340 μA/Mbps per channel Magnetic Field Immunity (8) (V DD2 = 5V, 3V<V DD1 <5.5V) Power Frequency Magnetic Immunity HPF 3,500 A/m 50Hz/60Hz Pulse Magnetic Field Immunity HPM 4,500 A/m tp = 8 µs Damped Oscillatory Magnetic Field HOSC 4,500 A/m 0.1Hz – 1MHz Cross -axis Immunity Multiplier (9) KX 2.5
Parameters Symbol Min. Typ. Max. Units Test Conditions Creepage Distance (external) MSOP QSOP 0.15" SOIC (8 or 16 pin) 0.3" SOIC 3.0 4.03 4.03 8.03 8.3 mm Per IEC 60601 Total Barrier Thickness (internal) 0.012 0.013 mm Leakage Current 0.2 µA 240 VRMS , 60 Hz Barrier Resistance RIO >10 14 Ω 500 V Barrier Capacitance CIO 4 pF f = 1 MHz Comparative Tracking Index CTI ≥175 V Per IEC 60112 High Voltage Endurance (Maximum Barrier Voltage for Indefinite Life) AC DC VIO 1000 1500 VRMS VDC At maximum operating temperature Barrier Life 44000 Years 100°C, 1000 V RMS , 60% CL activation energy Thermal Characteristics Parameter Symbol Min. Typ. Max. Units Test Conditions Junction–Ambient Thermal Resistance MSOP8 0.15" SOIC8 QSOP16 0.15" SOIC16 0.3" SOIC16 θ JA 184 134 100 °C/W Double-sided PCB in free air Junction–Case (Top) Thermal Resistance MSOP8 0.15" SOIC8 QSOP16 0.15" SOIC16 0.3" SOIC16 θ JC Junction–Ambient Thermal Resistance 0.3" SOIC θ JA 46 2s2p PCB in free air per JESD51 Junction–Case (Top) Thermal Resistance θ JC 9 Power Dissipation MSOP8 0.15" SOIC8 QSOP16 0.15" SOIC16 0.3" SOIC16 PD 500 675 675 700 1500 mW Notes : 1. Absolute maximum means the device will not be damaged if operated under these conditions. It does not guarantee performance. 2. PWD is defined as |t PHL − tPLH |. %PWD is equal to PWD divided by pulse width. 3. tPSK is the magnitude of the worst-case difference in tPHL and/or t PLH between devices at 25°C. 4. CM H is the maximum common mode voltage slew rate that can be sustained while maintaining V O> 0.8 V DD 2. CM L is the maximum common mode input voltage that can be sustained while maintaining V O< 0.8 V. The common mode voltage slew rates apply to both rising and falling common mode voltage edges. 5. Device is considered a two-terminal device: pins on each side of the package are shorted. 6. Dynamic power consumption is calculated per channel and is supplied by the channel’s input side power supply. 7. Minimum pulse width is the minimum value at which specified PWD is guaranteed. 8. The relevant test and measurement methods are given in the Electromagnetic Compatibility section on p. 12. 9. External magnetic field immunity is improved by this factor if the field direction is “end-to-end” rather than to “pin-to-pin” (see diagram on p. 12). 10. If internal clock is used, devices will respond to DC states on inputs within a maximum of 9 µs. Outputs may oscillate if the SYNC input slew rate is less than 1 V/ms. 11. toff is the maximum time for the internal refresh clock to shut down.
Application Information
Electrostatic Discharge Sensitivity This product has been tested for electrostatic sensitivity to the limits stated in the specifications. However, NVE recommends that all integrated circuits be handled with appropriate care to avoid damage. Damage caused by inappropriate handling or storage could range from performance degradation to complete failure. Electromagnetic Compatibility IsoLoop Isolators have the lowest EMC footprint of any isolation technology. IsoLoop Isolators’ Wheatstone bridge co nfiguration and differential magnetic field signaling ensure excellent EMC performance against all relevant standards. Additionally, on the IL810, the internal clock can be disabled for even better EMC performance. These isolators are fully compliant with IEC 61000-6-1 and IEC 61000-6-2 standards for immunity, and IEC 61000-6-3, IEC 61000-6-4, CISPR, and FCC Class A standards for emissions. Immunity to external magnetic fields is even higher if the field direction is “end-to-end” rather than to “pin-to-pi n” as shown in the diagram below: Cross-axis Field Direction Power Supply Decoupling Both power supplies should be decoupled with 0.1 µF typical (0.047 µF minimum) capacitors as close as possible to the V DD pins. Maintaining Creepage Creepage distances are often critical in isolated circuits. In addition to meeting JEDEC standards, NVE isolator packages have unique creepage specifications. Standard pad libraries often extend under the package, compromising creepage and clearance. Similarly, ground planes, if used, should be spaced to avoid compromising clearance. Package drawings and recommended pad layouts are included in this datasheet. Dynamic Power Consumption IsoLoop Isolators achieve their low power consumption from the way they transmit data across the isolation barrier. A magnetic field is created around the GMR Wheatstone bridge by detecting the edge transitions of the input logic signal and converting them to narrow current pulses. Depending on the direction of the magnetic field, the bridge causes the output comparator to switch following the input logic signal. Since the current pulses are narrow, about 2.5 ns, the power consumption is independent of mark-to-space ratio and solely dependent on frequency. This has obvious advantages over optocouplers, which have power consumption heavily dependent on mark-to-space ratio. DC Correctness, EMC, and the SYNC Function NVE digital isolators have the lowest EMC noise signature of any high-speed digital isolator on the market today because of the dc nature of the GMR sensors used. It is perhaps fair to include opto- couplers in that dc category too, but their limited parametric performance, physically large size, and wear-out problems effectively limit side by side comparisons between NVE’s isolators and isolators coupled with RF, matched capacitors, or transformers. IL800-Series isolators have an internal refresh clock which ensure the synchronization of input and output within 9 μs of the supply passing the 1.5 V threshold. The IL810 allows external control of the refresh clock through the SYNC pin thereby further lowering the EMC footprint. This can be advantageous in applications such as hi-fi, motor control and power conversion. The isolators can be used with Power on Reset (POR) circuits common in microcontroller applications, as the means of ensuring the output of the device is in the same state as the input a short time after power up. Figure 1 shows a practical Power on Reset circuit: Fig. 1. Typical Power-On Reset Circuit for IL810 After POR, the SYNC line goes high, the internal clock is disabled, and the EMC signature is optimized. Decoupling capacitors are omitted for clarity. POR SET OUT SYNC IN IL510 VOE Vdd1 Vdd2 IL810
A delta-sigma A-D converter interfaced with the three-channel IL814. Multiple channels can easily be combined using the IL814’s output enable function. Bridge + Iso SD Out Iso CS Iso SCK Bridge - OSC IL814 CS5532 Clock Generator Bridge Bias Delta Sigma A/D SD Out CS SCK SD OE
12-Bit D/A Converter Isolation The IL815 four-channel isolator is ideally suited for parallel bus isolation. The circuit above uses three IL815s to isolate a 12-bit DAC. /K44/K31 /K44/K32 /K44/K33 /K44/K34 /K44/K35 /K44/K36 /K44/K37 /K44/K38 /K44/K39 /K44/K31/K30 /K44/K31/K31 /K44/K31/K32 Data Bus Latch /K56 /K6F/K75/K74 12-Bit DAC3 x IL815 Latch Latch
Ultraminiature QSOP -16 Package (-1 suffix; 3 and 4 channel) 0.114 (2.90) 0.114 (2.90) 0.016 (0.40) 0.005 (0.13) 0.009 (0.23) 0.027 (0.70) 0.010 (0.25) 0.002 (0.05) 0.043 (1.10) 0.032 (0.80) 0.006 (0.15) 0.016 (0.40) 0.189 (4.80) 0.197 (5.00) 0.122 (3.10) 0.122 (3.10) Dimensions in inches (mm); scale = approx. 5X 0.024 (0.60) 0.028 (0.70) NOTE: Pin spacing is a BASIC dimension; tolerances do not accumulate 0.188 (4.77) 0.197 (5.00) 0.012 (0.3) NOTE: Pin spacing is a BASIC dimension; tolerances do not accumulate 0.054 (1.37) 0.072 (1.83) 0.228 (5.8) 0.244 (6.2) 0.150 (3.8) 0.157 (4.0) 0.052 (1.32) 0.062 (1.57) 0.013 (0.3) 0.020 (0.5) 0.007 (0.2) 0.013 (0.3) 0.016 (0.4) 0.050 (1.3) NOM Dimensions in inches (mm); scale = approx. 5X 0.188 (4.77) 0.197 (5.00) 0.010 (0.25) NOTE: Pin spacing is a BASIC dimension; tolerances do not accumulate 0.060 (1.52) 0.069 (1.75) 0.228 (5.8) 0.244 (6.2) 0.150 (3.8) 0.157 (4.0) 0.050 (1.27) 0.056 (1.42) 0.013 (0.3) 0.020 (0.5) 0.007 (0.20) 0.010 (0.25) 0.020 (0.50) 0.029 (0.75) NOM Dimensions in inches (mm); scale = approx. 5X
0.15" SOIC -16 Package (-3 suffix; 3 and 4 channel) True 8™ 0.3" SOIC -16 Package (no suffix; 2, 3, and 4 channel) 0.386□(9.8) 0.394□(10.0) 0.049□(1.24) 0.051□(1.30) 0.007□(0.2) 0.013□(0.3) Pin□1□identified by either□an indent□or□a marked dot 0.004□(0.1) 0.012□(0.3) 0.016□(0.4) 0.050□(1.3) NOTE: Pin□spacing□is□a□BASIC dimension;□tolerances do□not□accumulate 0.054□(1.4) 0.072□(1.8) 0.228□(5.8) 0.244□(6.2) 0.150□(3.81) 0.157□(3.99) 0.054□(1.37) 0.062□(1.58) 0.013□(0.3) 0.020□(0.5) NOM Dimensions□in□inches□(mm);□scale□=□approx.□5X 0.049 (1.24) 0.051 (1.30) 0.017 (0.43)* 0.022 (0.56) 0.292 (7.42)* 0.299 (7.59) 0.007 (0.18)* 0.010 (0.25) 0.260 (6.60)* 0.280 (7.11) 0.033 (0.85)* 0.043 (1.10) 0.007 (0.2) 0.013 (0.3) Pin 1 identified by either an indent or a marked dot 0.08 (2.0) 0.10 (2.5) 0.397 (10.08) 0.413 (10.49) 0.394 (10.00) 0.419 (10.64) 0.092 (2.34) 0.105 (2.67) 0.004 (0.1) 0.012 (0.3) 0.016 (0.4) 0.050 (1.3) NOTE: Pin spacing is a BASIC dimension; tolerances do not accumulate 0.013 (0.3) 0.020 (0.5) Dimensions in inches (mm); scale = approx. 5X *Specified for True 8™ package to guarantee 8 mm creepage per IEC 60601.
Ultraminiature QSOP -16 Pad Layout 0.025 (0.65) 0.227 (5.77) 0.017 (0.43)
8 PLCS
0.120 (3.05) Dimensions in inches (mm); scale = approx. 5X 0.275 (6.99) 0.050 (1.27) 0.020 (0.51) Dimensions in inches (mm); scale = approx. 5X 0.160 (4.05) 0.275 (6.99) 0.025 (0.635) Dimensions in inches (mm); scale = approx. 5X 0.160 (4.05) 0.012 (0.30)
16 PLCS
0.15" SOIC -16 Pad Layout True 8 ™ 0.3" 16 -pin SOIC -16 Pad Layout 0.050 (1.27) 0.275 (6.99) 0.020 (0.51) 0.160 (4.06) Dimensions in inches (mm); scale = approx. 5X 0.050 (1.27) 0.449 (11.40) 0.020 (0.51) 0.317 (8.05) Dimensions in inches (mm); scale = approx. 5X
Blank = TR7 = 7'' Tape and Reel TR13 = 13'' Tape and Reel Package E = RoHS Compliant Package Type -1 = 8-pin MSOP or 16 -pin QSOP -3 = 0.15'' 8 -pin or 16 -pin SOIC Blank = True -8 0.3'' 16 -pin SOIC TM Temperature Range T = -40 ºC to 100 ºC Channels 10 = 1 Transmit Channel 11 = 2 Transmit Channels 21 = 1 Transmit Channel
1 Receive Channel
14 = 2 Transmit Channels; 15 = 4 Transmit Channels 16 = 2 Transmit Channels;
2 Receive Channels
17 = 3 Transmit Channels;
1 Receive Channels
8 = 110 Mbps, DC -Correct Product Family IL = Isolators 60 = 5 Transmit Channels; -40 ºC to 125 ºC Blank = Tube
Max. Temperature IL810T-1E 1 0 MSOP-8 125 ºC IL810T-3E 1 0 SOIC-8 125 ºC IL811T-1E 2 0 MSOP-8 125 ºC IL811T-3E 2 0 SOIC-8 125 ºC IL814T-1E 2 1 QSOP-16 125 ºC IL814T-3E 2 1 0.15" SOIC-16 125 ºC IL814TE 2 1 True 8 0.3" SOIC-16 125 ºC IL815T-1E 4 0 QSOP-16 125 ºC IL815T-3E 4 0 0.15" SOIC-16 125 ºC IL815TE 4 0 True 8 0.3" SOIC-16 125 ºC IL816T-1E 2 2 QSOP-16 125 ºC IL816T-3E 2 2 0.15" SOIC-16 125 ºC IL816TE 2 2 True 8 0.3" SOIC-16 125 ºC IL817T-3E 3 1 0.15" SOIC-16 125 ºC IL817TE 3 1 True 8 0.3" SOIC-16 125 ºC IL821T-3E 1 1 SOIC-8 125 ºC IL821TE 1 1 True 8 0.3" SOIC-16 125 ºC IL860-1E 5 0 QSOP-16 100 ºC
Change:
- Clarified thermal resistance specifications. IBS-DS-001-IL800-M October 2022 Changes:
- Upgraded to VDE 0884-17 (p. 3).
- Increased Working Voltage ratings based on latest V DE testing (p. 3).
- Changed IL815 pins 7 and 10 from “NC” to “DNC” to c larify they should not be connected (p. 5). IBS-DS-001-IL800-L September 2021 Changes:
- Added five-channel IL860-1.
- Upgrade from VDE V 0884-10 to VDE V 0884-11 / IEC 6 0747-17. IBS-DS-001-IL800-K April 2020 Changes:
- Eliminated IL815 “SYNC” and “OE” functions on lot n umbers >201900.
- Updated EMC standards.
- Revised thermal characteristics (p. 11). IBS-DS-001-IL800-J March 2018 Changes:
- VDE V 0884-10 (VDE V 0884-11 pending).
- MSOP added to UL 1577.
- Updated IL810, IL811, and IL815 input quiescent sup ply current values. SB-DS-001-IL800-I August 2017 Changes:
- Corrected order of package type and temperature ran ge suffixes in chart on p. 19.
- Deleted obsolete fax number. ISB-DS-001-IL800-H March 2017 Changes:
- Corrected 8-pin SOIC package outline dimensions.
- Removed minimum Magnetic Field Immunity specificati on. ISB-DS-001-IL800-G November 2016 Change:
- Updated IEC 60747-5-5 (VDE 0884) certification to V DE V 0884-10. ISB-DS-001-IL800-F June 2014 Changes:
- Added IL814T-1, IL815T-1, and IL816T-1 QSOP version s.
- Dropped IL812 configuration in favor of IL821 two-c hannel bidirectional configuration.
- Updated thermal characteristics.
- Added recommended pad layouts. ISB-DS-001-IL800-E November 2013 Changes:
- Added IL821TE part type (16-pin True8 wide-body pac kage).
- Added output enables to IL816 and IL817.
- Clarified pinouts for different package types.
- IEC 60747-5-5 (VDE 0884) certification.
- Upgraded from MSL 2 to MSL 1. ISB-DS-001-IL800-D August 2013 Changes:
- Tighter quiescent current specifications. Added IL817 part types.
The information and data provided in datasheets shall define the specification of the product as agreed between NVE and its customer, unless NVE and customer have explicitly agreed otherwise in writing. All specifications are based on NVE test protocols. In no event however, shall an agreement be valid in which the NVE product is deemed to offer functions and qualities beyond those described in the datasheet. Limited Warranty and Liability Information in this document is believed to be accurate and reliable. However, NVE does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 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