8155 AMD | Alldatasheet
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2048-Bit Static MOS RAM with I/O Ports and Timer Fa DISTINCTIVE CHARACTERISTICS BH | © 256 word x bits © 2 programmable 8-bit 1/0 ports S| © Single +5 V power supply © 1 programmable 6-bit I/O port = ‘© Completely static operation ‘© Programmable 14-bit binary counter/timer rs © Internal address latch ‘© Multiplexed address and data bus ty GENERAL DESCRIPTION The 8155(H) and 6156(H) are RAM and 1/0 chips to be _1/O ports. One of the three ports can be programmed to be used in the 8085AH MPU system. The RAM portion is ‘status pins, thus allowing the other two ports to operate in designed with 2K bit static celis organized as 256 x B. They handshake mode. have a maximum access time of 400ns to permit use with no wait states in 8O85AH CPU. The 8155H-2 and 8156H-2 A 14-bit programmable counter/timer is also included on have maximum access times of 330ns for use with the chip to provide either a square wave or terminal count pulse ‘8085AH. The |/O portion consists of thres general purpose ~— for the CPU system depending on timer mode. BLOCK DIAGRAM ‘om PORT A Krenn Adeady <> PORT B Keer ALE - port c K =» PCy PCs reser Comer] H THER OUT Vss(0V) 80003810 *8155H = CE, 8156H = CE ‘00034 c 7
3246 Issue Date: April 1967
pe, C1 © 40 [5 Veo 3 pc, C2 39 [7] Pcp ~ TIMER IN (C] 3 38 [-] Pc, Reset C14 37 [7] Po Pc, C45 36 5 Pe, TIMER OUT C] 6 35 [5] PB. om C17 34[7) PBs ceor CE (js 337] PB, em) 32 [7] PB wR CJ10 31 [2 PB, ae 30[-] Pe, AD, (J 12 2917) PB ao, C11 27 Py Ad, (] 15 26 [7 PAs ap, (16 25) Pay aos (J 17 24 [PA AD, (18 23 [7 Pap AD, (J 19 22 [PAY Vss (20 21 [Pag cDoosse4 Note: Pin 1 is marked for orientation. 3-287
o = ORDERING INFORMATION ry Commodity Products g 3 | AMD commodity products are available in several packages and operating ranges. The order number (Valid Combination) is formed {© | byacombination of: a. Temperature Range Es b. Package Type c. Device Number . Speed Option €. Optional Processing «@. OPTIONAL PROCESSING Blank = Standard Processing 8 = Burnin d. SPEED OPTION Blank = 2.5 MHz M22 a Me ©. DEVICE NUMBER/DESCRIPTION 8 155(H)/8156(H) 2o4@sBit Stasc MOS RAM wit 1/0 Posts and Timor b. PACKAGE TYPE P= 40-Ph Plastic DIP (PD 040) D=40-Pin Ceramic DIP (CD 040) ‘&. TEMPERATURE RANGE* Blank = Commercial (0 to + 70°C) |= Industrial (-40 to + 85°C) Valid Combinations (valid Combinations] Valid Combinations list configurations planned to be Nalid Combinations ‘supported in volume for this device. Consult the local AMD [ess sales office to contirm availability of specific valid [arssH | ‘combinations, to check on newly released valid combinations, [euss2 fand to obtain additional data on AMD's standard miltary [sissrz ———} grade products, eee] “This device is also available in Military temperature range. See MOS Microprocessors and Peripherals Military Handbook [ssez2 (Order #09275A/0) for electrical performance characteris- | tics. [e525 | [ ersexe | 3-248
RESET The Reset signal is a pulse provided by the B085AH to initialize the a system. Input high on this fine resets the chip and initializes the three | & 1/0 ports to input mode. The width of RESET pulse should typically be | 600ns. (Two 80B5AH clock cycle times). ~ ‘ADo-AD7 7) ‘These are 3-state Address/Data lines that interface with the CPU lower B-dit Address/Data Bus. The 8-bit address is latched into the address latch on the falling edge of the ALE. The address can be either for the memory section or the I/O section depending on the polarity of the 10/M input signal. The 8-bit data is either written into the chip or road from the chip depending on the status of WRITE or READ input signal. CE OR CE Chip Enable: On the 8155(H) this pin is CE and is active low. On the 8156(H) this pin is CE and is active high. Input low on this line with the Chip Enable active enables the ADo.7 butfers. 1 10/M pin is LOW, the RAM content will be read out to the ‘AD bus. Otherwise, the content of the selected I/O port will be read to the AD bus. Input low on this line with the Chip Enable active causes the data on the AD lines to be written to the RAM or I/O ports, depending on the polarity of 10/M. ALE Address Latch Enable: This contro! signal latches the address on the ‘ADo.7 lines and the state of the Chip Enable and 10/M into the chip at the falling edge of ALE. 7 om 1O/MEMORY Select: This line selects the memory if LOW and selects the 10 if HIGH, PAg-PA7 i) ‘These & pins are general purpose 1/0 pins. The in/out direction is selected by programming the Command/Status Register. PBp-PB7 v0 ‘These 8 pins are general purpose 1/0 pins. The in/out direction is selected by programming the Command/Status Register. 37-39, POp-PC5 i) These 6 pins can function as either input port, output port, or as control 14.2.5 signais for PA and PB. Programming is done through the C/S Register. When PCo.5 are used as control signals, they will provide the following: PCo-A INTR (Port A Interrupt) PC}-A BF (Port A Butter Full) PG2-A STB (Port A Strobe) PCe-B INTR (Port B Interrupt) PC,-B BF (Port B Butter Full) PCs-B STB (Port B Strobe) [eT mmeniy [1] Tis is the timer input to the counter timer, | TIMER This pin is the timer output. This output can be either a square wave or ouT @ pulse depending on the timer mode. a [eo vss | Ground rotenone, 3.249
format is shown below: and RD timing are shown in Strobed 1/0 Timing Diagrams. Figure 3. Command/Status Register Status 1 contents of the C/S Register. Also, depending on the 4. = 1 for output mode. ‘command, this port can operate in either the basic mode or = 0 for input mode. ‘© PC Register — This register has the address XXXXX011 read by a READ operation when appropriately addressed. indicating whether the butfer is full or empty, and the third is the input mode. will provide unpredictable results.
= Table 1, Table of Port Control Assignment 8 [en [ari [Are aT 3 m4 FS [Poo | Input Port | Output Port [A INTR (Port A Interrupt) [A INTR (Port A Interrupt) 4 | PCr | Input Port | Output Por [A BF (Port A Butter Full [A BF (Port A Butfer Full) 5 | Poa | input Por_| Output Port |A STB (Port A Strobe) JA STB (Port A Strobe) [pcs inp Por | Ovput Pon Ouse Pon —————*(BRTR on 8 rerun © BF (or 8 Bur Fu [ros [inet Por | Output Port [output Pon [8 STE (Port 8 Strobe) Timer Section 1 a [ve [mi [ti [te [11 [to | to [te | ‘he timer is a 14-bit down counter that counts the “timer input" pulses and provides either a square wave or pulse when terminal count (TC) is reached. TIMER MODE MSB OS CNT LENGTH The timer has the 1/0 adress 100X100 forthe low order byte of the register and the I/O address XXXXX101 for the Ct high order byte of the register. LSB OF CNT LENGTH To program the timer, the COUNT LENGTH REG is loaded Figure 5. Timer Format first, one byte at a time, by selecting the timer addresses. Bits 0 - 13 will specify the length of the next count, and bits 14-15 M2 and M1 define the timer mode as follows: will specify the timer output mode. The value loaded into the count length register can have any value from 2} through M2 M1 3FFFy in bits 0-13. 0 0 _ Puts out LOW during second half of count. 0 1 Square wave, i.¢., the period of the square There are four modes to choose from: wave equals the count length programmed with automatic reload at terminal count. (0-Puts out LOW during second half of count 1 0 Single pulse upon TC being reached. 1 1 Automatic reload, i.e. single pulse every 1-Square wave time TC is reached. 2-Single pulse upon TC being reached Note: n ease of an asymmetric count, ie. 9, larger half ofthe count wil be HIGH, the larger count will stay active as shown in Figure 5, 3-Repetitive single pulse every time TC is readied and automatic reload of counter upon TC being reached until i} instructed to stop by a new command loaded into C/S. en ee Bits 6 -7 of the Command/Status Register Contents are used to start and stop the counter. There are four commands to choose from. (See the further description on Command/ 4 Status Register.) c/S7 C/S6 5 0 0 _ NOP-Do not affect counter operation. o 4 STOP -NOP if timer has not started; stop \\WF007260 counting if the timer is running. Note: 5 and 4 rotar to the number of clock cycles in that time period. 1 0 STOP AFTER TC-Stop immediately after present TC is reached (NOP if timer has Figure 6. Asymmetric Count not started).
11 START—Load mode and CNT length and The counter in the 8155(H) is not initialized to any particular
start immediately attar loading (it timer is mode or count when hardware RESET occurs, but RESET not presently running). If timer is running, does stop the counting. Therefore, counting cannot begin start the new mode and CNT length imme- following RESET until a START command is issued via the diately after present TC is reached. CIS register. 3-252
Figure 8. 8088 Five-Chip System Configuration
- Cy ABSOLUTE MAXIMUM RATINGS OPERATING RANGES F All Signal Voltages With ‘Supply Voltage (Voc) 2 Stresses above those listed under ABSOLUTE MAXIMUM Supety Curent (oc) 100 ~ RATINGS may cause rent device falure, Functionality BASS BB enn TOD A at or above these limits is not implied. Exposure to absolute ne ‘maximum ratings for extended periods may affect device _ Industrial (I) Devices reliability. Temperature (TA) ...-ssscsssseseessssessseee 40 10 +88°C Supply Voltage (VOC) ...scssesseessesssesneeeseeesS V £10% Operating ranges define those limits between which the functionality of the device is guaranteed. DC CHARACTERISTICS over operating ranges unless otherwise specified Parameters [Description [Test Conattione [win | Max | Unita | A Ship tow Voge [eczema [| as | vom | Cupar Fgh Voge [ow=—100 ia [ee | vo) [| atte [ww=voow ow [| =| mm] ut Leiage Gren 048 v <Vour<vee_ | | 210 | a] [ema] lec Voc Supply Current T= ik W (C8) Chip Enable Leakage Vin = Voc to 0 V SWITCHING TEST INPUT/OUTPUT WAVEFORM * 3 er 20 > ama rest romrd as —/ Le WF007340 Inputs are driven at 2.4 V for a Logic "1" and 0.45 V for a Logic "0". Timing measurements are made at 2.0 V for a Logic "1" and 0.8 V for a Logic "0". SWITCHING TEST CIRCUIT oevice tOER Test T Too02191 GL = 150pF C Includes Jig Capacitance ‘Soe Section 6 for Thermal Charectonstos information 3-255
: oem [maa | | = 8155H, 8156H ‘8155H-2, 8156H-2 3 a | Description [wan [ex [um [mex wf Adtress wo tater Soup time ST] Ts | [ha | Adress Hots Time ator tateh | || [ue | taten to READ/WAITE Conor | 00 tT Ts [tap | Vat Data Out Ooty fom READ Conor | |__| [40 [ns | [ino [Adress Stable to Data Outved | | || 00 [io | taten to eta Outvetos TL mT Tar WRITE to TIMER-IN (For Writes Which Start [iw [ees men rememenes | ow [Of ae [| | [ou taten Erato wae SY tos [or [Bata Bun Flat ater READ] OT too | [es [tc | READIWRITE Conve to Latch Erato] || [ns [ter | WRITE Control to Latch Enable for C/S Regater [vas [as [ns [tec | READIWAITE Conor wien esos | [tow [oma into ware Soup tine | 80 [| oo [ns [wo [Bata inves Tine ator wre ||P s | [clay [Recovery Teme Between conto | of | mo Ts | [we [write te Po Oust TY TT 00s [ier | Pon input soup Tmo Ci Ts | [cine [Por ipa Hols Tine | fT fs [tsar | Swobe wo ButerFul || TT 00s | [ts | Swobe wan TT wo Ts | [woe | READ vo Butorempy TY O00 | [td Srotetw TR On| 00 [wor ReaDionmm ow Tf go Taos [wss [Pon Setup Tine to Supe | || Ts | [Ties | Por Heid Tine ater Swobe ||| too [|e | [“isse | stobe te ButterEmy SST OL 80 | [wer [WATE to Buter Ful | | to cos [cw Pwamew TR on CTY OT t00 os [Tm TIMER to TiMencuTiow || 00 [tm TMERAN to TiMEROUTHgh ||| 00s | [teoz | Data Bus Enabio tom READ Gono | 10 [| [ne | [ts PTNERIN tow ting Po Pe [te TIMER ign Time Tz os 3-256
SWITCHING WAVEFORMS. 3 co {—— 3 a 3 oe a, = “ y>7—7 Me = 8155(H)/8156(H) Read Cycle “me ey, 3 “ SS fe ke l 0 worn 8155(H)/8156(H) Write Cycie 3-257
z SWITCHING WAVEFORMS (Cont'd.) g = ” = tor ‘STROBE | / om “ -“\\ + ~ \\_N 2 vas pp ns vwr007290 Strobed Input Mode ‘STROBE wan te ours eee wr 007201 Strobed Output Mode Input Output oe et wm vou oarasue: — oara sue: XK oun wreore10 wrosraas *Data bus timing is shown in Read/Write Cycle diagrams. Basic I/O Timing Waveform 3-258
SWITCHING WAVEFORMS (Cont'd.) 3 emp Tg ng pmoNpOOMTERMOM CR 3 “ & _ 3 4 4 ~ tere oT ‘nore rn row z 7 (souane wave) Ne! tr oa we007390 Note 1; The timer output is periodic if in an automatic reload mode (My mode bit = 1). Timer Output Waveform Countdown from 5 to 1 3-250