ID2006 CHIPOWN | Alldatasheet

Document overview

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Technical content

Features

 Fully operational to+200 V  3.3V and 5V input logic compatible  dV/dt Immunity ± 50 V/nsec  Gate drive supply range from 6 V to 18 V  Typically Source / Sink current capability 1 A/1 A  Typically -9V negative Vs bias capability Package/Order Information ID2006

4 LOCOM

VDC, up to 200V M LOCOM LIN HIN VCC VB HO VS MCU 15V Rcs U Rcs W IF U IF V IF W BSDRB Q3 Q5 Q6Q4 Note 1: RB value suggest 10 ohms, ultra fast recovery or schottky diode should be used as BSD Note 2: CBS value according to PWM control condition Note 3: Driver circuit should be adjust according to the MOSFETs be used Note 4: Pull down resistor between Gate and Source of MOSFETs, 10k ohms is suggested Note 5: Resistors between HIN/LIN and MCU, recommended value is 100 to 1k ohms

www.chipown.com Wuxi Chipown Microelectronics Limited Rev.1.0 2/7 Pin Definitions Pin Name Pin Number Pin Function Description VCC 1 Low side and main power supply HIN 2 Logic input for high side gate driver output (HO) LIN 3 Logic input for low side gate driver output (LO) COM 4 Ground LO 5 Low side gate drive output, out of phase with LIN VS 6 High side floating supply return or bootstrap return HO 7 High side gate drive output, in phase with HIN VB 8 High side floating supply Block Diagram UVLO Delay Pulse Generator Noise filter R R S Q UVLO DriverDriver Dead Time HIN LIN COM LO VCC VS HO VB

www.chipown.com Wuxi Chipown Microelectronics Limited Rev.1.0 3/7 Absolute Maximum Ratings Exceeding these ratings may damage the device. The absolute maximum ratings are stress ratings only at TA=25° C, unless otherwise specified. Symbol Definition MIN. MAX. Units VB High side floating supply -0.3 220 V VS High side floating supply return VB – 20 VB + 0.3 VHO High side gate drive output VS – 0.3 VB + 0.3 VCC Low side and main power supply -0.3 20 VLO Low side gate drive output -0.3 VCC + 0.3 VIN Logic input of HIN & LIN -0.3 VCC + 0.3 ESD HBM Model 1.5 -- kV CDM Model 500 -- V RthJA Thermal Resistance Junction to Ambient -- 200 ° C /W TJ Junction Temperature -- 150 °C TS Storage Temperature -55 150 TL Lead Temperature (Soldering, 10 seconds) -- 300 Recommended Operating Conditions Symbol Definition MIN. MAX. Units VB High side floating supply VS + 6 VS + 18 V VS High side floating supply return -9 200 VHO High side gate drive output voltage VS VB VCC Low side supply 6 18 VLO Low side gate drive output voltage 0 VCC VIN logic input voltage (HIN & LIN) 0 VCC TA Ambient temperature -40 125 °C

www.chipown.com Wuxi Chipown Microelectronics Limited Rev.1.0 4/7 Dynamic Electrical Characteristics VBIAS (VCC, VBS) = 15V, CL = 1000 pF and TA = 25° C unless otherwise specified. Symbol Definition MIN TYP. MAX. Units tON High & low side turn on propagation delay -- 150 250 ns tOFF High & low side turn off propagation delay -- 110 250 MT Delay matching time (tON, tOFF) -- -- 50 DT Dead time -- 300 -- tR Turn on rising time -- 60 100 tF Turn off falling time -- 60 100 Static Electrical Characteristics VBIAS (VCC, VBS) = 15V, CL = 1000 pF and TA = 25° C unless otherwise specified. Symbol Definition MIN. TYP. MAX. Units ILK High-side floating supply leakage current -- -- 50 μA IQBS Quiescent VBS supply current -- 70 120 IQCC Quiescent VCC supply current -- 200 280 UVCCT VCC supply under-voltage trigger voltage 4.4 5.0 5.6 V VUVCCHY VCC supply under-voltage hysteresis -- 0.3 -- UVBST VBS supply under-voltage trigger voltage 3.2 3.8 4.4 VUVBSHY VBS supply under-voltage hysteresis -- 0.3 -- VOH High level output voltage drop, VBIAS - VO -- -- 0.2 V VOL Low level output voltage drop, VO -- -- 0.1 IO+ Output High short circuit pulsed current -- 1 -- A IO- Output low short circuit pulsed current -- 1 -- VIH High level input threshold voltage 2.5 -- -- V VIL Low level input threshold voltage -- -- 0.8 IIN+ Logic “1” input bias current (HIN “1” & LIN “1”) -- 10 20 μA IIN- Logic “0” input bias current (HIN “0” & LIN “0”) -- 15 30

www.chipown.com Wuxi Chipown Microelectronics Limited Rev.1.0 5/7 Function Timing Diagram LIN HIN LO HO Fig.1 Input and output timing waveform HIN/LIN HO/LO 15V 10% 90% 50% ton 50% tof f tftr Fig.2 Propagation and Rise/Fall time definition 10% 90% 50%50% LO HO MT LO HO MT 15V 15V 5VHIN/LIN Fig.3 Delay matching definition

www.chipown.com Wuxi Chipown Microelectronics Limited Rev.1.0 6/7

Package Information

D A2 A A1 L θc 0.25 b e B B E1 E BASE METAL SECTION B-B WITH PLATING b c1 c h Size Symbol Min. （mm） Typ. （mm） Max. （mm） Size Symbol Min. （mm） Typ. （mm） Max. （mm） A - - 1.75 D 4.70 4.90 5.10 A3 0.60 0.65 0.70 e 1.27BSC b 0.39 - 0.48 h 0.25 - 0.50 c 0.21 - 0.26 L1 1.05BSC c1 0.19 0.20 0.21 θ 0 - 8° Top mark Package iDR. ID2006 YWWXXXXX SOP8 Note：Y：Year Code；WW：Week Code；XXXXX：Internal Code Notes: 1. This drawing is subjected to change without notice. 2. Body dimensions do not include mold flash or protrusion.

www.chipown.com Wuxi Chipown Microelectronics Limited Rev.1.0 7/7 Important Notice Wuxi Chipown Microelectronics Co. Ltd. reserves the right to make changes without further notice to any products or specifications herein. Wuxi Chipown Microelectronics Co. Ltd. does not assume any responsibility for use of any its products for any particular purpose, nor does Wuxi Chipown Microelectronics Co. Ltd assume any liability arising out of the application or use of any its products or circuits. Wuxi Chipown Microelectronics Co. Ltd does not convey any license under its patent rights or other rights nor the rights of others.