IBIS4-1300

IBIS4-1300 CYPRESS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 37

Technical content

Features

• SXGA resolution: 1280 x 1024 pixels
• High sensitivity 20 µV/e-
• High fill factor 60%
• Quantum efficiency > 50% between 500 and 700 nm.
• 20 noise electrons = 50 noise photons
• Dynamic range: 69 dB (2750:1) in single slope operation
• Extended dynamic range mode (80…100 dB) in double slope integration
• On-chip 10 bit, 10 mega Samples/s ADC
• Programmable gain & offset output amplifier
• 4:1 sub sampling viewfinder mode (320x256 pixels)
• Electronic shutter
• 7 x 7 µm 2 pixels
• Low fixed pattern noise (1% Vsat p/p)
• Low dark current: 344 pA/cm2
• (1055 electrons/s, 1 minute auto saturation)
• RGB or monochrome
• Digital (ADC) gamma correction Part Number Part Number Package Glass lid RGB/B&W CYII4SC1300AA-QSC LCC S8612 RGB Bayer pattern CYII4SM1300AA-QDC LCC D263 B&W [+] Feedback [+] Feedback

Document Number: 38-05707 Rev. *B Page 2 of 37 TABLE OF CONTENTS LIST OF FIGURES Typical transfer characteristic of the output amplifier (no clipping, Voffset = 2 V, input signal during offset [+] Feedback [+] Feedback

Document Number: 38-05707 Rev. *B Page 3 of 37 Transmission characteristics of the BG39 glass used as NIR cut-off filter for the FUGA1000 color image Transmission characteristics of the D263 glass used as protective cover for the IBIS4-1300 monochrome LIST OF TABLES Co-ordinate of the row or column selected by the Y/X shift registers after a # clock periods in viewfinder [+] Feedback [+] Feedback

Figure 1. Architecture of the image sensor core

Note 1. The pixel rate can be boosted to 37.5 MHz. This requires a few measures.

• increase the analog bandwidth by halving the resistor on pin Nbias_oamp
• increase the ADC speed by the resistors related to the ADC speed (nbiasana1, nbiasana2, pbiasencload)
• experimentally fine tune the relative occurrence of the ADC clock relative to the X-pixel clock. Note 2. The pure digital scan speed in X and Y direction is roughly 50 MHz. This is the maximum speed for skipping rows and columns. Light sensitivity & detection Spectral sensitivity range 400 - 1000 nm Spectral response * fill factor 0.165 A/W @ 700 nm Quantum efficiency * fill factor > 30% between 500 & 700 nm Fill factor 60% Charge-to-voltage conversion gain 20 µV/e Output signal amplitude 1.2 V Full well charge [electrons] IBIS4-1300: about 90000 saturation, 50000 linear range Noise equivalent flux at focal plane (700 nm) 1.1e-4 lx*s (at focal plane) 6.3 e-7 s.W/m2 Sensitivity 7 V/lx.s 1260 V.m2/W.s MTF @ Nyquist frequency 0.4-0.5 @ 450 nm 0.25-0.35 @ 650 nm Optical cross talk 10% to 1 st neighbor 2% to 2nd neighbor Image quality Temporal noise (dark, short integration time) 20 noise electrons = 50 peak noise photons (*) 400 µV RMS Dynamic range (analog output, before ADC conversion) 2750:1 69 dB Dark current 344 pA/cm 2 @ 21ºC 19 mV/s 1055 electrons/s Dark current non-uniformity Typically 15% RMS of dark current level. Fixed pattern noise (dark, short integration time) 9.6 mV peak-to-peak 1-2 mV RMS Photo-response non-uniformity (PRNU) 10% peak-to-peak @ ½ of saturation signal

Table 1. optical & electrical characteristics

**Figure 3. Spectral response * fill factor of the IBIS4-1300 pixels**

Figure 5. IBIS4-1300 response curve - two pixels - lowest gain setting (0000)

Figure 5. shows the pixel response curve in linear response 138.75 ms (10 MHz pixel rate), at minimal gain setting 0000. mode of operation is not further documented. Table 2. shows the pins of the IC that are related to the image sensor core, describing their functionality. Table 2. Pins of the image sensor core

offset level. Gain and offset are controlled by 4-bit wide words. The offset setting is independent of the gain setting. The gain setting is independent of amplifier bandwidth. MHz and is located between 1.2 and 2.4 V. Table 3. summarizes the specifications of the amplifier.

• Default: connect to ground. The anti blooming is operational but not maximal.
• Apply about 1 V DC for improved anti-blooming Power & ground VDD_RESETL 59 Power supply for left reset line drivers apply 5 V DC (default) or about 4…4.5 V for dual slope mode VDD_RESETR 79 Power supply for right (default) reset line drivers 5 V DC VDD_ARRAY 55 Power supply for the pixel array 5 V DC VDD 11 Power supply of image sensor core & output amplifier 5 V DC GND 10 Ground of image sensor core & output amplifier

Table 3. Summary of output amplifier specifications

12 MHz

22 MHz

33 MHz

40 V/ µs 50 V/ µs8 0 V / µs

Table 4. Pins involved in output amplifier circuitry Vlow_dac 14 Low and high references for offs et control DAC of the analog output. Nbias_oamp 27 Output amplifier speed/power.

Figure 9. output amplifier DC gain

1. report all gain settings.

output amplifier bandwidth for all gain settings. Table 5. DC gain of output amplifier for different gain settings

The ADC converts on the falling edge of the CLK_ADC clock. Figure 13. ADC timing becomes valid 50 ns after the falling edge on TRI_ADC. When NONLINEAR is high, the ADC conversion is non-linear. bright areas, similar to gamma correction. Table 7. pins of the ADC

Then Z is an 11-bit linear output in the range 0...2047. Figure 15. typical operation mode (readout of a frame)

Figure 15. shows a typical operation mode of the image At the start of a new frame, the device may be (re-)configured. or the device is put in viewfinder mode. part of the first row blanking sequence. (SYNC_X) of the X-direction shift register. time. The integration is thus a multiple of the row readout time. The reset shift register always leads the readout shift register. be invalid. We will now discuss all steps in more detail.

• output amplifier offset level, set by 'dac_bit[0...3]'
• output amplifier gain setting, set by 'gc_bit[0...3]'
• choose the integration time of the next frame
• set/clear viewfinder mode (pin 'subsampl')
• in case when the fast adjustment of the offset level is used, plus 'calib_f' and 'unitygain' as described before in figures

Figure 7. and Figure 8. pixels read at all 4 borders of the image.

256 QVGA image sensor with one dummy pixel at the start of

Table 8. shows which column or row is selected after a synchronization- or start pulse. (sync_x, sync_yr, sync_yl). register selects a new row for readout or reset. Figure 16. Table 8. co-ordinate of the row or column selected by the Y/X shift registers after a # clock periods in viewfinder mode Viewfinder mode None None Row 1 Row 5 Row 9 Row 13 Row 17 Y reg. Full image mode None None Row 1 Row 2 Row 3 Row 4 Row 5 Y reg.

• The next row (=line) is selected after the falling edge of CLK_YR and CLK_YL,
• The column amplifiers receive the signals on the pixels array columns buses when SHY is low (transparent).
• The SIN pulse (high) forces the column amplifiers in an “offset nulling" state.
• After 3 us, the column amplifiers have reached offset-free equilibrium, and the SIN pulse is brought low again. The pixel's signal level is thus stored in the column amplifier.
• After that the pixels in the selected row (line) are be reset (first pulse on RESET).
• Consequently the reset level is frozen in the column amplifiers when SHY goes high. Both signal level and reset level have now been applied to the column amplifiers. The sample hold (SHY) guarantees that this information will not change anymore during readout of the line.
• Now, the row is ready for readout. A pulse on SYNC_X must be given to start the row readout. SYNC_X initiates the X-direction scanning register. The scanning itself is controlled by CLOCK_X.
• During the beginning of the row readout, or possibly before, the RESET pulse for the electronic shutter (ES) must be given, if the ES is used. This is a pulse on RESET together with a high level on L/R. If the ES is not used, L/R remains low and the second RESET pulse is not generated. During some or the entire row blanking times, the output amplifier can be calibrated. If the slow calibration method is used, pulse the 'CALIB_S' pin once per line. The calibration happens on the rising edge of the pulse. If the fast calibration is used, the 'CALIB_F' should be pulsed during the row blanking time of the first row only. This calibration happens during the time that the pulse is high. During this calibration, the input applied to the amplifier must be the dark reference, which can either be the built-in electrical dark reference, or an exter nal dark reference on the pin EXTIN.

Figure 19. Pulse on 'CALIB_F'& 'UNITYGAIN' to be given once per frame, or on CALIB_S once per line The X shift register behaves like the Y shift registers. be taken equal to some other pulse (e.g. CLOCK_Y).

Document Number: 38-05707 Rev. *B Page 29 of 37 Pin configuration Pin list Signal type symbols A Analog D Digital W Word bit I/O Symbols I Input O Output P Power supply G Ground No. Name Type I/O Description Signal

1 Nbiasarray A I 1MEG to VDD and decouple to GND Pixel source follower bias current

2 pbias2 A I 1MEG to GND and decouple to VDD Column amp 1st source follower (after SHY) bias current

3 Pbias A I 1MEG to GND and decouple to VDD Column amp current source bias current

4 xmux_nbias A I 100K to VDD and decouple to GND X-multiplexing bias current (/6)

5 Sync_yr\\ D I low active (0=sync) 0 = reset right shift register

6 clk_yr D I Shifts on falling edge clock right shift register

7 Eos_yr\\ D O Active low low 1st clk_yr pulse after last row

8 Eos_x\\ D O Active low low 1st clk_x pulse after last active column

9 Selextin D I input selector for output amp lifier 1 = external input; [0] = imager core

10 Gnd A G Analog GND

11 Vdd A P Analog VDD + 5 V DC

12 Extin A I external input to output amplifier

13 Output A O analog output of imager core Connect to in_adc (p73)

14 Vlow_dac A I low reference voltage offset DAC +/- 1 V

15 Vhigh_dac A I high reference voltage offset DAC +/- 2.5 V

16 Calib_s D I Slow dark offset level adjustment 0: connect to cap (st2) and in- (st1)

1: connect to rdac (st2) and output (st1) 17 gc_bit0 W I Lsb gain control output amplifier 18 gc_bit1 W I 19 gc_bit2 W I 20 gc_bit3 W I Msb

21 Unitygain D I sets output amplifier in unity gain High active

22 Calib_f D I fast dark offset level calibration High active

23 Dac_b3 W I Msb dac control for black offset level

24 Dac_b2 W I dac control for black offset level

25 Dac_b1 W I dac control for black offset level

26 Dac_b0 W I Lsb dac control for black offset level

27 Nbias_oamp A I 100K to VDD and decouple to GND output amplifier bias current

28 Sync_x\\ D I low active (0=syn c) 0 = reset X shift register

[+] Feedback [+] Feedback

Document Number: 38-05707 Rev. *B Page 30 of 37 29 clk_x D I Shifts on falling edge clock X shift register 30 shy D I Column parallel track and hold 1 = hold; 0 = track 31 dccon A I control voltage for DC reference generation Connect to GND (default) 32 dcref A O reference voltage Should be +/- 1.2 V, depends on dccon 33 gnd A G 34 vdd A P 35 sin D I Column amplifier calibration sign al 1 = calibrate, see timing diagram 36 sync_y\\l D I 0 = start left shift register low active (0=sync) 37 clk_yl D I clock left shift register Shifts on falling edge 38 eos_yl\\ D O low 1st clk_yl pu lse after last row Active low 39 bitinvert D I High active, 1 = invert bits inverts ADC output bits 40 select D I High active selects row indicated by left/right shift register 41 reset D I High active resets row indicated by left/right shift register 42 d9 W O MSB ADC output 43 d8 W O 44 d7 W O 45 d6 W O 46 d5 W O 47 d4 W O 48 d3 W O 49 d2 W O 50 d1 W O 51 d0 W O LSB 52 gnd A G 53 vdd A P + 5 V DC 54 gnd_ab A G Anti-blooming drain voltage GND or +1V for improved anti-blooming 55 vdd_array A P + 5 V DC Pixel power supply 56 vdd_dig D P + 5 V DC ADC digital power supply 57 gnd_dig D G ADC ground of digital circuits 58 vdd_an A P + 5 V DC ADC analog power supply 59 vdd_resetl A P 5 V DC default (5.5 V for large output swing) 4…4.5 V for double slope mode VDD for reset by left shift register 60 gnd_an A G ADC ground of analog circuits 61 vhigh_adc A I + 4 V DC High ADC reference voltage No. Name Type I/O Description Signal [+] Feedback [+] Feedback

Document Number: 38-05707 Rev. *B Page 31 of 37 Bonding pad geometry for the IBIS4-1300

• The 84 pins are distributed evenly around the perimeter of the Chip. At each edge there are 21 pins. Pin 1 is (in this drawing) in the middle of the left edge.
• The opening in the bonding pads (the useful area for bonding) is 200 x 150 um.
• The centers of the bonding pads are at all four edges at 150 um distance from the nominal chip border.
• The scribe line (=the spacing between the nominal borders of neighboring chips) is 250 um.
• The bonding pad pitch is 437 um in X-direction
• The bonding pad pitch in Y-direction is 393 um 62 clk_adc D I ADC Clock Converts on falling edge 63 tri_adc D I ADC output tristate control 1=tristate; 0=output 64 pbiasdig1 A I 100K to GND and decouple to VD D current bias for comparator after encoder 65 pbiasencload A I 100K to GND and decouple to VDD current bias for encoder 66 pbiasdig2 A I 100K to GND and decouple to VDD current bias for digital logic in columns 67 nonlinear D I high active (1 = non-linear conversion) control for non-linear behavior of sensor 68 n.c. not connected 69 nbiasana2 A I 100K to VDD and decouple to GND bias current 2nd comparator stage 70 nbiasana A I 100K to VDD and decouple to GND bias current 1st comparator stage 71 vlow_adc A I + 2 V DC, +-2 K between P71 and P61 Low ADC reference voltage 72 gnd_an A G ADC ground of analog circuits 73 in_adc A I Converts between vlow and vhigh (2-4V) ADC input 74 vdd_an A P + 5 V DC ADC analog power supply 75 gnd_dig D G ADC ground of digital circuits 76 vdd_dig D P + 5 V DC ADC digital power supply 77 vdd A P + 5 V DC 78 gnd A G 79 vdd_resetr A P 5 V DC default (5.5 for large signal swing) Power supply for reset by right (readout) shift register

80 L/R\\ D I 1=left; 0=right Selects left or right shift register for 'select'

and 'reset'

81 Pixel diode A O groups current of 24 x 18 pixels Test structure for spectral response

82 Photodiode A O 168x126 um2 (eq. 24 x 18 pi xels) Test structure for spectral response measurement of photodiode 83 clip A I Clips if output > 'clip' - Vth (P MOS) Clipping voltage for output amplifier 84 subsmpl D I high active, 1 = subsampling Selects viewfinder mode (1:4 = 320 x 256) No. Name Type I/O Description Signal [+] Feedback [+] Feedback

Document Number: 38-05707 Rev. *B Page 32 of 37

• Relative position of pads in corners: see next figure (measures in um). Color filter geometry Sensors with diagonal pattern have
• -pixel (1,1) is RED
• -first line sequence is BGRBGR
• -second line sequence is RBGRBG B sensors with Bayer pattern have
• -pixel (1,1) is GREEN
• -first line sequence is .GRGRG
• -second line sequence is .BGBGB 393 468 437 627 474 635 10158 9265 150 [+] Feedback [+] Feedback

Figure 28. Pin layout and package, top view

Document Number: 38-05707 Rev. *B Page 35 of 37

Ordering Information

Temperature dependence of dark signal The above graph is measured on an IBIS4-1300 under nominal operation, using breadboa rd. This particular sensor has about 100 "bad pixels" at RT. Average offset (=dark signal) and RMS (=FPN of dark signal) are measured versus temperature. Offset is referred to the "short tint" offset at 20 C. Integration time was 160 ms (= "long tint"). Y-axis is the output signal (100% = ADC range) Useful range of "double slope" Which total dynamic range can reasonably be obtained with the dual slope feature of the IBIS4-1300? Assuming that the "regular" S/N is 2000:1, and that one can put the knee point halfway the voltage range, the each piecewise linear halve has 1000:1 S/N. If the ratio between slopes is a, then the total dynamic range becomes (1000+a*1000):1. Example, is a=10, then t he total dynamic range becomes 11000:1. Table 10. FillFactory and Cypress part numbers

Document Number: 38-05707 Rev. *B Page 36 of 37 In practice, acceptable images are obtained with a up to 10. Larger a's are useable, but near the knee, contrast artifacts become annoying. Skipping rows or columns Although these modes are not described in the datasheets, it is possible to skip rows or columns by simply applying additional CLK_YR + CLR_YL, or CLK_X pulses. The maximum clock frequency is not documented. But it is probable that one can reach at least 10 MHz in Y and 40 MHz in X. Disclaimer FillFactory image sensors are only warranted to meet the specifications as described in the production data sheet. Specifications are subject to change without notice. [+] Feedback [+] Feedback

Document Number: 38-05707 Rev. *B Page 37 of 37 Document History Page Document Title: 1.3 MPxl Rolling Shutter CMOS Image Sensor Document Number: 38-05707 REV. ECN. Issue Date Orig. of Change Description of Change ** 310213 See ECN SIL Initial Cypress release *A 509557 See ECN QGS Converted to Frame file *B 642577 See ECN FPW Ordering information update [+] Feedback [+] Feedback