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2.8 Volt x16 Very Low Power Dual-Port Static RAM

Key Features:

Very low power true Dual-Port Static RAM with high speed access
Simultaneous memory access through two ports
LVTTL compatible; 2.8V power supply
Bus Width can easily expand to over 16 bits by using both MASTER and SLAVE select function
Interrupt, Semaphore , and Busy Logic
Supports Interrupt and Semaphore arbitration scheme s
Available packages: 108 ball 8mmx8mm 0.5mm pitch BGA and 84 ball 7mmx7mm 0.5mm pitch BGA
(-40°C to 85°C) Industrial operating temperature available for access time of 55ns Product Description: The HDV24VL Dual-Port Static RAM offers industry leading CMOS process technology and 4K x 16 memory configuration. The device supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. System designer has full flexibility of implementing deeper and wider memory using the depth and width expansion features. The HDV24VL is a stand alone 4K x 16 Asynchronous Dual-Port SRAM. For 32 bits or more bus width, the MASTER/SLAVE pin offers bus width expansion without additional discrete logic. Bus width expansion can easily be done without external logic. The device has low power consumption, hence minimizing system power requirements. It is ideal for applications such as data communication, telecommunication, multiprocessing, test equipment, network switching, etc.

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 3 of 3 A B C D E F G H J K 1 2 3 4 5 6 7 8 9 10 I/O7L I/O10L I/O11L I/O13L I/O12LI/O15L I/O14L VCC I/O5L I/O8L I/O9L GND GND I/O4L I/O6L I/O2LI/O3L I/O0L I/O1L GND I/O0R I/O1R I/O3RI/O5R I/O6RI/O8R I/O2RI/O4RI/O7R I/O9R I/O11R I/O12R I/O10R I/O13R I/O15R I/O14R OER SEMR R/WR UBRCER LBR SEML CEL R/WL OEL UBL LBL A11L A9L A10L A8L A7L A5L A6LA3L A4LA2L BUSYL A11R A8R A6R A4R A10R A9R A7R A2R A5R A1RA3R A0R A0L INTFL M/S INTFR BUSYR A1L HDV24VL BZ108 Top View VCC VCC GND GND VCC VCC GND 11 12 13 14 NC L M N P NC NC NC NC NC NC NC NCVCC NC VCC GND GND GND VCCGND VCCNC GND GND GND NC VCC Top View Figure 3.108 -Ball 0.5mm Pitch BGA (Order code: BZ )

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. All VCC connect to power supply and all GND connect to ground supply. Figure 4. Device Pin -Out

Absolute Max Ratings are for reference only. Permanent damage to the device may occur if

Recommended Operating Condition s.

VTERM must not exceed V CC +0.3V for more than 25% of the cycle time or 10ns

maximum , and is limited to <+ 20Ma for the period over V TERM =VDD+ 0.3V. Table 2. Absolute Maximum Ratings

TA is the “ instant on ” case temperature.
CIN and COUT are determined by device characterization , not production tested.

Table 3. Operating conditions

Eight semaphore flags are addressed by A0 -A2.

Table 7. Truth Table – Semapho re Read/Write Control must be initialized at power -up. Table 8. Truth Table – Interrupt Flag

If inputs to opposite port were stable prior to address and enable inputs of this port, then “L.” If inputs to the opposite port became stable after the address the enable inputs of
Writes to one port are internally ignored when its BUSY

outputs are LOW regardless of actual logic level on the pin. Table 9. Truth Table – Address BUSY NOTES: 1. Table shows sequence of events for one of the eight semaphores.

There are eight semaphore flags (A 0-2) written via I/O 0 and read from I/O0-15.

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 11 of 11 Timing Diagrams ADDR Valid Data(4) tRC t AA (4) t ACE (4) CE OE UB, LB R/W DATAOUT BUSYOUT t AOE(4) t ABE (4) t LZ (1) tBDD (3,4) t HZ (2) tOH NOTES: 1. tLZ timing is bases on which signal is asserted last, CE ,OE , LB or UB 2. tHZ timing is bases on which signal is de -asserted first, CE ,OE , LB or UB 3. tBDD is needed only where the opposite port is completing a write operation to the same address. BUSY has no effect on valid output data. 4. Valid data starts from the last of t AOE, tACE, tAA or tBDD. 5. SEM =VIH. Diagram 1. Read Cycles CE ICC I SB t PU 50% 50% t PD (1) Diagram 2. Power -Up Power -Down

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 12 of 12 tWC ADDR CE or SEM(9,10) OE UB or LB(9) R/W DATAOUT DATAIN tAW tHZ (7) t AS (6) t WP (2) tWZ tDW tDH tOW tWR (3) (4)(4) Diagram 3. Write Cycle No. 1, R/ W ____ Controlled Timing tWC ADDR CE or SEM(9,10) UB or LB(9) R/W DATAIN tAW tEW(2)t AS (6) tDW tDH t WR (3) Diagram 4. Write Cycle No. 2, CE , UB , LB , Controlled Timing NOTES: 1. R/W ____ or CE or UB and LB must be HIGH during all address transitions. 2. A write occurs when CE = VIL and a R/W ____ = VIL for memory write cycle. 3. tWR timing is from the earlier of CE or R/ W ____ (or SEM or R/ W ____ ) going HIGH to the end of write cycle. 4. The I/O pins are in the output state and input signals must not be applied during DATA out pe riod. 5. For CE or SEM =VIL transition simultaneously with or after the R/ W ____ = VIL transition, the outputs remain in the high -impedance state. 6. tAS timing is based on latter of CE or R/ W ____ 7. tHZ transition is measured 0mV from steady state with the Output Test Load. 8. For OE =VIL during R/ W ____ write cycle, the write pulse width is the larger of t WP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE = VIH during a n R/W ____ controlled writing cycle, the write pulse is specified as t WP. 9. Set CE =VIL and SEM = VIH to access memory. Set CE = VIH and SEM = VIL to access semaphore. tEW must be met for either condition.

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 13 of 13 A0-A2 SEM I/O R/W OE Valid Address Valid Address tSAA tACEtWRtAW tEW tSOP t OH DATAOUT Valid (2)DATAIN Valid tDW tDHtWPt AS tSWRD tAOE Write Cycle Read Cycle NOTES: 1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle) . 2. “DATA OUT VALID” represents all I/O’s (I/O 0-15) equal to the semaphore value. Diagram 5. Semaphore Read after Write Timing, Either Side SIDE A SIDE B A0A-A2A R/WA SEMA A0B-A2B R/WB SEMB Match Match t SPS NOTES: 1. DOR = DOL = VIL, CE L = CE R =VIH or both UB and LB =VIH. 2. Timing for both ports is the same. Port B is opposite of port A. 3. This parameter is measured from R/W ____ A or SEM A =VIH to R/ W ____ B or SEM B= VIH. 4. The semaphore will be sent to either side if tSPS is not met. It cannot be guaranteed which side receives semaphore. Diagram 6. Semaphore Write Contention

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 14 of 14 ADDRA t WC Match t WP t DW Valid t DH t APS tBAA t DDD tBDA t BDD BUSYB R/WA DATA INA ADDRB DATAOUTB Valid t WDD NOTES: 1. tAPS is ignored fo r SLAVE part (M/ S ___ = VIL) 2. CE L =CE R = VIH. 3. OE = VIL for the reading port. 4. For SLAVE mode (M/ S ___ = VIL), BUSY is an input. 5. Timing for both ports is the same. Port B is opposite of port A. Diagram 7. Write with Port -to-Port Read and BUSY (M/S = VIH) R/WA BUSYB R/WB t WB t WP tWH NOTES: 1. SLAVE (BUSY input) and MASTER ( BUSY output) must meet t WH. 2. BUSY is sent to port B blocking R/ W ____ B till BUSY B=VIH. 3. tWB is for SLAVE mode. Diagram 8. Write with BUSY (M/S = VIL) ADDRA and ADDRB Addresses Match CE A CE B BUSYB tAPS tBAC tBDC Diagram 9. BUSY Arbitration Controlled by CE Timing (M/ S = VIH)

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 15 of 15 ADDRA BUSYB ADDRB tBAA tAPS tBDA Addresses N Matching Addresses N Diagram 10. BUSY Arbitration Controlled by Address Match Timing (M/ S = VIH) ADDRA CE A R/W A INTF B Interrupt Set Address t AS t WR t INS t WC t RC Interrupt Clear Address t AS tINR ADDRB CE B OEB INTF B Diagram 11. Interrupt Timing

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 16 of 16 Functional Description HDV24VL supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. Interrupts A special memory location is associated with each port when the interrupt function is used. These special memory locations are best considered as mailboxes between the two ports and the corresponding interrupt signals as the flags of the mailboxes. When the right port writes a data word to the special location FFE (HEX), the left port interrupt flag ( INTF L) becomes active or LOW (a data write is defined as CE R = R/W ____ R = VIL). The left port can clear INTF L (HIGH) through either read or write access of the same memory location FFE (a data access is defined as CE L = OE L = VIL, and the value of R/W ____ is irrelevant in the case). Similarly, when the left port writes to the memory location FFF (HEX), the right port interru pt flag (INT R) becomes asserted (LOW). The right port must access the memory location FFF in order to clear INTF R (HIGH). The exact value of the data word at address FFE or FFF is user defined, and is irrelevant as far as the interrupt logic is concerned. If the user chooses not to use the interrupt function, the two special memory locations (FFE and FFF) are treated as part of the regular dual-port memory, and the interrupt flags can simply be ignored. Busy Logic When both ports attempt to access the same memory location at the same time, data corruption can potential ly occur. In the single-device or MASTER configuration (i.e. when the M/ S ___ pin is tied HIGH), the on-chip Busy Logic arbitrates simultaneous accesses to the same memory location, and determines the “ winner” between the two ports. If Busy Logic consi ders the right port lost in the arbitration, then the right port BUSY pin is set active (LOW) to signal the system that this memory location is “ busy” being accessed by the other port. Further more, the Busy Logic prevents the right port from writing to the same memory location for as long as the right port BUSY signal stays active (LOW). Once the left port finishes access to this memory location, the dual-port SRAM signals the system by setting the right port BUSY pin back to inactive (HIGH), so that the system can resume its normal access from the right port. Note that only the write operation from the losing port is inhibited; the read operation is nondestructive and can thus continue regardless of the arbitration result. The BUSY pins are output pins in the single-device or MASTER mode, but become input pins instead when the device is configured in SLAVE mode (this is accomplished by tying M/ S ___ pin LOW). In SLAVE mode the on-chip arbitration logic is disabled, and the device relies on the input BUSY signals for the results of arbitration when simultaneous access to the same memory location occurs. Specifically, when a BUSY pin is set to HIGH, normal operation can be performed from this port , but when a BUSY pin is set to LOW, write operations will be inhibited from this port. If width expansion with multiple HBA HDV24VL devices is used, it is recommended that only one of them be configured in MASTER mode, and the rest of them in SLAVE mode. The BUSY (output) signal from the master device should be connected to the respective BUSY (input) pins of the slave devices. This means that only one device (the master) is performing the Busy Logic arbitration, and all the other devices (the slaves) will follow this arbitration accordingly. This can prevent the conflicts caused by the potential inconsistent arbitration results from different dual-port SRAM devices. Note that if the user does not wish t he write operation to be inhibited by the Busy Logic, the user can disable this feature by configuring the device in SLAVE mode and tying the BUSY input pins to HIGH. The Busy arbitration logic is triggered whenever the two ports simultaneously attempt to access the same memory location, where data accesses are determined by the timings and values of the Address and Chip Enable signals only, not by the value of the R/ W ____ signal. This means that both read and write operations can trigger the Busy Logic, even though only the write operation is inhibited from the losing port. Note that i n a master/slave configuration, an additional timing constraint concerning the R/ W ____ signal needs to be met in order to prevent data corruption in the slave device: the write operation in the slave device cannot start before the BUSY signal – which originates from the output BUSY pin – is received by the slave device to ensure write inhibition. In other words, the R/ W ____ signal needs to stay high from the time the Busy Logic on the master device is triggered (through the changing of the Address and Chip Enable signals) till the BUSY signal is received by the slave device.

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 17 of 17 Semaphores A semaphore can be considered as a special one-bit dual-port memory cell that can be “owned” by (or granted to) only one port at any given time. Typically a semaphore is used as an arbiter for the exclusive ownership (or access privilege) of any shared resource in a system. A semaphore ownership can be requested by writing a zero “0” to the semaphore; a semaphore ownership can be relinquished by writing a one “1” to the semaphore; and a semaphore ownership can be tested by reading from the semaphore – a readout of zero “0” means that the semaphore is owned by this port, while a readout of one “1” means that either the semaphore is owned by the other port, or there is no owner at all. A to ken-passing system can be used to conceptualize the semaphore mechanism: requesting for the semaphore ownership is equivalent to requesting for the token, and relinquishing the semaphore ownership is equivalent to releasing the token. HBA HDV24VL device provides eight addressable semaphores in addition to the regular 4Kx16 dual-port memory space. A typical sequence of accessing a semaphore is as follows: first a port attempts to request for the token by writing a zero “0” to the semaphore. The result of the request is then tested by reading from the semaphore: if the readout is zero “0”, then the token request has succeeded; but if the readout is one “1”, then the token request has failed. The requester should then try to repeatedly read from the semaphore until the readout becomes zero “0”, upon which time the requester becomes the new possessor of the token, and can be granted exclusive access privilege to the shared resource the semaphore represents. In the case when both ports request for the token at the same time, the semaphore logic ensures that only one port is granted the token. In other words, at most one of the two semaphore readout ports can assume the value of zero “0”. When the token is not owned by any port, the semaphore will appear to contain the value one “1” to both ports. Note that a failed token request becomes an outstanding token request, and will remain valid until either the other port releases the token (which means the requester now becomes the new possessor of the token), or when the outstanding request is withdrawn by writing a one “1” to the semaphore before the other port releases the token. Semaphore accesses are distinguished from the regular memory access through the use of the semaphore select (SEM signal: SEM should remain HIGH when the regular dual-port memory is being accessed, but should be tied LOW when semaphores are being accessed. Other control signals such as CE , and R/ W ____ behave identically in both cases. Address pins A0 to A2 are used to address the eight semaphore flags (the values of the other address pins are irrelevant to semaphores). Only data pin D0 is used when writing to a semaphore. However, when reading from a semaphore, the one-bit semaphore value will be duplicated on all data pins (I/O0-I/OD15). Note that the semaphore l ogic is not automatically initialized during power up. The system has to handle the initialization of the semaphores during power up by writing ones from both sides to all semaphores ensure their availabilities for future use. As discussed previously, sema phores are typically used to resolve contentions of shared resources in a system. These shared resources can be a common data bus, a bi-directional shared buffer, or even a segment of the dual-port SRAM on an HBA HDV24VL device. Before any component in the system attempts to gain exclusive access to a shared resource, the semaphore can be used to ensure that no resource contention or data corruption will occur. One advantage in using hardware-supported semaphores is performance improvement by eliminating the processor wait states. HBA HDV24VL semaphores also provide system designers with higher flexibility because the resource sharing can be managed much more easily. With proper system software support, semaphores can even replace the Busy arbitration logic in certain cases, albeit with a coarser data granularity.

© 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. HDV24VL October 2003 ADP II 3HD166B Page 18 of 18 Order Information: *Speed – Ohter speeds available upon request. **Package – BZ: 108 Ball 8mm x8mm 0.5mm-pitch BGA BY: 84 Ball 7mm x7mm 0.5mm-pitch BGA Example: HDV24VL55BZI (4K x 16, 55ns, 108 ball BGA, Industrial temperature) USA Taiwan

2107 North First Street,

San Jose, CA 95131, USA www.hba.com Tel: 408.453.8885 Fax: 408.453.8886 No. 81, Suite 8F-9, Shui- Lee Rd. Hsinchu, Taiwan, R.O.C. www.hba.com Tel: 886.3.516.9118 Fax: 886.3.516.9181 HBA Device Family Device Type Power Speed (ns) * Package** Temperature Range XX XXX XX XX XX X HD V24 (4K x 16) Very Low 55 BZ BY I – Industrial (-40° to 85°C)

Product Information

HDV24VL specifications and overview.

Summary

2.8 Volt x16 Very Low Power Dual-Port Static RAM

Description

2.8 Volt x16 Very Low Power Dual-Port Static RAM

Source title HDV24VL Datasheet(PDF) - AMIC Technology

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