HA0083E

HT46R4A HOLTEK | Alldatasheet

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Features

/c183Operating voltage: fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V /c183Max of 27 bidirectional I/O lines /c183External interrupt input shared with I/O line /c183Two 8-bit programmable Timer/Event Counters with overflow interrupt /c183Integrated crystal and RC oscillator /c183Watchdog Timer /c1834096/c18015 program memory /c183192/c1808 data memory /c183PFD for audio frequency generation /c183Power down and wake-up functions to reduce power consumption /c183Up to 0.5/c109s instruction cycle with 8MHz system clock at VDD=5V /c1836-level subroutine nesting /c1836 channel 9-bit resolution A/D converter /c183Dual channel 8-bit PWM output shared with I/O lines /c183Bit manipulation instruction /c183Table read instructions /c18363 powerful instructions /c183All instructions executed in one or two machine cycles /c183Low voltage reset function /c18328-pin SKDIP/SOP, 32-pin DIP, 44-QFP package Technical Document /c183Tools Information /c183FAQs /c183Application Note /c45HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM /c45HA0049E Read and Write Control of the HT1380 /c45HA0051E Li Battery Charger Demo Board - Using the HT46R47 /c45HA0052E Microcontroller Application - Battery Charger /c45HA0083E Li Battery Charger Demo Board - Using the HT46R46 /c45HA0075E MCU Reset and Oscillator Circuits Application Note

Rev. 1.00 2 November 28, 2007 /G54 /G69 /G6D /G69 /G6E /G67 /G47 /G65 /G6E /G65 /G72 /G61 /G74 /G6F /G72 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G52 /G43 /G2F /G58 /G27 /G74 /G61 /G6C /G20 /G4F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G6F /G72 /G49 /G6E /G73 /G74 /G72 /G75 /G63 /G74 /G69 /G6F /G6E /G44 /G65 /G63 /G6F /G64 /G65 /G72 /G49 /G6E /G73 /G74 /G72 /G75 /G63 /G74 /G69 /G6F /G6E /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G57 /G44 /G54 /G4F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G6F /G72 /G44 /G61 /G74 /G61 /G4D /G65 /G6D /G6F /G72 /G79 /G41 /G64 /G64 /G72 /G65 /G73 /G73 /G20 /G44 /G65 /G63 /G6F /G64 /G65 /G72 /G4D /G65 /G6D /G6F /G72 /G79 /G50 /G6F /G69 /G6E /G74 /G65 /G72 /G4D /G55 /G58 /G41 /G43 /G43 /G4C /G6F /G6F /G6B /G2D /G75 /G70 /G54 /G61 /G62 /G6C /G65 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G52 /G65 /G73 /G65 /G74 /G20 /G26 /G4C /G56 /G52 /G43 /G6F /G6E /G66 /G69 /G67 /G2E /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G54 /G69 /G6D /G65 /G72 /G2F /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G43 /G6F /G6E /G66 /G69 /G67 /G2E /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G43 /G6F /G6E /G66 /G69 /G67 /G2E /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G49 /G2F /G4F /G50 /G6F /G72 /G74 /G73 /G44 /G65 /G76 /G69 /G63 /G65 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G6D /G69 /G6E /G67 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G72 /G79 /G43 /G6F /G6E /G66 /G69 /G67 /G75 /G72 /G61 /G74 /G69 /G6F /G6E /G4F /G70 /G74 /G69 /G6F /G6E /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G4D /G65 /G6D /G6F /G72 /G79 /G41 /G64 /G64 /G72 /G65 /G73 /G73 /G20 /G44 /G65 /G63 /G6F /G64 /G65 /G72 /G53 /G74 /G61 /G63 /G6B /G53 /G74 /G61 /G63 /G6B /G20 /G50 /G6F /G69 /G6E /G74 /G65 /G72 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G4C /G6F /G6F /G6B /G2D /G75 /G70 /G54 /G61 /G62 /G6C /G65 /G50 /G6F /G69 /G6E /G74 /G65 /G72 /G54 /G6F /G20 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G4D /G65 /G6D /G6F /G72 /G79 /G41 /G4C /G55 /G53 /G68 /G69 /G66 /G74 /G65 /G72 /G4D /G55 /G58 /G43 /G6F /G6E /G66 /G69 /G67 /G2E /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G50 /G57 /G4D /G50 /G46 /G44 /G41 /G2F /G44 /G43 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G48 /G54 /G34 /G36 /G52 /G34 /G41 /G20 /G20 /G20 /G32 /G38 /G20 /G53 /G4B /G44 /G49 /G50 /G2D /G41 /G2F /G53 /G4F /G50 /G2D /G41 /G50 /G42 /G35 /G2F /G41 /G4E /G35 /G50 /G42 /G34 /G2F /G41 /G4E /G34 /G50 /G41 /G33 /G2F /G50 /G46 /G44 /G50 /G41 /G32 /G50 /G41 /G31 /G50 /G41 /G30 /G50 /G42 /G33 /G2F /G41 /G4E /G33 /G50 /G42 /G32 /G2F /G41 /G4E /G32 /G50 /G42 /G31 /G2F /G41 /G4E /G31 /G50 /G42 /G30 /G2F /G41 /G4E /G30 /G56 /G53 /G53 /G50 /G43 /G30 /G50 /G43 /G31 /G50 /G43 /G32 /G50 /G42 /G36 /G50 /G42 /G37 /G50 /G41 /G34 /G2F /G54 /G4D /G52 /G30 /G50 /G41 /G35 /G2F /G49 /G4E /G54 /G50 /G41 /G36 /G50 /G41 /G37 /G2F /G54 /G4D /G52 /G31 /G4F /G53 /G43 /G32 /G4F /G53 /G43 /G31 /G56 /G44 /G44 /G52 /G45 /G53 /G50 /G44 /G31 /G2F /G50 /G57 /G4D /G31 /G50 /G44 /G30 /G2F /G50 /G57 /G4D /G30 /G50 /G43 /G34 /G50 /G43 /G33 /G32 /G38 /G32 /G37 /G32 /G36 /G32 /G35 /G32 /G34 /G32 /G33 /G32 /G32 /G32 /G31 /G32 /G30 /G31 /G39 /G31 /G38 /G31 /G37 /G31 /G36 /G31 /G35 /G31 /G32 /G33 /G34 /G35 /G36 /G37 /G38 /G39 /G31 /G30 /G31 /G31 /G31 /G32 /G31 /G33 /G31 /G34 /G48 /G54 /G34 /G36 /G52 /G34 /G41 /G20 /G20 /G20 /G33 /G32 /G20 /G44 /G49 /G50 /G2D /G41 /G50 /G42 /G36 /G50 /G42 /G37 /G50 /G41 /G34 /G2F /G54 /G4D /G52 /G30 /G50 /G41 /G35 /G2F /G49 /G4E /G54 /G50 /G41 /G36 /G50 /G41 /G37 /G2F /G54 /G4D /G52 /G31 /G4F /G53 /G43 /G32 /G4F /G53 /G43 /G31 /G56 /G44 /G44 /G52 /G45 /G53 /G50 /G44 /G32 /G50 /G44 /G31 /G2F /G50 /G57 /G4D /G31 /G50 /G44 /G30 /G2F /G50 /G57 /G4D /G30 /G50 /G43 /G37 /G50 /G43 /G36 /G50 /G43 /G35 /G50 /G42 /G35 /G2F /G41 /G4E /G35 /G50 /G42 /G34 /G2F /G41 /G4E /G34 /G50 /G41 /G33 /G2F /G50 /G46 /G44 /G50 /G41 /G32 /G50 /G41 /G31 /G50 /G41 /G30 /G50 /G42 /G33 /G2F /G41 /G4E /G33 /G50 /G42 /G32 /G2F /G41 /G4E /G32 /G50 /G42 /G31 /G2F /G41 /G4E /G31 /G50 /G42 /G30 /G2F /G41 /G4E /G30 /G56 /G53 /G53 /G50 /G43 /G30 /G50 /G43 /G31 /G50 /G43 /G32 /G50 /G43 /G33 /G50 /G43 /G34 /G31 /G32 /G33 /G34 /G35 /G36 /G37 /G38 /G39 /G31 /G30 /G31 /G31 /G31 /G32 /G31 /G33 /G31 /G34 /G31 /G35 /G31 /G36 /G31 /G37 /G31 /G38 /G31 /G39 /G32 /G30 /G33 /G32 /G33 /G31 /G33 /G30 /G32 /G39 /G32 /G38 /G32 /G37 /G32 /G36 /G32 /G35 /G32 /G34 /G32 /G33 /G32 /G32 /G32 /G31 /G50 /G41 /G32 /G50 /G41 /G31 /G50 /G41 /G30 /G4E /G43 /G50 /G42 /G33 /G2F /G41 /G4E /G33 /G50 /G42 /G32 /G2F /G41 /G4E /G32 /G50 /G42 /G31 /G2F /G41 /G4E /G31 /G50 /G42 /G30 /G2F /G41 /G4E /G30 /G56 /G53 /G53 /G4E /G43 /G50 /G43 /G30 /G4E /G43 /G50 /G41 /G34 /G2F /G54 /G4D /G52 /G30 /G50 /G41 /G35 /G2F /G49 /G4E /G54 /G50 /G41 /G36 /G50 /G41 /G37 /G2F /G54 /G4D /G52 /G31 /G4E /G43 /G4E /G43 /G4F /G53 /G43 /G32 /G4F /G53 /G43 /G31 /G56 /G44 /G44 /G4E /G43 /G4E /G43 /G4E /G43 /G4E /G43 /G4E /G43 /G50 /G42 /G37 /G50 /G42 /G36 /G4E /G43 /G50 /G42 /G35 /G2F /G41 /G4E /G35 /G50 /G42 /G34 /G2F /G41 /G4E /G34 /G4E /G43 /G50 /G41 /G33 /G2F /G50 /G46 /G44 /G52 /G45 /G53 /G50 /G44 /G32 /G50 /G44 /G31 /G2F /G50 /G57 /G4D /G31 /G50 /G44 /G30 /G2F /G50 /G57 /G4D /G30 /G50 /G43 /G37 /G50 /G43 /G36 /G50 /G43 /G35 /G50 /G43 /G34 /G50 /G43 /G33 /G50 /G43 /G32 /G50 /G43 /G31 /G31 /G32 /G33 /G34 /G35 /G36 /G37 /G38 /G39 /G31 /G30 /G31 /G31 /G31 /G32 /G31 /G33 /G31 /G34 /G31 /G35 /G31 /G36 /G31 /G37 /G31 /G38 /G31 /G39 /G32 /G30 /G32 /G31 /G32 /G32 /G32 /G33 /G32 /G34 /G32 /G35 /G32 /G36 /G32 /G37 /G32 /G38 /G32 /G39 /G33 /G30 /G33 /G31 /G33 /G32 /G33 /G33 /G33 /G34 /G33 /G35 /G33 /G36 /G33 /G37 /G33 /G38 /G33 /G39 /G34 /G30 /G34 /G31 /G34 /G32 /G34 /G33 /G34 /G34 /G48 /G54 /G34 /G36 /G52 /G34 /G41 /G20 /G20 /G20 /G20 /G34 /G34 /G20 /G51 /G46 /G50 /G2D /G41

Pin Name I/O Configuration Option Description PA0~PA2 PA3/PFD PA4/TMR0 PA5/INT PA6 PA7/TMR1 I/O Pull-high Wake-up PA3 or PFD Bidirectional 8-bit input/output port. Each individual pin on this port can be config- ured as a wake-up input by a configuration option. Software instructions deter - mine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. Pins PA3, PA4, PA7 and PA5 are pin-shared with PFD, TMR0, TMR1 and INT , respectively. PB0/AN0 PB1/AN1 PB2/AN2 PB3/AN3 PB4/AN4 PB5/AN5 PB6~PB7 I/O Pull-high Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PB is pin-shared with the A/D input pins. The A/D inputs are selected via software instructions. Once selected as an A/D in- put, the I/O function and pull-high resistor options are disabled automatically. PC0~PC7 I/O Pull-high Bidirectional 8-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration options determine which pins on the port have pull-high resistors. PD0/PWM0 PD1/PWM1 PD2 I/O Pull-high I/O or PWM Bidirectional 3-bit input/output port. Software instructions determine if the pin is a CMOS output or Schmitt Trigger input. Configuration option determines which pins on the port have pull-high resistors. The PWM outputs are pin-shared with pins PD0 and PD1 selected via configuration options. OSC1 OSC2 I O Crystal or RC OSC1, OSC2 are connected to an external RC network or external crystal, deter- mined by configuration option, for the internal system clock. If the RC system clock option is selected, pin OSC2 can be used to measure the system clock at 1/4 frequency. RES I /c190 Schmitt Trigger reset input. Active low. VDD /c190/c190 Positive power supply VSS /c190/c190 Negative power supply, ground Note: 1. Each pin on PA can be programmed through a configuration option to have a wake-up function. 2. Individual pins can be selected to have a pull-high resistor. 3. Pins PC5~PC7 and pin PD2 exist but are not bounded out on the 28-pin package. 4. Unbounded pins should be setup as outputs or as inputs with pull-high resistors to conserve power. Absolute Maximum Ratings Note: These are stress ratings only. Stresses exceeding the range specified under/c178Absolute Maximum Ratings/c178may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. HT46R4A Rev. 1.00 3 November 28, 2007

D.C. Characteristics Ta=25/c176C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions VDD Operating Voltage /c190fSYS=4MHz 2.2 /c190 5.5 V /c190fSYS=8MHz 3.3 /c190 5.5 V IDD1 Operating Current (Crystal OSC) 3V No load, fSYS=4MHz ADC disable /c190 0.6 1.5 mA 5V /c190 24 m A IDD2 Operating Current (RC OSC) 3V No load, f SYS=4MHz ADC disable /c190 0.8 1.5 mA 5V /c190 2.5 4 mA IDD3 Operating Current (Crystal OSC, RC OSC) 5V No load, f SYS=8MHz ADC disable /c190 48 m A ISTB1 Standby Current (WDT Enabled) 3V No load, system HALT /c190/c190 5 /c109A 5V /c190/c190 10 /c109A I STB2 Standby Current (WDT Disabled) 3V No load, system HALT /c190/c190 1 /c109A 5V /c190/c190 2 /c109A V IL1 Input Low Voltage for I/O Ports, TMR and INT /c190/c190 0 /c190 0.3VDD V VIH1 Input High Voltage for I/O Ports, TMR and INT /c190/c190 0.7VDD /c190 VDD V VIL2 Input Low Voltage (RES) /c190/c190 0 /c190 0.4VDD V VIH2 Input High Voltage (RES) /c190/c190 0.9VDD /c190 VDD V VLVR Low Voltage Reset /c190/c190 2.7 3.0 3.3 V IOL I/O Port Sink Current 3V VOL=0.1VDD 48 /c190 mA 5V VOL=0.1VDD 10 20 /c190 mA IOH I/O Port Source Current 3V VOH=0.9VDD /c452 /c454 /c190 mA 5V VOH=0.9VDD /c455 /c4510 /c190 mA RPH Pull-high Resistance 3V /c190 20 60 100 k/c87 5V /c190 10 30 50 k/c87 VAD A/D Input Voltage /c190/c190 0 /c190 VDD V EAD A/D Conversion Error /c190/c190 /c190 /c177 0.5 /c1771 LSB IADC Additional Power Consumption if A/D Converter is Used /c190 /c190 0.5 1 mA 5V /c190 1.5 3 mA HT46R4A Rev. 1.00 4 November 28, 2007

A.C. Characteristics Ta=25/c176C Symbol Parameter Test Conditions Min. Typ. Max. Unit VDD Conditions fSYS System Clock /c1902.2V~5.5V 400 /c190 4000 kHz /c1903.3V~5.5V 400 /c190 8000 kHz fTIMER Timer I/P Frequency (TMR) /c1902.2V~5.5V 0 /c190 4000 kHz /c1903.3V~5.5V 0 /c190 8000 kHz tWDTOSC Watchdog Oscillator Period 3V /c190 45 90 180 /c109s 5V /c190 32 65 130 /c109s tWDT1 Watchdog Time-out Period (RC) /c190/c190 215 /c190 216 tWDTOSC tWDT2 Watchdog Time-out Period (System Clock) /c190/c190 217 /c190 218 tSYS tRES External Reset Low Pulse Width /c190/c190 1 /c190/c190/c109s tSST System Start-up Timer Period /c190Wake-up from HALT /c190 1024 /c190 *tSYS tLVR Low Voltage Reset Time /c190/c190 0.25 1 2 ms tINT Interrupt Pulse Width /c190/c190 1 /c190/c190/c109s tAD A/D Clock Period /c190/c190 1 /c190/c190/c109s tADC A/D Conversion Time /c190/c190 /c190 76 /c190 tAD2 tADCS A/D Sampling Time /c190/c190 /c190 32 /c190 tAD2 Note: *tSYS=1/fSYS HT46R4A Rev. 1.00 5 November 28, 2007

Rev. 1.00 6 November 28, 2007 System Architecture A key factor in the high-performance features of the Holtek microcontrollers is attributed to the internal sys - tem architecture. The range of devices take advantage of the usual features found within RISC microcontrollers providing increased speed of operation and enhanced performance. The pipelining scheme is implemented in such a way that instruction fetching and instruction exe- cution are overlapped, hence instructions are effectively executed in one cycle, with the exception of branch or call instructions. An 8-bit wide ALU is used in practically all operations of the instruction set. It carries out arith - metic operations, logic operations, rotation, increment, decrement, branch decisions, etc. The internal data path is simplified by moving data through the Accumula- tor and the ALU. Certain internal registers are imple - mented in the Data Memory and can be directly or indirectly addressed. The simple addressing methods of these registers along with additional architectural fea - tures ensure that a minimum of external components is required to provide a functional I/O and A/D control sys- tem with maximum reliability and flexibility. Clocking and Pipelining The main system clock, derived from either a Crys - tal/Resonator or RC oscillator is subdivided into four in- ternally generated non-overlapping clocks, T1~T4. The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched. The remaining T2~T4 clocks carry out the decoding and execution functions. In this way, one T1~T4 clock cycle forms one instruction cycle. Although the fetching and execution of instructions takes place in consecutive in - struction cycles, the pipelining structure of the microcontroller ensures that instructions are effectively executed in one instruction cycle. The exception to this are instructions where the contents of the Program Counter are changed, such as subroutine calls or jumps, in which case the instruction will take one more instruction cycle to execute. When the RC oscillator is used, OSC2 is freed for use as a T1 phase clock synchronizing pin. This T1 phase clock has a frequency of f SYS/4 with a 1:3 high/low duty cycle. For instructions involving branches, such as jump or call instructions, two machine cycles are required to com - plete instruction execution. An extra cycle is required as the program takes one cycle to first obtain the actual jump or call address and then another cycle to actually execute the branch. The requirement for this extra cycle should be taken into account by programmers in timing sensitive applications Program Counter During program execution, the Program Counter is used to keep track of the address of the next instruction to be executed. It is automatically incremented by one each time an instruction is executed except for instructions, such as /c178JMP/c178or /c178CALL/c178that demand a jump to a non-consecutive Program Memory address. However, it must be noted that only the lower 8 bits, known as the Program Counter Low Register, are directly address- able by user. /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G28 /G50 /G43 /G29 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G28 /G50 /G43 /G2D /G31 /G29 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G28 /G50 /G43 /G2B /G31 /G29 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G28 /G50 /G43 /G29 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G28 /G50 /G43 /G2B /G32 /G29 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G28 /G50 /G43 /G2B /G31 /G29 /G50 /G43 /G50 /G43 /G2B /G31 /G50 /G43 /G2B /G32 /G4F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G6F /G72 /G20 /G43 /G6C /G6F /G63 /G6B /G28 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G43 /G6C /G6F /G63 /G6B /G29 /G50 /G68 /G61 /G73 /G65 /G20 /G43 /G6C /G6F /G63 /G6B /G20 /G54 /G31 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G50 /G68 /G61 /G73 /G65 /G20 /G43 /G6C /G6F /G63 /G6B /G20 /G54 /G32 /G50 /G68 /G61 /G73 /G65 /G20 /G43 /G6C /G6F /G63 /G6B /G20 /G54 /G33 /G50 /G68 /G61 /G73 /G65 /G20 /G43 /G6C /G6F /G63 /G6B /G20 /G54 /G34 /G50 /G69 /G70 /G65 /G6C /G69 /G6E /G69 /G6E /G67 System Clocking and Pipelining /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G31 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G31 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G32 /G46 /G6C /G75 /G73 /G68 /G20 /G50 /G69 /G70 /G65 /G6C /G69 /G6E /G65 /G31 /G32 /G33 /G34 /G35 /G36 /G44 /G45 /G4C /G41 /G59 /G3A /G4D /G4F /G56 /G20 /G41 /G2C /G5B /G31 /G32 /G48 /G5D /G43 /G41 /G4C /G4C /G20 /G44 /G45 /G4C /G41 /G59 /G43 /G50 /G4C /G20 /G5B /G31 /G32 /G48 /G5D /G3A /G3A /G4E /G4F /G50 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G32 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G33 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G36 /G45 /G78 /G65 /G63 /G75 /G74 /G65 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G36 /G46 /G65 /G74 /G63 /G68 /G20 /G49 /G6E /G73 /G74 /G2E /G20 /G37 Instruction Fetching

Rev. 1.00 7 November 28, 2007 When executing instructions requiring jumps to non-consecutive addresses such as a jump instruction, a subroutine call, interrupt or reset, etc., the microcontroller manages program control by loading the required address into the Program Counter. For condi - tional skip instructions, once the condition has been met, the next instruction, which has already been fetched during the present instruction execution, is dis- carded and a dummy cycle takes its place while the cor- rect instruction is obtained. The lower byte of the Program Counter, known as the Program Counter Low register or PCL, is available for program control and can be read nor written to. By trans- ferring data directly into this register, a short program jump can be executed directly, however, as only this low byte is available for manipulation, the jumps are limited to the present page of memory, that is 256 locations. When such program jumps are executed it should also be noted that a dummy cycle will be inserted. The lower byte of the Program Counter is fully accessi- ble under program control. Manipulating the PCL might cause program branching, so an extra cycle is needed to pre-fetch. Further information on the PCL register can be found in the Special Function Register section. Stack This is a special part of the memory which is used to save the contents of the Program Counter only. The stack is organised into 6 levels and is neither part of the data nor part of the program space, and is neither be read nor written to. The activated level is indexed by the Stack Pointer, SP, and can neither be read nor written to. At a subroutine call or interrupt acknowledge signal, the contents of the Program Counter are pushed onto the stack. At the end of a subroutine or an interrupt rou- tine, signaled by a return instruction, RET or RETI, the Program Counter is restored to its previous value from the stack. After a device reset, the Stack Pointer will point to the top of the stack. If the stack is full and an enabled interrupt takes place, the interrupt request flag will be recorded but the ac - knowledge signal will be inhibited. When the Stack Pointer is decremented, by RET or RETI, the interrupt will be serviced. This feature prevents stack overflow al- lowing the programmer to use the structure more easily. However, when the stack is full, a CALL subroutine in - struction can still be executed which will result in a stack overflow. Precautions should be taken to avoid such cases which might cause unpredictable program branching. Mode Program Counter Bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 Initial Reset 000000000000 External Interrupt 000000000100 Timer/Event Counter 0 Overflow 000000001000 Timer/Event Counter 1 Overflow 000000001100 A/D Converter Interrupt 000000010000 Skip Program Counter + 2 Loading PCL PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 Return from Subroutine S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Program Counter Note: PC11~PC8: Current Program Counter bits @7~@0: PCL bits #11~#0: Instruction code address bits S11~S0: Stack register bits The Program Counter is 12 bits wide, i.e. from b11~b0. /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G53 /G74 /G61 /G63 /G6B /G20 /G4C /G65 /G76 /G65 /G6C /G20 /G31 /G53 /G74 /G61 /G63 /G6B /G20 /G4C /G65 /G76 /G65 /G6C /G20 /G32 /G53 /G74 /G61 /G63 /G6B /G20 /G4C /G65 /G76 /G65 /G6C /G20 /G33 /G53 /G74 /G61 /G63 /G6B /G20 /G4C /G65 /G76 /G65 /G6C /G20 /G4E /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G4D /G65 /G6D /G6F /G72 /G79 /G54 /G6F /G70 /G20 /G6F /G66 /G20 /G53 /G74 /G61 /G63 /G6B /G53 /G74 /G61 /G63 /G6B /G50 /G6F /G69 /G6E /G74 /G65 /G72 /G42 /G6F /G74 /G74 /G6F /G6D /G20 /G6F /G66 /G20 /G53 /G74 /G61 /G63 /G6B

Rev. 1.00 8 November 28, 2007 Arithmetic and Logic Unit /c45ALU The arithmetic-logic unit or ALU is a critical area of the microcontroller that carries out arithmetic and logic op - erations of the instruction set. Connected to the main microcontroller data bus, the ALU receives related in - struction codes and performs the required arithmetic or logical operations after which the result will be placed in the specified register. As these ALU calculation or oper- ations may result in carry, borrow or other status changes, the status register will be correspondingly up- dated to reflect these changes. The ALU supports the following functions: /c183Arithmetic operations: ADD, ADDM, ADC, ADCM, SUB, SUBM, SBC, SBCM, DAA /c183Logic operations: AND, OR, XOR, ANDM, ORM, XORM, CPL, CPLA /c183Rotation RRA, RR, RRCA, RRC, RLA, RL, RLCA, RLC /c183Increment and Decrement INCA, INC, DECA, DEC /c183Branch decision, JMP, SZ, SZA, SNZ, SIZ, SDZ, SIZA, SDZA, CALL, RET, RETI Program Memory The Program Memory is the location where the user code or program is stored. For this device, the type of memory is One-Time Programmable, OTP, memory where users can program their application code into the device. By us- ing the appropriate programming tools, OTP devices of- fer users the flexibility to freely develop their applications which may be useful during debug or for products requir- ing frequent upgrades or program changes. OTP devices are also applicable for use in applications that require low or medium volume production runs. Structure The Program Memory has a capacity of 4K by 15 bits. The Program Memory is addressed by the Program Counter and also contains data, table information and interrupt entries. Table data, which can be setup in any location within the Program Memory, is addressed by separate table pointer registers. Special Vectors Within the Program Memory, certain locations are re - served for special usage such as reset and interrupts. /c183Location 000H This vector is reserved for use by the device reset for program initialisation. After a device reset is initiated, the program will jump to this location and begin execution. /c183Location 004H This vector is used by the external interrupt. If the ex- ternal interrupt pin on the device goes low, the pro - gram will jump to this location and begin execution if the external interrupt is enabled and the stack is not full. /c183Location 008H This internal vector is used by the Timer/Event Coun- ter 0. If a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. /c183Location 00CH This internal vector is used by the Timer/Event Coun- ter 1. If a counter overflow occurs, the program will jump to this location and begin execution if the timer/event counter interrupt is enabled and the stack is not full. /c183Location 010H This internal vector is used by the A/D converter. When an A/D conversion cycle is complete, the pro - gram will jump to this location and begin execution if the A/D interrupt is enabled and the stack is not full. Look-up Table Any location within the Program Memory can be defined as a look-up table where programmers can store fixed data. To use the look-up table, the table pointer must first be setup by placing the lower order address of the look up data to be retrieved in the table pointer register, TBLP. This register defines the lower 8-bit address of the look-up table. After setting up the table pointer, the table data can be retrieved from the current Program Memory page or last Program Memory page using the /c178TABRDC[m]/c178or /c178TABRDL [m]/c178instructions, respectively. When these in- structions are executed, the lower order table byte from the Program Memory will be transferred to the user de- fined Data Memory register [m] as specified in the in - struction. The higher order table data byte from the Program Memory will be transferred to the TBLH special register. Any unused bits in this transferred higher order byte will be read as /c1780/c178. /G49 /G6E /G69 /G74 /G69 /G61 /G6C /G69 /G73 /G61 /G74 /G69 /G6F /G6E /G20 /G56 /G65 /G63 /G74 /G6F /G72 /G45 /G78 /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G56 /G65 /G63 /G74 /G6F /G72 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G30 /G20 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G56 /G65 /G63 /G74 /G6F /G72 /G46 /G46 /G46 /G48 /G6E /G46 /G46 /G48 /G46 /G30 /G30 /G48 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G4D /G65 /G6D /G6F /G72 /G79 /G4C /G6F /G6F /G6B /G2D /G75 /G70 /G20 /G54 /G61 /G62 /G6C /G65 /G20 /G28 /G32 /G35 /G36 /G20 /G77 /G6F /G72 /G64 /G73 /G29 /G4C /G6F /G6F /G6B /G2D /G75 /G70 /G20 /G54 /G61 /G62 /G6C /G65 /G20 /G28 /G32 /G35 /G36 /G20 /G77 /G6F /G72 /G64 /G73 /G29 /G4E /G6F /G74 /G65 /G3A /G20 /G6E /G20 /G72 /G61 /G6E /G67 /G65 /G73 /G20 /G66 /G72 /G6F /G6D /G20 /G30 /G20 /G74 /G6F /G20 /G46 /G41 /G2F /G44 /G20 /G43 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G20 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G53 /G75 /G62 /G72 /G6F /G75 /G74 /G69 /G6E /G65 /G31 /G35 /G20 /G62 /G69 /G74 /G73 /G30 /G30 /G30 /G48 /G30 /G30 /G34 /G48 /G30 /G30 /G38 /G48 /G30 /G30 /G43 /G48 /G30 /G31 /G30 /G48 /G6E /G30 /G30 /G48 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G31 /G20 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G56 /G65 /G63 /G74 /G6F /G72 Program Memory Structure

Rev. 1.00 9 November 28, 2007 The diagram illustrates the addressing/data flow of the look-up table: Table Program Example The following example shows how the table pointer and table data is defined and retrieved from the microcontroller. This example uses raw table data lo - cated in the last page which is stored there using the ORG statement. The value at this ORG statement is /c178F00H/c178which refers to the start address of the last page within the 4K Program Memory. The table pointer is setup here to have an initial value of/c17806H/c178. This will en- sure that the first data read from the data table will be at the Program Memory address /c178F06H/c178or 6 locations af- ter the start of the last page. Note that the value for the table pointer is referenced to the first address of the present page if the /c178TABRDC [m]/c178instruction is being used. The high byte of the table data which in this case is equal to zero will be transferred to the TBLH register automatically when the /c178TABRDL [m]/c178instruction is ex- ecuted. /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G20 /G4D /G65 /G6D /G6F /G72 /G79 /G20 /G50 /G72 /G6F /G67 /G72 /G61 /G6D /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G20 /G20 /G20 /G20 /G20 /G20 /G48 /G69 /G67 /G68 /G20 /G42 /G79 /G74 /G65 /G54 /G42 /G4C /G50 /G54 /G42 /G4C /G48 /G53 /G70 /G65 /G63 /G69 /G66 /G69 /G65 /G64 /G20 /G62 /G79 /G20 /G5B /G6D /G5D /G54 /G61 /G62 /G6C /G65 /G20 /G43 /G6F /G6E /G74 /G65 /G6E /G74 /G73 /G20 /G48 /G69 /G67 /G68 /G20 /G42 /G79 /G74 /G65 /G54 /G61 /G62 /G6C /G65 /G20 /G43 /G6F /G6E /G74 /G65 /G6E /G74 /G73 /G20 /G4C /G6F /G77 /G20 /G42 /G79 /G74 /G65 tempreg1 db ? ; temporary register #1 tempreg2 db ? ; temporary register #2 mov a,06h ; initialise table pointer - note that this address ; is referenced mov tblp,a ; to the last page or present page tabrdl tempreg1 ; transfers value in table referenced by table pointer ; to tempregl ; data at prog. memory address/c178F06H/c178transferred to ; tempreg1 and TBLH dec tblp ; reduce value of table pointer by one tabrdl tempreg2 ; transfers value in table referenced by table pointer ; to tempreg2 ; data at prog.memory address/c178F05H/c178transferred to ; tempreg2 and TBLH ; in this example the data/c1781AH/c178is transferred to ; tempreg1 and data/c1780FH/c178to register tempreg2 ; the value/c17800H/c178will be transferred to the high byte ; register TBLH org F00h ; sets initial address of last page dc 00Ah, 00Bh, 00Ch, 00Dh, 00Eh, 00Fh, 01Ah, 01Bh Because the TBLH register is a read-only register and cannot be restored, care should be taken to ensure its protection if both the main routine and Interrupt Service Routine use table read instructions. If using the table read instructions, the Interrupt Service Routines may change the value of the TBLH and subsequently cause errors if used again by the main routine. As a rule it is recommended that simultaneous use of the table read instructions should be avoided. However, in situations where simultaneous use cannot be avoided, the interrupts should be disabled prior to the execution of any main routine table-read instructions. Note that all table related instructions require two instruction cycles to complete their operation. Instruction Table Location Bits b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 TABRDC[m] PC11 PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0 TABRDL [ m ] 1111 @ 7 @ 6 @ 5 @ 4 @ 3 @ 2 @ 1 @ 0 Table Location Note: PC11~PC8: Current Program Counter bits @7~@0: Table Pointer TBLP bits The Table address location is 12 bits, i.e. from b11~b0.

Rev. 1.00 10 November 28, 2007 Data Memory The Data Memory is a volatile area of 8-bit wide RAM internal memory and is the location where temporary in- formation is stored. Divided into two sections, the first of these is an area of RAM where special function registers are located. These registers have fixed locations and are necessary for correct operation of the device. Many of these registers can be read from and written to di - rectly under program control, however, some remain protected from user manipulation. The second area of Data Memory is reserved for general purpose use. All locations within this area are read and write accessible under program control. Structure The two sections of Data Memory, the Special Purpose and General Purpose Data Memory are located at con- secutive locations. All are implemented in RAM and are 8 bits wide but the length of each memory section is dic- tated by the type of microcontroller chosen. The start address of the Data Memory for all devices is the ad - dress /c17800H/c178. Registers which are common to all microcontrollers, such as ACC, PCL, etc., have the same Data Memory address. General Purpose Data Memory All microcontroller programs require an area of read/write memory where temporary data can be stored and retrieved for use later. It is this area of RAM memory that is known as General Purpose Data Memory. This area of Data Memory is fully accessible by the user pro- gram for both read and write operations. By using the /c178SET [m].i/c178and /c178CLR [m].i/c178instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulation in the Data Memory. Special Purpose Data Memory This area of Data Memory is where registers, necessary for the correct operation of the microcontroller, are stored. Most of the registers are both readable and writable but some are protected and are readable only, the details of which are located under the relevant Spe- cial Function Register section. Note that for locations that are unused, any read instruction to these addresses will return the value /c17800H/c178. /G47 /G65 /G6E /G65 /G72 /G61 /G6C /G20 /G50 /G75 /G72 /G70 /G6F /G73 /G65 /G44 /G61 /G74 /G61 /G20 /G4D /G65 /G6D /G6F /G72 /G79 /G53 /G70 /G65 /G63 /G69 /G61 /G6C /G20 /G50 /G75 /G72 /G70 /G6F /G73 /G65 /G44 /G61 /G74 /G61 /G20 /G4D /G65 /G6D /G6F /G72 /G79 /G30 /G30 /G48 /G34 /G30 /G48 /G46 /G46 /G48 /G33 /G46 /G48 /G48 /G54 /G34 /G36 /G52 /G34 /G41 Data Memory Structure Note: Most of the Data Memory bits can be directly manipulated using the /c178SET [m].i /c178and /c178CLR [m].i/c178with the exception of a few dedicated bits. The Data Memory can also be accessed through the memory pointer register MP. /G3A /G20 /G55 /G6E /G75 /G73 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G30 /G22 /G49 /G41 /G52 /G4D /G50 /G41 /G43 /G43 /G50 /G43 /G4C /G54 /G42 /G4C /G50 /G54 /G42 /G4C /G48 /G53 /G54 /G41 /G54 /G55 /G53 /G49 /G4E /G54 /G43 /G30 /G54 /G4D /G52 /G30 /G54 /G4D /G52 /G30 /G43 /G54 /G4D /G52 /G31 /G54 /G4D /G52 /G31 /G43 /G50 /G41 /G50 /G41 /G43 /G50 /G42 /G50 /G42 /G43 /G50 /G43 /G50 /G43 /G43 /G50 /G44 /G50 /G44 /G43 /G50 /G57 /G4D /G30 /G50 /G57 /G4D /G31 /G49 /G4E /G54 /G43 /G31 /G41 /G44 /G52 /G4C /G41 /G44 /G52 /G48 /G41 /G44 /G43 /G52 /G41 /G43 /G53 /G52 /G30 /G30 /G48 /G30 /G31 /G48 /G30 /G32 /G48 /G30 /G33 /G48 /G30 /G34 /G48 /G30 /G35 /G48 /G30 /G36 /G48 /G30 /G37 /G48 /G30 /G38 /G48 /G30 /G39 /G48 /G30 /G41 /G48 /G30 /G42 /G48 /G30 /G43 /G48 /G30 /G44 /G48 /G30 /G45 /G48 /G30 /G46 /G48 /G31 /G30 /G48 /G31 /G31 /G48 /G31 /G32 /G48 /G31 /G33 /G48 /G31 /G34 /G48 /G31 /G35 /G48 /G31 /G36 /G48 /G31 /G37 /G48 /G31 /G38 /G48 /G31 /G39 /G48 /G31 /G41 /G48 /G31 /G42 /G48 /G31 /G43 /G48 /G31 /G44 /G48 /G31 /G45 /G48 /G31 /G46 /G48 /G32 /G30 /G48 /G32 /G31 /G48 /G32 /G32 /G48 /G32 /G33 /G48 Special Purpose Data Memory

Rev. 1.00 11 November 28, 2007 Special Function Registers To ensure successful operation of the microcontroller, certain internal registers are implemented in the Data Memory area. These registers ensure correct operation of internal functions such as timers, interrupts, etc., as well as external functions such as I/O data control and A/D converter operation. The location of these registers within the Data Memory begins at the address 00H. Any unused Data Memory locations between these special function registers and the point where the General Pur- pose Memory begins is reserved for future expansion purposes, attempting to read data from these locations will return a value of 00H. Indirect Addressing Register /c45IAR The IAR register, located at Data Memory address /c17800H/c178, is not physically implemented. This special regis- ter allows what is known as indirect addressing, which permits data manipulation using Memory Pointers in - stead of the usual direct memory addressing method where the actual memory address is defined. Any actions on the IAR register will result in correspond- ing read/write operations to the memory location speci- fied by the Memory Pointer MP. Reading the IAR register indirectly will return a result of/c17800H/c178and writing to the register indirectly will result in no operation. Memory Pointer /c45MP One Memory Pointer, known as MP, is physically imple- mented in the Data Memory. The Memory Pointer can be written to and manipulated in the same way as nor - mal registers providing an easy way of addressing and tracking data. When using any operation on the indirect addressing register IAR, it is actually the address speci- fied by the Memory Pointer that the microcontroller will be directed to. The following example shows how to clear a section of four RAM locations already defined as locations adres1 to adres4. data .section /c162data/c162 adres1 db ? adres2 db ? adres3 db ? adres4 db ? block db ? code .section at 0/c162code/c162 org 00h start: mov a,04h ; setup size of block mov block,a mov a,offset adres1 ; Accumulator loaded with first RAM address mov mp,a ; setup memory pointer with first RAM address loop: clr IAR ; clear the data at address defined by MP inc mp ; increment memory pointer sdz block ; check if last memory location has been cleared jmp loop continue: The important point to note here is that in the example shown above, no reference is made to specific RAM addresses.

Rev. 1.00 12 November 28, 2007 Accumulator /c45ACC The Accumulator is central to the operation of any microcontroller and is closely related with operations carried out by the ALU. The Accumulator is the place where all intermediate results from the ALU are stored. Without the Accumulator it would be necessary to write the result of each calculation or logical operation such as addition, subtraction, shift, etc., to the Data Memory resulting in higher programming and timing overheads. Data transfer operations usually involve the temporary storage function of the Accumulator; for example, when transferring data between one user defined register and another, it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted. Program Counter Low Register /c45PCL To provide additional program control functions, the low byte of the Program Counter is made accessible to pro- grammers by locating it within the Special Purpose area of the Data Memory. By manipulating this register, direct jumps to other program locations are easily imple - mented. Loading a value directly into this PCL register will cause a jump to the specified Program Memory lo - cation, however, as the register is only 8-bit wide, only jumps within the current Program Memory page are per- mitted. When such operations are used, note that a dummy cycle will be inserted. Look-up Table Registers /c45TBLP, TBLH These two special function registers are used to control operation of the look-up table which is stored in the Pro- gram Memory. TBLP is the table pointer and indicates the location where the table data is located. Its value must be setup before any table read commands are ex- ecuted. Its value can be changed, for example using the /c178INC/c178or /c178DEC/c178instructions, allowing for easy table data pointing and reading. TBLH is the location where the high order byte of the table data is stored after a table read data instruction has been executed. Note that the lower order table data byte is transferred to a user de - fined location. Status Register /c45STATUS This 8-bit register contains the zero flag (Z), carry flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag (TO). These arithmetic/logical operation and system manage- ment flags are used to record the status and operation of the microcontroller. With the exception of the TO and PDF flags, bits in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the TO or PDF flag. In addition, opera - tions related to the status register may give different re- sults due to the different instruction operations. The TO flag can be affected only by a system power-up, a WDT time-out or by executing the /c178CLR WDT/c178or /c178HALT/c178in- struction. The PDF flag is affected only by executing the /c178HALT/c178or /c178CLR WDT/c178instruction or during a system power-up. The Z, OV, AC and C flags generally reflect the status of the latest operations. /c183C is set if an operation results in a carry during an ad- dition operation or if a borrow does not take place dur- ing a subtraction operation; otherwise C is cleared. C is also affected by a rotate through carry instruction. /c183AC is set if an operation results in a carry out of the low nibbles in addition, or no borrow from the high nib- ble into the low nibble in subtraction; otherwise AC is cleared. /c183Z is set if the result of an arithmetic or logical operation is zero; otherwise Z is cleared. /c183OV is set if an operation results in a carry into the high- est-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared. /c183PDF is cleared by a system power-up or executing the /c178CLR WDT/c178instruction. PDF is set by executing the /c178HALT/c178instruction. /c183TO is cleared by a system power-up or executing the /c178CLR WDT /c178or /c178HALT/c178instruction. TO is set by a WDT time-out. /G54 /G4F /G50 /G44 /G46 /G4F /G56 /G5A /G41 /G43 /G43 /G53 /G54 /G41 /G54 /G55 /G53 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G41 /G72 /G69 /G74 /G68 /G6D /G65 /G74 /G69 /G63 /G2F /G4C /G6F /G67 /G69 /G63 /G20 /G4F /G70 /G65 /G72 /G61 /G74 /G69 /G6F /G6E /G20 /G46 /G6C /G61 /G67 /G73 /G43 /G61 /G72 /G72 /G79 /G20 /G66 /G6C /G61 /G67 /G41 /G75 /G78 /G69 /G6C /G69 /G61 /G72 /G79 /G20 /G63 /G61 /G72 /G72 /G79 /G20 /G66 /G6C /G61 /G67 /G5A /G65 /G72 /G6F /G20 /G66 /G6C /G61 /G67 /G4F /G76 /G65 /G72 /G66 /G6C /G6F /G77 /G20 /G66 /G6C /G61 /G67 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G4D /G61 /G6E /G61 /G67 /G65 /G6D /G65 /G6E /G74 /G20 /G46 /G6C /G61 /G67 /G73 /G50 /G6F /G77 /G65 /G72 /G20 /G64 /G6F /G77 /G6E /G20 /G66 /G6C /G61 /G67 /G57 /G61 /G74 /G63 /G68 /G64 /G6F /G67 /G20 /G74 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G20 /G66 /G6C /G61 /G67 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 /G62 /G37 /G62 /G30 Status Register

Rev. 1.00 13 November 28, 2007 In addition, on entering an interrupt sequence or execut- ing a subroutine call, the status register will not be pushed onto the stack automatically. If the contents of the status registers are important and if the subroutine can corrupt the status register, precautions must be taken to correctly save it. Interrupt Control Register /c45INTC0, INTC1 These 8-bit registers, known as INTC0 and INTC1, con- trol the operation of both the external and internal inter- rupts. By setting various bits within these registers using standard bit manipulation instructions, the enable/dis - able function of the external interrupts and each of the internal interrupts can be independently controlled. A master interrupt bit within these registers, the EMI bit, acts like a global enable/disable and is used to set all of the interrupt enable bits on or off. This bit is cleared when an interrupt routine is entered to disable further in- terrupt and is set by executing the RETI/c178instruction. Note In situations where other interrupts may require servicing within present interrupt service rou - tines, the EMI bit can be manually set by the program after the present interrupt service rou- tine has been entered. Timer/Event Counter Registers /c45TMR0, TMR0C, TMR1, TMR1C The device contains two integrated 8-bit size Timer/ Event Counters. These have associated registers known as TMR0 and TMR1, where the timer /c162s values are located. Two associated control registers, known as TMR0C and TMR1C contain the setup information for these two timers. Note that all timer registers can be di- rectly written to in order to preload their contents with fixed data to allow different time intervals to be setup. Input/Output Ports and Control Registers Within the area of Special Function Registers, the I/O registers and their associated control registers play a prominent role. All I/O ports have a designated register correspondingly labeled as PA, PB, PC and PD. These labeled I/O registers are mapped to specific addresses within the Data Memory as shown in the Data Memory table, which are used to transfer the appropriate output or input data on that port. With each I/O port there is an associated control register labeled PAC, PBC, PCC and PDC, also mapped to specific addresses with the Data Memory. The control register specifies which pins of that port are set as inputs and which are set as outputs. To setup a pin as an input, the corresponding bit of the con- trol register must be set high, for an output it must be set low. During program initialisation, it is important to first setup the control registers to specify which pins are out- puts and which are inputs before reading data from or writing data to the I/O ports. One flexible feature of these registers is the ability to directly program single bits us- ing the /c178SET [m].i /c178and /c178CLR [m].i /c178instructions. The ability to change I/O pins from output to input and vice versa by manipulating specific bits of the I/O control reg- isters during normal program operation is a useful fea - ture of these devices. Pulse Width Modulator Registers /c45PWM0, PWM1 The device contains two Pulse Width Modulators. Each one has its own related independent control register. For devices with two PWM functions, their control register names are PWM0 and PWM1. The 8-bit contents of these registers, defines the duty cycle value for the modulation cycle of the corresponding Pulse Width Modulator. A/D Converter Registers /c45ADRL, ADRH, ADCR, ACSR The device contains a 6-channel 9-bit A/D converter. The correct operation of the A/D requires the use of two data registers, a control register and a clock source reg- ister. A high byte data register known as ADRH, and a low byte data register known as ADRL. These are the register locations where the digital value is placed after the completion of an analog to digital conversion cycle. The channel selection and configuration of the A/D con- verter is setup via the control register ADCR while the A/D clock frequency is defined by the clock source reg- ister, ACSR.

Rev. 1.00 14 November 28, 2007 Input/Output Ports Holtek microcontrollers offer considerable flexibility on their I/O ports. With the input or output designation of ev- ery pin fully under user program control, pull-high op - tions for all ports and wake-up options on certain pins, the user is provided with an I/O structure to meet the needs of a wide range of application possibilities. The device offers up to 27 bidirectional input/output lines labeled with port names PA, PB, PC and PD. These I/O ports are mapped to the Data Memory with specific addresses as shown in the Special Purpose Data Memory table. All of these I/O ports can be used for input and output operations. For input operation, these ports are non-latching, which means the inputs must be ready at the T2 rising edge of instruction/c178MOV A,[m]/c178, where m denotes the port address. For output operation, all the data is latched and remains un - changed until the output latch is rewritten. Pull-high Resistors Many product applications require pull-high resistors for their switch inputs usually requiring the use of an exter- nal resistor. To eliminate the need for these external re- sistors, all I/O pins, when configured as an input have the capability of being connected to an internal pull-high resistor. These pull-high resistors are selectable via configuration options and are implemented using a weak PMOS transistor. Port A Wake-up Each device has a HALT instruction enabling the microcontroller to enter a Power Down Mode and pre- serve power, a feature that is important for battery and other low-power applications. Various methods exist to wake-up the microcontroller, one of which is to change the logic condition on one of the Port A pins from high to low. After a HALT instruction forces the microcontroller into entering a Power Down condition, the device will re- main in a low-power state until a Port A pin receives a high to low going edge. This function is especially suit - able for applications that can be woken up via external switches. Note that each pin on Port A can be selected individually to have this wake-up feature. I/O Port Control Registers Each I/O port has its own control register PAC, PBC, PCC and PDC, to control the input/output configuration. With this control register, each CMOS output or input with or without pull-high resistor structures can be re - configured dynamically under software control. Each pin of the I/O ports is directly mapped to a bit in its associ - ated port control register. For the I/O pin to function as an input, the corresponding bit of the control register must be written as a /c1781/c178. This will then allow the logic state of the input pin to be directly read by instructions. When the corresponding bit of the control register is written as a/c1780/c178, the I/O pin will be setup as a CMOS out- put. If the pin is currently setup as an output, instructions can still be used to read the output register. However, it should be noted that the program will in fact only read the status of the output data latch and not the actual logic status of the output pin. Pin-shared Functions The flexibility of the microcontroller range is greatly en- hanced by the use of pins that have more than one func- tion. Limited numbers of pins can force serious design constraints on designers but by supplying pins with multi-functions, many of these difficulties can be over - come. For some pins, the chosen function of the multi-function I/O pins is set by configuration options while for others the function is set by application pro - gram control. /c183External Interrupt Input The external interrupt pin INT is pin-shared with the I/O pin PA5. For applications not requiring an external interrupt input, the pin-shared external interrupt pin can be used as a normal I/O pin, however to do this, the external interrupt enable bits in the INTC register must be disabled. /c183External Timer Clock Input The external timer pins TMR0 and TMR1 are pin-shared with the I/O pins PA4 and PA7, respec- tively. To configure these pins to operate as timer in- puts, the corresponding control bits in the timer control register must be correctly set. For applications that do not require an external timer input, these pin can be used as normal I/O pins. Note that if used as normal I/O pins the timer mode control bits in the timer control register must select the timer mode, which has an internal clock source, to prevent the input pin from interfering with the timer operation. /c183PFD Output Each device contains a PFD function whose single output is pin-shared with PA3. The output function of this pin is chosen via a configuration option and re - mains fixed after the device is programmed. Note that the corresponding bit of the port control register, PAC.3, must setup the pin as an output to enable the PFD output. If the PAC port control register has setup the pin as an input, then the pin will function as a nor- mal logic input with the usual pull-high option, even if the PFD configuration option has been selected. /c183PWM Outputs The devices contain two PWM outputs PWM0 and PWM1 are pin shared with pins PD0 and PD1, respectively. The PWM output functions are chosen via configuration options and remain fixed after the device is programmed. Note that the corresponding bit or bits of the port control register, PDC, must setup the pin as an output to enable the PWM output. If the PDC port control register has setup the pin as an in - put, then the pin will function as a normal logic input

Rev. 1.00 15 November 28, 2007 with the usual pull-high option, even if the PWM con- figuration option has been selected. /c183A/D Inputs The device has six A/D converter inputs. All of these analog inputs are pin-shared with I/O pins on Port B. If these pins are to be used as A/D inputs and not as normal I/O pins then the corresponding bits in the A/D Converter Control Register, ADCR, must be properly set. There are no configuration options associated with the A/D function. If used as I/O pins, then full pull-high resistor configuration options remain, how - ever if used as A/D inputs then any pull-high resistor options associated with these pins will be automati - cally disconnected. I/O Pin Structures The following diagrams illustrate the I/O pin internal structures. As the exact logical construction of the I/O pin may differ from these drawings, they are supplied as a guide only to assist with the functional understanding of the I/O pins. /G56 /G44 /G44 /G4D /G55 /G58 /G57 /G61 /G6B /G65 /G2D /G75 /G70 /G20 /G4F /G70 /G74 /G69 /G6F /G6E /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G57 /G61 /G6B /G65 /G2D /G75 /G70 /G52 /G65 /G61 /G64 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G42 /G69 /G74 /G50 /G75 /G6C /G6C /G2D /G48 /G69 /G67 /G68 /G4F /G70 /G74 /G69 /G6F /G6E /G44 /G61 /G74 /G61 /G20 /G42 /G75 /G73 /G57 /G72 /G69 /G74 /G65 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G68 /G69 /G70 /G20 /G52 /G65 /G73 /G65 /G74 /G52 /G65 /G61 /G64 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G57 /G72 /G69 /G74 /G65 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G44 /G61 /G74 /G61 /G20 /G42 /G69 /G74 /G49 /G2F /G4F /G20 /G50 /G69 /G6E /G57 /G65 /G61 /G6B /G50 /G75 /G6C /G6C /G2D /G75 /G70 /G44 /G51 /G43 /G4B /G53 /G51 /G44 /G51 /G43 /G4B /G53 /G51 /G50 /G41 /G20 /G6F /G6E /G6C /G79 Non-pin-shared Function Input/Output Ports /G56 /G44 /G44 /G4D /G55 /G58 /G52 /G65 /G61 /G64 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G42 /G69 /G74 /G50 /G75 /G6C /G6C /G2D /G48 /G69 /G67 /G68 /G4F /G70 /G74 /G69 /G6F /G6E /G44 /G61 /G74 /G61 /G20 /G42 /G75 /G73 /G57 /G72 /G69 /G74 /G65 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G68 /G69 /G70 /G20 /G52 /G65 /G73 /G65 /G74 /G52 /G65 /G61 /G64 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G57 /G72 /G69 /G74 /G65 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G44 /G61 /G74 /G61 /G20 /G42 /G69 /G74 /G20 /G20 /G49 /G4E /G54 /G20 /G66 /G6F /G72 /G20 /G50 /G41 /G35 /G20 /G6F /G6E /G6C /G79 /G54 /G4D /G52 /G30 /G20 /G66 /G6F /G72 /G20 /G50 /G41 /G34 /G20 /G6F /G6E /G6C /G79 /G54 /G4D /G52 /G31 /G20 /G66 /G6F /G72 /G20 /G50 /G41 /G37 /G20 /G6F /G6E /G6C /G79 /G50 /G41 /G34 /G2F /G54 /G4D /G52 /G30 /G20 /G50 /G41 /G35 /G2F /G49 /G4E /G54 /G50 /G41 /G37 /G2F /G54 /G4D /G52 /G31 /G57 /G61 /G6B /G65 /G2D /G75 /G70 /G20 /G4F /G70 /G74 /G69 /G6F /G6E /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G57 /G61 /G6B /G65 /G2D /G75 /G70 /G57 /G65 /G61 /G6B /G50 /G75 /G6C /G6C /G2D /G75 /G70 /G44 /G51 /G43 /G4B /G53 /G51 /G44 /G51 /G43 /G4B /G53 /G51 PA4/PA5 Input/Output Ports

Rev. 1.00 16 November 28, 2007 /G56 /G44 /G44 /G4D /G55 /G58 /G52 /G65 /G61 /G64 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G42 /G69 /G74 /G50 /G75 /G6C /G6C /G2D /G48 /G69 /G67 /G68 /G4F /G70 /G74 /G69 /G6F /G6E /G44 /G61 /G74 /G61 /G20 /G42 /G75 /G73 /G57 /G72 /G69 /G74 /G65 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G68 /G69 /G70 /G20 /G52 /G65 /G73 /G65 /G74 /G52 /G65 /G61 /G64 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G57 /G72 /G69 /G74 /G65 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G44 /G61 /G74 /G61 /G20 /G42 /G69 /G74 /G50 /G42 /G30 /G2F /G41 /G4E /G30 /G7E /G50 /G42 /G35 /G2F /G41 /G4E /G35 /G41 /G43 /G53 /G32 /G7E /G41 /G43 /G53 /G30 /G54 /G6F /G20 /G41 /G2F /G44 /G20 /G43 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G50 /G43 /G52 /G32 /G50 /G43 /G52 /G31 /G50 /G43 /G52 /G30 /G57 /G65 /G61 /G6B /G50 /G75 /G6C /G6C /G2D /G75 /G70 /G41 /G6E /G61 /G6C /G6F /G67 /G49 /G6E /G70 /G75 /G74 /G53 /G65 /G6C /G65 /G63 /G74 /G6F /G72 /G44 /G51 /G43 /G4B /G53 /G51 /G44 /G51 /G43 /G4B /G53 /G51 PB Input/Output Ports /G56 /G44 /G44 /G50 /G46 /G44 /G20 /G6F /G72 /G20 /G50 /G57 /G4D /G20 /G57 /G61 /G76 /G65 /G66 /G6F /G72 /G6D /G4D /G55 /G58 /G52 /G65 /G61 /G64 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G42 /G69 /G74 /G50 /G75 /G6C /G6C /G2D /G48 /G69 /G67 /G68 /G4F /G70 /G74 /G69 /G6F /G6E /G44 /G61 /G74 /G61 /G20 /G42 /G75 /G73 /G57 /G72 /G69 /G74 /G65 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G43 /G68 /G69 /G70 /G20 /G52 /G65 /G73 /G65 /G74 /G52 /G65 /G61 /G64 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G57 /G72 /G69 /G74 /G65 /G20 /G44 /G61 /G74 /G61 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G44 /G61 /G74 /G61 /G20 /G42 /G69 /G74 /G50 /G46 /G44 /G2F /G50 /G57 /G4D /G20 /G4F /G70 /G74 /G69 /G6F /G6E /G4D /G55 /G58 /G57 /G65 /G61 /G6B /G50 /G75 /G6C /G6C /G2D /G75 /G70 /G44 /G51 /G43 /G4B /G53 /G51 /G44 /G51 /G43 /G4B /G53 /G51 /G50 /G41 /G33 /G2F /G50 /G46 /G44 /G50 /G44 /G30 /G2F /G50 /G57 /G4D /G30 /G50 /G44 /G31 /G2F /G50 /G57 /G4D /G31 PA3/PFD and PD/PWM Input/Output Ports

Rev. 1.00 17 November 28, 2007 Programming Considerations Within the user program, one of the first things to con - sider is port initialisation. After a reset, all of the I/O data and port control registers will be set high. This means that all I/O pins will default to an input state, the level of which depends on the other connected circuitry and whether pull-high options have been selected. If the port control registers, PAC, PBC, PCC and PDC, are then programmed to setup some pins as outputs, these out- put pins will have an initial high output value unless the associated port data registers, PA, PB, PC and PD, are first programmed. Selecting which pins are inputs and which are outputs can be achieved byte-wide by loading the correct values into the appropriate port control regis- ter or by programming individual bits in the port control register using the /c178SET [m].i/c178and /c178CLR [m].i/c178instruc- tions. Note that when using these bit control instruc - tions, a read-modify-write operation takes place. The microcontroller must first read in the data on the entire port, modify it to the required new bit values and then re- write this data back to the output ports. Port A has the additional capability of providing wake-up functions. When the device is in the Power Down Mode, various methods are available to wake the device up. One of these is a high to low transition of any of the Port A pins. Single or multiple pins on Port A can be setup to have this function. Timer/Event Counters The provision of timers form an important part of any microcontroller, giving the designer a means of carrying out time related functions. The device contains two 8-bit count up timers. With three different operating modes, the timers can be configured to operate as a general timer, an external event counter or as a Pulse Width Measurement device. The provision of an internal 8- stage prescaler to the one clock circuitry of the timer/ event counters gives added range to the timer. There are two types of registers related to the Timer/Event Counters. The first is the register that con- tains the actual value of the timer and into which an ini- tial value can be preloaded. Reading from this register retrieves the contents of the Timer/Event Counter. The second type of associated register is the timer control register which defines the timer options and determines how the timer is to be used. The devices can have the timer clock configured to come from the internal clock source. In addition, the timer clock source can also be configured to come from an external timer pin. An external clock source is used when the timer is in the event counting mode, the clock source being provided on pin-shared pin PA4/TMR0 or PA7/TMR1. Depending upon the condition of the T0E or T1E bit in the corre - sponding timer control register, each high to low, or low to high transition on the external timer input pin will in - crement the counter by one. Configuring the Timer/Event Counter Input Clock Source The internal timer /c162s clock can originate from various sources, depending upon which timer is chosen. The in- ternal clock input timer source is used when the timer is in the timer mode or in the Pulse Width Measurement mode. Depending upon which timer is chosen this sys- tem clock timer source may be first divided by a prescaler, the division ratio of which is conditioned by the timer control register bits PSC2~PSC0. An external clock source is used when the timer is in the event counting mode, the clock source being provided on an external timer pin, TMR0 or TMR1 depending upon which timer is used. Depending upon the condition of the T0E or T1E bit, each high to low, or low to high transition on the external timer pin will increment the counter by one. Timer Register /c45TMR0, TMR1 The timer register are special function register location within the special purpose Data Memory where the ac- tual timer value is stored. The value in the timer registers increases by one each time an internal clock pulse is re- ceived or an external transition occurs on the PA4/TMR0 or PA7/TMR1 pin. The timer will count from the initial value loaded by the preload register to the full count value of FFH at which point the timer overflows and an internal interrupt signal generated. The timer value will then be reset with the initial preload register value and continue counting. For a maximum full range count of 00H to FFH the preload register must first be cleared to 00H. It should be noted that after power-on the preload register will be in an unknown condition. Note that if the Timer/Event Counter is not running and data is written to its preload register, this data will be im- mediately written into the actual counter. However, if the counter is enabled and counting, any new data written into the preload register during this period will remain in the preload register and will only be written into the ac- tual counter the next time an overflow occurs. /G54 /G31 /G54 /G32 /G54 /G33 /G54 /G34 /G54 /G31 /G54 /G32 /G54 /G33 /G54 /G34 /G57 /G72 /G69 /G74 /G65 /G20 /G74 /G6F /G20 /G50 /G6F /G72 /G74 /G52 /G65 /G61 /G64 /G20 /G66 /G72 /G6F /G6D /G20 /G50 /G6F /G72 /G74 /G53 /G79 /G73 /G74 /G65 /G6D /G20 /G43 /G6C /G6F /G63 /G6B /G50 /G6F /G72 /G74 /G20 /G44 /G61 /G74 /G61 Read/Write Timing

Rev. 1.00 18 November 28, 2007 Timer Control Register /c45TMR0C, TMR1C The flexible features of the Holtek microcontroller Timer/ Event Counters enable them to operate in three different modes, the options of which are determined by the con- tents of their respective control register. The device con- tains two timer control registers known as TMR0C and TMR1C. It is the timer control register together with its corresponding timer registers that control the full opera- tion of the Timer/Event Counters. Before the timers can be used, it is essential that the appropriate timer control register is fully programmed with the right data to ensure its correct operation, a process that is normally carried out during program initialisation. To choose which of the three modes the timer is to oper- ate in, either in the timer mode, the event counting mode or the Pulse Width Measurement mode, bits 7 and 6 of the Timer Control Register, which are known as the bit pair T0M1/T0M0 or T1M1/T1M0 respectively, depend - ing upon which timer is used, must be set to the required logic levels. The timer-on bit, which is bit 4 of the Timer Control Register and known as T0ON or T1ON, depend- ing upon which timer is used, provides the basic on/off control of the respective timer. Setting the bit high allows the counter to run, clearing the bit stops the counter. Timer/Event Counter 0 also contains a prescaler func - tion, with bits 0~2 of the Timer Control Register deter - mining the division ratio of the input clock. The prescaler bit settings have no effect if an external clock source is used. If the timer is in the Event Count or Pulse Width Measurement mode, the active transition edge level type is selected by the logic level of bit 3 of the Timer Control Register which is known as T0E or T1E, de- pending upon which timer is used. Configuring the Timer Mode In this mode, the timer can be utilized to measure fixed time intervals, providing an internal interrupt signal each time the counter overflows. To operate in this mode, the bit pair, T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 1 and 0 respectively. In this mode the internal clock is used as the timer clock. Note that for the Timer/Event Counter 0, the timer input clock frequency is further divided by a prescaler, the value of which is determined by the bits PSC2~PSC0 in the Timer Control Register. The timer-on bit, T0ON or T1ON depending upon which timer is used, must be set high to enable the timer to run. Each time an internal clock high to low transition occurs, the timer increments by one; when the timer is full and overflows, an interrupt signal is generated and the timer will preload the value already loaded into the preload register and continue counting. A timer overflow condition and corresponding internal interrupt is one of the wake-up sources, how - ever, the internal interrupts can be disabled by ensuring that the ET0I and ET1I bits of the respective interrupt register are reset to zero. It should be noted that a timer overflow is one of the interrupt and wake-up sources. /G50 /G41 /G34 /G2F /G54 /G4D /G52 /G30 /G54 /G30 /G45 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G4D /G6F /G64 /G65 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G54 /G30 /G4F /G4E /G50 /G72 /G65 /G6C /G6F /G61 /G64 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G44 /G61 /G74 /G61 /G20 /G42 /G75 /G73 /G52 /G65 /G6C /G6F /G61 /G64 /G4F /G76 /G65 /G72 /G66 /G6C /G6F /G77 /G74 /G6F /G20 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G20 /G20 /G32 /G38 /G2D /G73 /G74 /G61 /G67 /G65 /G20 /G50 /G72 /G65 /G73 /G63 /G61 /G6C /G65 /G72 /G50 /G53 /G43 /G32 /G7E /G50 /G53 /G43 /G30 /G28 /G31 /G2F /G31 /G7E /G31 /G2F /G31 /G32 /G38 /G29 /G38 /G2D /G42 /G69 /G74 /G20 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G54 /G30 /G4D /G31 /G54 /G30 /G4D /G30 /G20 /G20 /G66 /G53 /G59 /G53 /G50 /G46 /G44 /GB8 8-bit Timer/Event Counter 0 Structure /G50 /G41 /G37 /G2F /G54 /G4D /G52 /G31 /G54 /G31 /G45 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G4D /G6F /G64 /G65 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G54 /G31 /G4F /G4E /G50 /G72 /G65 /G6C /G6F /G61 /G64 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G44 /G61 /G74 /G61 /G20 /G42 /G75 /G73 /G52 /G65 /G6C /G6F /G61 /G64 /G4F /G76 /G65 /G72 /G66 /G6C /G6F /G77 /G74 /G6F /G20 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G38 /G2D /G42 /G69 /G74 /G20 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G54 /G31 /G4D /G31 /G54 /G31 /G4D /G30 /G20 /G20 /G66 /G53 /G59 /G53 /G2F /G34 8-bit Timer/Event Counter 1 Structure

Rev. 1.00 19 November 28, 2007 /G54 /G4D /G52 /G30 /G43 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 /G62 /G37 /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G41 /G63 /G74 /G69 /G76 /G65 /G20 /G45 /G64 /G67 /G65 /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G31 /G3A /G20 /G63 /G6F /G75 /G6E /G74 /G20 /G6F /G6E /G20 /G66 /G61 /G6C /G6C /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G30 /G3A /G20 /G63 /G6F /G75 /G6E /G74 /G20 /G6F /G6E /G20 /G72 /G69 /G73 /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G20 /G54 /G30 /G45 /G54 /G30 /G4F /G4E /G54 /G30 /G4D /G30 /G54 /G30 /G4D /G31 /G54 /G69 /G6D /G65 /G72 /G20 /G50 /G72 /G65 /G73 /G63 /G61 /G6C /G65 /G72 /G20 /G52 /G61 /G74 /G65 /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G62 /G30 /G50 /G53 /G43 /G32 /G50 /G53 /G43 /G31 /G50 /G53 /G43 /G30 /G50 /G53 /G43 /G31 /G30 /G30 /G31 /G31 /G30 /G30 /G31 /G31 /G50 /G53 /G43 /G32 /G30 /G30 /G30 /G30 /G31 /G31 /G31 /G31 /G50 /G53 /G43 /G30 /G30 /G31 /G30 /G31 /G30 /G31 /G30 /G31 /G54 /G69 /G6D /G65 /G72 /G20 /G52 /G61 /G74 /G65 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G31 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G32 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G34 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G38 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G31 /G36 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G33 /G32 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G36 /G34 /G20 /G20 /G20 /G20 /G20 /G31 /G3A /G31 /G32 /G38 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G30 /G20 /G43 /G6F /G75 /G6E /G74 /G69 /G6E /G67 /G20 /G45 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G30 /G3A /G20 /G64 /G69 /G73 /G61 /G62 /G6C /G65 /G4F /G70 /G65 /G72 /G61 /G74 /G69 /G6E /G67 /G20 /G4D /G6F /G64 /G65 /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G54 /G30 /G4D /G31 /G30 /G30 /G31 /G31 /G54 /G30 /G4D /G30 /G30 /G31 /G30 /G31 /G6E /G6F /G20 /G6D /G6F /G64 /G65 /G20 /G61 /G76 /G61 /G69 /G6C /G61 /G62 /G6C /G65 /G65 /G76 /G65 /G6E /G74 /G20 /G63 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G6D /G6F /G64 /G65 /G20 /G74 /G69 /G6D /G65 /G72 /G20 /G6D /G6F /G64 /G65 /G70 /G75 /G6C /G73 /G65 /G20 /G77 /G69 /G64 /G74 /G68 /G20 /G6D /G65 /G61 /G73 /G75 /G72 /G65 /G6D /G65 /G6E /G74 /G20 /G6D /G6F /G64 /G65 /G50 /G75 /G6C /G73 /G65 /G20 /G57 /G69 /G64 /G74 /G68 /G20 /G4D /G65 /G61 /G73 /G75 /G72 /G65 /G6D /G65 /G6E /G74 /G20 /G41 /G63 /G74 /G69 /G76 /G65 /G20 /G45 /G64 /G67 /G65 /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G31 /G3A /G20 /G73 /G74 /G61 /G72 /G74 /G20 /G63 /G6F /G75 /G6E /G74 /G69 /G6E /G67 /G20 /G6F /G6E /G20 /G72 /G69 /G73 /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G2C /G20 /G73 /G74 /G6F /G70 /G20 /G6F /G6E /G20 /G66 /G61 /G6C /G6C /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G30 /G3A /G20 /G73 /G74 /G61 /G72 /G74 /G20 /G63 /G6F /G75 /G6E /G74 /G69 /G6E /G67 /G20 /G6F /G6E /G20 /G66 /G61 /G6C /G6C /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G2C /G20 /G73 /G74 /G6F /G70 /G20 /G6F /G6E /G20 /G72 /G69 /G73 /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G20 Timer/Event Counter 0 Control Register /G54 /G4D /G52 /G31 /G43 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 /G62 /G37 /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G41 /G63 /G74 /G69 /G76 /G65 /G20 /G45 /G64 /G67 /G65 /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G31 /G3A /G20 /G63 /G6F /G75 /G6E /G74 /G20 /G6F /G6E /G20 /G66 /G61 /G6C /G6C /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G30 /G3A /G20 /G63 /G6F /G75 /G6E /G74 /G20 /G6F /G6E /G20 /G72 /G69 /G73 /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G20 /G54 /G31 /G45 /G54 /G31 /G4F /G4E /G54 /G31 /G4D /G30 /G54 /G31 /G4D /G31 /G62 /G30 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G31 /G20 /G43 /G6F /G75 /G6E /G74 /G69 /G6E /G67 /G20 /G45 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G30 /G3A /G20 /G64 /G69 /G73 /G61 /G62 /G6C /G65 /G4F /G70 /G65 /G72 /G61 /G74 /G69 /G6E /G67 /G20 /G4D /G6F /G64 /G65 /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G54 /G31 /G4D /G31 /G30 /G30 /G31 /G31 /G54 /G31 /G4D /G30 /G30 /G31 /G30 /G31 /G6E /G6F /G20 /G6D /G6F /G64 /G65 /G20 /G61 /G76 /G61 /G69 /G6C /G61 /G62 /G6C /G65 /G65 /G76 /G65 /G6E /G74 /G20 /G63 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G6D /G6F /G64 /G65 /G20 /G74 /G69 /G6D /G65 /G72 /G20 /G6D /G6F /G64 /G65 /G70 /G75 /G6C /G73 /G65 /G20 /G77 /G69 /G64 /G74 /G68 /G20 /G6D /G65 /G61 /G73 /G75 /G72 /G65 /G6D /G65 /G6E /G74 /G20 /G6D /G6F /G64 /G65 /G50 /G75 /G6C /G73 /G65 /G20 /G57 /G69 /G64 /G74 /G68 /G20 /G4D /G65 /G61 /G73 /G75 /G72 /G65 /G6D /G65 /G6E /G74 /G20 /G41 /G63 /G74 /G69 /G76 /G65 /G20 /G45 /G64 /G67 /G65 /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G31 /G3A /G20 /G73 /G74 /G61 /G72 /G74 /G20 /G63 /G6F /G75 /G6E /G74 /G69 /G6E /G67 /G20 /G6F /G6E /G20 /G72 /G69 /G73 /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G2C /G20 /G73 /G74 /G6F /G70 /G20 /G6F /G6E /G20 /G66 /G61 /G6C /G6C /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G30 /G3A /G20 /G73 /G74 /G61 /G72 /G74 /G20 /G63 /G6F /G75 /G6E /G74 /G69 /G6E /G67 /G20 /G6F /G6E /G20 /G66 /G61 /G6C /G6C /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G2C /G20 /G73 /G74 /G6F /G70 /G20 /G6F /G6E /G20 /G72 /G69 /G73 /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G20 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 Timer/Event Counter 1 Control Register

Rev. 1.00 20 November 28, 2007 Configuring the Event Counter Mode In this mode, a number of externally changing logic events, occurring on the external timer pin, can be re - corded by the internal timer. For the timer to operate in the event counting mode, the bit pair T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must be set to 0 and 1 respectively. The timer-on bit T0ON or T1ON, depending upon which timer is used, must be set high to enable the timer to count. Depending upon which counter is used, if T0E or T1E is low, the counter will in- crement each time the external timer pin receives a low to high transition. If T0E or T1E is high, the counter will increment each time the external timer pin receives a high to low transition. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal interrupt signal. The counter will then preload the value already loaded into the preload register. As the external timer pins are pin-shared with other I/O pins, to ensure that the pin is configured to operate as an event counter input pin, two things have to happen. The first is to ensure that the T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event Counter in the event counting mode, the second is to en- sure that the port control register configures the pin as an input. It should be noted that a timer overflow is one of the interrupt and wake-up sources. Also in the Event Counting mode, the Timer/Event Counter will continue to record externally changing logic events on the timer input pin, even if the microcontroller is in the Power Down Mode. As a result when the timer overflows it will generate a wake-up and if the interrupts are enabled also generate a timer interrupt signal. Configuring the Pulse Width Measurement Mode In this mode, the width of external pulses applied to the pin-shared external pin PA4/TMR0 or PA7/TMR1 can be measured. In the Pulse Width Measurement Mode the timer clock source is supplied by the internal clock. For the timer to operate in this mode, the bit pair T0M1/T0M0 or T1M1/T1M0, depending upon which timer is used, must both be set high. Depending upon which counter is used, if T0E or T1E is low, once a high to low transition has been received on the PA4/TMR0 or PA7/TMR1 pin, the timer will start counting until the PA4/TMR0 or PA7/TMR1 pin returns to its original high level. At this point the T0ON or T1ON bit, depending upon which counter is used, will be automatically reset to zero and the timer will stop counting. If the T0E or T1E bit is high, the timer will begin counting once a low to high transition has been received on the PA4/TMR0 or PA7/TMR1 pin and stop counting when the PA4/TMR0 or PA7/TMR1 pin returns to its original low level. As be- fore, the T0ON or T1ON bit will be automatically reset to zero and the timer will stop counting. It is important to note that in the Pulse Width Measurement Mode, the T0ON or T1ON bit is automatically reset to zero when the external control signal on the external timer pin re- turns to its original level, whereas in the other two modes the T0ON or T1ON bit can only be reset to zero under program control. The residual value in the timer, which can now be read by the program, therefore repre- sents the length of the pulse received on the PA4/TMR0 or PA7/TMR1 pin. As the T0ON or T1ON bit has now been reset, any further transitions on the external timer pin, will be ignored. Not until the T0ON or T1ON bit is again set high by the program can the timer begin fur - ther Pulse Width Measurements. In this way, single shot pulse measurements can be easily made. It should be noted that in this mode the counter is controlled by logi- cal transitions on the PA4/TMR0 or PA7/TMR1 pin and not by the logic level. As in the case of the other two modes, when the counter is full, the timer will overflow and generate an internal in- terrupt signal. The counter will also be reset to the value already loaded into the preload register. As the external timer pins are pin-shared with other I/O pins, to ensure that the pins are configured to operate as pulse width measuring input pins, two things have to happen. The first is to ensure that the T0M1/T0M0 or T1M1/T1M0 bits place the Timer/Event Counter in the pulse width mea - suring mode, the second is to ensure that the port con- trol register configures the pin as an input. It should be noted that a timer overflow is one of the interrupt and wake-up sources. /G49 /G6E /G63 /G72 /G65 /G6D /G65 /G6E /G74 /G54 /G69 /G6D /G65 /G72 /G20 /G43 /G6F /G6E /G74 /G72 /G6F /G6C /G6C /G65 /G72 /G50 /G72 /G65 /G73 /G63 /G61 /G6C /G65 /G72 /G20 /G4F /G75 /G74 /G70 /G75 /G74 /G54 /G69 /G6D /G65 /G72 /G20 /G2B /G20 /G31 /G54 /G69 /G6D /G65 /G72 /G20 /G2B /G20 /G32 /G54 /G69 /G6D /G65 /G72 /G20 /G2B /G20 /G4E /G54 /G69 /G6D /G65 /G72 /G20 /G2B /G20 /G4E /G20 /G2B /G20 /G31 Timer Mode Timing Chart /G54 /G69 /G6D /G65 /G72 /G2B /G32 /G45 /G78 /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G45 /G76 /G65 /G6E /G74 /G49 /G6E /G63 /G72 /G65 /G6D /G65 /G6E /G74 /G54 /G69 /G6D /G65 /G72 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G54 /G69 /G6D /G65 /G72 /G2B /G33 /G54 /G69 /G6D /G65 /G72 /G2B /G31 Event Counter Mode Timing Chart

Rev. 1.00 21 November 28, 2007 /G2B /G31 /G2B /G32 /G2B /G33 /G2B /G34 /G54 /G69 /G6D /G65 /G72 /G45 /G78 /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G54 /G69 /G6D /G65 /G72 /G50 /G69 /G6E /G20 /G49 /G6E /G70 /G75 /G74 /G54 /G30 /G4F /G4E /G20 /G6F /G72 /G20 /G54 /G31 /G4F /G4E /G28 /G77 /G69 /G74 /G68 /G20 /G54 /G30 /G45 /G20 /G6F /G72 /G20 /G54 /G31 /G45 /G3D /G30 /G29 /G50 /G72 /G65 /G73 /G63 /G61 /G6C /G65 /G72 /G20 /G4F /G75 /G74 /G70 /G75 /G74 /G49 /G6E /G63 /G72 /G65 /G6D /G65 /G6E /G74 /G54 /G69 /G6D /G65 /G72 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G50 /G72 /G65 /G73 /G63 /G61 /G6C /G65 /G72 /G20 /G4F /G75 /G74 /G70 /G75 /G74 /G20 /G69 /G73 /G20 /G73 /G61 /G6D /G70 /G6C /G65 /G64 /G20 /G61 /G74 /G20 /G65 /G76 /G65 /G72 /G79 /G20 /G66 /G61 /G6C /G6C /G69 /G6E /G67 /G20 /G65 /G64 /G67 /G65 /G20 /G6F /G66 /G20 /G54 /G31 /G2E Pulse Width Measure Mode Timing Chart /G54 /G69 /G6D /G65 /G72 /G20 /G4F /G76 /G65 /G72 /G66 /G6C /G6F /G77 /G50 /G46 /G44 /G20 /G43 /G6C /G6F /G63 /G6B /G50 /G41 /G33 /G20 /G44 /G61 /G74 /G61 /G50 /G46 /G44 /G20 /G4F /G75 /G74 /G70 /G75 /G74 /G20 /G61 /G74 /G20 /G50 /G41 /G33 PFD Output Control Programmable Frequency Divider /c45PFD The PFD output is pin-shared with the I/O pin PA3. The PFD function is selected via configuration option, how- ever, if not selected, the pin can operate as a normal I/O pin. The timer overflow signal from Timer/Event Counter 0 is the clock source for the PFD circuit. The output fre- quency is controlled by loading the required values into the timer registers and programming the prescaler bits to give the required division ratio. The counter, driven by the system clock which is divided by the prescaler value, will begin to count-up from this preload register value until full, at which point an overflow signal is generated, causing the PFD output to change state. The counter will then be automatically reloaded with the preload reg- ister value and continue counting-up. For the PFD output to function, it is essential that the corresponding bit of the Port A control register PAC bit 3 is setup as an output. If setup as an input the PFD output will not function, however, the pin can still be used as a normal input pin. The PFD output will only be activated if bit PA3 is set to /c1781/c178. This output data bit is used as the on/off control bit for the PFD output. Note that the PFD output will be low if the PA3 output data bit is cleared to /c1780/c178. Using this method of frequency generation, and if a crystal oscillator is used for the system clock, very pre- cise values of frequency can be generated. Prescaler Bits PSC0~PSC2 of the TMR0C register can be used to define the pre-scaling stages of the internal clock source of Timer/Event Counter 0. The Timer/Event Counter 0 overflow signal can be used to generate signals for the PFD and Timer 0 interrupt. I/O Interfacing The Timer/Event Counter, when configured to run in the event counter or pulse width measurement mode, re- quire the use of the external PA4/TMR0 or PA7/TMR1 pin for correct operation. As these pins are shared pins they must be configured correctly to ensure they are setup for use as Timer/Event Counter inputs and not as normal I/O pins. This is implemented by ensuring that the mode select bits in the Timer/Event Counter control register, select either the event counter or pulse width measurement mode. Additionally the Port Control Reg- ister PAC bit 4 or bit 7 must be set high to ensure that the pin is setup as an input. Any pull-high resistor configura- tion option on this pin will remain valid even if the pin is used as a Timer/Event Counter input. Programming Considerations When configured to run in the timer mode, the internal system clock is used as the timer clock source and is therefore synchronised with the overall operation of the microcontroller. In this mode when the appropriate timer register is full, the microcontroller will generate an inter- nal interrupt signal directing the program flow to the re- spective internal interrupt vector. For the pulse width measurement mode, the internal system clock is also used as the timer clock source but the timer will only run when the correct logic condition appears on the external

Rev. 1.00 22 November 28, 2007 timer input pin. As this is an external event and not syn- chronised with the internal timer clock, the microcontroller will only see this external event when the next timer clock pulse arrives. As a result, there may be small differences in measured values requiring pro - grammers to take this into account during programming. The same applies if the timer is configured to be in the event counting mode, which again is an external event and not synchronised with the internal system or timer clock. When the Timer/Event Counter is read, or if data is writ- ten to the preload register, the clock is inhibited to avoid errors, however as this may result in a counting error, this should be taken into account by the programmer. Care must be taken to ensure that the timers are properly in- itialised before using them for the first time. The associ- ated timer enable bits in the interrupt control register must be properly set otherwise the internal interrupt associated with the timer will remain inactive. The edge select, timer mode and clock source control bits in timer control regis- ter must also be correctly set to ensure the timer is prop- erly configured for the required application. It is also important to ensure that an initial value is first loaded into the timer registers before the timer is switched on; this is because after power-on the initial values of the timer reg- isters are unknown. After the timer has been initialised the timer can be turned on and off by controlling the en- able bit in the timer controlregister.Note that setting the timer enable bit high to turn the timer on, should only be executed after the timer mode bits have been properly setup. Setting the timer enable bit high together with a mode bit modification, may lead to improper timer oper- ation if executed as a single timer control register byte write instruction. When the Timer/Event counter overflows, its corre - sponding interrupt request flag in the interrupt control register will be set. If the timer interrupt is enabled this will in turn generate an interrupt signal. However irre - spective of whether the interrupts are enabled or not, a Timer/Event counter overflow will also generate a wake-up signal if the device is in a Power-down condi - tion. This situation may occur if the Timer/Event Counter is in the Event Counting Mode and if the external signal continues to change state. In such a case, the Timer/Event Counter will continue to count these exter- nal events and if an overflow occurs the device will be woken up from its Power-down condition. To prevent such a wake-up from occurring, the timer interrupt re - quest flag should first be set high before issuing the HALT instruction to enter the Power Down Mode. Timer Program Example This program example shows how the Timer/Event Counter registers are setup, along with how the inter - rupts are enabled and managed. Note how the Timer/Event Counter 0 is turned on, by setting bit 4 of the TMR0C as an independent instruction. The Timer/ Event Counter 0 can be turned off in a similar way by clearing the same bit. This example program sets the Timer/Event Counter 0 to be in the timer mode, which uses the internal system clock as the clock source. org 04h ; external interrupt vector reti org 08h ; Timer/Event Counter interrupt vector jmp tmrint0 ; jump here when Timer/Event Counter 0 overflows org 20h ; main program ;internal Timer/Event Counter 0 interrupt routine tmrint0: ; Timer/Event Counter 0 main program placed here reti begin: ;setup Timer registers mov a,09bh ; setup Timer preload value mov tmr0,a; mov a,081h ; setup Timer control register mov tmrc0,a ; timer mode and prescaler set to /2 ; setup interrupt register mov a,005h ; enable Master and Timer/Event Counter 0 interrupt mov intc0,a set tmr0c.4 ; start Timer/Event Counter 0 - note mode bits must be previously setup

Rev. 1.00 23 November 28, 2007 Pulse Width Modulator The device contains two Pulse Width Modulation, PWM, outputs. Useful for such applications such as motor speed control, the PWM function provides outputs with a fixed frequency but with a duty cycle that can be varied by setting particular values into the corresponding PWM register. Channels PWM Mode Output Pins Register Name 2 6+2 PD0/ PD1 PWM0/ PWM1 Two registers are provided and are known as PWM0 and PWM1. It is in these registers, that the 8-bit value, which represents the overall duty cycle of one modula - tion cycle of the output waveform, should be placed. To increase the PWM modulation frequency, each modula- tion cycle is modulated into four individual modulation sub-sections, known as the 6+2 mode. Note that it is only necessary to write the required modulation value into the corresponding PWM register as the subdivision of the waveform into its sub-modulation cycles is imple- mented automatically within the microcontroller hard - ware. For all devices, the PWM clock source is the system clock f SYS. This method of dividing the original modulation cycle into a further 4 sub-cycles enables the generation of higher PWM frequencies, which allow a wider range of applications to be served. As long as the periods of the generated PWM pulses are less than the time constants of the load, the PWM output will be suitable as such long time constant loads will average out the pulses of the PWM output. The difference between what is known as the PWM cycle frequency and the PWM modulation fre- quency should be understood. As the PWM clock is the system clock, f SYS, and as the PWM value is 8-bits wide, the overall PWM cycle frequency is f SYS/256, while the PWM modulation frequency for the 6+2 mode of opera- tion will be fSYS/64. PWM Modulation Frequency PWM Cycle Frequency PWM Cycle Duty fSYS/64 f SYS/256 (PWM register value)/256 6+2 PWM Mode Each full PWM cycle, as it is controlled by an 8-bit PWM, PWM0 or PWM1 register, has 256 clock periods. How- ever, in the 6+2 PWM Mode, each PWM cycle is subdi- vided into four individual sub-cycles known as modulation cycle 0~modulation cycle 3, denoted as /c178i/c178 in the table. Each one of these four sub-cycles contains 64 clock cycles. In this mode, a modulation frequency increase by a factor of four is achieved. The 8-bit PWM, PWM0 or PWM1 register value, which represents the overall duty cycle of the PWM waveform, is divided into two groups. The first group which consists of bit2~bit7 is denoted here as the DC value. The second group which consists of bit0~bit1 is known as the AC value. In the 6+2 PWM mode, the duty cycle value of each of the four modulation sub-cycles is shown in the following table. Parameter AC (0~3) DC (Duty Cycle) Modulation cycle i (i=0~3) i<AC DC 1 i/c179AC DC 6+2 Mode Modulation Cycle Values The diagram illustrates the waveforms associated with the 6+2 mode of PWM operation. It is important to note how the single PWM cycle is subdivided into 4 individual modulation cycles, numbered from 0~3 and how the AC value is related to the PWM value. PWM Output Control The PWM outputs are pin-shared with pins PD0 and PD1. To operate as PWM outputs and not as I/O pins, the correct PWM configuration options must be se - lected. A /c1780/c178must also be written to the corresponding bit in the I/O port control register, PDC, to ensure that the required PWM output pin is setup as an output. After these two initial steps have been carried out, and of course after the required PWM value has been written into the PWM register, writing a/c1781/c178to the corresponding bit in the PD output data register will enable the PWM data to appear on the pin. Writing a /c1780/c178to the corre - sponding bit in the PD output data register will disable the PWM output function and force the output low. In this way, the Port D data output register can be used as an on/off control for the PWM function. Note that if the con- figuration options have selected the PWM function, but a /c1781/c178has been written to its corresponding bit in the PDC control register to configure the pin as an input, then the pin can still function as a normal input line, with pull-high resistor options.

Rev. 1.00 24 November 28, 2007 PWM Programming Example The following sample program shows how the PWM outputs are setup and controlled. Before use the corresponding PWM output configuration options must first be selected. mov a,64h ; setup PWM0 value of 100 decimal which is 64H mov pwm0,a clr pdc.0 ; setup pin PD0 as an output set pd.0 ; PD.0=1; enable the PWM0 output clr pd.0 ; disable the PWM0 output - PD0 will remain low /G66 /G53 /G59 /G53 /G2F /G32 /G50 /G57 /G4D /G5B /G50 /G57 /G4D /G5D /G20 /G3D /G31 /G30 /G30 /G5B /G50 /G57 /G4D /G5D /G20 /G3D /G31 /G30 /G31 /G50 /G57 /G4D /G5B /G50 /G57 /G4D /G5D /G20 /G3D /G31 /G30 /G32 /G50 /G57 /G4D /G5B /G50 /G57 /G4D /G5D /G20 /G3D /G31 /G30 /G33 /G50 /G57 /G4D /G50 /G57 /G4D /G20 /G63 /G79 /G63 /G6C /G65 /G20 /G3A /G20 /G32 /G35 /G36 /G2F /G66 /G53 /G59 /G53 /G32 /G35 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G35 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G32 /G36 /G2F /G36 /G34 /G4D /G6F /G64 /G75 /G6C /G61 /G74 /G69 /G6F /G6E /G20 /G63 /G79 /G63 /G6C /G65 /G20 /G30 /G50 /G57 /G4D /G20 /G6D /G6F /G64 /G75 /G6C /G61 /G74 /G69 /G6F /G6E /G20 /G70 /G65 /G72 /G69 /G6F /G64 /G20 /G3A /G20 /G36 /G34 /G2F /G66 /G53 /G59 /G53 /G4D /G6F /G64 /G75 /G6C /G61 /G74 /G69 /G6F /G6E /G20 /G63 /G79 /G63 /G6C /G65 /G20 /G31 /G4D /G6F /G64 /G75 /G6C /G61 /G74 /G69 /G6F /G6E /G20 /G63 /G79 /G63 /G6C /G65 /G20 /G32 /G4D /G6F /G64 /G75 /G6C /G61 /G74 /G69 /G6F /G6E /G20 /G63 /G79 /G63 /G6C /G65 /G20 /G33 /G4D /G6F /G64 /G75 /G6C /G61 /G74 /G69 /G6F /G6E /G20 /G63 /G79 /G63 /G6C /G65 /G20 /G30 6+2 PWM Mode /G50 /G57 /G4D /G30 /G2C /G20 /G50 /G57 /G4D /G31 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G62 /G37 /G62 /G30 /G41 /G43 /G20 /G20 /G76 /G61 /G6C /G75 /G65 /G44 /G43 /G20 /G76 /G61 /G6C /G75 /G65 Pulse Width Modulation Registers

Rev. 1.00 25 November 28, 2007 Analog to Digital Converter The need to interface to real world analog signals is a common requirement for many electronic systems. However, to properly process these signals using a microcontroller, they must first be converted into digital signals by A/D converters. By integrating the A/D con - version electronic circuitry into the microcontroller, the need for external components is reduced significantly with the corresponding follow-on benefits of lower costs and reduced component space requirements. A/D Overview The device contains a 6-channel analog to digital con - verter which can directly interface to external analog sig- nals, such as that from sensors or other control signals and convert these signals directly into an 9-bit digital value. Input Channels Conversion Bits Input Pins 6 9 PB0~PB5 The diagram shows the overall internal structure of the A/D converter, together with its associated registers. A/D Converter Data Registers /c45ADRL, ADRH The device, has a 9-bit A/D converter, two registers are required, a high byte register, known as ADRH, and a low byte register, known as ADRL. After the conversion process takes place, these registers can be directly read by the microcontroller to obtain the digitised conversion value. For devices which use two A/D Converter Data Registers, note that only the high byte register ADRH utilises its full 8-bit contents. The low byte register uti- lises only 1 bit of its 8-bit contents as it contains only the lowest bit of the 9-bit converted value. In the following table, D0~D8 is the A/D conversion data result bits. Register Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 ADRL D0 /c190/c190/c190/c190/c190/c190/c190 ADRH D8 D7 D6 D5 D4 D3 D2 D1 A/D Data Register A/D Converter Control Register /c45ADCR To control the function and operation of the A/D con - verter, a control register known as ADCR is provided. This 8-bit register defines functions such as the selec - tion of which analog channel is connected to the internal A/D converter, which pins are used as analog inputs and which are used as normal I/Os as well as controlling the start function and monitoring the A/D converter end of conversion status. One section of this register contains the bits ACS2~ACS0 which define the channel number. As each of the devices contains only one actual analog to digital converter circuit, each of the individual 6 analog inputs must be routed to the converter. It is the function of the ACS2~ACS0 bits in the ADCR register to determine which analog channel is actually connected to the inter- nal A/D converter. The ADCR control register also contains the PCR2~PCR0 bits which determine which pins on Port B are used as analog inputs for the A/D converter and which pins are to be used as normal I/O pins. If the 3-bit address on PCR2~PCR0 has a value of /c178110/c178, then all six pins, namely AN0, AN1, AN2, AN3, AN4 and AN5 will all be set as analog inputs. Note that if the PCR2~PCR0 bits are all set to zero, then all the Port B pins will be setup as normal I/Os and the internal A/D converter circuitry will be powered off to reduce the power consumption. /G43 /G6C /G6F /G63 /G6B /G20 /G53 /G6F /G75 /G72 /G63 /G65 /G66 /G53 /G59 /G53 /G2F /G32 /GB8 /G4E /G41 /G43 /G53 /G52 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G41 /G44 /G43 /G56 /G44 /G44 /G50 /G42 /G30 /G2F /G41 /G4E /G30 /G50 /G42 /G35 /G2F /G41 /G4E /G35 /G41 /G2F /G44 /G20 /G72 /G65 /G66 /G65 /G72 /G65 /G6E /G63 /G65 /G20 /G76 /G6F /G6C /G74 /G61 /G67 /G65 /G41 /G44 /G52 /G4C /G41 /G44 /G52 /G48 /G50 /G43 /G52 /G30 /G7E /G50 /G43 /G52 /G32 /G41 /G44 /G43 /G53 /G30 /G7E /G41 /G44 /G43 /G53 /G32 /G53 /G54 /G41 /G52 /G54 /G45 /G4F /G43 /G42 /G41 /G44 /G43 /G52 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G50 /G69 /G6E /G20 /G43 /G6F /G6E /G66 /G69 /G67 /G75 /G72 /G61 /G74 /G69 /G6F /G6E /G42 /G69 /G74 /G73 /G43 /G68 /G61 /G6E /G6E /G65 /G6C /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G42 /G69 /G74 /G73 /G53 /G74 /G61 /G72 /G74 /G20 /G61 /G6E /G64 /G20 /G45 /G6E /G64 /G20 /G6F /G66 /G43 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G42 /G69 /G74 /G73 /G43 /G6C /G6F /G63 /G6B /G20 /G44 /G69 /G76 /G69 /G64 /G65 /G20 /G52 /G61 /G74 /G69 /G6F A/D Converter Structure

Rev. 1.00 26 November 28, 2007 The START bit in the ADCR register is used to start and reset the A/D converter. When the microcontroller sets this bit from low to high and then low again, an analog to digital conversion cycle will be initiated. When the START bit is brought from low to high but not low again, the EOCB bit in the ADCR register will be set to a /c1781/c178 and the analog to digital converter will be reset. It is the START bit that is used to control the overall on/off opera- tion of the internal analog to digital converter. The EOCB bit in the ADCR register is used to indicate when the analog to digital conversion process is com - plete. This bit will be automatically set to /c1780/c178by the microcontroller after a conversion cycle has ended. In addition, the corresponding A/D interrupt request flag will be set in the interrupt control register, and if the inter- rupts are enabled, an appropriate internal interrupt sig- nal will be generated. This A/D internal interrupt signal will direct the program flow to the associated A/D inter- nal interrupt address for processing. If the A/D internal interrupt is disabled, the microcontroller can be used to poll the EOCB bit in the ADCR register to check whether it has been cleared as an alternative method of detect - ing the end of an A/D conversion cycle. A/D Converter Clock Source Register /c45ACSR The clock source for the A/D converter, which originates from the system clock f SYS, is first divided by a division ratio, the value of which is determined by the ADCS1 and ADCS0 bits in the ACSR register. Although the A/D clock source is determined by the sys- tem clock f SYS, and by bits ADCS1 and ADCS0, there are some limitations on the maximum A/D clock source speed that can be selected. As the minimum value of permissible A/D clock period, tAD is 1/c109s, care must be taken for system clock speeds in excess of 2MHz. For system clock speeds in excess of 2MHz, the ADCS1 and ADCS0 bits should not be set to/c17800/c178. Doing so will give A/D clock periods that are less than the minimum A/D clock period which may result in inaccurate A/D conversion values. Refer to the following table for examples, where values marked with an asterisk * show where, depending upon the device, special care must be taken, as the values may be less than the speci- fied minimum A/D Clock Period. /G41 /G44 /G43 /G52 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G53 /G65 /G6C /G65 /G63 /G74 /G20 /G41 /G2F /G44 /G20 /G63 /G68 /G61 /G6E /G6E /G65 /G6C /G62 /G37 /G62 /G30 /G53 /G54 /G41 /G52 /G54 /G50 /G43 /G52 /G32 /G50 /G43 /G52 /G31 /G50 /G43 /G52 /G30 /G41 /G43 /G53 /G32 /G41 /G43 /G53 /G31 /G41 /G43 /G53 /G30 /G41 /G43 /G53 /G31 /G30 /G30 /G31 /G31 /G30 /G30 /G31 /G41 /G43 /G53 /G32 /G30 /G30 /G30 /G30 /G31 /G31 /G31 /G41 /G43 /G53 /G30 /G30 /G31 /G30 /G31 /G30 /G31 /G58 /G3A /G20 /G41 /G4E /G30 /G3A /G20 /G41 /G4E /G31 /G3A /G20 /G41 /G4E /G32 /G3A /G20 /G41 /G4E /G33 /G3A /G20 /G41 /G4E /G34 /G3A /G20 /G41 /G4E /G35 /G3A /G20 /G75 /G6E /G64 /G65 /G66 /G69 /G6E /G65 /G64 /G2C /G20 /G6D /G75 /G73 /G74 /G20 /G6E /G6F /G74 /G20 /G62 /G65 /G20 /G75 /G73 /G65 /G64 /G20 /G50 /G6F /G72 /G74 /G20 /G42 /G20 /G41 /G2F /G44 /G20 /G63 /G68 /G61 /G6E /G6E /G65 /G6C /G20 /G63 /G6F /G6E /G66 /G69 /G67 /G75 /G72 /G61 /G74 /G69 /G6F /G6E /G73 /G50 /G43 /G52 /G32 /G30 /G30 /G30 /G30 /G31 /G31 /G31 /G50 /G43 /G52 /G31 /G30 /G30 /G31 /G31 /G30 /G30 /G31 /G50 /G43 /G52 /G30 /G30 /G31 /G30 /G31 /G30 /G31 /G30 /G3A /G20 /G20 /G50 /G6F /G72 /G74 /G20 /G42 /G20 /G41 /G2F /G44 /G20 /G63 /G68 /G61 /G6E /G6E /G65 /G6C /G73 /G20 /G2D /G20 /G61 /G6C /G6C /G20 /G6F /G66 /G66 /G3A /G20 /G20 /G50 /G42 /G30 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G64 /G20 /G61 /G73 /G20 /G41 /G4E /G30 /G3A /G20 /G20 /G50 /G42 /G30 /G7E /G50 /G42 /G31 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G64 /G20 /G61 /G73 /G20 /G41 /G4E /G30 /G7E /G41 /G4E /G31 /G3A /G20 /G20 /G50 /G42 /G30 /G7E /G50 /G42 /G32 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G64 /G20 /G61 /G73 /G20 /G41 /G4E /G30 /G7E /G41 /G4E /G32 /G20 /G3A /G20 /G20 /G50 /G42 /G30 /G7E /G50 /G42 /G33 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G64 /G20 /G61 /G73 /G20 /G41 /G4E /G30 /G7E /G41 /G4E /G33 /G3A /G20 /G20 /G50 /G42 /G30 /G7E /G50 /G42 /G34 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G64 /G20 /G61 /G73 /G20 /G41 /G4E /G30 /G7E /G41 /G4E /G34 /G3A /G20 /G20 /G50 /G42 /G30 /G7E /G50 /G42 /G35 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G64 /G20 /G61 /G73 /G20 /G41 /G4E /G30 /G7E /G41 /G4E /G35 /G45 /G6E /G64 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G66 /G6C /G61 /G67 /G31 /G3A /G20 /G6E /G6F /G74 /G20 /G65 /G6E /G64 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G2D /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G77 /G61 /G69 /G74 /G69 /G6E /G67 /G20 /G6F /G72 /G20 /G69 /G6E /G20 /G70 /G72 /G6F /G67 /G72 /G65 /G73 /G73 /G30 /G3A /G20 /G65 /G6E /G64 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G2D /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G65 /G6E /G64 /G65 /G64 /G53 /G74 /G61 /G72 /G74 /G20 /G74 /G68 /G65 /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G30 /G20 /GAE /G20 /G31 /G20 /GAE /G20 /G30 /G20 /G3A /G20 /G53 /G74 /G61 /G72 /G74 /G30 /G20 /GAE /G20 /G31 /G20 /G3A /G20 /G52 /G65 /G73 /G65 /G74 /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G20 /G61 /G6E /G64 /G20 /G73 /G65 /G74 /G20 /G45 /G4F /G43 /G42 /G20 /G74 /G6F /G20 /G22 /G31 /G22 /G45 /G4F /G43 /G42 A/D Converter Control Register /G41 /G43 /G53 /G52 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G53 /G65 /G6C /G65 /G63 /G74 /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G20 /G63 /G6C /G6F /G63 /G6B /G20 /G73 /G6F /G75 /G72 /G63 /G65 /G62 /G37 /G62 /G30 /G54 /G45 /G53 /G54 /G41 /G44 /G43 /G53 /G31 /G41 /G44 /G43 /G53 /G30 /G41 /G44 /G43 /G53 /G31 /G30 /G30 /G31 /G31 /G41 /G44 /G43 /G53 /G30 /G30 /G31 /G30 /G31 /G3A /G20 /G73 /G79 /G73 /G74 /G65 /G6D /G20 /G63 /G6C /G6F /G63 /G6B /G2F /G32 /G3A /G20 /G73 /G79 /G73 /G74 /G65 /G6D /G20 /G63 /G6C /G6F /G63 /G6B /G2F /G38 /G3A /G20 /G73 /G79 /G73 /G74 /G65 /G6D /G20 /G63 /G6C /G6F /G63 /G6B /G2F /G33 /G32 /G3A /G20 /G75 /G6E /G64 /G65 /G66 /G69 /G6E /G65 /G64 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 /G46 /G6F /G72 /G20 /G74 /G65 /G73 /G74 /G20 /G6D /G6F /G64 /G65 /G20 /G75 /G73 /G65 /G20 /G6F /G6E /G6C /G79 A/D Converter Clock Source Register

Rev. 1.00 27 November 28, 2007 fSYS A/D Clock Period (tAD) ADCS1, ADCS0=00 (fSYS/2) ADCS1, ADCS0=01 (fSYS/8) ADCS1, ADCS0=10 (fSYS/32) ADCS1, ADCS0=11 1MHz 2/c109s8 /c109s3 2 /c109s Undefined 2MHz 1/c109s4 /c109s1 6 /c109s Undefined 4MHz 500ns* 2/c109s8 /c109s Undefined 8MHz 250ns* 1/c109s4 /c109s Undefined A/D Clock Period Examples A/D Input Pins All of the A/D analog input pins are pin-shared with the I/O pins on Port B. Bits PCR2~PCR0 in the ADCR regis- ter, not configuration options, determine whether the in- put pins are setup as normal Port B input/output pins or whether they are setup as analog inputs. In this way, pins can be changed under program control to change their function from normal I/O operation to analog inputs and vice versa. Pull-high resistors, which are setup through configuration options, apply to the input pins only when they are used as normal I/O pins, if setup as A/D inputs the pull-high resistors will be automatically disconnected. Note that it is not necessary to first setup the A/D pin as an input in the PBC port control register to enable the A/D input, when the PCR2~PCR0 bits enable an A/D input, the status of the port control register will be overridden. The VDD power supply pin is used as the A/D converter reference voltage, and as such analog inputs must not be allowed to exceed this value. Appropriate measures should also be taken to ensure that the VDD pin remains as stable and noise free as possible. Initialising the A/D Converter The internal A/D converter must be initialised in a spe - cial way. Each time the Port B A/D channel selection bits are modified by the program, the A/D converter must be re-initialised. If the A/D converter is not initialised after the channel selection bits are changed, the EOCB flag may have an undefined value, which may produce a false end of conversion signal. To initialise the A/D con- verter after the channel selection bits have changed, then, within a time frame of one to ten instruction cycles, the START bit in the ADCR register must first be set high and then immediately cleared to zero. This will ensure that the EOCB flag is correctly set to a high condition. Summary of A/D Conversion Steps The following summarizes the individual steps that should be executed in order to implement an A/D con - version process. /c183Step 1 Select the required A/D conversion clock by correctly programming bits ADCS1 and ADCS0 in the ACSR register. /c183Step 2 Select which channel is to be connected to the internal A/D converter by correctly programming the ACS2~ACS0 bits which are also contained in the ADCR register. /c183Step 3 Select which pins on Port B are to be used as A/D in- puts and configure them as A/D input pins by correctly programming the PCR2~PCR0 bits in the ADCR reg- ister. Note that this step can be combined with Step 2 into a single ADCR register programming operation. /c183Step 4 If the interrupts are to be used, the interrupt control registers must be correctly configured to ensure the A/D converter interrupt function is active. The master interrupt control bit, EMI, in the INTC0 interrupt control register must be set to/c1781/c178and the A/D converter inter- rupt bit, EADI, in the INTC1 register must also be set to /c1781/c178. /c183Step 5 The analog to digital conversion process can now be initialised by setting the START bit in the ADCR regis- ter from /c1780/c178to /c1781/c178and then to/c1780/c178again. Note that this bit should have been originally set to /c1780/c178. /c183Step 6 To check when the analog to digital conversion pro - cess is complete, the EOCB bit in the ADCR register can be polled. The conversion process is complete when this bit goes low. When this occurs the A/D data registers ADRL and ADRH can be read to obtain the conversion value. As an alternative method if the in - terrupts are enabled and the stack is not full, the pro- gram can wait for an A/D interrupt to occur. Note: When checking for the end of the conversion process, if the method of polling the EOCB bit in the ADCR register is used, the interrupt enable step above can be omitted.

Rev. 1.00 28 November 28, 2007 The following timing diagram shows graphically the various stages involved in an analog to digital conversion process and its associated timing. The setting up and operation of the A/D converter func- tion is fully under the control of the application program as there are no configuration options associated with the A/D converter. After an A/D conversion process has been initiated by the application program, the microcontroller internal hardware will begin to carry out the conversion, during which time the program can continue with other functions. The time taken for the A/D conversion is equal to 76t AD where tAD is the A/D clock period tAD. Programming Considerations When programming, special attention must be given to the A/D channel selection bits in the ADCR register. If these bits are all cleared to zero no external pins will be selected for use as A/D input pins allowing the pins to be used as normal I/O pins. When this happens the power supplied to the internal A/D circuitry will be reduced re- sulting in a reduction of supply current. This ability to re- duce power by turning off the internal A/D function by clearing the A/D channel selection bits may be an impor- tant consideration in battery powered applications. Another important programming consideration is that when the A/D channel selection bits change value the A/D converter must be re-initialised. This is achieved by pulsing the START bit in the ADCR register immediately after the channel selection bits have changed state. The exception to this is where the channel selection bits are all cleared, in which case the A/D converter is not re- quired to be re-initialised. A/D Programming Example The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the bit in the ADCR reg- ister is used to detect when the conversion cycle is com- plete, whereas in the second example, the A/D interrupt is used to determine when the conversion is complete. /G30 /G30 /G30 /G42 /G30 /G30 /G30 /G42 /G30 /G31 /G31 /G42 /G30 /G31 /G30 /G42 /G53 /G54 /G41 /G52 /G54 /G45 /G4F /G43 /G42 /G50 /G43 /G52 /G32 /G7E /G50 /G43 /G52 /G30 /G41 /G43 /G53 /G32 /G7E /G41 /G43 /G53 /G30 /G50 /G6F /G77 /G65 /G72 /G2D /G6F /G6E /G52 /G65 /G73 /G65 /G74 /G45 /G6E /G64 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G31 /G3A /G20 /G44 /G65 /G66 /G69 /G6E /G65 /G20 /G50 /G42 /G20 /G63 /G6F /G6E /G66 /G69 /G67 /G75 /G72 /G61 /G74 /G69 /G6F /G6E /G32 /G3A /G20 /G53 /G65 /G6C /G65 /G63 /G74 /G20 /G61 /G6E /G61 /G6C /G6F /G67 /G20 /G63 /G68 /G61 /G6E /G6E /G65 /G6C /G53 /G74 /G61 /G72 /G74 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G52 /G65 /G73 /G65 /G74 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G30 /G30 /G30 /G42 /G53 /G74 /G61 /G72 /G74 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G52 /G65 /G73 /G65 /G74 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G30 /G30 /G30 /G42 /G31 /G2E /G20 /G50 /G42 /G20 /G70 /G6F /G72 /G74 /G20 /G73 /G65 /G74 /G75 /G70 /G20 /G61 /G73 /G20 /G49 /G2F /G4F /G73 /G32 /G2E /G20 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G20 /G69 /G73 /G20 /G70 /G6F /G77 /G65 /G72 /G65 /G64 /G20 /G6F /G66 /G66 /G20 /G20 /G20 /G20 /G74 /G6F /G20 /G72 /G65 /G64 /G75 /G63 /G65 /G20 /G70 /G6F /G77 /G65 /G72 /G20 /G63 /G6F /G6E /G73 /G75 /G6D /G70 /G74 /G69 /G6F /G6E /G31 /G30 /G30 /G42 /G30 /G30 /G31 /G42 /G53 /G74 /G61 /G72 /G74 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G52 /G65 /G73 /G65 /G74 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G44 /G6F /G6E /G27 /G74 /G20 /G63 /G61 /G72 /G65 /G45 /G6E /G64 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G45 /G6E /G64 /G20 /G6F /G66 /G20 /G41 /G2F /G44 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G53 /G54 /G41 /G52 /G54 /G20 /G62 /G69 /G74 /G20 /G73 /G65 /G74 /G20 /G68 /G69 /G67 /G68 /G20 /G77 /G69 /G74 /G68 /G69 /G6E /G20 /G6F /G6E /G65 /G20 /G74 /G6F /G20 /G74 /G65 /G6E /G20 /G69 /G6E /G73 /G74 /G72 /G75 /G63 /G74 /G69 /G6F /G6E /G20 /G63 /G79 /G63 /G6C /G65 /G73 /G20 /G61 /G66 /G74 /G65 /G72 /G20 /G74 /G68 /G65 /G20 /G50 /G43 /G52 /G30 /G7E /G50 /G43 /G52 /G32 /G20 /G62 /G69 /G74 /G73 /G20 /G63 /G68 /G61 /G6E /G67 /G65 /G20 /G73 /G74 /G61 /G74 /G65 /G41 /G2F /G44 /G20 /G63 /G6C /G6F /G63 /G6B /G20 /G6D /G75 /G73 /G74 /G20 /G62 /G65 /G20 /G66 /G53 /G59 /G53 /G2F /G32 /G2C /G20 /G66 /G53 /G59 /G53 /G2F /G38 /G20 /G6F /G72 /G20 /G66 /G53 /G59 /G53 /G2F /G33 /G32 /G4E /G6F /G74 /G65 /G3A /G20 /G41 /G2F /G44 /G20 /G73 /G61 /G6D /G70 /G6C /G69 /G6E /G67 /G20 /G74 /G69 /G6D /G65 /G41 /G2F /G44 /G20 /G73 /G61 /G6D /G70 /G6C /G69 /G6E /G67 /G20 /G74 /G69 /G6D /G65 /G41 /G2F /G44 /G20 /G73 /G61 /G6D /G70 /G6C /G69 /G6E /G67 /G20 /G74 /G69 /G6D /G65 /G20 /G20 /G33 /G32 /G74 /G41 /G44 /G20 /G20 /G33 /G32 /G74 /G41 /G44 /G20 /G20 /G33 /G32 /G74 /G41 /G44 /G74 /G41 /G44 /G43 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G74 /G69 /G6D /G65 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G74 /G69 /G6D /G65 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G20 /G74 /G69 /G6D /G65 /G74 /G41 /G44 /G43 /G74 /G41 /G44 /G43 A/D Conversion Timing Example: using an EOCB polling method to detect the end of conversion clr EADI ; disable ADC interrupt mov a,00000001B mov ACSR,a ; setup the ACSR register to select f SYS/8 as ; the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D ; converter : ; As the Port B channel bits have changed the ; following START ; signal (0-1-0) must be issued within 10 ; instruction cycles

Rev. 1.00 29 November 28, 2007 Start_conversion: clr START set START ; reset A/D clr START ; start A/D Polling_EOC: sz EOCB ; poll the ADCR register EOCB bit to detect end ; of A/D conversion jmp polling_EOC ; continue polling mov a,ADRL ; read low byte conversion value mov adr_low_buffer,a ; save result to user defined memory mov a,ADRH ; read high byte conversion value mov adr_high_buffer,a ; save result to user defined memory jmp start_conversion ; start next A/D conversion Example: using an interrupt method to detect the end of conversion clr EADI ; disable ADC interrupt a,00000001B mov ACSR,a ; setup the ACSR register to select fSYS/8 as ; the A/D clock mov a,00100000B ; setup ADCR register to configure Port PB0~PB3 ; as A/D inputs mov ADCR,a ; and select AN0 to be connected to the A/D ; converter ; As the Port B channel bits have changed the ; following START ; signal (0-1-0) must be issued within 10 ; instruction cycles Start_conversion: clr START set START ; reset A/D clr START ; start A/D clr ADF ; clear ADC interrupt request flag set EADI ; enable ADC interrupt set EMI ; enable global interrupt ; ADC interrupt service routine ADC_ISR: mov acc_stack,a ; save ACC to user defined memory mov a,STATUS mov status_stack,a ; save STATUS to user defined memory mov a,ADRL ; read low byte conversion value mov adr_low_buffer,a ; save result to user defined register mov a,ADRH ; read high byte conversion value mov adr_high_buffer,a ; save result to user defined memory EXIT_INT_ISR: mov a,status_stack mov STATUS,a ; restore STATUS from user defined memory mov a,acc_stack ; restore ACC from user defined memory reti

Rev. 1.00 30 November 28, 2007 A/D Transfer Function As the device contains a 9-bit A/D converter, its full-scale converted digitised value is equal to 1FFH giv- ing a single bit analog input value of VDD/512. The graph show the ideal transfer function between the analog in- put value and the digitised output value for the A/D con- verter. Note that to reduce the quantisation error, a 0.5 LSB off- set is added to the A/D Converter input. Except for the digitised zero value, the subsequent digitised values will change at a point 0.5 LSB below where they would change without the offset, and the last full scale digitised value will change at a point 1.5 LSB below the V DD level. Interrupts Interrupts are an important part of any microcontroller system. When an external event or an internal function such as a Timer/Event Counter or an A/D converter re- quires microcontroller attention, their corresponding in- terrupt will enforce a temporary suspension of the main program allowing the microcontroller to direct attention to their respective needs. Each device in this series con- tains a single external interrupt and two internal inter - rupts functions. The external interrupt is controlled by the action of the external INT pin, while the internal inter- rupts are controlled by the Timer/Event Counter over- flow and the A/D converter interrupt. Interrupt Register Overall interrupt control, which means interrupt enabling and request flag setting, is controlled by INTC0 and INTC1 registers, which are located in Data Memory. By controlling the appropriate enable bits in this register each individual interrupt can be enabled or disabled. Also when an interrupt occurs, the corresponding re - quest flag will be set by the microcontroller. The global enable flag if cleared to zero will disable all interrupts. Interrupt Operation A Timer/Event Counter overflow, an end of A/D conver- sion or the external interrupt line being pulled low will all generate an interrupt request by setting their corre - sponding request flag, if their appropriate interrupt en - able bit is set. When this happens, the Program Counter, which stores the address of the next instruction to be executed, will be transferred onto the stack. The Program Counter will then be loaded with a new ad - dress which will be the value of the corresponding inter- rupt vector. The microcontroller will then fetch its next instruction from this interrupt vector. The instruction at this vector will usually be a JMP statement which will jump to another section of program which is known as the interrupt service routine. Here is located the code to control the appropriate interrupt. The interrupt service routine must be terminated with a RETI statement, which retrieves the original Program Counter address from the stack and allows the microcontroller to continue with normal execution at the point where the interrupt occurred. The various interrupt enable bits, together with their as- sociated request flags, are shown in the following dia - gram with their order of priority. Once an interrupt subroutine is serviced, all the other in- terrupts will be blocked, as the EMI bit will be cleared au- tomatically. This will prevent any further interrupt nesting from occurring. However, if other interrupt requests oc- cur during this interval, although the interrupt will not be immediately serviced, the request flag will still be re- corded. If an interrupt requires immediate servicing while the program is already in another interrupt service routine, the EMI bit should be set after entering the rou- tine, to allow interrupt nesting. If the stack is full, the in- terrupt request will not be acknowledged, even if the related interrupt is enabled, until the Stack Pointer is decremented. If immediate service is desired, the stack must be prevented from becoming full. /G31 /G46 /G45 /G48 /G28 /G20 /G20 /G20 /G20 /G20 /G20 /G20 /G20 /G20 /G29 /G41 /G2F /G44 /G20 /G43 /G6F /G6E /G76 /G65 /G72 /G73 /G69 /G6F /G6E /G52 /G65 /G73 /G75 /G6C /G74 /G31 /G46 /G46 /G48 /G31 /G46 /G44 /G48 /G30 /G33 /G48 /G30 /G32 /G48 /G30 /G31 /G48 /G30 /G2E /G35 /G20 /G4C /G53 /G42 /G30 /G31 /G32 /G33 /G35 /G30 /G39 /G35 /G31 /G30 /G35 /G31 /G31 /G35 /G31 /G32 /G41 /G6E /G61 /G6C /G6F /G67 /G20 /G49 /G6E /G70 /G75 /G74 /G20 /G56 /G6F /G6C /G74 /G61 /G67 /G65 /G31 /G2E /G35 /G20 /G4C /G53 /G42 /G56 /G44 /G44 /G35 /G31 /G32 Ideal A/D Transfer Function

Rev. 1.00 31 November 28, 2007 /G49 /G4E /G54 /G43 /G31 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G62 /G37 /G62 /G30 /G45 /G41 /G44 /G49 /G41 /G2F /G44 /G20 /G43 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G30 /G3A /G20 /G64 /G69 /G73 /G61 /G62 /G6C /G65 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 /G41 /G2F /G44 /G20 /G63 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G72 /G65 /G71 /G75 /G65 /G73 /G74 /G20 /G66 /G6C /G61 /G67 /G31 /G3A /G20 /G61 /G63 /G74 /G69 /G76 /G65 /G30 /G3A /G20 /G69 /G6E /G61 /G63 /G74 /G69 /G76 /G65 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 /G20 /G41 /G44 /G46 /G4E /G6F /G74 /G20 /G69 /G6D /G70 /G6C /G65 /G6D /G65 /G6E /G74 /G65 /G64 /G2C /G20 /G72 /G65 /G61 /G64 /G20 /G61 /G73 /G20 /G22 /G30 /G22 Interrupt Control Registers /G49 /G4E /G54 /G43 /G30 /G20 /G52 /G65 /G67 /G69 /G73 /G74 /G65 /G72 /G4D /G61 /G73 /G74 /G65 /G72 /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G67 /G6C /G6F /G62 /G61 /G6C /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G67 /G6C /G6F /G62 /G61 /G6C /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G30 /G3A /G20 /G67 /G6C /G6F /G62 /G61 /G6C /G20 /G64 /G69 /G73 /G61 /G62 /G6C /G65 /G45 /G78 /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G30 /G3A /G20 /G64 /G69 /G73 /G61 /G62 /G6C /G65 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G30 /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G30 /G3A /G20 /G64 /G69 /G73 /G61 /G62 /G6C /G65 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G31 /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G30 /G3A /G20 /G64 /G69 /G73 /G61 /G62 /G6C /G65 /G45 /G78 /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G30 /G20 /G72 /G65 /G71 /G75 /G65 /G73 /G74 /G20 /G66 /G6C /G61 /G67 /G31 /G3A /G20 /G61 /G63 /G74 /G69 /G76 /G65 /G30 /G3A /G20 /G69 /G6E /G61 /G63 /G74 /G69 /G76 /G65 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G30 /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G65 /G6E /G61 /G62 /G6C /G65 /G31 /G3A /G20 /G61 /G63 /G74 /G69 /G76 /G65 /G30 /G3A /G20 /G69 /G6E /G61 /G63 /G74 /G69 /G76 /G65 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G31 /G20 /G69 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G72 /G65 /G71 /G75 /G65 /G73 /G74 /G20 /G66 /G6C /G61 /G67 /G31 /G3A /G20 /G61 /G63 /G74 /G69 /G76 /G65 /G30 /G3A /G20 /G69 /G6E /G61 /G63 /G74 /G69 /G76 /G65 /G46 /G6F /G72 /G20 /G74 /G65 /G73 /G74 /G20 /G6D /G6F /G64 /G65 /G20 /G75 /G73 /G65 /G64 /G20 /G6F /G6E /G6C /G79 /G4D /G75 /G73 /G74 /G20 /G62 /G65 /G20 /G77 /G72 /G69 /G74 /G74 /G65 /G6E /G20 /G61 /G73 /G20 /G22 /G30 /G22 /G3B /G20 /G6F /G74 /G68 /G65 /G72 /G77 /G69 /G73 /G65 /G20 /G6D /G61 /G79 /G20 /G72 /G65 /G73 /G75 /G6C /G74 /G20 /G69 /G6E /G20 /G75 /G6E /G70 /G72 /G65 /G64 /G69 /G63 /G74 /G61 /G62 /G6C /G65 /G20 /G6F /G70 /G65 /G72 /G61 /G74 /G69 /G6F /G6E /G62 /G37 /G62 /G30 /G45 /G45 /G49 /G45 /G4D /G49 /G45 /G49 /G46 /G45 /G54 /G31 /G49 /G54 /G31 /G46 /G54 /G30 /G46 /G45 /G54 /G30 /G49 Interrupt Priority Interrupts, occurring in the interval between the rising edges of two consecutive T2 pulses, will be serviced on the latter of the two T2 pulses, if the corresponding inter- rupts are enabled. In case of simultaneous requests, the following table shows the priority that is applied. These can be masked by resetting the EMI bit. Interrupt Source All Devices Priority External Interrupt 1 Timer/Event Counter 0 Overflow 2 Timer/Event Counter 1 Overflow 3 A/D Converter Interrupt 4 In cases where both external and internal interrupts are enabled and where an external and internal interrupt oc- curs simultaneously, the external interrupt will always have priority and will therefore be serviced first. Suitable masking of the individual interrupts using the INTC0/INTC1 register can prevent simultaneous occur- rences. External Interrupt For an external interrupt to occur, the global interrupt en- able bit, EMI, and external interrupt enable bit, EEI, must first be set. An actual external interrupt will take place when the external interrupt request flag, EIF, is set, a situ- ation that will occur when a high to low transition appears on the INT line. The external interrupt pin is pin-shared with the I/O pin PA5 and can only be configured as an ex- ternal interrupt pin if the corresponding external interrupt enable bit in the INTC 0 register has been set. The pin must also be setup as an input by setting the correspond- ing PAC.5 bit in the port control register. When the inter- rupt is enabled, the stack is not full and a high to low transition appears on the external interrupt pin, a subrou- tine call to the external interrupt vector at location 04H, will take place. When the interrupt is serviced, the exter- nal interrupt request flag, EIF; bit 4 of INTC0 will be auto- matically reset and the EMI bit will be automatically cleared to disable other interrupts. Note that any pull-high resistor configuration options on this pin will remain valid even if the pin is used as an external interrupt input.

Rev. 1.00 32 November 28, 2007 /G41 /G75 /G74 /G6F /G6D /G61 /G74 /G69 /G63 /G61 /G6C /G6C /G79 /G20 /G43 /G6C /G65 /G61 /G72 /G65 /G64 /G20 /G62 /G79 /G20 /G49 /G53 /G52 /G4D /G61 /G6E /G75 /G61 /G6C /G6C /G79 /G20 /G53 /G65 /G74 /G20 /G6F /G72 /G20 /G43 /G6C /G65 /G61 /G72 /G65 /G64 /G20 /G62 /G79 /G20 /G53 /G6F /G66 /G74 /G77 /G61 /G72 /G65 /G45 /G78 /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G52 /G65 /G71 /G75 /G65 /G73 /G74 /G20 /G46 /G6C /G61 /G67 /G20 /G45 /G49 /G46 /G45 /G45 /G49 /G45 /G4D /G49 /G50 /G72 /G69 /G6F /G72 /G69 /G74 /G79 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G50 /G6F /G6C /G6C /G69 /G6E /G67 /G48 /G69 /G67 /G68 /G41 /G75 /G74 /G6F /G6D /G61 /G74 /G69 /G63 /G61 /G6C /G6C /G79 /G20 /G44 /G69 /G73 /G61 /G62 /G6C /G65 /G64 /G20 /G62 /G79 /G20 /G49 /G53 /G52 /G43 /G61 /G6E /G20 /G62 /G65 /G20 /G45 /G6E /G61 /G62 /G6C /G65 /G64 /G20 /G4D /G61 /G6E /G75 /G61 /G6C /G6C /G79 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G30 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G52 /G65 /G71 /G75 /G65 /G73 /G74 /G20 /G46 /G6C /G61 /G67 /G20 /G54 /G30 /G46 /G45 /G54 /G30 /G49 /G4C /G6F /G77 /G45 /G41 /G44 /G49 /G41 /G2F /G44 /G20 /G43 /G6F /G6E /G76 /G65 /G72 /G74 /G65 /G72 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G52 /G65 /G71 /G75 /G65 /G73 /G74 /G20 /G46 /G6C /G61 /G67 /G20 /G41 /G44 /G46 /G54 /G69 /G6D /G65 /G72 /G2F /G45 /G76 /G65 /G6E /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /G20 /G31 /G49 /G6E /G74 /G65 /G72 /G72 /G75 /G70 /G74 /G20 /G52 /G65 /G71 /G75 /G65 /G73 /G74 /G20 /G46 /G6C /G61 /G67 /G20 /G54 /G31 /G46 /G45 /G54 /G31 /G49 Interrupt Structure Timer/Event Counter Interrupt For a Timer/Event Counter interrupt to occur, the global interrupt enable bit, EMI, and the corresponding timer interrupt enable bit, ET0I/ET1I; bit 2/bit 3 of INTC0 must first be set. An actual Timer/Event Counter interrupt will take place when the Timer/Event Counter request flag, T0F/T1F; bit 5/bit 6 of INTC0 is set, a situation that will occur when the Timer/Event Counter overflows. When the interrupt is enabled, the stack is not full and a Timer/Event Counter overflow occurs, a subroutine call to the timer interrupt vector at location 08H/0CH, will take place. When the interrupt is serviced, the timer in- terrupt request flag, T0F/T1F, will be automatically reset and the EMI bit will be automatically cleared to disable other interrupts. A/D Interrupt For an A/D interrupt to occur, the global interrupt enable bit, EMI, and the corresponding interrupt enable bit, EADI, must be first set. An actual A/D interrupt will take place when the A/D converter request flag, ADF; bit 4 of INTC1 is set, a situation that will occur when an A/D con- version process has completed. When the interrupt is enabled, the stack is not full and an A/D conversion pro- cess finishes execution, a subroutine call to the A/D in- terrupt vector at location 10H, will take place. When the interrupt is serviced, the A/D interrupt request flag, ADF, will be automatically reset and the EMI bit will be auto - matically cleared to disable other interrupts. Programming Considerations By disabling the interrupt enable bits, a requested inter- rupt can be prevented from being serviced, however, once an interrupt request flag is set, it will remain in this condition in the INTC0/INTC1 register until the corre - sponding interrupt is serviced or until the request flag is cleared by a software instruction. It is recommended that programs do not use the/c178CALL subroutine/c178instruction within the interrupt subroutine. Interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications. If only one stack is left and the interrupt is not well con - trolled, the original control sequence will be damaged once a /c178CALL subroutine/c178is executed in the interrupt subroutine. All of these interrupts have the capability of waking up the processor when in the Power Down Mode. Only the Program Counter is pushed onto the stack. If the contents of the register or status register are altered by the interrupt service program, which may corrupt the desired control sequence, then the contents should be saved in advance. Reset and Initialisation A reset function is a fundamental part of any microcontroller ensuring that the device can be set to some predetermined condition irrespective of outside parameters. The most important reset condition is after power is first applied to the microcontroller. In this case, internal circuitry will ensure that the microcontroller, af- ter a short delay, will be in a well defined state and ready to execute the first program instruction. After this power-on reset, certain important internal registers will be set to defined states before the program com - mences. One of these registers is the Program Counter, which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address. In addition to the power-on reset, situations may arise where it is necessary to forcefully apply a reset condition when the microcontroller is running. One example of this is where after power has been applied and the microcontroller is already running, the RES line is force- fully pulled low. In such a case, known as a normal oper- ation reset, some of the microcontroller registers remain unchanged allowing the microcontroller to proceed with normal operation after the reset line is allowed to return high. Another type of reset is when the Watchdog Timer overflows and resets the microcontroller. All types of re- set operations result in different register conditions be - ing setup.

Rev. 1.00 33 November 28, 2007 Another reset exists in the form of a Low Voltage Reset, LVR, where a full reset, similar to the RESreset is imple- mented in situations where the power supply voltage falls below a certain threshold. Reset Functions There are five ways in which a microcontroller reset can occur, through events occurring both internally and ex - ternally: /c183Power-on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller. As well as ensuring that the Program Memory begins execution from the first memory ad - dress, a power-on reset also ensures that certain other registers are preset to known conditions. All the I/O port and port control registers will power up in a high condition ensuring that all pins will be first set to inputs. Although the microcontroller has an internal RC reset function, if the VDD power supply rise time is not fast enough or does not stabilise quickly at power-on, the internal reset function may be incapable of providing proper reset operation. For this reason it is recom - mended that an external RC network is connected to the RES pin, whose additional time delay will ensure that the RES pin remains low for an extended period to allow the power supply to stabilise. During this time delay, normal operation of the microcontroller will be inhibited. After the RES line reaches a certain voltage value, the reset delay time tRSTD is invoked to provide an extra delay time after which the microcontroller will begin normal operation. The abbreviation SST in the figures stands for System Start-up Timer. For most applications a resistor connected between VDD and the RES pin and a capacitor connected be- tween VSS and the RESpin will provide a suitable ex- ternal reset circuit. Any wiring connected to the RES pin should be kept as short as possible to minimise any stray noise interference. For applications that operate within an environment where more noise is present the Enhanced Reset Cir- cuit shown is recommended. More information regarding external reset circuits is located in Application Note HA0075E on the Holtek website. /c183RES Pin Reset This type of reset occurs when the microcontroller is already running and the RES pin is forcefully pulled low by external hardware such as an external switch. In this case as in the case of other reset, the Program Counter will reset to zero and program execution initi- ated from this point. /c183Low Voltage Reset /c45LVR The microcontroller contains a low voltage reset cir- cuit in order to monitor the supply voltage of the de- vice. The LVR function is selected via a configuration option. If the supply voltage of the device drops to within a range of 0.9V~V LVR such as might occur when changing the battery, the LVR will automatically reset the device internally. For a valid LVR signal, a low sup- ply voltage, i.e., a voltage in the range between 0.9V~V LVR must exist for a time greater than that spec- ified by tLVR in the A.C. characteristics. If the low sup- ply voltage state does not exceed this value, the LVR will ignore the low supply voltage and will not perform a reset function. The actual V LVR value can be se - lected via configuration options. /G52 /G45 /G53 /G56 /G44 /G44 /G53 /G53 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G49 /G6E /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G52 /G65 /G73 /G65 /G74 /G30 /G2E /G39 /G20 /G56 /G44 /G44 /G74 /G52 /G53 /G54 /G44 Power-On Reset Timing Chart /G52 /G45 /G53 /G53 /G53 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G49 /G6E /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G52 /G65 /G73 /G65 /G74 /G30 /G2E /G39 /G20 /G56 /G44 /G44 /G30 /G2E /G34 /G20 /G56 /G44 /G44 /G74 /G52 /G53 /G54 /G44 RES Reset Timing Chart /G52 /G45 /G53 /G30 /G2E /G31 /G6D /G46 /G31 /G30 /G30 /G6B /G57 /G56 /G44 /G44 /G56 /G53 /G53 /G30 /G2E /G30 /G31 /G6D /G46 /G31 /G30 /G6B /G57 Enhanced Reset Circuit /G52 /G45 /G53 /G56 /G44 /G44 /G56 /G53 /G53 /G30 /G2E /G31 /G6D /G46 /G31 /G30 /G30 /G6B /G57 Basic Reset Circuit /G4C /G56 /G52 /G53 /G53 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G49 /G6E /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G52 /G65 /G73 /G65 /G74 /G74 /G52 /G53 /G54 /G44 Low Voltage Reset Timing Chart

Rev. 1.00 34 November 28, 2007 /c183Watchdog Time-out Reset during Normal Operation The Watchdog time-out Reset during normal opera - tion is the same as a hardware RES pin reset except that the Watchdog time-out flag TO will be set to /c1781/c178. /c183Watchdog Time-out Reset during Power Down The Watchdog time-out Reset during Power Down is a little different from other kinds of reset. Most of the conditions remain unchanged except that the Pro - gram Counter and the Stack Pointer will be cleared to /c1780/c178and the TO flag will be set to/c1781/c178. Refer to the A.C. Characteristics for t SST details. Reset Initial Conditions The different types of reset described affect the reset flags in different ways. These flags, known as PDF and TO are located in the status register and are controlled by various microcontroller operations, such as the Power Down function or Watchdog Timer. The reset flags are shown in the table: TO PDF RESET Conditions 0 0 RES reset during power-on u u RES or LVR reset during normal operation 1 u WDT time-out reset during normal operation 1 1 WDT time-out reset during Power Down Note: /c178u/c178stands for unchanged The following table indicates the way in which the vari - ous components of the microcontroller are affected after a power-on reset occurs. Item Condition After RESET Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Clear after reset, WDT begins counting Timer/Event Counter Timer Counter will be turned off Prescaler The Timer Counter Prescaler will be cleared Input/Output Ports I/O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of resets all affect the internal regis- ters of the microcontroller in different ways. To ensure reliable continuation of normal program execution after a reset occurs, it is important to know what condition the microcontroller is in after a particular reset occurs. The following table describes how each type of reset affects each of the microcontroller internal registers. /G57 /G44 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G53 /G53 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G49 /G6E /G74 /G65 /G72 /G6E /G61 /G6C /G20 /G52 /G65 /G73 /G65 /G74 /G74 /G52 /G53 /G54 /G44 WDT Time-out Reset during Normal Operation Timing Chart /G57 /G44 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G53 /G53 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G74 /G53 /G53 /G54 WDT Time-out Reset during Power Down Timing Chart

Rev. 1.00 35 November 28, 2007 Register Reset (Power-on) RES or LVR Reset WDT Time-out (Normal Operation) WDT Time-out (HALT) MP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu ACC xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu PCL 0000 0000 0000 0000 0000 0000 0000 0000 TBLP xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu TBLH /c45xxx xxxx /c45uuu uuuu /c45uuu uuuu /c45uuu uuuu STATUS /c45/c4500 xxxx /c45/c45uu uuuu /c45/c451u uuuu /c45/c4511 uuuu INTC0 /c45000 0000 /c45000 0000 /c45000 0000 /c45uuu uuuu INTC1 /c45/c45/c450 /c45/c45/c450 /c45/c45/c450 /c45/c45/c450 /c45/c45/c450 /c45/c45/c450 /c45/c45/c45u /c45/c45/c45u TMR0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR0C 00 /c450 1000 00 /c450 1000 00 /c450 1000 uu /c45u uuuu TMR1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu TMR1C 00 /c450 1000 00 /c450 1000 00 /c450 1000 uu /c45u uuuu PA 1111 1111 1111 1111 1111 1111 uuuu uuuu PAC 1111 1111 1111 1111 1111 1111 uuuu uuuu PB 1111 1111 1111 1111 1111 1111 uuuu uuuu PBC 1111 1111 1111 1111 1111 1111 uuuu uuuu PC 1111 1111 1111 1111 1111 1111 uuuu uuuu PCC 1111 1111 1111 1111 1111 1111 uuuu uuuu PD /c45 /c45 /c45/c32/c45 /c45111 /c45 /c45 /c45/c32/c45 /c45111 /c45 /c45 /c45/c32/c45 /c45111 /c45 /c45 /c45/c32/c45 /c45uuu PDC /c45 /c45 /c45/c32/c45 /c45111 /c45 /c45 /c45/c32/c45 /c45111 /c45 /c45 /c45/c32/c45 /c45111 /c45 /c45 /c45/c32/c45 /c45uuu PWM0 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu PWM1 xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADRL x /c45/c45 /c32 /c45 /c45/c45/c45/c45x /c45/c45 /c32 /c45 /c45/c45/c45/c45x /c45/c45 /c32 /c45 /c45/c45/c45/c45u /c45/c45 /c32 /c45 /c45/c45/c45/c45 ADRH xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu ADCR 0100 0000 0100 0000 0100 0000 uuuu uuuu ACSR 1 /c45 /c45/c32/c45 /c45 /c4500 1 /c45 /c45/c32/c45 /c45 /c4500 1 /c45 /c45/c32/c45 /c45 /c4500 u /c45 /c45/c32/c45 /c45 /c45uu /c178u/c178stands for unchanged /c178x/c178stands for unknown /c178/c45/c178stands for unimplemented

Rev. 1.00 36 November 28, 2007 Oscillator Various oscillator options offer the user a wide range of functions according to their various application require- ments. Two types of system clocks can be selected while various clock source options for the Watchdog Timer are provided for maximum flexibility. All oscillator options are selected through the configuration options. More information regarding the oscillator is located in Clock Source Modes There are two methods of generating the system clock, using an external crystal/ceramic oscillator and an ex - ternal RC network. One of these two methods must be selected using the configuration options. /c183External Crystal/Ceramic Oscillator The simple connection of a crystal across OSC1 and OSC2 will create the necessary phase shift and feed- back for oscillation, without requiring external capaci- tors. However, for some crystal types and frequencies, to ensure oscillation, it may be neces - sary to add two small value capacitors, C1 and C2. Using a ceramic resonator will usually require two small value capacitors, C1 and C2, to be connected as shown for oscillation to occur. The values of C1 and C2 should be selected in consultation with the crystal or resonator manufacturer/c162s specification. Table: capacitor selection for system crystal/ceramic oscillator. C1, C2 Value Crystal Frequency C1 C2 CL* 8MHz TBD TBD TBD 4MHz TBD TBD TBD 1MHz TBD TBD TBD 400kHz TBD TBD TBD Note: 1. The C1, C2 value is for design guidance only and not optimized. Due to the different performance of various crystals/resonators, it/c162s suggested to test it over expected VDD and temperature for the application, and consult the manufacturer for appropriate val- ues of external components. 2. /c178CL*/c178is the load capacitor for tested crys- tal which is specified in crystal specification. Table: Build-in RC value for system crystal/ceramic oscillator. Ca, Cb, Rf Value (5V, 25/c176C) Ca Cb Rf TBD TBD TBD /c183External RC Oscillator Using the external RC network as an oscillator requires that a resistor, with a value between 24k/c87and 1M/c87,i s connected between OSC1 and ground, and a 470pF capacitor is connected to VDD. The generated system clock divided by 4 will be provided on OSC2 as an out- put which can be used for external synchronization pur- poses. Note that as the OSC2 output is an NMOS open-drain type, a pull high resistor should be con - nected if it to be used to monitor the internal frequency. Although this is a cost effective oscillator configuration, the oscillation frequency can vary with VDD, tempera- ture and process variations on the device itself and is therefore not suitable for applications where timing is critical or where accurate oscillator frequencies are re- quired. For the value of the external resistor R OSC please refer to the Appendix section for typical RC Os- cillator vs. Temperature and VDD characteristics graph- ics. /G4F /G53 /G43 /G31 /G4F /G53 /G43 /G32 /G52 /G66 /G54 /G6F /G20 /G69 /G6E /G74 /G65 /G72 /G6E /G61 /G6C /G63 /G69 /G72 /G63 /G75 /G69 /G74 /G48 /G6F /G6C /G74 /G65 /G6B /G20 /G4D /G43 /G55 /G43 /G31 /G43 /G32 /G43 /G61 /G43 /G62 /G52 /G70 /G4E /G6F /G74 /G65 /G3A /G55 /G73 /G75 /G61 /G6C /G6C /G79 /G2C /G20 /G61 /G6E /G20 /G61 /G64 /G64 /G69 /G74 /G69 /G6F /G6E /G61 /G6C /G20 /G70 /G61 /G72 /G61 /G6C /G6C /G65 /G6C /G20 /G66 /G65 /G65 /G64 /G62 /G61 /G63 /G6B /G20 /G72 /G65 /G73 /G69 /G73 /G74 /G6F /G72 /G20 /G28 /G52 /G70 /G29 /G69 /G73 /G20 /G6E /G6F /G74 /G20 /G6E /G65 /G63 /G65 /G73 /G73 /G61 /G72 /G79 /G20 /G28 /G49 /G74 /G20 /G6D /G61 /G79 /G20 /G62 /G65 /G20 /G72 /G65 /G71 /G75 /G69 /G72 /G65 /G64 /G20 /G74 /G6F /G20 /G61 /G73 /G73 /G69 /G73 /G74 /G20 /G6F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G69 /G6F /G6E /G73 /G74 /G61 /G72 /G74 /G2D /G75 /G70 /G29 /G2E External Crystal/Ceramic Oscillator

Rev. 1.00 37 November 28, 2007 Note that it is the only microcontroller internal circuitry together with the external resistor, that determine the frequency of the oscillator. The external capacitor shown on the diagram does not influence the frequency of oscillation. The external capacitor is added to improve oscillator stability, especially if the open-drain OSC2 output is utilised in the application circuit. Watchdog Timer Oscillator The WDT oscillator is a fully self-contained free running on-chip RC oscillator with a typical period of 65/c109sa t5 V requiring no external components. When the device en- ters the Power Down Mode, the system clock will stop running but the WDT oscillator continues to free-run and to keep the watchdog active. However, to preserve power in certain applications the WDT oscillator can be disabled via a configuration option. Power Down Mode and Wake-up Power Down Mode All of the Holtek microcontrollers have the ability to enter a Power Down Mode. When the device enters this mode, the normal operating current, will be reduced to an extremely low standby current level. This occurs be- cause when the device enters the Power Down Mode, the system oscillator is stopped which reduces the power consumption to extremely low levels, however, as the device maintains its present internal condition, it can be woken up at a later stage and continue running, without requiring a full reset. This feature is extremely important in application areas where the MCU must have its power supply constantly maintained to keep the device in a known condition but where the power supply capacity is limited such as in battery applications. Entering the Power Down Mode There is only one way for the device to enter the Power Down Mode and that is to execute the /c178HALT/c178instruc- tion in the application program. When this instruction is executed, the following will occur: /c183The system oscillator will stop running and the appli - cation program will stop at the /c178HALT/c178instruction. /c183The Data Memory contents and registers will maintain their present condition. /c183The WDT will be cleared and resume counting if the WDT clock source is selected to come from the WDT internal oscillator. The WDT will stop if its clock source originates from the system clock. /c183The I/O ports will maintain their present condition. /c183In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO, will be cleared. Standby Current Considerations As the main reason for entering the Power Down Mode is to keep the current consumption of theMCUto as low a value as possible, perhaps only in the order of several micro-amps, there are other considerations which must also be taken into account by the circuit designer if the power consumption is to be minimised. Special atten - tion must be made to the I/O pins on the device. All high-impedance input pins must be connected to either a fixed high or low level as any floating input pins could create internal oscillations and result in increased cur - rent consumption. Care must also be taken with the loads, which are connected to I/O pins, which are setup as outputs. These should be placed in a condition in which minimum current is drawn or connected only to external circuits that do not draw current, such as other CMOS inputs. Also note that additional standby current will also be required if the configuration options have en- abled the Watchdog Timer internal oscillator. Wake-up After the system enters the Power Down Mode, it can be woken up from one of various sources listed as follows: /c183An external reset /c183An external falling edge on Port A /c183A system interrupt /c183A WDT overflow If the system is woken up by an external reset, the de - vice will experience a full system reset, however, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Although both of these wake-up methods will initiate a reset operation, the ac - tual source of the wake-up can be determined by exam- ining the TO and PDF flags. The PDF flag is cleared by a system power-up or executing the clear Watchdog Timer instructions and is set when executing the/c178HALT/c178 instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only resets the Program Counter and Stack Pointer, the other flags remain in their original status. Each pin on Port A can be setup via an individual config- uration option to permit a negative transition on the pin to wake-up the system. When a Port A pin wake-up oc- curs, the program will resume execution at the instruc - tion following the /c178HALT/c178instruction. /G4F /G53 /G43 /G31 /G4F /G53 /G43 /G32 /G66 /G53 /G59 /G53 /G2F /G34 /G20 /G4E /G4D /G4F /G53 /G20 /G4F /G70 /G65 /G6E /G20 /G44 /G72 /G61 /G69 /G6E /G34 /G37 /G30 /G70 /G46 /G56 /G44 /G44 /G52 /G4F /G53 /G43 External RC Oscillator

Rev. 1.00 38 November 28, 2007 If the system is woken up by an interrupt, then two possi- ble situations may occur. The first is where the related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program will resume exe- cution at the instruction following the/c178HALT/c178instruction. In this situation, the interrupt which woke-up the device will not be immediately serviced, but will rather be ser - viced later when the related interrupt is finally enabled or when a stack level becomes free. The other situation is where the related interrupt is enabled and the stack is not full, in which case the regular interrupt response takes place. If an interrupt request flag is set to /c1781/c178be- fore entering the Power Down Mode, the wake-up func- tion of the related interrupt will be disabled. No matter what the source of the wake-up event is, once a wake-up situation occurs, a time period equal to 1024 system clock periods will be required before normal sys- tem operation resumes. However, if the wake-up has originated due to an interrupt, the actual interrupt sub - routine execution will be delayed by an additional one or more cycles. If the wake-up results in the execution of the next instruction following the/c178HALT/c178instruction, this will be executed immediately after the 1024 system clock period delay has ended. Watchdog Timer The Watchdog Timer is provided to prevent program mal- functions or sequences from jumping to unknown loca- tions, due to certain uncontrollable external events such as electrical noise. It operates by providing a device reset when the WDT counter overflows. The WDT clock is sup- plied by one of two sources selected by configuration op- tion: its own self contained dedicated internal WDT oscillator or f SYS/4. Note that if the WDT configuration op- tion has been disabled, then any instruction relating to its operation will result in no operation. In the device, all Watchdog Timer options, such as en - able/disable, WDT clock source and clear instruction type all selected through configuration options. There are no internal registers associated with the WDT in the Cost-Effective A/D Type MCU series. One of the WDT clock sources is an internal oscillator which has an ap - proximate period of 65/c109s at a supply voltage of 5V. How- ever, it should be noted that this specified internal clock period can vary with VDD, temperature and process variations. The other WDT clock source option is the f SYS/4 clock. Whether the WDT clock source is its own internal WDT oscillator, or from f SYS/4, it is further di - vided by 16 via an internal 15-bit counter and a clearable single bit counter to give longer Watchdog time-outs. As this ratio is fixed it gives an overall Watchdog Timer time-out value of 2 15/fS to 216/fS. As the clear instruction only resets the last stage of the divider chain, for this reason the actual division ratio and corresponding Watchdog Timer time-out can vary by a factor of two. The exact division ratio depends upon the residual value in the Watchdog Timer counter before the clear instruc- tion is executed. It is important to realise that as there are no independent internal registers or configuration options associated with the length of the Watchdog Timer time-out, it is completely dependent upon the fre- quency of f SYS/4 or the internal WDT oscillator. If the fSYS/4 clock is used as the WDT clock source, it should be noted that when the system enters the Power Down Mode, then the instruction clock is stopped and the WDT will lose its protecting purposes. For systems that operate in noisy environments, using the internal WDT oscillator is strongly recommended. Under normal program operation, a WDT time-out will initialise a device reset and set the status bit TO. How - ever, if the system is in the Power Down Mode, when a WDT time-out occurs, the TO bit in the status register will be set and only the Program Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the WDT. The first is an external hardware reset, which means a low level on the RES pin, the second is using the watchdog software instruc- tions and the third is via a /c178HALT/c178instruction. There are two methods of using software instructions to clear the Watchdog Timer, one of which must be chosen by configuration option. The first option is to use the sin- gle /c178CLR WDT/c178instruction while the second is to use the two commands/c178CLR WDT1/c178and /c178CLR WDT2/c178. For the first option, a simple execution of /c178CLR WDT/c178will clear the WDT while for the second option, both/c178CLR WDT1/c178 and /c178CLR WDT2/c178must both be executed to successfully clear the WDT. Note that for this second option, if/c178CLR WDT1/c178is used to clear the WDT, successive executions of this instruction will have no effect, only the execution of a /c178CLR WDT2/c178instruction will clear the WDT. Similarly after the /c178CLR WDT2/c178instruction has been executed, only a successive/c178CLR WDT1/c178instruction can clear the Watchdog Timer. /G57 /G44 /G54 /G20 /G43 /G6C /G6F /G63 /G6B /G20 /G53 /G6F /G75 /G72 /G63 /G65 /G43 /G6F /G6E /G66 /G69 /G67 /G75 /G72 /G61 /G74 /G69 /G6F /G6E /G4F /G70 /G74 /G69 /G6F /G6E /G43 /G6C /G65 /G61 /G72 /G20 /G57 /G44 /G54 /G20 /G54 /G79 /G70 /G65 /G43 /G6F /G6E /G66 /G69 /G67 /G75 /G72 /G61 /G74 /G69 /G6F /G6E /G20 /G4F /G70 /G74 /G69 /G6F /G6E /G43 /G4C /G52 /G20 /G57 /G44 /G54 /G31 /G20 /G46 /G6C /G61 /G67 /G43 /G4C /G52 /G20 /G57 /G44 /G54 /G32 /G20 /G46 /G6C /G61 /G67 /G43 /G4C /G52 /G20 /G57 /G44 /G54 /G20 /G54 /G69 /G6D /G65 /G2D /G6F /G75 /G74 /G32 /G31 /G35 /G2F /G66 /G53 /G7E /G32 /G31 /G36 /G2F /G66 /G53 /G31 /G35 /G2D /G62 /G69 /G74 /G20 /G43 /G6F /G75 /G6E /G74 /G65 /G72 /GB8 /G32 /G57 /G44 /G54 /G20 /G4F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G6F /G72 /G66 /G53 /G59 /G53 /G2F /G34 /G31 /G20 /G6F /G72 /G20 /G32 /G20 /G49 /G6E /G73 /G74 /G72 /G75 /G63 /G74 /G69 /G6F /G6E /G73 /G57 /G44 /G54 /G20 /G43 /G6C /G6F /G63 /G6B /G20 /G53 /G6F /G75 /G72 /G63 /G65 /G66 /G53 Watchdog Timer

Rev. 1.00 39 November 28, 2007 Configuration Options Configuration options refer to certain options within the MCU that are programmed into the device during the program- ming process. During the development process, these options are selected using the HT-IDE software development tools. As these options are programmed into the device using the hardware programming tools, once they are selected they cannot be changed later as the application software has no control over the configuration options. All options must be defined for proper system function, the details of which are shown in the table. No. Options

1 Watchdog Timer clock source: WDT oscillator or f

2 Watchdog Timer function: enable or disable

3 CLRWDT instructions: 1 or 2 instructions

4 System oscillator: Crystal or RC

5 PA, PB, PC and PD: pull-high enable or disable

6 PWM0, PWM1: enable or disable

7 PA0~PA7: wake-up enable or disable - bit option

8 PFD: normal I/O or PFD output

9 LVR function: enable or disable

Rev. 1.00 40 November 28, 2007 /G4F /G53 /G43 /G31 /G4F /G53 /G43 /G32 /G4F /G53 /G43 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G50 /G44 /G30 /G2F /G50 /G57 /G4D /G30 /G50 /G42 /G30 /G2F /G41 /G4E /G30 /G7E /G50 /G42 /G35 /G2F /G41 /G4E /G35 /G50 /G42 /G36 /G7E /G50 /G42 /G37 /G50 /G41 /G30 /G7E /G50 /G41 /G32 /G50 /G41 /G33 /G2F /G50 /G46 /G44 /G50 /G41 /G34 /G2F /G54 /G4D /G52 /G30 /G50 /G41 /G35 /G2F /G49 /G4E /G54 /G50 /G41 /G36 /G7E /G50 /G41 /G37 /G50 /G43 /G30 /G7E /G50 /G43 /G37 /G50 /G44 /G31 /G2F /G50 /G57 /G4D /G31 /G50 /G41 /G36 /G48 /G54 /G34 /G36 /G52 /G34 /G41 /G52 /G45 /G53 /G30 /G2E /G31 /G6D /G46 /G31 /G30 /G30 /G6B /G57 /G56 /G44 /G44 /G56 /G53 /G53 /G30 /G2E /G31 /G6D /G46 /G56 /G44 /G44 /G52 /G65 /G73 /G65 /G74 /G43 /G69 /G72 /G63 /G75 /G69 /G74 /G53 /G65 /G65 /G20 /G4F /G73 /G63 /G69 /G6C /G6C /G61 /G74 /G6F /G72 /G53 /G65 /G63 /G74 /G69 /G6F /G6E

Rev. 1.00 41 November 28, 2007 Instruction Set Introduction Central to the successful operation of any microcontroller is its instruction set, which is a set of pro- gram instruction codes that directs the microcontroller to perform certain operations. In the case of Holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro- gramming overheads. For easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. Instruction Timing Most instructions are implemented within one instruc - tion cycle. The exceptions to this are branch, call, or ta- ble read instructions where two instruction cycles are required. One instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8MHz system oscillator, most instructions would be implemented within 0.5/c109s and branch or call instructions would be im- plemented within 1 /c109s. Although instructions which re - quire one more cycle to implement are generally limited to the JMP, CALL, RET, RETI and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the Program Counter Low register or PCL will also take one more cycle to imple- ment. As instructions which change the contents of the PCL will imply a direct jump to that new address, one more cycle will be required. Examples of such instruc- tions would be /c178CLR PCL/c178or /c178MOV PCL, A /c178. For the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. Moving and Transferring Data The transfer of data within the microcontroller program is one of the most frequently used operations. Making use of three kinds of MOV instructions, data can be transferred from registers to the Accumulator and vice-versa as well as being able to move specific imme- diate data directly into the Accumulator. One of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. Arithmetic Operations The ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. Within the Holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. Care must be taken to en - sure correct handling of carry and borrow data when re- sults exceed 255 for addition and less than 0 for subtraction. The increment and decrement instructions INC, INCA, DEC and DECA provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. Logical and Rotate Operations The standard logical operations such as AND, OR, XOR and CPL all have their own instruction within the Holtek microcontroller instruction set. As with the case of most instructions involving data manipulation, data must pass through the Accumulator which may involve additional programming steps. In all logical data operations, the zero flag may be set if the result of the operation is zero. Another form of logical data manipulation comes from the rotate instructions such as RR, RL, RRC and RLC which provide a simple means of rotating one bit right or left. Different rotate instructions exist depending on pro- gram requirements. Rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the Carry bit from where it can be examined and the necessary serial bit set high or low. Another application where rotate data operations are used is to implement multiplication and division calculations. Branches and Control Transfer Program branching takes the form of either jumps to specified locations using the JMP instruction or to a sub- routine using the CALL instruction. They differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub- routine has been carried out. This is done by placing a return instruction RET in the subroutine which will cause the program to jump back to the address right after the CALL instruction. In the case of a JMP instruction, the program simply jumps to the desired location. There is no requirement to jump back to the original jumping off point as in the case of the CALL instruction. One special and extremely useful set of branch instructions are the conditional branches. Here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. Depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. These instructions are the key to decision making and branching within the pro- gram perhaps determined by the condition of certain in- put switches or by the condition of internal data bits.

Rev. 1.00 42 November 28, 2007 Bit Operations The ability to provide single bit operations on Data Mem- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the/c178SET [m].i/c178or /c178CLR [m].i/c178instructions respectively. The fea- ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. This read-modify-write pro - cess is taken care of automatically when these bit oper- ation instructions are used. Table Read Operations Data storage is normally implemented by using regis - ters. However, when working with large amounts of fixed data, the volume involved often makes it inconve- nient to store the fixed data in the Data Memory. To over- come this problem, Holtek microcontrollers allow an area of Program Memory to be setup as a table where data can be directly stored. A set of easy to use instruc- tions provides the means by which this fixed data can be referenced and retrieved from the Program Memory. Other Operations In addition to the above functional instructions, a range of other instructions also exist such as the /c178HALT/c178in- struction for Power-down operations and instructions to control the operation of the Watchdog Timer for reliable program operations under extreme electric or electro - magnetic environments. For their relevant operations, refer to the functional related sections. Instruction Set Summary The following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow- ing listed conventions. Table conventions: x: Bits immediate data m: Data Memory address A: Accumulator i: 0~7 number of bits addr: Program memory address Mnemonic Description Cycles Flag Affected Arithmetic ADD A,[m] ADDM A,[m] ADD A,x ADC A,[m] ADCM A,[m] SUB A,x SUB A,[m] SUBM A,[m] SBC A,[m] SBCM A,[m] DAA [m] Add Data Memory to ACC Add ACC to Data Memory Add immediate data to ACC Add Data Memory to ACC with Carry Add ACC to Data memory with Carry Subtract immediate data from the ACC Subtract Data Memory from ACC Subtract Data Memory from ACC with result in Data Memory Subtract Data Memory from ACC with Carry Subtract Data Memory from ACC with Carry, result in Data Memory Decimal adjust ACC for Addition with result in Data Memory Note 1Note Note 1Note 1Note Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV Z, C, AC, OV C Logic Operation AND A,[m] OR A,[m] XOR A,[m] ANDM A,[m] ORM A,[m] XORM A,[m] AND A,x OR A,x XOR A,x CPL [m] CPLA [m] Logical AND Data Memory to ACC Logical OR Data Memory to ACC Logical XOR Data Memory to ACC Logical AND ACC to Data Memory Logical OR ACC to Data Memory Logical XOR ACC to Data Memory Logical AND immediate Data to ACC Logical OR immediate Data to ACC Logical XOR immediate Data to ACC Complement Data Memory Complement Data Memory with result in ACC Note 1Note 1Note Note Z Z Z Z Z Z Z Z Z Z Z Increment & Decrement INCA [m] INC [m] DECA [m] DEC [m] Increment Data Memory with result in ACC Increment Data Memory Decrement Data Memory with result in ACC Decrement Data Memory Note 1Note Z Z Z Z

Rev. 1.00 43 November 28, 2007 Mnemonic Description Cycles Flag Affected Rotate RRA [m] RR [m] RRCA [m] RRC [m] RLA [m] RL [m] RLCA [m] RLC [m] Rotate Data Memory right with result in ACC Rotate Data Memory right Rotate Data Memory right through Carry with result in ACC Rotate Data Memory right through Carry Rotate Data Memory left with result in ACC Rotate Data Memory left Rotate Data Memory left through Carry with result in ACC Rotate Data Memory left through Carry Note 1Note 1Note 1Note None None C C None None C C Data Move MOV A,[m] MOV [m],A MOV A,x Move Data Memory to ACC Move ACC to Data Memory Move immediate data to ACC Note None None None Bit Operation CLR [m].i SET [m].i Clear bit of Data Memory Set bit of Data Memory Note 1Note None None Branch JMP addr SZ [m] SZA [m] SZ [m].i SNZ [m].i SIZ [m] SDZ [m] SIZA [m] SDZA [m] CALL addr RET RET A,x RETI Jump unconditionally Skip if Data Memory is zero Skip if Data Memory is zero with data movement to ACC Skip if bit i of Data Memory is zero Skip if bit i of Data Memory is not zero Skip if increment Data Memory is zero Skip if decrement Data Memory is zero Skip if increment Data Memory is zero with result in ACC Skip if decrement Data Memory is zero with result in ACC Subroutine call Return from subroutine Return from subroutine and load immediate data to ACC Return from interrupt Note 1note 1Note 1Note 1Note 1Note 1Note 1Note None None None None None None None None None None None None None Table Read TABRDC [m] TABRDL [m] Read table (current page) to TBLH and Data Memory Read table (last page) to TBLH and Data Memory Note 2Note None None Miscellaneous NOP CLR [m] SET [m] CLR WDT CLR WDT1 CLR WDT2 SWAP [m] SWAPA [m] HALT No operation Clear Data Memory Set Data Memory Clear Watchdog Timer Pre-clear Watchdog Timer Pre-clear Watchdog Timer Swap nibbles of Data Memory Swap nibbles of Data Memory with result in ACC Enter power down mode Note 1Note Note None None None TO, PDF TO, PDF TO, PDF None None TO, PDF Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution. 3. For the /c178CLR WDT1/c178and /c178CLR WDT2/c178instructions the TO and PDF flags may be affected by the execution status. The TO and PDF flags are cleared after both /c178CLR WDT1/c178and /c178CLR WDT2/c178instructions are consecutively executed. Otherwise the TO and PDF flags remain unchanged.

ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. Operation ACC /c172A C C+[ m ]+C Affected flag(s) OV, Z, AC, C ADCM A,[m] Add ACC to Data Memory with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the specified Data Memory. Operation [m] /c172A C C+[ m ]+C Affected flag(s) OV, Z, AC, C ADD A,[m] Add Data Memory to ACC Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the Accumulator. Operation ACC /c172ACC + [m] Affected flag(s) OV, Z, AC, C ADD A,x Add immediate data to ACC Description The contents of the Accumulator and the specified immediate data are added. The result is stored in the Accumulator. Operation ACC /c172A C C+x Affected flag(s) OV, Z, AC, C ADDM A,[m] Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added. The result is stored in the specified Data Memory. Operation [m] /c172ACC + [m] Affected flag(s) OV, Z, AC, C AND A,[m] Logical AND Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical AND op - eration. The result is stored in the Accumulator. Operation ACC /c172ACC /c178AND/c178[m] Affected flag(s) Z AND A,x Logical AND immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical AND operation. The result is stored in the Accumulator. Operation ACC /c172ACC /c178AND/c178x Affected flag(s) Z ANDM A,[m] Logical AND ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical AND op - eration. The result is stored in the Data Memory. Operation [m] /c172ACC /c178AND/c178[m] Affected flag(s) Z HT46R4A Rev. 1.00 44 November 28, 2007

Description Unconditionally calls a subroutine at the specified address. The Program Counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address. As this instruction requires an additional operation, it is a two cycle instruc- tion. Operation Stack /c172Program Counter + 1 Program Counter /c172addr Affected flag(s) None CLR [m] Clear Data Memory Description Each bit of the specified Data Memory is cleared to 0. Operation [m] /c17200H Affected flag(s) None CLR [m].i Clear bit of Data Memory Description Bit i of the specified Data Memory is cleared to 0. Operation [m].i /c1720 Affected flag(s) None CLR WDT Clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Operation WDT cleared TO /c1720 PDF /c1720 Affected flag(s) TO, PDF CLR WDT1 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc- tion with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT2 will have no effect. Operation WDT cleared TO /c1720 PDF /c1720 Affected flag(s) TO, PDF CLR WDT2 Pre-clear Watchdog Timer Description The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunc - tion with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Re- petitively executing this instruction without alternately executing CLR WDT1 will have no effect. Operation WDT cleared TO /c1720 PDF /c1720 Affected flag(s) TO, PDF HT46R4A Rev. 1.00 45 November 28, 2007

CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1 /c162s complement). Bits which previously contained a 1 are changed to 0 and vice versa. Operation [m] /c172[m] Affected flag(s) Z CPLA [m] Complement Data Memory with result in ACC Description Each bit of the specified Data Memory is logically complemented (1 /c162s complement). Bits which previously contained a 1 are changed to 0 and vice versa. The complemented result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC /c172[m] Affected flag(s) Z DAA [m] Decimal-Adjust ACC for addition with result in Data Memory Description Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value re - sulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of 6 will be added to the high nibble. Essentially, the decimal conversion is performed by add- ing 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C flag may be affected by this instruction which indicates that if the original BCD sum is greater than 100, it allows multiple precision decimal addition. Operation [m] /c172ACC + 00H or [m] /c172ACC + 06H or [m] /c172ACC + 60H or [m] /c172ACC + 66H Affected flag(s) C DEC [m] Decrement Data Memory Description Data in the specified Data Memory is decremented by 1. Operation [m] /c172[m] /c451 Affected flag(s) Z DECA [m] Decrement Data Memory with result in ACC Description Data in the specified Data Memory is decremented by 1. The result is stored in the Accu - mulator. The contents of the Data Memory remain unchanged. Operation ACC /c172[m] /c451 Affected flag(s) Z HALT Enter power down mode Description This instruction stops the program execution and turns off the system clock. The contents of the Data Memory and registers are retained. The WDT and prescaler are cleared. The power down flag PDF is set and the WDT time-out flag TO is cleared. Operation TO /c1720 PDF /c1721 Affected flag(s) TO, PDF HT46R4A Rev. 1.00 46 November 28, 2007

INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. Operation [m] /c172[ m ]+1 Affected flag(s) Z INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu - lator. The contents of the Data Memory remain unchanged. Operation ACC /c172[ m ]+1 Affected flag(s) Z JMP addr Jump unconditionally Description The contents of the Program Counter are replaced with the specified address. Program execution then continues from this new address. As this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. Operation Program Counter /c172addr Affected flag(s) None MOV A,[m] Move Data Memory to ACC Description The contents of the specified Data Memory are copied to the Accumulator. Operation ACC /c172[m] Affected flag(s) None MOV A,x Move immediate data to ACC Description The immediate data specified is loaded into the Accumulator. Operation ACC /c172x Affected flag(s) None MOV [m],A Move ACC to Data Memory Description The contents of the Accumulator are copied to the specified Data Memory. Operation [m] /c172ACC Affected flag(s) None NOP No operation Description No operation is performed. Execution continues with the next instruction. Operation No operation Affected flag(s) None OR A,[m] Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR oper - ation. The result is stored in the Accumulator. Operation ACC /c172ACC /c178OR/c178[m] Affected flag(s) Z HT46R4A Rev. 1.00 47 November 28, 2007

OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op - eration. The result is stored in the Accumulator. Operation ACC /c172ACC /c178OR/c178x Affected flag(s) Z ORM A,[m] Logical OR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical OR oper - ation. The result is stored in the Data Memory. Operation [m] /c172ACC /c178OR/c178[m] Affected flag(s) Z RET Return from subroutine Description The Program Counter is restored from the stack. Program execution continues at the re - stored address. Operation Program Counter /c172Stack Affected flag(s) None RET A,x Return from subroutine and load immediate data to ACC Description The Program Counter is restored from the stack and the Accumulator loaded with the specified immediate data. Program execution continues at the restored address. Operation Program Counter /c172Stack ACC /c172x Affected flag(s) None RETI Return from interrupt Description The Program Counter is restored from the stack and the interrupts are re-enabled by set- ting the EMI bit. EMI is the master interrupt global enable bit. If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine will be processed be- fore returning to the main program. Operation Program Counter /c172Stack EMI /c1721 Affected flag(s) None RL [m] Rotate Data Memory left Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit Operation [m].(i+1) /c172[m].i; (i = 0~6) [m].0 /c172[m].7 Affected flag(s) None RLA [m] Rotate Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory re- main unchanged. Operation ACC.(i+1) /c172[m].i; (i = 0~6) ACC.0 /c172[m].7 Affected flag(s) None HT46R4A Rev. 1.00 48 November 28, 2007

RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0. Operation [m].(i+1) /c172[m].i; (i = 0~6) [m].0 /c172C C /c172[m].7 Affected flag(s) C RLCA [m] Rotate Data Memory left through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.(i+1) /c172[m].i; (i = 0~6) ACC.0 /c172C C /c172[m].7 Affected flag(s) C RR [m] Rotate Data Memory right Description The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into bit 7. Operation [m].i /c172[m].(i+1); (i = 0~6) [m].7 /c172[m].0 Affected flag(s) None RRA [m] Rotate Data Memory right with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i /c172[m].(i+1); (i = 0~6) ACC.7 /c172[m].0 Affected flag(s) None RRC [m] Rotate Data Memory right through Carry Description The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. Operation [m].i /c172[m].(i+1); (i = 0~6) [m].7 /c172C C /c172[m].0 Affected flag(s) C RRCA [m] Rotate Data Memory right through Carry with result in ACC Description Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 re - places the Carry bit and the original carry flag is rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged. Operation ACC.i /c172[m].(i+1); (i = 0~6) ACC.7 /c172C C /c172[m].0 Affected flag(s) C HT46R4A Rev. 1.00 49 November 28, 2007

SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub - tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC /c172ACC /c45[m] /c45C Affected flag(s) OV, Z, AC, C SBCM A,[m] Subtract Data Memory from ACC with Carry and result in Data Memory Description The contents of the specified Data Memory and the complement of the carry flag are sub - tracted from the Accumulator. The result is stored in the Data Memory. Note that if the re- sult of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] /c172ACC /c45[m] /c45C Affected flag(s) OV, Z, AC, C SDZ [m] Skip if decrement Data Memory is 0 Description The contents of the specified Data Memory are first decremented by 1. If the result is 0 the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] /c172[m] /c451 Skip if [m] = 0 Affected flag(s) None SDZA [m] Skip if decrement Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first decremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation ACC /c172[m] /c451 Skip if ACC = 0 Affected flag(s) None SET [m] Set Data Memory Description Each bit of the specified Data Memory is set to 1. Operation [m] /c172FFH Affected flag(s) None SET [m].i Set bit of Data Memory Description Bit i of the specified Data Memory is set to 1. Operation [m].i /c1721 Affected flag(s) None HT46R4A Rev. 1.00 50 November 28, 2007

SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation [m] /c172[ m ]+1 Skip if [m] = 0 Affected flag(s) None SIZA [m] Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. The result is stored in the Accumulator but the specified Data Memory contents remain unchanged. As this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC /c172[ m ]+1 Skip if ACC = 0 Affected flag(s) None SNZ [m].i Skip if bit i of Data Memory is not 0 Description If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is 0 the program proceeds with the following instruction. Operation Skip if [m].i /c1850 Affected flag(s) None SUB A,[m] Subtract Data Memory from ACC Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC /c172ACC /c45[m] Affected flag(s) OV, Z, AC, C SUBM A,[m] Subtract Data Memory from ACC with result in Data Memory Description The specified Data Memory is subtracted from the contents of the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation [m] /c172ACC /c45[m] Affected flag(s) OV, Z, AC, C SUB A,x Subtract immediate data from ACC Description The immediate data specified by the code is subtracted from the contents of the Accumu - lator. The result is stored in the Accumulator. Note that if the result of subtraction is nega- tive, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1. Operation ACC /c172ACC /c45x Affected flag(s) OV, Z, AC, C HT46R4A Rev. 1.00 51 November 28, 2007

SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. Operation [m].3~[m].0 /c171[m].7 ~ [m].4 Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged. Operation ACC.3 ~ ACC.0 /c172[m].7 ~ [m].4 ACC.7 ~ ACC.4 /c172[m].3 ~ [m].0 Affected flag(s) None SZ [m] Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruc- tion. Operation Skip if [m] = 0 Affected flag(s) None SZA [m] Skip if Data Memory is 0 with data movement to ACC Description The contents of the specified Data Memory are copied to the Accumulator. If the value is zero, the following instruction is skipped. As this requires the insertion of a dummy instruc- tion while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program proceeds with the following instruction. Operation ACC /c172[m] Skip if [m] = 0 Affected flag(s) None SZ [m].i Skip if bit i of Data Memory is 0 Description If bit i of the specified Data Memory is 0, the following instruction is skipped. As this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0, the program proceeds with the following instruction. Operation Skip if [m].i = 0 Affected flag(s) None TABRDC [m] Read table (current page) to TBLH and Data Memory Description The low byte of the program code (current page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] /c172program code (low byte) TBLH /c172program code (high byte) Affected flag(s) None TABRDL [m] Read table (last page) to TBLH and Data Memory Description The low byte of the program code (last page) addressed by the table pointer (TBLP) is moved to the specified Data Memory and the high byte moved to TBLH. Operation [m] /c172program code (low byte) TBLH /c172program code (high byte) Affected flag(s) None HT46R4A Rev. 1.00 52 November 28, 2007

XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op - eration. The result is stored in the Accumulator. Operation ACC /c172ACC /c178XOR/c178[m] Affected flag(s) Z XORM A,[m] Logical XOR ACC to Data Memory Description Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR op - eration. The result is stored in the Data Memory. Operation [m] /c172ACC /c178XOR/c178[m] Affected flag(s) Z XOR A,x Logical XOR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical XOR operation. The result is stored in the Accumulator. Operation ACC /c172ACC /c178XOR/c178x Affected flag(s) Z HT46R4A Rev. 1.00 53 November 28, 2007

Package Information

28-pin SKDIP (300mil) Outline Dimensions Symbol Dimensions in mil Min. Nom. Max. A 1375 /c190 1395 B 278 /c190 298 C 125 /c190 135 D 125 /c190 145 E1 6 /c190 20 F5 0 /c190 70 G /c190 100 /c190 H 295 /c190 315 I 330 /c190 375 /c97 0/c176/c190 15/c176 HT46R4A Rev. 1.00 54 November 28, 2007 /G20 /G20 /G32 /G38 /G31 /G31 /G35 /G31 /G34 /G61 /G41 /G42 /G43 /G44 /G45 /G46 /G47 /G48 /G49

28-pin SOP (300mil) Outline Dimensions Symbol Dimensions in mil Min. Nom. Max. A 394 /c190 419 B 290 /c190 300 C1 4 /c190 20 C/c162 697 /c190 713 D9 2 /c190 104 E /c190 50 /c190 F4 /c190/c190 G3 2 /c190 38 H4 /c190 12 /c97 0/c176/c190 10/c176 HT46R4A Rev. 1.00 55 November 28, 2007 /G32 /G38 /G31 /G31 /G35 /G31 /G34 /G41 /G42 /G43 /G44 /G46 /G43 /G27 /G47 /G48 /G61 /G45

32-pin DIP (600mil) Outline Dimensions Symbol Dimensions in mil Min. Nom. Max. A 1635 /c190 1665 B 535 /c190 555 C 145 /c190 155 D 125 /c190 145 E1 6 /c190 20 F5 0 /c190 70 G /c190 100 /c190 H 595 /c190 615 I 635 /c190 670 /c97 0/c176/c190 15/c176 HT46R4A Rev. 1.00 56 November 28, 2007 /G33 /G32 /G31 /G31 /G37 /G31 /G36 /G61 /G41 /G42 /G43 /G44 /G45 /G46 /G47 /G48 /G49

44-pin QFP (10/c18010) Outline Dimensions Symbol Dimensions in mm Min. Nom. Max. A1 3 /c190 13.4 B 9.9 /c190 10.1 C1 3 /c190 13.4 D 9.9 /c190 10.1 E /c190 0.8 /c190 F /c190 0.3 /c190 G 1.9 /c190 2.2 H /c190/c190 2.7 I 0.25 /c190 0.5 J 0.73 /c190 0.93 K 0.1 /c190 0.2 L /c190 0.1 /c190 /c97 0/c176/c190 7/c176 HT46R4A Rev. 1.00 57 November 28, 2007 /G33 /G34 /G31 /G31 /G31 /G34 /G34 /G41 /G42 /G32 /G32 /G31 /G32 /G45 /G46 /G47 /G48 /G49 /G4A /G4B /G61 /G33 /G33 /G32 /G33 /G43 /G44 /G4C

Product Tape and Reel Specifications Reel Dimensions SOP 28W (300mil) Symbol Description Dimensions in mm A Reel Outer Diameter 330/c1771 B Reel Inner Diameter 62/c1771.5 C Spindle Hole Diameter 13+0.5 /c450.2 D Key Slit Width 2/c1770.5 T1 Space Between Flange 24.8+0.3 /c450.2 T2 Reel Thickness 30.2/c1770.2 HT46R4A Rev. 1.00 58 November 28, 2007 /G41 /G43 /G42 /G54 /G31 /G54 /G32 /G44

SOP 28W (300mil) Symbol Description Dimensions in mm W Carrier Tape Width 24/c1770.3 P Cavity Pitch 12/c1770.1 E Perforation Position 1.75/c1770.1 F Cavity to Perforation (Width Direction) 11.5/c1770.1 D Perforation Diameter 1.5+0.1 D1 Cavity Hole Diameter 1.5+0.25 P0 Perforation Pitch 4/c1770.1 P1 Cavity to Perforation (Length Direction) 2/c1770.1 A0 Cavity Length 10.85/c1770.1 B0 Cavity Width 18.34/c1770.1 K0 Cavity Depth 2.97/c1770.1 t Carrier Tape Thickness 0.35/c1770.01 C Cover Tape Width 21.3 HT46R4A Rev. 1.00 59 November 28, 2007 /G50 /G44 /G31 /G57 /G50 /G31 /G50 /G30 /G44 /G45 /G46 /G74 /G4B /G30 /G42 /G30 /G41 /G30 /G43

Rev. 1.00 60 November 28, 2007 Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shanghai Sales Office) 7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233 Tel: 86-21-6485-5560 Fax: 86-21-6485-0313 http://www.holtek.com.cn Holtek Semiconductor Inc. (Shenzhen Sales Office) 5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor Inc. (Beijing Sales Office) Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031 Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752 Fax: 86-10-6641-0125 Holtek Semiconductor Inc. (Chengdu Sales Office) 709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016 Tel: 86-28-6653-6590 Fax: 86-28-6653-6591 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com Copyright /c2112007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as - sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek/c162s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.