GP24BC01-16 ETL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 9

Technical content

Features

&Internally organized as 128x8 (1K), 256x8 (2K) 512x8 (4K), 1024x8 (8K), 2048x8 (16K), &Low-voltage and standard-voltage operation: 1.8V~5.5V &¯-wire serial interface bus &Date retention: 100years &High endurance: 1,000,000 Write Cycles &100KHz (1.8V) & 400KHz (5V) compatibility &Bi-directional data transfer protocol &Self-timed write cycle (5ms max) &Write protect pin for hardware data protection &8-byte page (1K, 2K) and 16-byte page (4K,8K,16K) write modes &Allows for partial page write Package Dimensions A - 0.5334 c1 0.203 0.279 A1 0.381 - D 9.017 10.16 A2 2.921 4.953 E 6.096 7.112 b 0.356 0.559 E1 7.620 8.255 b1 0.356 0.508 e 2.540 BSC b2 1.143 1.778 HE - 10.92 b3 0.762 1.143 L 2.921 3.810 c 0.203 0.356 Figure 1. Pin Configurations these specifications are not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Figure 2. Block Diagram defined as an open-drain connection, a pull-up resistor is needed. single bus system and should be hard-wired. system. The A0 pin in not used, but should be grounded if possible. devices may be addressed. The A0 and A1 pins are not used, but should be grounded if possible. bus system. Therefore, the A0, A1 and A2 pins are not used, but should be grounded if possible. CC, no data can be overwritten.

GP24BC01/02/02/04/08/16 Page: 3/9 ISSUED DATE :2006/08/17 REVISED DATE : Memory Organization The internal memory organization for the GP24BC family is arranged differently for each of the densities. The GP24BC01, for instance, is internally organized as 16 pages of 8 bytes each and requires a 7-bit data word address. The GP24BC16, on the other hand, is organized as 128 pages of 16 bytes each with an 11-bit data word address. The table below summarizes these differences. Density # of pages Bytes per page Data word address length GP24BC01 (1K) 16 pages 8 bytes 7 bits GP24BC02 (2K) 32 pages 8 bytes 8 bits GP24BC04 (4K) 32 pages 16 bytes 9 bits GP24BC08 (8K) 64 pages 16 bytes 10 bits GP24BC16 (16K) 128 pages 16 bytes 11 bits PIN Capacitance Applicable over recommended operating range from TA=25:, f=1.0MHz, Vcc=+1.8V Symbol Test Condition Max Unit Condition CI/O Input/Output Capacitance (SDA) 8 pF VI/O=0V CIN Input Capacitance (A0, A1, A2, SCL) 6 pF VIN=0V Note: 1.This parameter is characterized and not 100% tested. DC Characteristics Applicable over recommended operating range from: TA=-40 ~ +85:, VCC=+1.8 ~ +5V (unless otherwise noted) Parameter Symbol Test Condition Min TYP Max Unit Supply Voltage VCC1 1.8 - 5.5 V Supply Voltage VCC2 2.7 - 5.5 V Supply Voltage VCC3 4.5 - 5.5 V Supply Current VCC=5.0V ICC READ at 100KHz - 0.4 1.0 mA Supply Current VCC=5.0V ICC WRITE at 100KHz - 2.0 3.0 mA Standby Current VCC=1.8V ISB1 VIN= VCC or VSS - 0.6 3.0 A Standby Current VCC=2.5V ISB2 VIN= VCC or VSS - 1.4 4.0 A Standby Current VCC=5.5V ISB3 VIN= VCC or VSS - 5.0 18 A Input Leakage Current ILI VIN= VCC or VSS - 0.2 5.0 A Output Leakage Current ILO VOUT= VCC or VSS - 0.1 5.0 A Input Low Level (1) VIL -0.6 - VCCx0.3 V Input High Level (1) VIH VCCx0.7 - VCC+0.5 V Output Low Level VCC=3.0V VOL2 IOL=2.1mA - - 0.4 V Output Low Level VCC=3.0V VOL1 IOL=0.15mA - - 0.2 V Note 1: VIL and VIH max are reference only and are not tested.

GP24BC01/02/02/04/08/16 Page: 4/9 ISSUED DATE :2006/08/17 REVISED DATE : AC Characteristics Applicable over recommended operating range from: TA=-40 ~ +85:, VCC=+1.8 ~ 5.5V, CL=1 TTL Gate & 100pF (unless otherwise noted) Parameter Symbol Test Condition Min TYP Max Unit Clock Frequency, SCL fSCL VCC=1.8V

400 KHz

Clock Pulse Width Low tLOW VCC=1.8V VCC=2.7 ~ 5.5V 4.7 1.2 - - s Clock Pulse Width High tHIGH VCC=1.8V VCC=2.7 ~ 5.5V 4.0 0.6 - - s Noise Suppression Time (1) tI VCC=1.8V 50 ns Clock Low to Data Out Valid tAA VCC=1.8V VCC=2.7 ~ 5.5V 0.1 0.1 - 4.5 0.9 s Time the bus must be free before a new transmission can start (1) tBUF VCC=1.8V VCC=2.7 ~ 5.5V 4.7 1.2 - - s Start Hold Time tHD.STA VCC=1.8V VCC=2.7 ~ 5.5V 4.0 0.6 - - s Start Setup Time tSU.STA VCC=1.8V VCC=2.7 ~ 5.5V 4.7 0.6 - - s Data in Hold Time tHD.DAT VCC=1.8V VCC=2.7 ~ 5.5V - - s Data in Setup Time tUS.DAT VCC=1.8V VCC=2.7 ~ 5.5V 200 100 - - ns Input Rise Time (1) tR VCC=1.8V 0.3 s Input Fall Time (1) tF VCC=1.8V 300 ns Stop Setup Time tSU.STO VCC=1.8V VCC=2.7 ~ 5.5V 4.7 0.6 - - s Data Out Hold Time tDH VCC=1.8V VCC=2.7 ~ 5.5V 100 - - ns Write Cycle Time tWR VCC=1.8V 5 ms 5.0V, 25:, Byte Mode Endurance (1) VCC=1.8V VCC=2.7 ~ 5.5V 1M - - Write Cycles Note: 1. This parameter is characterized and not 100% tested. Device Operation Clock and Data Transitions: Transitions on the SDA pin should only occur when SCL is low (refer to the Data Validity timing diagram in Figure 5). If the SDA pin changes when SCL is high, then the transition will be interpreted as a START or STOP condition. START Condition: A START condition occurs when the SDA transitions form high to low when SCL is high. The START signal is usually used to initiate a command (refer to the Start and Stop Definition timing diagram in Figure 6). STOP Condition: A STOP condition occurs when the SDA transitions form low to high when SCL is high (refer to Figure 6. START and STOP Definition timing diagram). The STOP command will put the device into standby mode after no acknowledgment is issued during the read sequence. Acknowledge: An acknowledgement is sent by pulling the SDA low to confirm that a word has been successfully received. All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words, so acknowledgments are usually issued during the 9th clock cycle. Standby Mode: Standby mode is entered when the chip is initially powered-on or after a STOP command has been issued and any internal operations have been completed. . Memory Reset: In the event of unexpected power or connection loss, a START condition can be issued to restart the input command sequence. If the device is currently in write cycle mode, this command will be ignored.

GP24BC01/02/02/04/08/16 Page: 9/9 ISSUED DATE :2006/08/17 REVISED DATE : Ordering Code Package Operating Ranges GP24BC01I GP24BC02I GP24BC04I GP24BC08I GP24BC16I DIP-8 Industrial (-40 ~ +85::::) Product Ordering Information GP24BCXXY Important Notice: All rights are reserved. Reproduction in whole or in part is prohibited without the prior written approval of GTM. GTM reserves the right to make changes to its products without notice. GTM semiconductor products are not warranted to be suitable for use in life-support Applications, or systems. GTM assumes no liability for any consequence of customer product design, infringement of patents, or application assistance. Head Office And Factory: TEL : 886-3-597-7061 FAX : 886-3-597-9220, 597-0785 China: (201203) No.255, Jang-Jiang Tsai-Lueng RD. , Pu-Dung-Hsin District, Shang-Hai City, China TEL : 86-21-5895-7671 ~ 4 FAX : 86-21-38950165 P=DIP-8 G=GTM 24=Device Type Supply Voltage BC=1.8V to 5.5V Device Function 01= 1 Kbit (128x8) 02= 2 Kbit (256x8) 04= 4 Kbit (512x8) 08= 8 Kbit (1024x8) 16=16 Kbit (2048x8) Temperature I=Industrial (-40 ~ +85:*