GA06JT12-247 GENESIC | Alldatasheet
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Technical content
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg1 of 10 S D G Normally – OFF Silicon Carbide Junction Transistor Features Package 175 °C Maximum Operating Temperature Gate Oxide Free SiC Switch Exceptional Safe Operating Area Excellent Gain Linearity Temperature Independent Switching Performance Low Output Capacitance Positive Temperature Coefficient of R DS,ON Suitable for Connecting an Anti-parallel Diode RoHS Compliant TO-247AB Advantages Applications Compatible with Si MOSFET/IGBT Gate Drive ICs > 20 µs Short-Circuit Withstand Capability Lowest-in-class Conduction Losses High Circuit Efficiency Minimal Input Signal Distortion High Amplifier Bandwidth Down Hole Oil Drilling, Geothermal Instrumentation Hybrid Electric Vehicles (HEV) Solar Inverters Switched-Mode Power Supply (SMPS) Power Factor Correction (PFC) Induction Heating Uninterruptible Power Supply (UPS) Motor Drives Absolute Maximum Ratings Parameter Symbol Conditions Value Unit Notes Drain – Source Voltage V DS VGS = 0 V 1200 V Continuous Drain Current I D TC = 150 °C 6 A Fig. 19 Continuous Gate Current I GM 1.5 A Turn-Off Safe Operating Area RBSOA TVJ = 175 oC, IG = 1 A, Clamped Inductive Load ID,max = 6 @ VDS ≤ VDSmax A Fig. 16 Short Circuit Safe Operating Area SCSOA TVJ = 175 oC, IG = 1 A, VDS = 800 V, Non Repetitive 20 µs Reverse Gate – Source Voltage V SG 30 V Reverse Drain – Source Voltage V SD 40 V Power Dissipation P tot TC = 150 °C 24 W Fig. 14 Storage Temperature T stg -55 to 175 °C
Electrical Characteristics
S G D D VDS = 1200 V RDS(ON) = 200 mΩ ID @ Tc=150°C = 6 A hFE Tc=25°C = 54 Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Drain – Source On Resistance R DS(ON) ID = 6 A, Tj = 25 °C ID = 6 A, Tj = 125 °C ID = 6 A, Tj = 175 °C 200 280 370 mΩ Fig. 5 Gate Forward Voltage V GS(FWD) IG = 500 mA, Tj = 25 °C IG = 500 mA, Tj = 175 °C 3.1 2.9 V Fig. 4 DC Current Gain h FE VDS = 5 V, ID = 6 A, Tj = 25 °C VDS = 5 V, ID = 6 A, Tj = 175 °C 53 33 – Fig. 5 Drain Leakage Current I DSS VR = 1200 V, VGS = 0 V, Tj = 25 °C VR = 1200 V, VGS = 0 V, Tj = 125 °C VR = 1200 V, VGS = 0 V, Tj = 175 °C 0.5 μA Fig. 6 Gate Leakage Current I SG VSG = 20 V, Tj = 25 °C 20 nA
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg2 of 10 Capacitance Characteristics Switching Characteristics1 1 – All times are relative to the Drain-Source Voltage VDS Thermal Characteristics Figures Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 125 °C Parameter Symbol Conditions Value Unit Notes Min. Typical Max. Input Capacitance C iss VGS = 0 V, VD = 500 V, f = 1 MHz 700 pF Fig. 7 Reverse Transfer/Output Capacitance C rss/Coss VD = 500 V, f = 1 MHz 25 pF Fig. 7 Output Capacitance Stored Energy E OSS VGS = 0 V, VD = 1000 V, f = 1 MHz 10.2 µJ Fig. 8 Internal Gate Resistance, Zero Bias R G(INT-ZERO) f = 1 MHz, VAC = 25 mV, Tj = 175 ºC 5.85 Ω Internal Gate Resistance, On R G(INT-ON) VGS > 2.5 V 0.9 Ω Turn On Delay Time t d(on) Tj = 25 ºC, VDS = 800 V, ID = 6 A, VG = 20/-5 V, Load = 133 Ω Refer to Fig. 20 for IG Waveform 10 ns Fall Time, VDS t f 26 ns Fig. 9, 11 Turn Off Delay Time t d(off) 24 ns Rise Time, VDS t r 19 ns Fig. 10, 12 Turn On Delay Time t d(on) Tj = 175 ºC, VDS = 800 V, ID = 6 A, VG = 20/-5 V, Load = 133 Ω Refer to Fig. 20 for IG Waveform 12 ns Fall Time, VDS t f 23 ns Fig. 9 Turn Off Delay Time t d(off) 36 ns Rise Time, VDS t r 14 ns Fig. 10 Turn-On Energy Per Pulse E on Tj = 25 ºC, VDS = 800 V, ID = 6 A, VG = 20/-5 V, Load = 1.05 mH 138 µJ Fig. 9, 11 Turn-Off Energy Per Pulse E off 19 µJ Fig. 10, 12 Total Switching Energy E tot 157 µJ Turn-On Energy Per Pulse E on Tj = 175 ºC, VDS = 800 V, ID = 6 A, VG = 20/-5 V, Load = 1.05 mH 139 µJ Fig. 9 Turn-Off Energy Per Pulse E off 12 µJ Fig. 10 Total Switching Energy E tot 151 µJ Thermal resistance, junction - case R thJC 1.03 °C/W Fig. 17
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg6 of 10 Driving the GA06JT12-247 A: Gate Drive Theory of Operation The SJT is a current controlled transistor which requires a positive gate current for turn-on as well as to remain in on-state. An ideal gate current waveform for ultra-fast switching of the SJT, while maintaining low gate drive losses, is shown in Figure 21. Figure 21: Idealized Gate Current Waveform A:1: Gate Currents, IG,pk/-IG,pk and Voltages during Turn-On and Turn-Off An SJT is rapidly switched from its blocking state to on-state, when the necessary gate charge, Q G, for turn-on is supplied by a burst of high gate current, IG,on, until the gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged. The IG,pon pulse should ideally terminate, when the drain voltage falls to its on-state value, in order to avoid unnecessary drive losses during the steady on-state. In practice, the rise time of the I G,on pulse is affected by the parasitic inductances, L par in the TO-247 package and drive circuit. A voltage developed across the parasit ic inductance in the source path, L s, can de-bias the gate-source junction, when high drain currents begin to flow through the device. The applied gate voltage should be maintained high enough, above the V GS,ON level to counter these effects. A high negative peak current, -IG,off is recommended at the start of the turn-off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn-off. While sati sfactory turn off can be achieved with V GS = 0 V, a negative gate voltage V GS may be used in order to speed up the turn-off transition. A:2: Steady On-State After the device is turned on, I G may be advantageously lowered to I G,steady for reducing unnecessary gate drive losses. The I G,steady is determined by noting the DC current gain, hFE, of the device. The desired I G,steady is determined by the peak device junction temperature T J during operation, drain current I D, DC current gain h FE, and a 50 % safety margin to ensure operating the device in the saturation region with low on-state voltage drop by the equation: ሻ1 . 5
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg7 of 10 B: Gate Drive Implementation Examples B:1: Using the IXYS IX2204 Gate Driver The IXYS IX2204 is a dual output gate drive integrated circuit which can be used to drive an SJ T by supplying the required gate drive current IG in a low-power gate drive solution. This conf iguration features an external gate capacitor, C G, which creates the brief current peak I G,on during device turn-on and I G,off during turn-off for fast switching and an external gate resistor R G(EXT) to set the continuous gate current I G,steady required for the device to remain on. This configuration is shown in Figure 2 with further details provided below. Figure 2: Gate drive configuration using an IXYS IX2204 gate drive IC. Table 1: Recommended Component List for implementing the IX2204 based Gate Drive for the GA06JT12-247 Reference Component Description Suggested Part RG(EXT) Gate Resistance, External 2.0 Ω, 2 W CRM2512-JW-2R2ELF CG Gate Capacitance 10 nF C1812C103J1GACTU RCG Damping Resistor 1.0 Ω, 0.5 W ERJ-1TYJ1R0U DRG Silicon Schottky Diode 40 V, 2 A SS24T3G Rb BJT Base Resistor 1.0 Ω, 0.5 W ERJ-1TYJ1R0U QHA, QHB Current Boost NPN 40 V, 8 A, Silicon NPN BJT MJD44H11 QLA, QLB Current Boost PNP 40 V, 8 A, Silicon PNP BJT MJD45H11 U1 Signal Isolator Opto-Isolator –or– Transformer Isolator ACPL-4800 / ADUM3210 X1 DC/DC Converter, V GH Supply VOUT = +20 V, VIN = +12 V, 2 W, VISO = 5.2 kV MGJ2D122005SC X2 DC/DC Converter, V GL Supply V OUT = +5 V, VIN = +12 V, 3 W, VISO = 3.0 kV MEV3S1205SC X3 DC/DC Converter, V EE Supply V OUT = -5 V, VIN = +12 V, 2 W, VISO = 5.2 kV MGJ2D122005SC B:2: Voltage Supply Selection The IX2204 gate drive design requires three supply voltages V GH, V GL, and V EE (listed in Table 2) optionally supplied through DC/DC converters. During device turn-on, V GH charges the external capacitor C G thereby delivering the narrow width, high current pulse I G,on to the SJT gate and charges the SJT’s internal terminal capacitances C GD and CGS. For a given level of parasitic inductance in the gate circuit and SJT package, the rise time of I G,on is controlled by the choice of V GH and CG. During the steady on-state, V GL in combination with the internal and external gate resistances provi des a continuous gate current for the GA06JT12-247 to remain on. The V EE supply sets the gate negative during turn-off and steady off-state for faster switching and to av oid spurious turn-on which may be caused by external circuit noise. The power rating of the voltage supplies should be adequate to meet the gate drive power requirements as determined by 2ீு 2ாா ܦ
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg8 of 10 Table 2: IX2204 Gate Drive Example Component List Symbol Parameter Values Range Typical VGH Supply Voltage, Driver Output A 15 – 20 + 20.0 VGL Supply Voltage, Driver Output B 5.0 – 7.0 + 5.0 VEE Negative Supply Voltage -10 – GND - 5.0 B:3: Gate Capacitor CG Selection Figure 23: Primary gate drive circuit passive components with series gate resistance Schottky rectifier. An external gate capacitor C G connected directly to the device gate pin delivers the positive current peak I G,on during device turn-on and the negative current peak IG,off during turn-off. A low value resistor R CG is connected in series with C G to damp potential high-frequency oscillation. A high value resistor Rch in parallel with CG sets the SJT gate to a defined potential (-VEE) during steady off-state. At device turn-on, C G is pulled to V GH which produces a transient peak of gate voltage and current. This current peak rapidly charges the internal SJT CGS and CGD capacitances. A Schottky diode, D RG, in series with R G(EXT) blocks any CG induced current from draining out through RG(EXT) and ensures that all of the charge within C G flows only into the device gate, allowing for an ultra-fast device turn-on. During steady on- state, a potential of V GH - VGS = VGH – 3 V is across C G. When the device is turned off, C G is pulled to negative V EE and V GS is pulled to a transient peak of V GS,turn-off = VEE – (V GH – 3 V), this induces the negative current peak I G,off out of the gate which discharges the SJT internal capacitances. B:4: External Gate Resistor RG(EXT) Selection An external gate resistor RG(EXT) connected directly to the SJT gate pin acts to deliver a continuous current I G,steady during steady on-state. The gate current is determined by: ௌ The on-state gate-source voltage V GS(FWD) can be approximated to 3 V and the Schottky on-state voltage V Sch can be approximated to 0.3 V which simplifies the equation to: The desired IG,steady is determined by the peak device junction temperature TJ during operation, drain current ID, DC current gain β, and a 50 % safety margin to avoid operating the device in saturation. IG,steady may also be approximated from the temperature dependent on-state curves of the device in Figures Error! Reference source not found. – Error! Reference source not found., provided that a 50 % increase is given. Table 3: Passive Output Component List Symbol Parameter Values Range Typical Units CG Gate Capacitor, External 5 – 20 10 nF RCG Damping Resistor of Gate Capacitor 0.5 – 2.0 1.0 Ω Rch Charging Resistor 500 – 10k 1k Ω RG(EXT) Gate Resistor, External 0.4 – 5 2.0 Ω RG(INT-ON) Gate Resistance, Internal, On-State 0.6 – 1.5 0.9 Ω DRG Schottky Diode of Gate Resistor -- -- IG CG RG(EXT) D S DRG RG(INT) RCG VGL / VEE VGH / VEE Rch G
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg9 of 10 B:5: Optional Gate Current Boost Network An optional output totem-pole network may be attached to the IX2204 output pins as shown in Figur e 22 using either silicon BJTs (shown) or MOSFETs. This configuration allows the IX2204 to directly driv e the BJT bases or MOSFET gates and not supply the full peak and steady state gate current entering the SJT gate. The primary gate curr ent delivery device is transferred to the discrete components which have higher power dissipation ratings than the IX2204. B:6: Voltage Supply Isolation The DC/DC supply voltage converters are suggested to prov ide isolation at a minimu m of twice the working V DS on the SJT transistor during off-state to provide adequate protection to circuitry external to the gate drive ci rcuit. Suggested DC/DC converters have an is olation of 3.0 kV or greater. Alternatively, DC/DC converter galvanic isolation may be bypassed and direct connection of variable voltage supplies may be done, this may be convenient during testing and prototyping but carries risk and is not suggested for extended usage. Figure 24: Typical DC/DC converter configuration B:7: Signal Isolation The gate supply signal is suggested to be isolated to twice the working V DS on the SJT during off-state to provide adequate protection to circuitry external to the gate drive circuit. This may be done using opto or galvanic isolation techniques. B:8: Additional Features The IX2204 has additional functionality available which is unused in the given configuration. Desaturation detection and fault status monitoring may be implemented by un-grounding the DESAT, BLANK, and TRISTA TE pins and configuring them as recommended in the IX2204 datasheet, available from IXYS. Active mill er clamping is also available on other gat e drive ICs which may also be desired in s ome SJT switching applications but is not required, refer to specific gate drive IC datasheets for more information. C: Alternative Gate Drive ICs dividual product manufacturers. Table 4 features a partial list of alternative gate drive ICs which may be used for driving the GA06JT 12-247; specific product informa tion should be obtained from the individual product manufacturers. Table 4: Additional Commercial Gate Drivers Compatible with GA06JT12-247
Features
Manufacturer Part Number Optical Signal Isolation Desaturation Detection Active Miller Gate Clamping High Side Capability Number of Outputs Avago Tech. HCPL-316J – 1 Avago Tech. HCPL-322J 1 Micrel MIC4452YN – – – 1 Microsemi LX4510 – – – 1 Texas Instruments UCC27322 – – – 1 – Active Miller Gate Clamping recommended for VEE = GND switching applications as SJT and/or output BJT secondary gate discharge path.
Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg10 of 10 Package Dimensions: TO-247AB PACKAGE OUTLINE NOTE 1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER. 2. DIMENSIONS DO NOT INCLUDE END FLASH, MOLD FLASH, MATERIAL PROTRUSIONS
Revision History
Date Revision Comments Supersedes 2014/08/26 4 Updated Electric al Characteristics 2013/11/13 3 Updated Electric al Characteristics 2013/06/24 2 Updated Electric al Characteristics 2013/02/21 1 Revised Electr ical Characteristics 2012/11/30 0 Initial Release Published by GeneSiC Semiconductor, Inc.
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Aug 2014 http://www.genesicsemi.com/commercial-sic/sic-junction-transistors/ Pg 1 of 1 SPICE Model Parameters This is a secure document. Please copy this code from the SPICE model PDF file on our website (http://www.genesicsemi.com/images/products_sic/sjt/GA06JT12-247_SPICE.pdf) into LTSPICE (version 4) software for simulation of the GA06JT12-247. * MODEL OF GeneSiC Semiconductor Inc. * $Revision: 1.2 $ * $Date: 26-AUG-2014 $ * GeneSiC Semiconductor Inc. * 43670 Trade Center Place Ste. 155 * Dulles, VA 20166 * COPYRIGHT (C) 2014 GeneSiC Semiconductor Inc. * ALL RIGHTS RESERVED * These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY * OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED * TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A * PARTICULAR PURPOSE." * Models accurate up to 2 times rated drain current. .model GA06JT12 NPN + IS 5.08E-47 + ISE 1.26E-28 + EG 3.2 + BF 58.31 + BR 0.55 + IKF 200 + NF 1 + NE 1.892 + RB 5.85 + RBM 0.9 + IRB 1e-4 + RE 0.1039 + RC 0.06188 + CJC 2.73E-10 + VJC 3.04 + MJC 0.448 + CJE 6.86E-10 + VJE 2.89 + MJE 0.466 + XTI 3 + XTB -1.33 + TRC1 1.90E-2 + VCEO 1200 + ICRATING 6 + MFG GeneSiC_Semiconductor *End of GA06JT12 SPICE Model