FS6377-01

FS6377-01 AMI | Alldatasheet

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www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet I2C-bus Interface Power Down Control Post Divider C Post Divider B FS6377 PD Post Divider A CLK_A CLK_B CLK_C Reference Oscillator PLL A PLL B XOUT XIN Mux B Mux CPLL C Post Divider D CLK_DMux D Mux A SEL_CD SCL SDA ADDR OE

1.0 Features

• Three on-chip PLLs with programmable reference and feedback dividers
• Four independently programmable muxes and post dividers
• I 2C™-bus serial interface
• Programmable power-down of all PLLs and output clock drivers
• One PLL and two mux/post-divider combinations can be modified by SEL_CD input
• Tristate outputs for board testing
• 5V to 3.3V operation
• Accepts 5MHz to 27MHz crystal resonators
• Commercial (FS6377-01) and industrial (FS6377-01i) temperature ranges

2.0 Description

The FS6377 is a CMOS clock generator IC designed to minimize cost and component count in a variety of electronic systems. Three I 2C-programmable phase- locked loops feeding four programmable muxes and post dividers provide a high degree of flexibility. 1 16 SDA SEL_CD PD VSS XIN XOUT OE VDD ADDR CLK_D VSS CLK_C CLK_B VDD CLK_A SCL FS6377 16-pin (0.150") SOIC Figure 1: Pin Configuration Figure 2: Block Diagram

Table 1. Pin Descriptions

1 DIuO SDA Serial interface data input/output

2 DIu SEL_CD Selects one of two PLL C, mux D/C and post divider C/D combinations

3 DIu PD Power-down input

4 P VSS Ground

5 AI XIN Crystal oscillator input

6 AO XOUT Crystal oscillator output

7 DIu OE Output enable input

9 DIu ADDR Address select

10 DO CLK_D D clock output

11 P VSS Ground

12 DO CLK_C C clock output

13 DO CLK_B B clock output

15 DO CLK_A A clock output

16 DIu SCL Serial interface clock input

3.0 Functional Block Description

(VCO), and a feedback divider. R for the reference divider. The divided reference is then fed into the PFD. frquency appearing at the inputs of the PFD are equal. 3.1 Phase Locked Loops fVCO = fREF () .

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet

3.1.2 Feedback Divider

The feedback divider is based on a dual-modulus pre- scaler technique. The technique allows the same granularity as a fully programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also called a prescaler) is placed between the VCO and the programmable feedback divider because of the high speeds at which the VCO can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall power consumption of the divider. For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective modulus of the entire feedback divider to multiples of eight. This limitation would restrict the ability of the PLL to achieve a desired input-frequency-to-output- frequency ratio without making both the reference and feedback divider values comparatively large. A large feedback modulus means that the divided VCO frequency is relatively low, requiring a wide loop band- width to permit the low frequencies. A narrow loop band- width tuned to high frequencies is essential to minimizing jitter; therefore, divider moduli should always be as small as possible. To understand the operation, refer to Figure 4. The M- counter (with a modulus always equal to M) is cascaded with the dual-modulus prescaler. The A-counter controls the modulus of the prescaler. If the value programmed into the A-counter is A, the prescaler will be set to divide by N+1 for A prescaler outputs. Thereafter, the prescaler divides by N until the M-counter output resets the A- counter, and the cycle begins again. Note that N=8 and A and M are binary numbers. Suppose that the A-counter is programmed to zero. The modulus of the prescaler will always be fixed at N; and the entire modulus of the feedback divider becomes MxN. Next, suppose that the A-counter is programmed to a one. This causes the prescaler to switch to a divide-by-N+1 for its first divide cycle and then revert to a divide-by-N. In effect, the A-counter absorbs (or "swallows") one extra clock during the entire cycle of the feedback divider . The overall modulus is now seen to be equal to MxN+1. This example can be extended to show that the feedback divider modulus is equal to MxN+A, where A< The reference divider is designed for low phase jitter. The divider accepts the output of the reference oscillator and provides a divided-down frequency to the PFD. The reference divider is an 8-bit divider, and can be programmed for any modulus from 1 to 255 by programming the equivalent binary value. A divide-by-256 can also be achieved by programming the eight bits to 00h.

3.1.1 Reference Divider

A Counter M Counter fVCO fPD FBKDIV[10:3]FBKDIV[2:0] Figure 4: Feedback Divider

values is listed in Table 2. programmed to any value up to 2047.

3.1.3 Feedback Divider Programming

Table 2. Feedback Divider Modulus Under 56

3.2 Post Divider Muxes

lection is done via the I 2C-bus. a logic-level input on the SEL_CD pin.

3.3 Post Dividers

frequencies must be achieved exactly. reprogramming by a logic level on the SEL_CD pin.

4.0 Device Operation

significant-bit (MSB) to least-significant-bit (LSB) order .

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet

4.1 SEL_CD Input

The SEL_CD pin provides a way to alter the operation of PLL C, muxes C and D and post dividers C and D without having to reprogram the device. A logic-low on the SEL_CD pin selects the control bits with a "C1" or "D1" notation, per Table 3. A logic-high on the SEL_CD pin selects the control bits with "C2" or "D2" notation, per Table 3. Note that changing between two running frequencies us- ing the SEL_CD pin may produce glitches in the output, especially if the post-divider(s) is/are altered.

4.2 Power-Down and Output Enable

A logic-high on the PD pin powers down only those portions of the FS6377 which have their respective powerdown control bits enabled. Note that the PD pin has an internal pull-up. When a post divider is powered down, the associated output driver is forced low. When all PLLs and post dividers are powered down the crystal oscillator is also powered down. The XIN pin is forced low, and the XOUT pin is pulled high. A logic-low on the OE pin tristates all output clocks. Note that this pin has an internal pull-up.

4.3 Oscillator Overdrive

For applications where an external reference clock is provided (and the crystal oscillator is not required), the reference clock should be connected to XOUT and XIN should be left unconnected (float). For best results, make sure the reference clock signal is as jitter-free as possible, can drive a 40pF load with fast rise and fall times and can swing rail-to-rail. If the reference clock is not a rail-to-rail signal, the refer- ence must be AC coupled to XOUT through a 0.01 mF or 0.1mF cap acitor. A minimum 1V peak-to-peak signal is required to drive the internal differential oscillator buffer.

5.0 I2C-bus Control Interface

This device is a read/write slave device meeting all Philip s I 2C-bus specifications except a "general call." The bus has to be controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and STOP conditions while the device works as a slave. Both master and slave can operate as a transmitter or receiver, but the master device determines which mode is activated. A device that sends data onto the bus is defined as the transmitter , and a device receiving data as the receiver. I 2C-bus logic levels noted herein are based on a percentage of the power supply (V DD). A logic-one corresponds to a nominal voltage of VDD, while a logic-zero corresponds to ground (VSS).

5.1 Bus Conditions

Data transfer on the bus can only be initiated when the bus is not busy. During the data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is high. Changes in the data line while the clock line is high will be interpreted by the device as a START or STOP condition. The following bus conditions are defined by the I 2C-bus protocol.

5.1.1 Not Busy

Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet

5.1.2 START Data Transfer

A high to low transition of the SDA line while the SCL input is high indicates a START condition. All commands to the device must be preceded by a START condition.

5.1.3 STOP Data Transfer

A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be followed by a STOP condition.

5.1.4 Data Valid

The state of the SDA line represents valid data if the SDA line is stable for the duration of the high period of the SCL line after a START condition occurs. The data on the SDA line must be changed only during the low period of the SCL signal. There is one clock pulse per data bit. Each data transfer is initiated by a ST ART condition and terminated with a STOP condition. The number of data bytes transferred between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is overwritten to the device after the first sixteen bytes will overflow into the first register, then the second, and so on, in a first-in, first- overwritten fashion.

5.1.5 Acknowledge

When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the high period of the master acknowledge clock pulse. Setup and hold times must be taken into account. The master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been read (clocked) out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition. 5.2 I 2C-bus Operation All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The device accepts the following I2C-bus commands.

5.2.1 Slave Address

After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the device is: where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different devices to exist on the same bus. Note that every device on an I 2C-bus must have a unique address to avoid bus conflict s. The default address sets A2 to one via the pull-up on the ADDR pin. A6 A5 A4 A3 A2 A1 A0 1 0 1 1 X 0 0

5.2.2 Random Register Write Procedure

Random write operations allow the master to directly write to any register . To initiate a write procedure, the R/W bit that is transmitted af ter the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet eight bits of data into the addressed register. A final acknowledge is returned by the device, and the master generates a STOP condition. If either a STOP or a repeated START condition occurs during a register write, the data that has been transferred is ignored.

5.2.3 Random Register Read Procedure

Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic- low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master gen- erates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits the eight-bit word. The master does not acknowledge the transfer but does generate a STOP condition.

5.2.4 Sequential Register Write Procedure

Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after each write. This procedure is more efficient than the random register write if several registers must be written. To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to sixteen bytes of data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the device between each byte of data must occur before the next data byte is sent. Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the ST OP condition to occur . Registers are therefore updated at dif ferent times during a sequential register write.

5.2.5 Sequential Register Read Procedure

Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by one af ter each read. This procedure is more ef ficient than the random register read if several registers must be read. To perform a read procedure, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device that a register address will follow after the slave device acknowledges its device address. The register address is then written into the slave's address pointer. Following an acknowledge by the slave, the master generates a repeated START condition. The repeated START terminates the write procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all 16 bytes of data starting with the initial addressed register. The register address pointer will overflow if the initial register address is larger than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.

6.0 Programming Information

Table 3. Register Map

6.1 Control Bit Assignment

related to the programmed loop filter time const ant.

6.1.1 Power Down

All power-down functions are controlled by enable bit s. when the PD input is asserted.

Table 4. Power-Down Bits Table 5. Divider Control Bits Table 6. Divider Control Bits Table 7. Post Divider Modulus

Table 8. PLL Tuning Bits Table 9. Mux Select Bits

7.0 Electrical Specifications

Table 10. Absolute Maximum Ratings high-energy electrostatic discharge. Table 11. Operating Conditions device performance, functionality and reliability.

Table 12. DC Electrical Specifications

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet -200 -150 -100 -50 100 150 Output Voltage (V) Output Current (mA) MIN TYP MAX Voltage (V) Low Drive Current (mA) Voltage (V) High Drive Current (mA) 0 0 0 0 0 -87 -112 -150 0.2 9 11 12 0.5 -85 -110 -147 0.5 22 25 29 1 -83 -108 -144 0.7 29 34 40 1.5 -80 -104 -139 1 39 46 55 2 -74 -97 -131 1.2 44 52 64 2.5 -65 -88 -121 1.5 51 61 76 2.7 -61 -84 -116 1.7 55 66 83 3 -53 -77 -108 2 60 73 92 3.2 -48 -71 -102 2.2 62 77 97 3.5 -39 -62 -92 2.5 65 81 104 3.7 -32 -55 -85 2.7 65 83 108 4 -21 -44 -74 3 66 85 112 4.2 -13 -36 -65 3.5 67 87 117 4.5 0 -24 -52 4 68 88 119 4.7 -15 -43 4.5 69 89 120 5 0 -28 5 91 121 5.2 -11 5.5 123 5.5 0 The data in this table represents nominal charaterization data only. Figure 9: CLK_A, CLK_B, CLK_C, CLK_D Clock Outputs

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet 100 110 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 Output Frequency (MHz) Dynamic Current (mA) Figure 10: Dynamic Current vs. Output Frequency VDD = 5.0V; Reference Frequency = 27.00MHz; VCO Frequency = 200MHz, C L = 17pF except where noted 0 10 20 30 40 50 60 70 80 90 100 Output Frequency (MHz) Dynamic Current (mA) VDD = 3.3V; Reference Frequency = 27.00MHz; VCO Frequency = 100MHz, C L = 17pF except where noted All outputs at the same frequency All outputs at 200MHz except output under test All outputs at the same frequency, CL = OpF All outputs at 4MHz except output under test All outputs off except output under test All outputs off except output under test, C L = OpF All outputs at the same frequency All outputs at 100MHz except output under test All outputs off except output under test All outputs at the same frequency, CL = OpF All outputs at 2MHz except output under test All outputs off except output under test, C L = OpF

Table 13. AC Timing Specifications characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3 s from typical.

Table 13. AC Timing Specifications, Continued characterization data and are not currently production tested to any specific limits. Min. and Max. characterization data are ± 3 s from typical.

8.0 Package Information - For Both ‘Green’ and ‘Non-Green’

Table 15. 16-pin SOIC (0.150”) Package Dimensions Table 16. 16-pin SOIC (0.150”) Package Characteristics

9.0 Ordering Information

9.1 Device Ordering Codes

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet

10.0 Demonstration Software

Windows 3.1x/95/98-based software is available from AMI Semiconductor that illustrates the capabilities of the FS6377. The software can operate under Windows NT. Contact your local sales representative or the company directly for more information.

10.1 Software Requirements

• PC running MS Windows 3.1x or 95/98. Software runs on Windows NT in a calculation mode only.
• 1.8MB available space on hard drive C

10.2 Software Installation Instructions

At the appropriate disk drive prompt (A:\\) unzip the compressed demo files to a directory of your choice. Run setup.exe to install the software.

10.3 Demo Program Operation

Launch the fs6377.exe program. Note that the parallel port can not be accessed if your machine is running Windows NT. A warning message will appear stating: "This version of the demo program cannot communicate with the FS6377 hardware when running on a Windows NT operating system. Do you want to continue anyway, using just the calculation features of this program?" Clicking OK starts the program for calculation only. FS6377 demo hardware is no longer supported. The opening screen is shown in Figure 13. Figure 13: Opening Screen

www.amis.com FS6377-01/FS6377-01g Programmable 3-PLL Clock Generator IC Data Sheet

10.3.1 Example Programming

Type a value for the crystal resonator frequency in MHz in the reference crystal box. This frequency provides the basis for all of the PLL calculations that follow. Next, click on the PLL A box. A pop-up screen similar to Figure 14 should appear. Type in a desired output clock frequency in MHz, set the operating voltage (3.3V or 5V) and the desired maximum output frequency error. Pressing calculate solutions generates several possible divider and VCO-speed combinations. For a 100MHz output, the VCO should ideally operate at a higher frequency, and the reference and feedback dividers should be as small as possible. In this example, highlight Solution #7. Notice the VCO operates at 200MHz with a post divider of two to obt ain an optimal 50 percent duty cycle. Now choose which mux and post divider to use (that is, choose an output pin for the 100MHz output). Selecting A places the PostDiv value in Solution #7 into post divider A and switches mux A to take the output of PLL A. The PLL screen should disappear, and now the value in the PLL A box is the new VCO frequency chosen in Solution #7. Also note that mux A has been switched to PLL A and the post pivider A has the chosen 100MHz output displayed. Repeat the steps for PLL B. PLL C supports two different output frequencies depending on the setting of the SEL_CD pin. Both mux C Figure 14: PLL Screen and mux D are also affected by the logic level on the SEL_CD pin, as are the post dividers C and D. Figure 15: Post Divider Menu Click on PLL C1 to open the PLL screen. Set a desired frequency, however, now choose the post divider B as the output divider. Notice the post divider box has split in two (as shown in Figure 15). The post divider B box now shows that the divider is dependent on the setting of the SEL_CD pin for as long as mux B is the PLL C output. Clicking on post divider A reveals a pull-down menu provided to permit adjustment of the post divider value independently of the PLL screen. A typical menu is shown in Figure 15. The range of possible post divider values is also given in Table 7. The register settings are shown to the left in the screen shown in Figure 13. Clicking on a register location displays a screen shown in Figure 16. Individual bits can be poked, or the entire register value can be changed. Figure 16: Register Screen © 2004 AMI Semiconductor, Inc. AMI Semiconductor makes no warranty for the use of its products, other than those expressly contained in the company’s standard warranty contained in AMI Semiconductor’s Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of AMI Semiconductor are granted by the company in connection with the sale of AMI Semiconductor products, expressly or by implication. I 2C is a licensed trademark of Philips Electronics, N.V. AMI Semiconductor reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. GM