FS501 FORTUNE | Alldatasheet
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Technical content
Datasheet sections
- 1.1 Characteristics
- 1.2 Block Diagram of FS501
- 3.1 Package and Terminal Assignment of LQFP44
- 3.2 Terminal Description
- 4.1 Control Registers
- 4.2 Interrupt Process
- 4.3 Measure Registers
- 5.1 Bias Current Source Generator
- 5.2 Power Saving Mode
- 5.3 Switchable Power Output
- 5.4 Power Low Detector
- 6.1 Clock Generator
- 7.1 Measure Mode
- 7.2 Multiplexer and Pre-filter
- 7.3 Operation Amplifier (Op Amp)
- 7.4 Ohm Voltage Source
- 8.1 The Operation of the Delta-Sigma () Modulator ADC
- 8.2 Gain Stage Setting
- 8.3 Digital Filter
- 8.4 Reading and Calculating of Digital-to-Analog Converter
- 8.5 The Conversion of the Digital Codes and Equivalent Voltage
- 8.6 Other Control Setting
- 9.1 Application Circuit of Electronics Scale (Using Internal OP)
- 9.2 Application Circuit of Electronics Scale (Using External OP)
REV. 4.1 FS501-DS-41_EN MAY 2014 Datasheet FS501 18-bit ADC with two low noise OPAMPs FORTUNE' Properties For Reference Only
Fortune Semiconductor Corporation 富晶電子股份有限公司 Danshui Town, Taipei County 251, Taiwan Tel.：886-2-28094742 Fax：886-2-28094874 www.ic-fortune.com This manual contains new product information. Fortune Semiconductor Corporation reserves the rights to modify the product specification without further notice. No liability is assumed b y Fortune Semiconductor Corporation as a result of the use of this product. No rights under any patent accompany the sale of the product. FORTUNE' Properties For Reference Only
FORTUNE' Properties For Reference Only
- Introduction to FS501 Chip
the reference voltages are fully differential. This mechanism can measure the fully differential small signals. The application includes electronic scale and infrared ear thermometer. 12-b/325Hz resolution output. Table 1. FS501 IC Chip
- Embed High resolution ADC
- Five 18-bit high resolution outputs per second
- 325 12-bit outputs per second
- Embed two op amps
- Embed a voltage regulator, input: 5 V, outputs: 2.5 V and 4V
- Chip current is less than 1.2mA
- With power saving mode
- 50/60 Hz noise distortion
- Embed crystal oscillation circuits
- Standard 4-bit parallel port interface, can be directly connected to microprocessor I/O ports
- With four programmable ADC direct input channels FORTUNE' Properties For Reference Only
M U X O P A m p s Modulator Digital Filter Digital Interface Control RegistorsOscillator Regulator Functional Network RST_ IRQO XTALOXTALI CS_ALEWR_RD_AD0AD1AD2AD3 VCCVCCRGNDR Low Battery Detector VSS TENM HUNK SMV SDB ADRF ACB ACA RCTP RCTN RCTO AX2 AX3 AX4 AX5 FTA FTB FTC VCCS VDDSVDDVDDA SGND AGND VSSD VBAT 2. Electrical Characteristics
- (VDD = 6V, VSS = 0V, TA=+25℃, unless otherwise indicated) PARAMETER TEST CONDITIONS MIN. TYP . MAX. UNITS Analog-to-Digital Converter Zero Input Reading VIN=0V, 500mV Scale -1 0 1 Counts Zero Reading Drift VIN=0V, 0℃<TA<+70℃ 0 1 μ V/℃ Linearity (Max. deviation from best straight line fit) 500mV Scale -2 0 2 Counts Input Common -Mode Rejection Ratio VCM=±1V, VIN=0V, 500mV Scale 120 μ V/V Input Common -Mode Voltage Range VIN=0V, 500mV Scale, ±12 Counts -1 1 V Noise (p-p Value not Exceeding 95% of Time) VIN=0V, 500mV Scale 0 1 Counts Rollover Error (Difference in reading for equal positive and negative inputs near Full Scale) -VIN=+VIN=500.00mV 0 1 5 Counts Input Leakage Current VIN=0V 1 10 pA Scale Factor Temperature Coefficient VIN=500.00mV, 0℃<TA<+70℃ 7.5 ppm/℃ Current Consumption 660 800 A FORTUNE' Properties For Reference Only
PARAMETER TEST CONDITIONS MIN. TYP . MAX. UNITS Instrumentation Amplifier @ Gain = 30, Vref=0.5V, TA=25℃ Input Offset Voltage without AZ Rs<100 20 V Input Offset Voltage with AZ Rs<100 0 3 V Input Offset Drift without AZ -20℃<TA<+50℃ 200 nV/℃ Input Offset Drift with AZ -20℃<TA<+50℃ 20 nV/℃ Input Referred Noise Rs=100 0.3 0.6 Vpp Input Bias Current [2] 100 300 pA Current Consumption 180 220 A Regulator Analog Ground Source Capability ΔVO=-0.1V 15 20 μA Analog Ground Sink Capability ΔVO=0.1V 3 5 mA VBAT 5.5 9 V Low Battery Detection Voltage 6.7 6.8 6.9 V VDD Operating Current VIN=0, 500mV Scale 960 μA Sleep Current 10 30 μA Parasitic Capacitance 10 15 pF Digital Output High IOUT=-1mA 5 V Digital Output Low IOUT=1mA 25 mV Digital Input High V Digital Input Low V Temperature Range Operating Temperature Range -40 25 85 C Storage Temperature Range -65 25 150 C These parameters are guaranteed by design and are tested only by sampling while mass production. While a voltage source with large output impedance is measured by an instrumentation amplifier having input bias current, an additional input offset voltage will be introduced. However, this offset voltage could be cancelled by mirrored offset cancellation technique. FORTUNE' Properties For Reference Only
- Package and Terminal Assignments FS501F/LQ44 VCC RST_ FTC TENM HUNK FTA FTB SGND AGND VDDA SMV SDB ADRF VSSA REFH CSFB ACB ACA RCTP RCTN RCTO AX3 AX4AX5 AX2 GNDR VDDS VDD VCCR VCCS VCC VBAT VSSD XTALI XTALO IRQO AD<3> AD<2> AD<1> AD<0> RD_ WR_ ALE CS_ (0,0) Pad opening : 90um Chip size : 3.578mm X 3.146mm h ttp://www.fs c .c o m.tw X Y 123456789101112 23 24 25 26 27 28 29 30 31 32 33 34 35 36 4344 FORTUNE' Properties For Reference Only
Dice size： 3.578*3.146 mm Pad No. Name X[mm] Y[mm] Pad No. Name X[mm] Y[mm] 1 XTALO 2.675 2.937 31 RCTO 1.828 0.209 2 IRQO 2.340 2.937 32 AX3 2.290 0.209 3 AD<3> 2.120 2.937 33 AX4 2.444 0.209 4 AD<2> 1.900 2.937 34 AX5 2.753 0.209 5 AD<1> 1.679 2.937 35 AX2 2.906 0.209 6 AD<0> 1.459 2.937 36 GNDR 3.282 0.209 7 RD_ 1.255 2.937 37 VDDS 3.368 0.961 8 WR_ 1.051 2.937 38 VDDS 3.368 1.110 9 ALE 0.847 2.937 39 VCCR 3.368 1.272 10 CS_ 0.643 2.937 40 VCCS 3.368 1.503 11 VCC 0.496 2.937 41 VCC 3.368 1.674 12 RST_ 0.349 2.937 41 VCC 3.368 1.845 13 FTC 0.209 2.468 41 VCC 3.368 2.016 14 TENM 0.209 2.313 41 VCC 3.368 2.761 15 HUNK 0.209 2.006 42 VBAT 3.368 2.952 16 FTA 0.209 1.544 43 VSSD 3.046 2.937 17 FTB 0.209 1.390 44 XTAL1 2.899 2.937 18 SGND 0.209 1.236 19 AGND 0.209 1.082 20 VDDA 0.209 0.935 21 SMV 0.209 0.788 22 SDB 0.209 0.480 23 ADRF 0.209 0.325 24 VSSA 0.449 0.209 25 REFH 0.597 0.209 26 CSFB 0.750 0.209 27 ACB 1.213 0.209 28 ACA 1.366 0.209 29 RCTP 1.521 0.209 30 RCTN 1.674 0.209 FORTUNE' Properties For Reference Only
SOP 40 LQ 44 Attribute Name Function 1 18 AI SGND Signal Ground 2 19 API AGND Power Supply Ground for Analog Signal (+2.5 V) 3 20 API VDDA Power Supply VDD for Analog Signal（+5 V） 4 21 AIO SMV Input of Analog Signal Na 22 AIO SDB Reference Resistance Bottom Input for the (Thermistor) Resistance Measuring 5 23 AI ADRF Input Reference Voltage of the ADC 6 24 API VSSA Power Supply VSS (0V) of the Analog Signal 7 25 AI REFH Reference Voltage Input of the Embedded Analog Power Source 8 26 AIO CSFB Current Source Feedback 9-10 27-28 AIO ACB, ACA ACBUF Op Amp Terminals 11-12 29-30 AIO RCTP, RCTN Inputs of RCTOP Op Amp 13 31 AIO RCTO Output of RCTOP Op Amp 14 32 AIO AX3 Programmable Input Channel 3 Na 33 AIO AX4 Programmable Input Channel 4 Na 34 AIO AX5 Programmable Input Channel 5 15 35 AIO AX2 Programmable Input Channel 2 16 36 APO GNDR Analog Ground Output of the Embedded Volt age Regulator (+2.5 V) 17 37 PO VDDS VDD Output Via Internal Switches 18 38 PI VDD VDD (+5V) Input for Voltage Regulator 19 39 DPO VCCR VCC (+5 V) Output from the Voltage Regulator 20 40 DPO VCCS VCC Output Via Internal Switches 21-22 41 DPI VCC Power Supply VCC (4~5V) for Digital Signal Na 42 AI VBAT Input of Power Low Detector 23 Na DO OSCO Crystal Oscillation Output. It can be used by the microprocessor directly. 24 43 DPI VSSD VSS (0V) for Digital Signal 25-26 44-1 DIO XTALI, XTALO Crystal Oscillator Inputs 27 2 DO IRQO Interrupt Output Signal for Measure Events 28-31 3-6 DIO AD<3:0> Data Input/Output of the Microprocessor Interface 32 7 DI RD_ Read Terminal of the Microprocessor (Active Low Oriented) 33 8 DI WR_ Write Terminal of the Microprocessor (Active Low Oriented) 34 9 DI ALE Address Latch Enable of the Microprocessor. When it is high, AD<3:0> is the address bus. 35 10 DI CS_ Chip Select of the Microprocessor Interface (Active Low Oriented) 36 11 DPI VCC VCC (+4V) for Digital Signal 37 12 DI RST_ Reset. It is low to reset all the internal registers to zero. 38 13 AIO FTC Terminal of the Pre RC Filter Na 14-15 AIO TENM, HUNK Reference Resistance Terminals for the (Thermistor) Resistance Measuring 39-40 16-17 AIO FTA, FTB Terminals of the Pre RC Filter Notations: 1. D stands for Digital. 2. A stands for Analog 3. P stands for Power. 4. stands for Output. 5. I stands for Input. 6. For example: DIO means “Digital Input/Output” FORTUNE' Properties For Reference Only
- Microprocessor Interfaces
to check the status of the chip. Table 2. The Address of Control Registers and Interrupt Registers.
05 ADG<7:0> ENAD
06 SETADC
09 INTRG<7:0>
addresses, 00~09. The functions are briefly described in Table 3. Table 3. Brief Description of the Function of FS501 Registers high speed TAP and high resolution TAP setting of the digital filter.
The read/write timing sequences of all the control registers are shown in Fig. 1. The length of the data is 8-bit wide, therefore, it needs to read and write consecutively twice (MSB 4 bits first then LSB 4 bits). Otherwise, the activation of next ALE will reset the CYCNTR (cycle counter) and it will start from the MSB 4 bits of next instruction. ALE RD_ CS_ Address, 00~08 DATA<7:4> READ CONTROL REGISTER CYCLE DATA<3:0> AD<3:0> ALE WR_ CS_ Address, 00~08 DATA<7:4> WRITE CONTROL REGISTER CYCLE DATA<3:0> Next Address CYCNTR 0 1 2 CYCNTR 0 1 2 AD<3:0> Fig. 1. The Read/Write Timing Diagram of the Control Registers Interrupt Process If new data are converted by the ADC and are read by the interface of the microprocessor, that is new event occurred, this chip activates an interrupt signal through IRQO to the microprocessor to request for accessing. When the microprocessor receives a negative edge-triggered interrupt signal, the measure register of FS501 has measured new data. The interrupt of the measured event is triggered by signal INTEN (as shown in Table 4). Table 4. Interrupt Status Register INSTA INSTA<1> INSTA<0> Event High speed low resolution AD conversion High resolution low speed AD conversion INTEN INTEN<1> INTEN<0> Function Corresponding IRQO enable Corresponding IRQO enable When the microprocessor is reading data from the measure register, the corresponding interrupt bit is cleared to 0 to wait for next new measured data. Interrupt status register, INSTA<0>, is a read-only register. Whereas interrupt enable register, INTEN<0>, is a read/write register. The read/write timing sequences of these two registers are the same as that of control registers (as shown in Fig. 1). FORTUNE' Properties For Reference Only
(1) When new data appear in the enabled measure register, IRQO is cleared to 0 and kept in 0. (3) After the read of interrupt status register, IRQO is set to 1. the interrupt status register again. interrupt enable register. The interrupt enable register only affects the IRQO output. Table 5. Measure Register (read/write cycle counter) to 0. The read count of the measure register is shown in the last column of Table 5. ADC is 83.3kHz; then the first read cycle for reading the measure register should be greater than 12us.
- Voltage Regulator FS501 Regulator 309K 800K GNDR VSS VDD S81250 OUTIN COM VCCR 20 uF 20 uF VDD VSS 9V Battery VBAT AGND 20 uF VCC VDD ENGNDR_ REFH Fig. 3. Block Diagram of FS501 Voltage Regulator The block diagram of FS501 voltage regulator is shown in Fig. 3. In the circuit, we need a low cost voltage regulator, S81250, to regulate the battery voltage (more than 6.8V) to 6.4V VDD. The VDD power supply is used for: (1) analog circuit power supply, (2) as the reference voltage of the voltage regulator. In Fig. 3, voltages VDD and REFH are used as reference voltages to generate VCCR, GNDR, and VSS for FS501. If VSS is set to 0V, then VCCR and GNDR will be regulated to 5V and 3.2V respectively. Users can select the power supply source for FS501 by themselves, either generated internally or supplied externally. The power sources of analog circuits of FS501 are supported through terminals of VDDA, AGND, and VSSA. Therefore, we can directly connect the voltage regulator outputs of VCCR, GNDR, and VSS to terminals of VCC, AGND, and VSSA respectively. If the user can find stable power source externally, the power sources can be applied to terminals of VCC, AGND, and VSSA directly instead of internal power sources of VCCR and GNDR. Most of the power consumption of the analog circuit is due to the static current. In FS501 the current of analog part is designed to be less than 1mA, and the current of digital part is less than 0.5mA . Bias Current Source Generator FS501 Current Bias AGND ENGNDR_ CSFB VSS Current Bias 3uA412K VDD LM385/1.23V 82K AGND Fig. 4. FS501 Bias Current Source Generator The bias current source generator as shown in Fig. 4 generates the bias current for all the analog circuits of FS501. If the embedded op amp works, CSFB will be pulled to AGND by the feedback; there are 1.2V in resistor 412K, and 3uA bias current can be obtained. If the value of the 412K-resistor is reduced, the working current of the chip will be increased, and some of the specs can be improved. FORTUNE' Properties For Reference Only
Table 6. Setting of the Power Saving Mode
Fig. 6. Power Low Detector Power low detector is shown in Fig. 6. LBS is the dividing voltage of VBAT and is fed into the input of the power low detector. The output voltage, LBO, of the power low detector can detect whether the dividing voltage of VBAT is less than AGND. If it is less than AGND, LBO is high and the user has to replace the battery. Before reading LBO, we have to set ENLBS to Hi (high), and pull ENLBS to low after approximately 0.1ms; we can then read LBO. By the ADC multiplexer, the LBS voltage can be selected by the ADC, and by Equation 1 the LBS voltage can be found. Equation 2 LBSBAT VV 2.2 In power saving mode, we can set ENGDR_ (MISC<1>) to high to turn off GNDR to save power consumption. 6. Clock Generator Clock Generator
4 MHz
ENXTL_ ENOSCO_ FS FSDIV Fig. 7. Clock Generator The block diagram of the clock generator is shown in Fig. 7. We connect a 4MHz crystal oscillator to the clock generator to generate a 4MHz clock frequency. A frequency divider is used to divide the clock signal to generate a signal FS, and the ADC uses this FS signal to do data conversion. FS is controlled by ENXTAL_ and FORTUNE' Properties For Reference Only
FSDIV; the truth table is shown in Table 7. Table 7. Truth Table of the FS Generation ENXTAL_ FSDIV FS L L 166.67 kHz L H 83.33 kHz H X 0, (L) When ENOSCO_=0, the output is a fixed 2.000 MHz square wave. When ENOSCO_=1, the output is 0, and can save VCC power consumption. FORTUNE' Properties For Reference Only
- Function Network SMV ACB ACBUF ACA ACDIV ACDIV ACEN BPACBF RCTOP 12K RCTN RCTP RCTO INHMUX SMV SDV NC SGND SDB NC AX5 FTIN SINH<3:0> INLMUX SGND SCV SDV INL SINL<2:0> VRHMUX ADRF SCV SMV VRH SRFH<1:0> VRLMUX AGND SCV SDB VRL SRFL<2:0> CMPHMUX SMV SDV NC CMPH SCMPH<3:0> ADRF AX1 AX2 RCTE N FTR FTR FTA FTB BPFTR FTC INH INL VRH VRL SGND ADRF AX2 AX3 SMV SGND ADRF AX2 AX3 ACBO CMP1 CMPEN1 AGND CMP1 HUNK TENM tenm <0> tenm <1> hunk <0> hunk <1> hunk <2> tenm <1> OSRMUX AX5 Vrefh OSRC osr osr osr OSRC SOSR1:0 (VDD) OSRO SMV AX3 AX4 AX3 NC SDB AX2 AX3 AX4 ADRF ACBO CMPH AX1 AX2 AX3 AX4 LBS SCV SDV Fig. 8. Function Network of FS501 The function network is shown in Fig. 8. There are multiplexers, op amps, and comparators. Control registers can set multiplexers, INHMUX, INLMUX, VRHMUX, VRLMUX, and SCMPHMUX, to select working channels. The op amps, ACBUF and RCTOP , can be used as the amplifier or input voltage buffer. OSRC is the embedded Ohm voltage source for resistance measuring. The comparator is to compare the input signal with AGND, and the output can be read through the register. FORTUNE' Properties For Reference Only
FS501 has voltage measuring and resistance measuring modes, and the modes are controlled by 00F register MODE3:0. When MODE=0, it is in the voltage measuring mode. The measured voltage can be either directly fed from INHMUX to ADC, or fed through the ACBUF amplifier and then fed to the ADC. ON CHIPOFF CHIP OSRC Rth HUNK TENM Rref2 Rref1 OSR OSR OSREN AGND SGND hunk<1> OSRC hunk<0> tenm<0> SDB INL INH VRL VRH hunk<2> tenm<1> tenm<1> Fig. 9. Resistance Measuring Circuit When MODE=1, it is in the resistance measuring mode. The circuit is shown in Fig. 9. Suppose that the reference resistance is Rref, and the measured resistance to be Rth. The measuring equation is as follows. Equation 3 out VRLVRH INLINH refth DGVV VVRR Where D out is the ADC output, and thereafter the resistance can be measured. The control setting of the resistance measuring circuit is shown in Table 8. Table 8. Setup Table of the Resistance Measuring Circuit Range Mode MODE3:0 HUNK hunk2:0 tenm1:0 HUNK 1001 1 111 00 TENM 1001 0 000 11 FORTUNE' Properties For Reference Only
control registers and the selections are shown in Tables 9, 10, 11, and 12. Table 9. Setting of INH Multiplexer Table 10. Setting of INL Multiplexer Table 11. Setting of VRH Multiplexer Table 12. Setting of VRL Multiplexer Table 13. Setting of CMPH Multiplexer Op amp of ACBUF, control switch of ACDIV and the external resistors can form a gain loop.
the output is in high impedance. the op amp is determined by the external resistance. can be directly set by the control register. chip driving terminator. Therefore, the load affects the effective load voltage. Table 14. Control Values of the Ohm Voltage Source
- Analog to Digital Converter (ADC) The Operation of the Delta-Sigma () Modulator ADC This high resolution ADC is designed by the technology of delta-sigma () modulator. The continuous analog signals are sampled by a very high sampling rate that is much higher than the bandwidth of the input signal. The delta-sigma modulator converts the input signal to a series of 1-bit codes. These 1-bit codes are then fed to the digital filter to filter out the high frequency quantization noise to find high resolution digital outputs. It can be used in the high resolution digital multimeters. This kind of ADC quantizes one bit in the analog part, therefore, it has very good linearity. Because it is in a fully differential configuration, the common mode rejection ratio (CMRR) is very high and can reduce the common mode signals effectively. ANALO GINTE GRATO R DIGITAL LOW P ASS DECIM ATION FILTER COM P ARATOR ANALO GINPU T Vin Dout C Fig. 10. The Symbolic Diagram of the Delta-Sigma Analog-to-Digital Converter The symbolic diagram of the delta-sigma ADC is shown in Fig. 10. It consists of an analog subtractor, an integrator, a comparator, a 1-bit digital-to -analog converter (DAC), and a low-pass digital filter. The analog signals are continuously sampled and are subtracted by the expected voltage. The difference of the signals is fed into the integrator, and then the signal is compared with a reference voltage to find a digital output. This digital output is converted by the 1-bit DAC to become an analog signal (+ Vref or -Vref) and then negatively fed back into the integrator. Due to the infinitive DC gain of the integrator, if the change of the input signal is much slower than the sampling speed, the average voltage obtained by the delta-sigma modulator will be very close to the input signal. In some resolution they can be treated to be the same, therefore, the 1-bit output data from the comparator are equivalent to the Vref analog signal values. The digital filter then decimates the 1-bit data to get a very high resolution digital code. Gain Stage Setting 0.5 0.5 0.25 0.1 ADG<0> ADG<1> ADG<2> ADG<3> VIN to ADC signal input 1.0 0.25 ADG<4> ADG<5> VREF to ADC reference input a b c d x y Fig. 11. Diagram of FS501Gain Stage Setting There are four different gain paths to the input of the FS501 ADC, and they are controlled by control register ADG<3:0>; the block diagram is shown in Fig. 11. Two different gain paths control the input reference voltage, and they are controlled by control register ADG<5:4>. The gains shown here are not accurate. The accurate gains can be found by careful calibration. FORTUNE' Properties For Reference Only
measuring applications. Table 15 shows values of ADG<5:0> for three frequently used applications. Table 15. FS501 ADC Typical Gain Setting accurate gains for the reference voltages and input voltages can be found by careful calibration.
In Fig. 10, the 1-bit output of the comparator should be fed to the digital low pass filter to do decimation to find the high resolution multiple-bit digital output. The transfer function of the FS501 digital filter is: Equation 5 H f N N f f f f S S sin sin Where N is TAP of the digital filter. Suppose the sampling rate of the ADC is 166KHz, the TAP of the digital filter is 16600. We can find the frequency response diagram of the digital filter as shown in Fig. 12. The first zero is at: Equation 6 f f NZ S 166000 Hz 16600 10 Hz Fig. 12. The Frequency Response Diagram of FS501 Digital Filter The zero points fall at multiples of 10Hz. The digital filter will filter out all the signals near the zero points. From Fig. 12, we can find that the noises at 50Hz and 60Hz are suppressed very well. If the sampling rate is 83KHz and the TAP of the filter is 16600, the first zero-frequency is at 5Hz. There are two programmable TAP digital filters in FS970x, and they are COMB1 and COMB2; the outputs are SUM1 and SUM2 respectively. The TAP of COMB1 is higher than that of COMB2; therefore COMB1 is used for high resolution measuring, and COMB2 is used for low resolution but high speed measuring. The TAP’s of COMB1 and COMB2 are programmable, and can be set by TPS1 and TPS2 respectively; they are shown in Table 16. The first zero-frequency is computed by taking 83.3 kHz as sampling frequency and applies Equation 5. At TPS1=TPS2=11, the resolutions of high speed and low speed are 18-bit and 12-bit respectively. The resolutions for other conditions are according to the actual measuring. 0 20 40 60 80 100 -200 -150 -100 -50 Hz dB FORTUNE' Properties For Reference Only
Table 16. TAP Setting of the Comb Digital Filter and the First Zero Frequency [FS=83.3 kHz]
8.4.1 ADC Output SUM1
Equation 1. This mode is suitable for high resolution measurement.
The Conversion of the Digital Codes and Equivalent Voltage The output of the FS501 ADC is SUM1<23:0>, which is a 24- bit 2’s complement number. SUM1<23> is the sign bit; 0 represents a positive number, and 1 represents a negative number. The decimal point lies in between SUM1<22> and SUM1<21>. If SUM1<23:0>=0010_1000_0000_0000_0000_0000, the equivalent floating point number is: Equation 7 625.0125.05.0 0000_0000_0000_0000_1000_10.00 2254321 SUM1 If SUM1<23:0>=1101_1111_1111_1111_1111_1111, the equivalent floating point number is: 5000002384.0 )0001_0000_0000_0000_0000_10.00( 1111_1111_1111_1111_1111_01.11 224321 SUM1 From Equation 1, if gain 'G equals 1 and reference voltage refV =1.00000V, the value of SUM1, 0010_1000_0000_0000_0000_0000, can be used to calculate the measured voltage as: V62500.0625.01 V00000.1 ref x D G Vv If SUM1=1101_1111_1111_1111_1111_1111, the measured voltage can be calculated: V50000.05000002384.01 V00000.1 ref x D G Vv However, due to the manufacture process drift 'G is not exactly equal to 1, and there will be around %1 offset. Similarly the reference voltage source and resistors may affect the reference voltage refV , and make refV not to be exact 1.00000V. Therefore, we have to calibrate the ADC. Other Control Setting ENAD(ADG<7>) is the enable control signal for the ADC. It is 1 to enable the ADC; it is 0 to turn off the ADC and can save power. CPVR(ADG<6>) is the enhancement mode for resistance measuring. It is set to 1 to improve the linearity when measuring resistance. FORTUNE' Properties For Reference Only
- Application Information Application Circuit of Electronics Scale (Using Internal OP) 825K590K 27nF 250K 90K FS501F/LQ44 VCC RST_ FTC TENM HUNK FTA FTB SGND AGND VDDA SMV SDB ADRF VSSA REFH CSFB ACB ACA RCTP RCTN RCTO AX3 AX4AX5 AX2 GNDR VDDS VDD VCCR VCCS VCC VBAT VSSD XTALI XTALO IRQO AD<3> AD<2> AD<1> AD<0> RD_ WR_ ALE CS_ VCC 4.00MHz Micro-Processor VSS SGND AGND VDDS VDD VCC VCCS VCC VSS 500K 10nF VSS Rth AGND 27nF AGND VDDS VSS 10uF VCC VSS 10uF VDD VSS 10uF VDD AGND 10uF VSS AGND Thermistor VOUT S-81250 VIN AGND VDD VDD 350 350 350 350 VSS 3K 90K VDDS 2.25K5002.25K VSSVDDS FORTUNE' Properties For Reference Only
Application Circuit of Electronics Scale (Using External OP) 825K590K 27nF 250K FS501F/LQ44 VCC RST_ FTC TENM HUNK FTA FTB SGND AGND VDDA SMV SDB ADRF VSSA REFH CSFB ACB ACA RCTP RCTN RCTO AX3 AX4AX5 AX2 GNDR VDDS VDD VCCR VCCS VCC VBAT VSSD XTALI XTALO IRQO AD<3> AD<2> AD<1> AD<0> RD_ WR_ ALE CS_ VCC 4.00MHz M icro-Processor VSS SGND AGND VDDS VDD VCC VCCS VCC VSS 500K 10nF VSS Rth AGND 27nF AGND VDDS VSS 10uF VCC VSS 10uF VDD VSS 10uF VDD AGND 10uF VSS AGND Therm istor VOUT S-81250 VIN AGND VDD VDD 350 350 350 350 VSS 3K 90K VDDS 2.25K5002.25K VSSVDDS OP07/177 90K3K FORTUNE' Properties For Reference Only
- IC Dimension Max. Rated Value FORTUNE' Properties For Reference Only
FORTUNE' Properties For Reference Only
- Ordering Information Product Number Description Package Type FS501F Die form (44 pins) FS501F 44-pin LQFP (Not Pb free package) FS501F-PCD 44-pin LQFP Pb free package part number. 44-pin LQFP (Pb free package) 12. Revision History Version Date Page Description 3.8 2004/04/16 30 Reformat and correct the contents Add ordering information. 3.9 2005/08/02 32 Correct 1 low noise OPAMP to two low noise OPAMPs. Revise ordering information. Add Pb free package part number. Add Revision History. 4.0 2006/12/21 All Revise datasheet format 4.1 2014/05/22 2 Revised company address FORTUNE' Properties For Reference Only