FM28V202A-TG

FM28V202A CYPRESS | Alldatasheet

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■ 2-Mbit ferroelectric random access memory (F-RAM) logically organized as 128 K × 16 ❐ Configurable as 256 K × 8 using UB and LB ❐ High-endurance 100 trillion (1014) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Page mode operation to 30-ns cycle time ❐ Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 128 K × 16 SRAM pinout ❐ 60-ns access time, 90-ns cycle time ■ Advanced features ❐ Software-programmable block write-protect ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ■ Low power consumption ❐ Active current 7 mA (typ) ❐ Standby current 120 A (typ) ■ Low-voltage operation: VDD = 2.0 V to 3.6 V ■ Industrial temperature: –40 C to +85 C ■ 44-pin thin small outline package (TSOP) Type II ■ Restriction of hazardous substances (RoHS) compliant Functional Overview The FM28V202A is a 128 K × 16 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. The FM28V202A operation is si milar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Read cycles may be triggered by CE or simply by changing the address and write cycles may be triggered by CE or WE . The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM28V202A ideal for nonvolatile memory applications requiring frequent or rapid writes. The device is available in a 400-mil, 44-pin TSOP-II surface mount package. Device specifications are guaranteed over the industrial temperature range –40 °C to +85 °C. For a complete list of related documentation, click here. Address Latch & Write Protect CE Control Logic WE Block & Row Decoder A I/O Latch & Bus Driver OE DQ

16 K x 16 block 16 K x 16 block

A . . . Column Decoder . . . UB, LB ZZ 16-0 16-2 A1-0 15-0 Logic Block Diagram

Figure 1. 44-pin TSOP II pinout address lines A1–A0 may be used for page mode read and write operations. DQ0–DQ15 Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array. available. Deasserting OE HIGH tristates the DQ pins. UB Input Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH. LB Input Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH. condition. ZZ must be HIGH for a normal read/write operation. This pin must be tied to VDD if not used. VSS Ground Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device. NC No connect No connect. This pin is not connected to the die.

Document Number: 001-90309 Rev. *G Page 4 of 22 Device Operation The FM28V202A is a word wide F-RAM memory logically organized as 131,072 × 16 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation, which provides high-speed access to addresses within a page (row). Access to a different page requires that either CE transitions LOW or the upper address (A16–A2) changes. See the Functional Truth Table on page 17 for a complete description of read and write modes. Memory Operation Users access 131,072 memory locations, each with 16 data bits through a parallel interface. The F-RAM array is organized as eight blocks, each having 4096 rows. Each row has four column locations, which allow fast access in page mode operation. When an initial address is latched by the falling edge of CE subsequent column locations may be accessed without the need to toggle CE . When CE is deasserted HIGH, a pre-charge operation begins. Writes occur immediately at the end of the access with no delay. The WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to F-RAM called NoDelay writes. Read Operation A read operation begins on the falling edge of CE . The falling edge of CE causes the address to be latched and starts a memory read cycle if WE is HIGH. Data becomes available on the bus after the access time is met. When the address is latched and the access completed, a new access to a random location (different row) may begin while CE is still LOW. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM28V202A's CE -initiated access time is faster than the address access time. The FM28V202A will drive the data bus when OE and at least one of the byte enables (UB , LB) is asserted LOW. The upper data byte is driven when UB is LOW, and the lower data byte is driven when LB is LOW. If OE is asserted after the memory access time is met, the data bus will be driven with valid data. If OE is asserted before completing the memory access, the data bus will not be driven until valid dat a is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven to the bus. When OE is deasserted HIGH, the data bus will remain in a HI-Z state. Write Operation In the FM28V202A, writes occur in the same interval as reads. The FM28V202A supports both CE and WE controlled write cycles. In both case s, the address A 16–A2 is latched on the falling edge of CE. In a CE -controlled write, the WE signal is asserted before beginning the memory cycle. That is, WE is LOW when CE falls. In this case, the device begins the memory cycle as a write. The FM28V202A will not drive the data bus regardless of the state of OE as long as WE is LOW. Input data must be valid when CE is deasserted HIGH. In a WE -controlled write, the memory cycle begins on the falling edge of CE. The WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if OE is LOW; however, it will be HI-Z when WE is asserted LOW. The CE- and WE-controlled write timing cases are shown in the Switching Waveforms on page 13. Write access to the array begins on the falling edge of WE after the memory cycle is initiated. The write access terminates on the rising edge of WE or CE , whichever comes first. A valid write operation requires the user to meet the access time specification before deasserting WE or CE. The data setup time indicates the interval during which data cannot change before the end of the write access (rising edge of WE or CE). Unlike other nonvolatile memory technologies, there is no write delay with F-RAM. Because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The F-RAM array is organized as eight blocks, each having 4096 rows. Each row has four column-address locations. Address inputs A1–A0 define the column address to be accessed. An access can start on any column address, and other column locations may be accessed without the need to toggle the CE pin. For fast access reads, after the first data byte is driven to the bus, the column address inputs A 1–A0 may be changed to a new value. A new data byte is then driven to the DQ pins no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. While CE is LOW, a subsequent write pulse along with a new column address provides a page mode write access. Pre-charge Operation The pre-charge operation is an in ternal condition in which the memory state is prepared fo r a new access. Pre-charge is user-initiated by driving the CE signal HIGH. It must remain HIGH for at least the minimum pre-charge time, tPC. Pre-charge is also activated by changing the upper addresses, A16–A2. The current row is first closed before accessing the new row. The device automatically detects an upper order address change, which starts a pre-charge operation. The new address is latched and the new read data is valid within the t AA address access time; see Figure 8 on page 13. A similar sequence occurs for write cycles; see Figure 13 on page 14 . The rate at which random addresses can be issued is tRC and tWC, respectively. Sleep Mode The device incorporates a sleep mode of operation, which allows the user to achieve the lowest power supply current condition. It enters a low-power sleep mode by asserting the ZZ pin LOW. Read and write operations must complete before the ZZ pin going LOW. When ZZ is LOW, all pins are ignored except the ZZ pin. When ZZ is deasserted HIGH, there is some time delay (tZZEX) before the user can access the device. If sleep mode is not used, the ZZ pin must be tied to VDD.

Figure 3. Write-Protect State Machine

to toggle for each new address. CE may remain LOW indefinitely. write-protect is not available if the chip enable pin is hard-wired. CE signal should be active (LOW) only during memory accesses. device draws no more than the maximum standby current, ISB. specifications. Refer to the FM21L16 datasheet. whether a single 16-bit word or all four words are read or written.

33 MHz due to initial read latency and an extra clock cycle to

loop causes each byte to experience only one endurance cycle. at a 33-MHz system bus clock rate. Figure 6. Use of Pull-up Resistor on WE Figure 7. FM28V202A Wired as 256 K x 8 Table 2. Time to Reach 100 Trillion Cycles for Repeating

Document Number: 001-90309 Rev. *G Page 9 of 22 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Maximum accumulated storage time Ambient temperature Voltage applied to outputs Transient voltage (< 20 ns) on Package power dissipation Surface mount Pb soldering DC output current (1 output at a time, 1s duration) .... 15 mA Static discharge voltage Operating Range Range Ambient Temperature (TA) VDD Industrial –40 C to +85 C 2.0 V to 3.6 V Over the Operating Range Parameter Description Test Conditions Min Typ [2] Max Unit VDD Power supply voltage 2.0 3.3 3.6 V IDD VDD supply current V DD = 3.6 V, CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2 V or VDD – 0.2 V), all DQ pins unloaded. –7 1 2 m A ISB Standby current V DD = 3.6 V, CE at VDD, All other pins are static and at CMOS levels (0.2 V or VDD – 0.2 V), ZZ is HIGH TA = 25 C – 120 150 µA TA = 85 C– – 2 5 0 µ A IZZ Sleep mode current V DD = 3.6 V, ZZ is LOW, All other inputs VSS or VDD. TA = 25 C –35 µ A TA = 85 C ––8 µ A ILI Input leakage current V IN between VDD and VSS –– + 1µ A ILO Output leakage current V OUT between VDD and VSS –– + 1µ A VIH1 Input HIGH voltage V DD = 2.7 V to 3.6 V 2.2 – V DD + 0.3 V VIH2 Input HIGH voltage V DD = 2.0 V to 2.7 V 0.7 × V DD –– V VIL1 Input LOW voltage V DD = 2.7 V to 3.6 V – 0.3 – 0.8 V VIL2 Input LOW voltage V DD = 2.0 V to 2.7 V – 0.3 – 0.3 × V DD V VOH1 Output HIGH voltage I OH = –1 mA, VDD > 2.7 V 2.4 – – V VOH2 Output HIGH voltage I OH = –100 µA V DD – 0.2 – – V VOL1 Output LOW voltage I OL = 2 mA, VDD > 2.7 V – – 0.4 V VOL2 Output LOW voltage I OL = 150 µA – – 0.2 V Note 2. Typical values are at 25 °C, V DD = VDD (typ). Not 100% tested.

Document Number: 001-90309 Rev. *G Page 10 of 22 AC Test Conditions Data Retention and Endurance Parameter Description Test condition Min Max Unit TDR Data retention T A = 85 C 10 – Years TA = 75 C3 8 – TA = 65 C1 5 1 – NVC Endurance Over operating temperature 10 14 – Cycles Capacitance Parameter Description Test Conditions Max Unit CI/O Input/Output capacitance (DQ) T A = 25 C, f = 1 MHz, VDD = VDD(Typ) 8p F CIN Input capacitance 6p F CZZ Input capacitance of ZZ pin 8 pF Thermal Resistance Parameter Description Test Conditions 44-pin TSOP II Unit JA Thermal resistance (junction to ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 107 C/W JC Thermal resistance (junction to case) 25 C/W

Document Number: 001-90309 Rev. *G Page 11 of 22 AC Switching Characteristics Over the Operating Range Parameters [3]

Description

VDD = 2.0 V to 2.7 V VDD = 2.7 V to 3.6 V UnitCypress Parameter Alt Parameter Min Max Min Max SRAM Read Cycle tCE tACE Chip enable access time – 70 – 60 ns tRC – Read cycle time 105 – 90 ns tAA – Address access time, A16-2 –1 0 5– 9 0 ns tOH tOHA Output hold time, A16-2 20 – 20 – ns tAAP – Page mode access time, A1-0 –4 0 – 30 ns tOHP – Page mode output hold time, A1-0 3– 3 – ns tCA – Chip enable active time 70 – 60 – ns tPC – Pre-charge time 35 – 30 – ns tBA tBW UB, LB access time – 25 – 15 ns tAS tSA Address setup time (to CE LOW) 0– 0 – ns tAH tHA Address hold time (CE Controlled) 70 – 60 – ns tOE tDOE Output enable access time – 25 – 15 ns tHZ [4, 5] tHZCE Chip Enable to output HI-Z – 15 – 10 ns tOHZ [4, 5] tHZOE Output enable HIGH to output HI-Z – 15 – 10 ns tBHZ [4, 5] tHZBE UB, LB HIGHHIGH to output HI-Z – 15 – 10 ns Notes 3. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 0 to 3 V, output loading of the specified IOL/IOH and 30-pF load capacitance shown in AC Test Conditions on page 10. 4. t HZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 5. This parameter is characterized but not 100% tested.

Document Number: 001-90309 Rev. *G Page 12 of 22 SRAM Write Cycle tWC tWC Write cycle time 105 – 90 – ns tCA – Chip enable active time 70 – 60 – ns tCW tSCE Chip enable to write enable HIGH 70 – 60 – ns tPC – Pre-charge time 35 – 30 – ns tPWC – Page mode write enable cycle time 40 – 30 – ns tWP tPWE Write enable pulse width 22 – 18 – ns tWP2 tBW UB, LB pulse width 22 – 18 – ns tWP3 tPWE WE LOW to UB, LB HIGH 22 – 18 – ns tAS tSA Address setup time (to CE LOW) 0 – 0 – ns tAH tHA Address hold time (CE Controlled) 70 – 60 – ns tASP – Page mode address setup time (to WE LOW) 8 – 5 – ns tAHP – Page mode address hold time (to WE LOW) 20 – 15 – ns tWLC tPWE Write enable LOW to chip disabled 30 – 25 – ns tBLC tBW UB, LB LOW to chip disabled 30 – 25 – ns tWLA – Write enable LOW to address change, A16-2 30 – 25 – ns tAWH – Address change to write enable HIGH, A16-2 105 – 90 – ns tDS tSD Data input setup time 20 – 15 – ns tDH tHD Data input hold time 0 – 0 – ns tWZ [6, 7] tHZWE Write enable LOW to output HI-Z – 10 – 10 ns tWX [7] – Write enable HIGH to output driven 8 – 5 – ns tBDS – Byte disable setup time (to WE LOW) 8 – 5 – ns tBDH – Byte disable hold time (to WE HIGH) 8 – 5 – ns AC Switching Characteristics (continued) Over the Operating Range Parameters [3] VDD = 2.0 V to 2.7 V VDD = 2.7 V to 3.6 V UnitCypress Parameter Alt Parameter Min Max Min Max Notes 6. t WZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 7. This parameter is characterized but not 100% tested.

Figure 16. Power Cycle and Sleep Mode Timing

1. Slope measured at any point on the VDD waveform.

Document Number: 001-90309 Rev. *G Page 17 of 22 Functional Truth Table CE WE A16-2 A1-0 ZZ Operation [12, 13] X X X X L Sleep Mode H X X X H Standby/Idle L H H V V V V H H Read L H No Change Change H Page Mode Read L H Change V H Random Read L L L V V V V H H CE-Controlled Write[13] LV V H W E -Controlled Write [13, 14] L No Change V H Page Mode Write [15] L X X X X X X H H Starts pre-charge Byte Select Truth Table WE OE LB UB Operation [16] H H X X Read; Outputs disabled XHH H L H L Read upper byte; HI-Z lower byte L H Read lower byte; HI-Z upper byte L L Read both bytes L X H L Write upper byte; Mask lower byte L H Write lower byte; Mask upper byte L L Write both bytes Notes 12. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, = toggle LOW, = toggle HIGH. 13. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first. 14. WE-controlled write cycle begins as a Read cycle and then A16-2 is latched. 15. Addresses A1-0 must remain stable for at least 15 ns during page mode operation. 16. The UB and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256K x 8.

Document Number: 001-90309 Rev. *G Page 18 of 22 Ordering Code Definitions

Ordering Information

(ns) Ordering Code Package Diagram Package Type Operating Range

60 FM28V202A-TG 51-85087 44-pin TSOP II with software WP , sleep mode Industrial

All the above parts are Pb-free. Option: blank = Standard; TR = Tape and Reel Package Type: TG = 44-pin TSOP II Die Revision: A Density: 202 = 2-Mbit Voltage: V = 2.0 V to 3.6 V Parallel F-RAM Cypress 28FM V 202 A - TG TR

Figure 17. 44-pin TSOP Package Outline, 51-85087

Document Number: 001-90309 Rev. *G Page 20 of 22 Acronyms Document Conventions Units of MeasureAcronym Description UB Upper Byte LB Lower Byte CE Chip Enable CMOS Complementary Metal Oxide Semiconductor EIA Electronic Industries Alliance F-RAM Ferroelectric Random Access Memory I/O Input/Output OE Output Enable RoHS Restriction of Hazardous Substances RW Read and Write SRAM Static Random Access Memory TSOP Thin Small Outline Package WE Write Enable Symbol Unit of Measure °C degree Celsius Hz hertz kHz kilohertz k kilohm MHz megahertz A microampere F microfarad s microsecond mA milliampere ms millisecond M megaohm ns nanosecond  ohm % percent pF picofarad V volt W watt

Document Number: 001-90309 Rev. *G Page 21 of 22 Document History Page Document Title: FM28V202A, 2-Mbit (128 K × 16) F-RAM Memory Document Number: 001-90309 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 4209369 GVCH 01/22/2014 New data sheet. *A 4372700 GVCH 05/07/2014 Changed datasheet status from “Preliminary to Final” Maximum Ratings: Static discharge voltage Removed Machine Model Updated ISB and IZZ description Updated IZZ test condition Updated Figure 8 for more clarity Removed FM28V202A-TGES part number *B 4379377 GVCH 05/14/2014 No technical updates. *C 4375244 GVCH 06/30/2014 Pin Definitions: ZZ pin Added sentence: This pin must be tied to VDD if not used Removed sentence: The ZZ pin is internally pulled up *D 4462029 ZSK 07/31/2014 No technical updates. *E 4567856 ZSK 11/12/2014 Added related documentation hyperlink in page 1. *F 4881722 ZSK / PSR 08/12/2015 Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Updated to new template. *G 5702283 AESATMP8 04/20/2017 Upda ted logo and Copyright.

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