FM28V100 CYPRESS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 13
Technical content
Features
1Mbit Ferroelectric Nonvolatile RAM Organized as 128Kx8 High Endurance 100 Trillion (1014) Read/Writes NoDelay™ Writes Page Mode Operation to 33MHz Advanced High-Reliability Ferroelectric Process Superior to Battery-backed SRAM Modules No battery concerns Monolithic reliability True surface mount solution, no rework steps Superior for moisture, shock, and vibration SRAM Replacement JEDEC 128Kx8 SRAM pinout 60 ns Access Time, 90 ns Cycle Time Low Power Operation 2.0V – 3.6V Power Supply Standby Current 90 A (typ) Active Current 7 mA (typ) Industry Standard Configurations Industrial Temperature -40 C to +85 C 32-pin “Green”/RoHS Package General Description The FM 28V100 is a 128K x 8 nonvolatile memory that reads and writes like a standard SRAM . A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed . It provides data retention for over 10 years while eliminating the reliability concer ns, functional disadvantages , and system design complexities of battery -backed SRAM (BBSRAM). Fast write timing and very high write endurance make F-RAM superior to other types of memory. In-system operation of the FM 28V100 is very similar to other RAM d evices and can be used as a drop -in replacement for standard SRAM . Read and write cycles may be triggered by toggling a chip enable pin or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM28V100 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. Device specifications are guaranteed over the industrial temperature range -40°C to +85°C. Pin Configuration * Reserved for A17 on 2Mb
Ordering Information
FM28V100-TG 32-pin “Green”/RoHS TSOP FM28V100-TGTR 32-pin “Green”/RoHS TSOP, Tape & Reel TSOP-I A11 A13 WE CE2 A15 VDD NC* A16 A14 A12 OE A10 CE1 DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0
Figure 1. Block Diagram CE2 (while /CE1 low). Addresses A(2:0) are used for page mode read and write operations. address is latched internally at this point. The CE2 pin is pulled up internally. latches a new column address for fast page mode write cycles. available. Deasserting /OE high tri-states the DQ pins. DQ(7:0) I/O Data: 8-bit bi-directional data bus for accessing the F-RAM array. NC - No Connect: This pin has no internal connection.
Rev. 3.0 Apr. 2012 Page 3 of 13 Functional Truth Table 1 /CE1 CE2 /WE A(16:3) A(2:0) Operation H X X L X X X X X X Standby/Idle L H H H V V V V Read L H H No Change Change Page Mode Read L H H Change V Random Read L L L V V V V /CE-Controlled Write 2 L H V V /WE-Controlled Write 2, 3 L H No Change V Page Mode Write 4 L X X X X X X Starts Precharge Notes: 1) H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care. 2) For write cycles, data -in is latched on the rising edge of /CE 1 or /WE of the falling edge of CE2 , whichever comes first. 3) /WE-controlled write cycle begins as a Read cycle and A(16:3) is latched then. 4) Addresses A(2:0) must remain stable for at least 15 ns during page mode operation.
Rev. 3.0 Apr. 2012 Page 4 of 13 Overview The FM 28V100 is a bytewide F-RAM memory logically organized as 131,072 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a different page is triggered by toggling a chip enable pin or simply by changing the upper address A(16:3). Memory Operation Users acces s 131,072 memory locations with 8 data bits each through a parallel interface. The F-RAM array is organized as 16,384 rows and each row has 8 column locations (bytes), which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low) , subsequent column locations may be acces sed without the need to toggle a chip enable. When either chip enable pin is deasserted, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. Read Operation A read operation begins on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). The /CE -initiated access causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the access time has been satisfied. Once the address has been latche d and the access completed, a new access to a random location (different row) may begin while both chip enables are still active. The minimum cycle time for random addresses is t RC. Note that unlike SRAMs, the FM28V100’s /CE- initiated access time is faste r than the address cycle time. The FM 28V100 will drive the data bus only when /OE is asserted low and the memory access time has been satisfied. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive, the data bus will remain hi-Z. Write Operation Writes occur in the FM 28V100 in the same tim e interval as reads. The FM 28V100 supports both /CE- and /WE -controlled w rite cycles. In both cases, the address is latched on the falling edge of /CE1 (while CE2 high) or the rising edge of CE2 (while /CE1 low). In a /CE -controlled write, the /WE signal i s asserted prior to beginning the memory cycle. That is, /WE is low when the device is activated with a chip enable . In this case, the device begins the memory cycle as a write. The FM 28V100 will not drive the data bus regardless of the state of /OE as lon g as /WE is low. Input data must be valid when the device is deselected with a chip enable . In a /WE -controlled write, the memory cycle begins when the device is activated with a chip enable . The /WE signal falls some time later . Therefore, the memory cyc le begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is asserted low. The /CE- and /WE -controlled write timing cases are shown on page 12. In the Write Cycle Timing 2 diagram, t he data bus is shown as a hi-Z condit ion while the chip is write-enabled and before the required setup time. Although this is drawn to look like a mid -level voltage, it is recommended that all DQ pins comply with the minimum V IH/VIL operating levels. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the deassertion of /WE, /CE1, or CE2, whichever come s first. A valid write operation requires the user to meet the access time specification prior to deasserting /WE, / CE1, or CE2 . Data setup time indicates the interval during which data cannot change prior to the end of the write access. Unlike other truly nonvolatile memory technologies, there is no write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM28V100 provides the user fast access to any data within a row element. Each row has eight column locations (bytes). An access can start anywhere within a row and other column locations may be accessed without the need to toggle the CE pins. For pag e mode reads, once the first data byte is driven onto the bus, the column address inputs A(2:0) may be changed to a new value. A new data byte is then driven to the DQ pins. For page mode writes, the first write pulse defines the first write access. While the device is selected (both chip enables asserted), a subsequent write pulse along with a new column address provides a page mode write access.
operates with a read and restore mechanism. row is counted only once in an endurance calculation. to satisfy the device’s precharge timing constraint tPC. Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop
Rev. 3.0 Apr. 2012 Page 7 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +4.5V VIN Voltage on any signal pin with respect to VSS -1.0V to +4.5V and VIN < VDD+1V TSTG Storage Temperature -55C to +125C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 2kV 1.25kV 200V Package Moisture Sensitivity Level MSL-3 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions abov e those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 2.0 3.3 3.6 V IDD VDD Supply Current 7 12 mA 1 ISB Standby Current – CMOS 90 150 A 2 ILI Input Leakage Current 1 A 3 ILO Output Leakage Current 1 A 3 VIH Input High Voltage 0.7 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 VDD V VOH1 Output High Voltage (IOH = -1 mA, VDD=2.7V) 2.4 V VOH2 Output High Voltage (IOH = -100 A) VDD-0.2 V VOL1 Output Low Voltage (IOL = 2 mA, VDD=2.7V) 0.4 V VOL2 Output Low Voltage (IOL = 150 A) 0.2 V RIN Address Input Resistance (CE2) For VIN = VIH (min) For VIN = VIL (max) Notes 3. VIN, VOUT between VDD and VSS. 4. The input pull-up circuit is stronger (>40K) when the input voltage is above VIH and weak (>1M) when the input voltage is below VIL.
Rev. 3.0 Apr. 2012 Page 8 of 13 Read Cycle AC Parameters (TA = -40 C to +85 C, CL = 30 pF, unless otherwise specified) VDD 2.0 to 2.7V VDD 2.7 to 3.6V Symbol Parameter Min Max Min Max Units Notes tRC Read Cycle Time 105 - 90 - ns tCE Chip Enable Access Time - 70 - 60 ns tAA Address Access Time - 105 - 90 ns tOH Output Hold Time 20 - 20 - ns tAAP Page Mode Address Access Time - 40 - 30 ns tOHP Page Mode Output Hold Time 3 - 3 - ns tCA Chip Enable Active Time 70 - 60 - ns tPC Precharge Time 35 - 30 - ns tAS Address Setup Time (to /CE1, CE2 active) 0 - 0 - ns tAH Address Hold Time (/CE-controlled) 70 - 60 - ns tOE Output Enable Access Time - 25 - 15 ns tHZ Chip Enable to Output High-Z - 10 - 10 ns 1 tOHZ Output Enable High to Output High-Z - 10 - 10 ns 1 Write Cycle AC Parameters (TA = -40 C to +85 C, unless otherwise specified) VDD 2.0 to 2.7V VDD 2.7 to 3.6V Symbol Parameter Min Max Min Max Units Notes tWC Write Cycle Time 105 - 90 - ns tCA Chip Enable Active Time 70 - 60 - ns tCW Chip Enable to Write Enable High 70 - 60 - ns tPC Precharge Time 35 - 30 - ns tPWC Page Mode Write Enable Cycle Time 40 - 30 - ns tWP Write Enable Pulse Width 22 - 18 - ns tAS Address Setup Time (to /CE1, CE2 active) 0 - 0 - ns tAH Address Hold Time (/CE-controlled) 70 - 60 - ns tASP Page Mode Address Setup Time (to /WE low) 8 - 5 - ns tAHP Page Mode Address Hold Time (to /WE low) 20 - 15 - ns tWLC Write Enable Low to Chip Disabled 30 - 25 - ns tWLA Write Enable Low to A(16:3) Change 30 - 25 - ns tAWH A(16:3) Change to Write Enable High 105 - 90 - ns tDS Data Input Setup Time 20 - 15 - ns tDH Data Input Hold Time 0 - 0 - ns tWZ Write Enable Low to Output High Z - 10 - 10 ns 1 tWX Write Enable High to Output Driven 5 - 5 - ns 1 tWS Write Enable to CE-Active Setup Time 0 - 0 - ns 1,2 tWH Write Enable to CE-Inactive Hold Time 0 - 0 - ns 1,2 Notes 1 This parameter is characterized but not 100% tested. 2 The relationship between CE’s and /WE determines if a /CE- or /WE-controlled write occurs. Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes tVR VDD Rise Time 50 - s/V 1 tVF VDD Fall Time 100 - s/V 1 tPU Power Up (VDD min) to First Access Time 250 - s tPD Last Access to Power Down (VDD min) 0 - s Notes 1 Slope measured at any point on VDD waveform.
Rev. 3.0 Apr. 2012 Page 9 of 13 Data Retention (TA = -40C to + 85C) Parameter Min Max Units Notes Data Retention 10 - Years Capacitance (TA = 25 C , f=1 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CI/O Input/Output Capacitance (DQ) - 8 pF 1 CIN Input Capacitance - 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels 0 to 3V Input rise and fall times 3 ns Input and output timing levels 1.5V Output Load Capacitance 30 pF Read Cycle Timing 1 (/CE1 low, CE2 high, /OE low) A(16:0) DQ(7:0) tRC tOH tAA tOH Read Cycle Timing 2 (/CE-controlled) CE2 A(16:0) OE DQ(7:0) tAS tCE tCA tPC tOE tOHZ tHZ tAH CE1
Rev. 3.0 Apr. 2012 Page 10 of 13 Page Mode Read Cycle Timing CE2 A(16:3) OE DQ(7:0) tAS tCA A(2:0) tOE tCE tOHZ tAAP tOHP tHZ tPC Col 0 Data 0 Col 1 Data 1 Col 2 Data 2 CE1 Although sequential column addressing is shown, it is not required. Write Cycle Timing 1 (/WE-Controlled) Note: /OE is low only to show effect of /WE on DQ pins D in CE1 A(16:0) WE tCA tPC DQ(7:0) tWP tCW tAS D out D out tDS tDH tWX tWZ tHZ tWLC CE2 Write Cycle Timing 2 (/CE-Controlled) CE2 A(16:0) WE DQ(7:0) tCA tPC tWS tAS tWH tDH tDS CE1 tAH NOTE: See Write Operation section for detailed description (page 4).
Rev. 3.0 Apr. 2012 Page 11 of 13 Write Cycle Timing 3 (/CE1 low, CE2 high) Note: /OE is low only to show effect of /WE on DQ pins D in A(16:0) WE DQ(7:0) tWC tDH tWLA tDS tAWH D out D out tWZ tWX D in Page Mode Write Cycle Timing CE2 A(16:3) WE tCA tPC DQ(7:0) tCW A(2:0) Col 0 Col 1 Data 0 Col 2 tAS tDS Data 1 tWP tDH Data 2 OE tAHP tPWC tASPtAH CE1 tWLC Although sequential column addressing is shown, it is not required. Power Cycle Timing VDD t VF VDD min minVDD tVR tPU tPD Access Allowed
Rev. 3.0 Apr. 2012 Page 12 of 13 Mechanical Drawing 32-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters Pin 1 8.00 ±0.10 1.20 max 0.17-0.27 typ 0.50 typ 0.10 mm 0.5-0.7 0.21 0.10 14.20 0.30 0.50 Recommended PCB Footprint 11.80 ±0.10 1.60 13.55 13.30 0.15 0.05 0°-5° Legend: XXXXXX= part number, P= package/option (T=TSOP “Green”) R=rev code, YY=year, WW=work week, LLLLLLL= lot code Example: FM28V100, “Green”/RoHS TSOP-I package, Rev. A, Year 2010, Work Week 18, Lot 9482296 RAMTRON FM28V100-TG A9482296TG 1018 RAMTRON XXXXXXX-P RLLLLLLL YYWW
Rev. 3.0 Apr. 2012 Page 13 of 13
Revision History
1.0 10/10/2008 Initial release. 1.1 3/25/2009 Added tape & reel ordering information. Added ESD ratings. Removed software write protect feature. 1.2 5/25/2010 Changed MSL package rating. Expanded explanation of precharge operation. Updated lead temperature rating in Abs Max table. Changed package marking scheme. 3.0 4/24/2012 Changed to Production status.