FM28V020-SGTR

FM28V020 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

256Kbit Ferroelectric Nonvolatile RAM Organized as 32K x 8

1014 Read/Write Cycles

NoDelay™ Writes Page Mode Operation Advanced High-Reliability Ferroelectric Process Superior to Battery-backed SRAM Modules No battery concerns Monolithic reliability True surface mount solution, no rework steps Superior for moisture, shock, and vibration Resistant to negative voltage undershoots SRAM Replacement JEDEC 32Kx8 SRAM pinout 70 ns Access Time, 140 ns Cycle Time Low Power Operation 2.0V – 3.6V Power Supply Standby Current 90 A (typ) Active Current 5 mA (typ) Industry Standard Configurations Industrial Temperature -40 C to +85 C 28-pin “Green”/RoHS SOIC (-SG) 28-pin “Green”/RoHS TSOP (-T28G) 32-pin “Green”/RoHS TSOP (-TG) General Description The FM28V020 is a 32K x 8 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile , which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the r eliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and virtually unlimited write endurance make F-RAM superior to other types of memory. In-system operation of the FM 28V020 is very similar to other RAM devices and can be used as a drop -in replacement for standard SRAM . Read and write cycles may be triggered by /CE or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric me mory process. T hese features make the FM 28V020 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. The device is available in a 28 -pin SOIC, 28 -pin TSOP-I, or 32-pin TSOP -I surface mount package. Device specifications ar e guaranteed over the industrial temperature range -40°C to +85°C.

Ordering Information

FM28V020-SG 28-pin “Green”/RoHS SOIC FM28V020-SGTR 28-pin “Green”/RoHS SOIC, Tape & Reel FM28V020-T28G 28-pin “Green”/RoHS TSOP FM28V020-T28GTR 28-pin “Green”/RoHS TSOP, Tape & Reel FM28V020-TG 32-pin “Green”/RoHS TSOP FM28V020-TGTR 32-pin “Green”/RoHS TSOP, Tape & Reel

Figure 1. Block Diagram mode read and write operations. edge of /CE. The entire address is latched internally at this point. latches a new column address for fast page mode write cycles. available. Deasserting /OE high tri-states the DQ pins. DQ(7:0) I/O Data: 8-bit bi-directional data bus for accessing the F-RAM array.

Document Number: 001-86204 Rev. *A Page 3 of 16 Functional Truth Table /CE /WE A(14:3) A(2:0) Operation H X X X Standby/Idle H V V Read L H No Change Change Page Mode Read L H Change V Random Read L V V /CE-Controlled Write 2 L V V /WE-Controlled Write 2, 3 L No Change V Page Mode Write 4 X X X Starts Precharge Notes: 1) H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care. 2) For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first. 3) /WE-controlled write cycle begins as a Read cycle and A(14:3) is latched then. 4) Addresses A(2:0) must remain stable for at least 15 ns during page mode operation. Pin Configurations SOIC A14 DQ0 DQ1 DQ2 VSS DQ4 DQ5 DQ6 DQ7 OE A13 WE A10 A11 VDD A12 CE DQ3 28-pin TSOP-I (-T28G) OE A11 A13 WE VDD A14 A12 A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 32-pin TSOP-I (-TG) NC OE A11 A13 WE VDD A14 A12 NC NC A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 NC

Document Number: 001-86204 Rev. *A Page 4 of 16 Overview The FM 28V020 is a bytewide F-RAM memory logically organized as 32,768 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a differe nt page is triggered by toggling the chip enable pin or simply by changing the upper address A(14:3). Memory Operation Users acces s 32,768 memory locations with 8 data bits each through a parallel interface. The F-RAM array is organi zed as 8 blocks each h aving 512 rows. Each row has 8 column locations, which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE, subsequent column locations may be acces sed without the need to toggle the chip enable . When either chip enable pin is deasserted, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. Read Operation A read operation begi ns on the falling edge of / CE. The /CE-initiated access causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the acces s time has been satisfied. Once the address has been latched and the access completed , a new access to a random location (different row) may begin while /CE is still active . The minimum cycle time for random addresses is t RC. Note that unlike SRAMs, the FM28V020’s /CE-initiated access time is faster than the address cycle time. The FM 28V020 will drive the data bus only when /OE is asserted low and the memory access time has been satisfied. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive, the data bus will remain hi-Z. Write Operation Writes occur in the FM 28V020 in the same time interval as reads. The FM 28V020 supports both /CE- and /WE -controlled w rite cycles. In both cases, the address is latched on the falling edge of /CE. In a CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. Th at is, /WE is low when the device is activated with the chip enable. In this case, the device begins the memory cycle as a write. The FM 28V020 will not drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when the device is deselected with the chip enable. In a /WE -controlled write, the memory cycle b egins when the device is activated with the chip enable. The /WE signal falls some time later . Therefore, the memory cycle begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is as serted low. The /CE- and /WE -controlled write timing cases are shown on page 9. In the Write Cycle Timing 2 diagram, t he data bus is shown as a hi-Z condition while the chip is write-enabled and before the required setup time. Although this is drawn to l ook like a mid -level voltage, it is recommended that all DQ pins comply with the minimum V IH/VIL operating levels. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the deassertion of /WE or /CE, whichever come s first. A valid write operation requires the user to meet the access time specification prior to deasserting /WE or /CE. Data setup time indicates the interval during which data cannot change prior to the end of the write access. Unlike other truly nonvolatile memory technologies, there is no write delay with F-RAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operatio n occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM28V020 provides the user fast access to any data within a row element. Each row has eight column lo cations. An access can start anywhere within a row and other column locations may be accessed without the need to toggle the /CE pin. For page mode reads, once the first data byte is driven onto the bus, the column address inputs A(2:0) may be changed to a new value. A new data byte is then driven to the DQ pins. For page mode writes, the first write pulse defines the first write access. While the device is sele cted (/CE low ), a subsequent write pulse along with a new column address provides a page mode write access. Precharge Operation The precharge operation is an internal condition in which the state of the memory is preparing for a new

operates with a read and restore mechanism. if the addressing is contiguous in nature. and write endurance is virtually unlimited. Table 1. Time to Reach 100 Trillion Cycles for Repeating 256-byte Loop

Document Number: 001-86204 Rev. *A Page 7 of 16 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +4.5V VIN Voltage on any signal pin with respect to VSS -1.0V to +4.5V and VIN < VDD+1V TSTG Storage Temperature -55 C to +125 C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 2kV 1.25kV 200V Package Moisture Sensitivity Level MSL-2 (SOIC) MSL-3 (TSOP) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 2.0 3.3 3.6 V IDD VDD Supply Current 5 8 mA 1 ISB Standby Current – CMOS 90 150 A 2 ILI Input Leakage Current A 3 ILO Output Leakage Current A 3 VIH Input High Voltage 0.7 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.3 VDD V VOH1 Output High Voltage (IOH = -1 mA, VDD=2.7V) 2.4 V VOH2 Output High Voltage (IOH = -100 A) VDD-0.2 V VOL1 Output Low Voltage (IOL = 1 mA, VDD=2.7V) 0.4 V VOL2 Output Low Voltage (IOL = 150 A) 0.2 V Notes 3. VIN, VOUT between VDD and VSS.

Document Number: 001-86204 Rev. *A Page 8 of 16 Read Cycle AC Parameters (TA = -40 C to +85 C, CL = 30 pF, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes tRC Read Cycle Time 140 - ns tCE Chip Enable Access Time - 70 ns tAA Address Access Time - 140 ns tOH Output Hold Time 20 - ns tAAP Page Mode Address Access Time - 40 ns tOHP Page Mode Output Hold Time 3 - ns tCA Chip Enable Active Time 70 - ns tPC Precharge Time 70 - ns tAS Address Setup Time (to /CE low) 0 - ns tAH Address Hold Time (/CE-controlled) 70 - ns tOE Output Enable Access Time - 20 ns 3 tHZ Chip Enable to Output High-Z - 10 ns 1 tOHZ Output Enable High to Output High-Z - 10 ns 1 Write Cycle AC Parameters (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes tWC Write Cycle Time 140 - ns tCA Chip Enable Active Time 70 - ns tCW Chip Enable to Write Enable High 70 - ns tPC Precharge Time 70 - ns tPWC Page Mode Write Enable Cycle Time 35 - ns tWP Write Enable Pulse Width 18 - ns tAS Address Setup Time (to /CE low) 0 - ns tAH Address Hold Time (/CE-controlled) 70 - ns tASP Page Mode Address Setup Time (to /WE low) 5 - ns tAHP Page Mode Address Hold Time (to /WE low) 20 - ns tWLC Write Enable Low to /CE High 25 - ns tWLA Write Enable Low to A(14:3) Change 25 - ns tAWH A(14:3) Change to Write Enable High 140 - ns tDS Data Input Setup Time 15 - ns tDH Data Input Hold Time 0 - ns tWZ Write Enable Low to Output High Z - 10 ns 1 tWX Write Enable High to Output Driven 5 - ns 1 tWS Write Enable to /CE Low Setup Time 0 - ns 1,2 tWH Write Enable to /CE High Hold Time 0 - ns 1,2 Notes 1 This parameter is characterized but not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. 3 For VDD < 2.7V, tOE max is 25ns. Power Cycle Timing (TA = -40 C to +85 C, VDD = 2.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes tVR VDD Rise Time 50 - s/V 1 tVF VDD Fall Time 100 - s/V 1 tPU Power Up (VDD min) to First Access Time 250 - s tPD Last Access to Power Down (VDD min) 0 - s Notes 1 Slope measured at any point on VDD waveform.

Document Number: 001-86204 Rev. *A Page 9 of 16 Data Retention (VDD = 2.0V to 3.6V, +85 Parameter Min Max Units Notes Data Retention 10 - Years Capacitance (TA = 25 C , f=1 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CI/O Input/Output Capacitance (DQ) - 8 pF 1 CIN Input Capacitance - 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels 0 to 3V Input rise and fall times 3 ns Input and output timing levels 1.5V Output Load Capacitance 30 pF Read Cycle Timing 1 (/CE low, /OE low) A(14:0) DQ(7:0) tRC tOH tAA tOH Read Cycle Timing 2 (/CE-controlled) A(14:0) OE DQ(7:0) tAS tCE tCA tPC tOE tOHZ tHZ tAH CE

Document Number: 001-86204 Rev. *A Page 10 of 16 Page Mode Read Cycle Timing A(14:3) OE DQ(7:0) tAS tCA A(2:0) tOE tCE tOHZ tAAP tOHP tHZ tPC Col 0 Data 0 Col 1 Data 1 Col 2 Data 2 CE Although sequential column addressing is shown, it is not required. Write Cycle Timing 1 (/WE-Controlled) Note: /OE is low only to show effect of /WE on DQ pins D in CE A(14:0) WE tCA tPC DQ(7:0) tWP tCW tAS D out D out tDS tDH tWX tWZ tHZ tWLC Write Cycle Timing 2 (/CE-Controlled) A(14:0) WE DQ(7:0) tCA tPC tWS tAS tWH tDH tDS CE tAH NOTE: See Write Operation section for detailed description (page 4).

Document Number: 001-86204 Rev. *A Page 11 of 16 Write Cycle Timing 3 (/CE low) Note: /OE is low only to show effect of /WE on DQ pins D in A(14:0) WE DQ(7:0) tWC tDH tWLA tDS tAWH D out D out tWZ tWX D in Page Mode Write Cycle Timing A(14:3) WE tCA tPC DQ(7:0) tCW A(2:0) Col 0 Col 1 Data 0 Col 2 tAS tDS Data 1 tWP tDH Data 2 OE tAHP tPWC tASPtAH CE tWLC Although sequential column addressing is shown, it is not required. Power Cycle Timing VDD t VF 1.0V VDD min minVDD 1.0V tVR tPU tPD Access Allowed

Document Number: 001-86204 Rev. *A Page 12 of 16 Mechanical Drawing 28-pin SOIC (JEDEC MS-013D Variation AE) All dimensions in millimeters Pin 1 17.90 ±0.20 0.10 0.30 2.35 2.65 0.33 0.51 1.27 typ 0.10 0.25 0.75 0.40 1.27 0.23 0.32 0?- 8? Legend: XXXXXX= part number, P= package type (SG=SOIC “Green”) R=Rev, YY=year, WW=work week, LLLLLLL= lot code Example: FM28V020, “Green”/RoHS SOIC package, Rev. A, Year 2010, Work Week 18, Lot code 9482296 RAMTRON FM28V020-SG A10189482296G RAMTRON XXXXXXX-P RYYWWLLLLLLL

Document Number: 001-86204 Rev. *A Page 13 of 16 28-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters Complies with JEDEC MO-183 8.00 ±0.10 1.20 max 0.27 0.17 0.55 nom 0.10 mm 0.3-0.7 0.20 0.10 14.20 0.30 0.55 Recommended PCB Footprint 11.80 ±0.10 1.60 13.60 13.20 0.15 0.05 0°-5° Pin 1 Legend: XXXXXX= part number, P= package/option (TG=TSOP “Green”) R=rev code, YY=year, WW=work week, LLLLLLL= lot code Example: FM28V020-T28G, “Green” 28-lead TSOP package, Rev. A, Year 2012, Work Week 18, Lot 9482296 RAMTRON FM28V020T28G A9482296TG 1218 RAMTRON XXXXXXX-P RLLLLLLL YYWW

Document Number: 001-86204 Rev. *A Page 14 of 16 32-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters Pin 1 8.00 ±0.10 1.20 max 0.17-0.27 typ 0.50 typ 0.10 mm 0.5-0.7 0.21 0.10 14.20 0.30 0.50 Recommended PCB Footprint 11.80 ±0.10 1.60 13.55 13.30 0.15 0.05 0°-5° Legend: XXXXXX= part number, P= package/option (TG=TSOP “Green”) R=rev code, YY=year, WW=work week, LLLLLLL= lot code Example: FM28V020-TG, “Green” TSOP package, Rev. A, Year 2010, Work Week 18, Lot 9482296 RAMTRON FM28V020-TG A9482296TG 1018 RAMTRON XXXXXXX-P RLLLLLLL YYWW

Document Number: 001-86204 Rev. *A Page 15 of 16

Revision History

1.0 4/15/2009 Initial release. 1.1 9/8/2009 Added TSOP package and MSL rating. Expanded explanation of precharge operation. Updated lead temperature rating in Abs Max table. 1.2 4/22/2010 Updated MSL rating on SOIC package. 2.0 5/25/2010 Changed to Pre-Production status. Added ESD ratings. Changed part marking scheme. 2.1 6/10/2011 Changed AC timing specs. Changed VOL1 test condition. Changed endurance section. Document History Document Title: FM28V020 256Kbit (32Kx8) Bytewide F-RAM Memory Document Number: 001-86204 Revision ECN Orig. of Change Submission Date Description of Change ** 3912932 GVCH 02/25/2013 New Spec *A 3924836 GVCH 03/07/2013 Changed to Production status Added 28-pin TSOP package type Changed IDD limit min spec from 7mA to 5mA and max spec from 12mA to 8mA. Read Cycle AC Parameters: Changed tAAP spec value from 60 to 40ns and tOE spec value from 15 ns to 20 ns Write Cycle AC Parameters: Changed tPWC spec value from 30 to 35 ns and tAHP spec value from 15 to 20ns

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