FM25CL64B-GA

FM25CL64B-GA CYPRESS | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 15

Technical content

Features

64K bit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits High Endurance 10 Trillion (1013) Read/Writes NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Serial Peripheral Interface - SPI Up to 16 MHz Frequency Direct Hardware Replacement for EEPROM SPI Mode 0 & 3 (CPOL, CPHA=0,0 & 1,1) Sophisticated Write Protection Scheme Hardware Protection Software Protection Low Power Consumption Low Voltage Operation 3.0-3.6V A Standby Current (+85 Industry Standard Configuration Automotive Temperature -40 C to +125 C o Qualified to AEC Q100 Specification “Green”/RoHS 8-pin SOIC

Description

The FM25CL64B is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provide s reliable data retention for years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM25CL64B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte has been transferred to the d evice. The next bus cycle may commence without the need for data polling. The FM25CL64B is capable of supporting 10 13 read/write cycles, or 10 million times more write cycles than EEPROM. These capabilities make the FM25 CL64B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding automotive controls where the long write time of EEPROM can cause data loss. The FM25 CL64B provides subs tantial benefits to users of serial EEPROM as a hardware drop -in replacement. The FM25 CL64B uses the high -speed SPI bus, which enhances the high -speed write capability of FRAM technology. Device specifications are guaranteed over the automotive temperature range of -40°C to +125°C. Pin Configuration Pin Name Function /CS Chip Select /WP Write Protect /HOLD Hold SCK Serial Clock SI Serial Data Input SO Serial Data Output VDD Supply Voltage VSS Ground

Ordering Information

FM25CL64B-GA “Green”/RoHS 8-pin SOIC, Automotive Grade 1 FM25CL64B-GATR “Green”/RoHS 8-pin SOIC, Automotive Grade 1, Tape & Reel CS SO WP VSS VDD HOLD SCK SI

FM25CL64B - Automotive Temp. Figure 1. Block Diagram /WP Input Write Protect: This active low pin prevents write operations to the Status Register . function of /WP is different from the FM25040 where it prevents all writes to the part. logic level to meet IDD specifications.

• SI may be connected to SO for a single pin data interface.

the falling edge of the serial clock.

• SO may be connected to SI for a single pin data interface.

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 3 of 15 Overview The FM25 CL64B is a serial FRAM memory. The memory array is logically organized as 8,192 x 8 and is accessed using an industry standard Serial Peripheral Interface or SPI bus. Functional operation of the FRAM is similar to serial EEPROMs. The major difference between the FM25 CL64B and a serial EEPROM with the same pinout is the FRAM‟s superior write performance. Memory Architecture When accessing the FM25 CL64B, the user addresses 8,192 locations of 8 data bits each. These data bits are shifted serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an op -code, and a two -byte address. The upper 3 bits of the address range are „don‟t care‟ values. The complete address of 13-bits specifies each byte address uniquely. Most functions of the FM25 CL64B either are controlled by the SPI interface or are handled automatically by on -board circuitry. The access time for memory operation is essentially zero, beyond the time needed fo r the serial protocol. That is, the memory is read or written at the speed of the SPI bus. Unlike an EEPROM, it is not necessary to poll the device for a ready condition since writes occur at bus speed. So, by the time a new bus transaction can be shifted into the device, a write operation will be complete. This is explained in more detail in the interface section. Users expect several obvious system benefits from the FM25CL64B due to its fast write cycle and high endurance as compared with EEPROM. In add ition there are less obvious benefits as well. For example in a high noise environment, the fast -write operation is less susceptible to corruption than an EEPROM since it is completed quickly. By contrast, an EEPROM requiring milliseconds to write is vulnerable to noise during much of the cycle. Note that the FM25 CL64B contains no power management circuits other than a simple internal power-on reset. It is the user‟s responsibility to ensure that VDD is within datasheet tolerances to prevent incorrect operation. Serial Peripheral Interface – SPI Bus The FM25 CL64B employs a Serial Peripheral Interface (SPI) bus. It is specified to operate at speeds up to 16 MHz. This high -speed serial bus provides high performance serial communication to a host microcontroller. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcontrollers that do not. The FM25CL64B operates in SPI Mode 0 and 3. The SPI interface uses a total of four pins: clock, data-in, data -out, and chip select. It is possible to connect the two data pins together. Figure 2 illustrates a typical system configuration using the FM25CL64B with a microcontroller that offers an SPI port. Figure 3 shows a similar configuration for a microcontroller that has no hardware support for the SPI bus. Protocol Overview The SPI interface is a synchronous serial interface using clock and data pins. It is intended to support multiple devices on the bus. Each device is activated using a chip select. Once chip select is activated by the bus master, the FM25 CL64B will begin monitoring the clock and data lines. The relationship between the falling edge of /CS, the clock and data is dictated by the SPI mode. The device wi ll make a determination of the SPI mode on the falling edge of each chip select. While there are four such modes, the FM25CL64B supports modes 0 and 3. Figure 4 shows the required signal relationships for modes 0 and 3. For both modes, data is clocked in to the FM25CL64B on the rising edge of SCK and data is expected on the first rising edge after /CS goes active. If the clock begins from a high state, it will fall prior to beginning data transfer in order to create the first rising edge. The SPI protoco l is controlled by op -codes. These op-codes specify the commands to the device. After /CS is activated the first byte transferred from the bus master is the op -code. Following the op -code, any addresses and data are then transferred. Note that the WREN and WRDI op -codes are commands with no subsequent data transfer. Important: The /CS pin must go inactive after an operation is complete and before a new op -code can be issued. There is one valid op -code only per active chip select.

FM25CL64B - Automotive Temp. protect inadvertent changes to the block protect bits. register is write protected if WPEN=1 and /WP=0. write protection conditions. Table 4. Write Protection

0 X X Protected Protected Protected

any number of sequential writes may be performed. op-code. The next op -code is the WRITE instruction. edge of /CS terminates a READ op -code op eration. A read operation is shown in Figure 10. but the SCK pin can toggle during a hold state.

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 9 of 15 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +5.0V VIN Voltage on any pin with respect to VSS -1.0V to +5.0V and VIN < VDD+1.0V TSTG Storage Temperature -55 C to + 125 C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 4kV 1.25kV 300V Package Moisture Sensitivity Level MSL-1 Stresses above those listed under A bsolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to +125 C, VDD = 3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply Voltage 3.0 3.3 3.6 V IDD VDD Supply Current @ SCK = 1.0 MHz @ SCK = 16.0 MHz 0.3 mA mA ISB Standby Current @ +85 C @ +125 C A A ILI Input Leakage Current - A 3 ILO Output Leakage Current - A 3 VIH Input High Voltage 0.75 VDD VDD + 0.3 V VIL Input Low Voltage -0.3 0.25 VDD V VOH Output High Voltage @ IOH = -2 mA VDD – 0.5 - V VOL Output Low Voltage @ IOL = 2 mA - 0.4 V VHYS Input Hysteresis 0.05 VDD - V 4 Notes 1. SCK toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCK = SI = /CS=VDD. All inputs VSS or VDD. 3. VSS VIN VDD and VSS VOUT VDD. 4. Characterized but not 100% tested in production. Applies only to /CS and SCK pins.

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 10 of 15 AC Parameters (TA = -40 C to +125 C, VDD = 3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes fCK SCK Clock Frequency 0 16 MHz tCH Clock High Time 25 ns 1 tCL Clock Low Time 25 ns 1 tCSU Chip Select Setup 10 ns tCSH Chip Select Hold 10 ns tOD Output Disable Time 20 ns 2 tODV Output Data Valid Time 25 ns tOH Output Hold Time 0 ns tD Deselect Time 60 ns tR Data In Rise Time 50 ns 2,3 tF Data In Fall Time 50 ns 2,3 tSU Data Setup Time 5 ns tH Data Hold Time 5 ns tHS /HOLD Setup Time 10 ns tHH /HOLD Hold Time 10 ns tHZ /HOLD Low to Hi-Z 20 ns 2 tLZ /HOLD High to Data Active 20 ns 2 Notes 1. tCH + tCL = 1/fCK. 2. Characterized but not 100% tested in production. 3. Rise and fall times measured between 10% and 90% of waveform. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CO Output Capacitance (SO) - 8 pF 1 CI Input Capacitance - 6 pF 1 Notes 1. This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 10% and 90% of VDD Input and output timing levels 0.5 VDD Input rise and fall times 5 ns Output Load Capacitance 30 pF Power Cycle Timing VDD min tPU VDD CS tVR tPD tVF Power Cycle Timing (TA = -40 C to +125 C, VDD = 3.0V to 3.6V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU VDD(min) to First Access Start 1 - ms tPD Last Access Complete to VDD(min) 0 - s tVR VDD Rise Time 30 - s/V 1 tVF VDD Fall Time 20 - s/V 1 Notes 1. Slope measured at any point on VDD waveform.

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 11 of 15 Serial Data Bus Timing 1/fCK tCL tCH tCSH tODV tOH tOD tCSU tSU tH tD tRtF /Hold Timing Data Retention (VDD = 3.0V to 3.6V unless otherwise specified) Automotive Grade SS Retention Experiment Results OS Retention AEC-Q100 Grade 3 AEC-Q100 Grade 2 AEC-Q100 Grade 1 Unlimited Unlimited Unlimited 10.9 yrs @ 85OC 5.5 years @ 105OC 11,200 hours @ 125OC

10 Years

5 Years

Note : Data retention qualification tests are accelerated tests and are performed such that all three conditions have been applied : (1) 10 years at a temperature of +85 C, (2) 5 years at +105 C, and (3) 11,000 hours at +125

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 12 of 15 Opposite State Data Retention Graphs for Grade 1, 2 and 3 Automotive: These specifications can be used for different multi-temperature thermal profiles. Example of an AEC – Q100 Grade 1 Automotive F-RAM application. Temperature ( T ) Time Factor ( t ) Profile Life Time L( P ) T1 = 125oC T2 = 105oC T3 = 85oC T4 = 55oC 10% 15% 25% 50% > 10.46 years

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 13 of 15 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 0.40 1.27 0.19 0.25 0 - 8 Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXXXX = part number, P = package type, T = temp (A = automotive grade, blank = ind.) RR = rev code, LLLLL = lot code, Z = Package code RIC = Ramtron Int‟l Corp, YY = year, WW = work week = Pb-free Example: FM25CL64B, “Green”/RoHS SOIC, Automotive Temperature Rev. BA, Lot 64179, SOIC Year 2013, Work Week 07 Pb-free 25CL64B-GA BA64179S RIC1307 XXXXXXX-PT RRLLLLLZ RICYYWW

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 14 of 15

Revision History

1.0 2/18/2011 Initial release. 1.1 5/3/2011 Added ESD ratings. 3.0 9/12/2011 Changed to Production status. 3.1 3/31/2012 Improved tPU and tVF specs. 3.2 10/31/2012 Changed Retention specifications Document History Document Title: FM25CL64B 64Kb Serial 3V F-RAM Memory (Automotive Temp) Document Number: 001-86149 Revision ECN Orig. of Change Submission Date Description of Change ** 3912930 GVCH 02/25/2013 New Spec *A 3985108 GVCH 05/07/2013 Updated SOIC package marking scheme

FM25CL64B - Automotive Temp. Document Number: 001-86149 Rev. *A Page 15 of 15 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/usb PSoC® Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support RAMTRON is a registered trademark and NoDelay™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are the property of their respective owners. © Cypress Semi conductor Corporation, 2011 -2013. The information contained herein is su bject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress p roduct. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life -support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and s ubject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non -exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does no t assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life -support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.