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■ 16-Kbit ferroelectric random access memory (F-RAM) logically organized as 2 K × 8 ❐ High-endurance 10 trillion (1013) read/writes ❐ 121-year data retention (See the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Advanced high-reliability ferroelectric process ■ Very fast serial peripheral interface (SPI) ❐ Up to 15 MHz frequency ❐ Direct hardware replacement for serial flash and EEPROM ❐ Supports SPI mode 0 (0,0) and mode 3 (1,1) ■ Sophisticated write protection scheme ❐ Hardware protection using the Write Protect (WP) pin ❐ Software protection using Write Disable instruction ❐ Software block protection for 1/4, 1/2, or entire array ■ Low power consumption ❐ 300 A active current at 1 MHz ❐ 10 A (typ) standby current at +85 C ■ Voltage operation: VDD = 4.5 V to 5.5 V ■ Automotive-E temperature: –40 C to +125 C ■ 8-pin small outline integrated circuit (SOIC) package ■ AEC Q100 Grade 1 compliant ■ Restriction of hazardous substances (RoHS) compliant Functional Overview The FM25C160B is a 16-Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 121 years while eliminating the complexities, overhead, and system level reliability problems caused by serial flash, EEPROM, and other nonvolatile memories. Unlike serial flash and EEPR OM, the FM25C160B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte is successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the product offers substantial write endurance compared with other nonvolatile memories. The FM25C160B is capable of supporting 13 read/write cycles, or 10 million times more write cycles than EEPROM. These capabilities make the FM25C160B ideal for nonvolatile memory applications requirin g frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or EEPROM can cause data loss. The FM25C160B provides substantial benefits to users of serial EEPROM or flash as a hardwa re drop-in replacement. The FM25C160B uses the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. The device specifications are guaranteed over an automotive-e temperature range of –40 C to +125 C. Instruction Decoder Clock Generator Control Logic Write Protect Instruction Register Address Register Counter
2 K x 8
Figure 1. 8-pin SOIC pinout internally activates the SCK signal. A falling edge on CS must occur before every opcode. frequency may be any value between 0 and 15 MHz and may be interrupted at any time. is different from the FM25160. VSS Power supply Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device.
- SI may be connected to SO for a single pin data interface .
Document Number: 001-86150 Rev. *A Page 4 of 20 Overview The FM25C160B is a serial F-RAM memory. The memory array is logically organized as 2,048 × 8 bits and is accessed using an industry standard serial peripheral interface (SPI) bus. The functional operation of the F-RAM is similar to serial flash and serial EEPROMs. The majo r difference between the FM25C160B and a serial flash or EEPROM with the same pinout is the F-RAM's superior write performance, high endurance, and low power consumption. It also differs from Cypress’s 25160 by supporting SPI mode 3 and the industry standard 16-bit addressing protocol. This makes the FM25C160B a drop-in replacement for most 16-Kbit SPI EEPROMs that support modes 0 & 3. Memory Architecture When accessing the FM25C160B, the user addresses 2K locations of eight data bits each. These eight data bits are shifted in or out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an opcode, and a two-byte address. The upper 5 bits of the address range are 'don't care' values. The complete address of 11 bits specifies each byte address uniquely. Most functions of the FM25C160 B are either controlled by the SPI interface or handled by on-board circuitry. The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. Th at is, the memory is read or written at the speed of the SPI bus. Unlike a serial flash or EEPROM, it is not necessary to poll the device for a ready condition because writes occur at bus speed. By the time a new bus transaction can be shifted into the device, a write operation is complete. This is explained in more detail in the interface section. Note The FM25C160B contains no power management circuits other than a simple internal power-on reset circuit. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25C160B is a SPI slave device and operates at speeds up to 15 MHz. This high-speed serial bus provides high-performance serial communication to a SPI master. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcon trollers that do not. The FM25C160B operates in SPI Mode 0 and 3. SPI Overview The SPI is a four-pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on the SPI bus is activated using the CS pin. The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In both of these modes, data is clocked into the F-RAM on the rising edge of SCK starting from the first rising edge after CS goes active. The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS is activated, the first byte transferred from the bus master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued. The commonly used terms in the SPI protocol are as follows: SPI Master The SPI master device controls the operations on a SPI bus. An SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are synchronized with this clock. SPI Slave The SPI slave device is activated by the master through the Chip Select line. A slave device gets the SCK as an input from the SPI master and all the communicat ion is synchronized with this clock. An SPI slave never initiates a communication on the SPI bus and acts only on the instruction from the master. The FM25C160B operates as an SPI slave and may share the SPI bus with other SPI slave devices. Chip Select (CS) To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high-impedance state. Note A new instruction must begin with the falling edge of CS . Therefore, only one opcode can be issued for each active Chip Select cycle. Serial Clock (SCK) The Serial Clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW. The FM25C160B enables SPI modes 0 and 3 for data communication. In both of these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first bit (MSB) of a SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK.
factory for bits in the Status Register is ‘0’). Bits 0 and 4-6 are fixed at ‘0’; none of these bits can be modified. the software write-protection f eatures and are nonvolatile bits. The WEL flag indicates the state of the Write Enable Latch. WREN and WRDI commands, respectively. the WPEN bit is set to ‘0’, the status of the WP pin is ignored. write-protected only when WPEN = ‘1’ and WP = ‘0’. Table 5 summarizes the write protection conditions. therefore, clears the Write Enable Latch. Table 2. Status Register Table 3. Status Register Bit Definition Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read. Bit 1 (WEL) Write Enable Latch WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 4 on page 7. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 4 on page 7. Bit 4-6 Don’t care These bits are non-writable and always return ‘0’ upon read. Bit 7 (WPEN) Write Protect Enable bit Used to ena ble the function of Write Protect Pin (WP). For details, see Table 5 on page 7. Table 4. Block Memory Write Protection Table 5. Write Protection
0 X X Protected Protected Protected
and CS pin can toggle during a hold state. Figure 10. Memory Write (WREN not shown) Figure 11. Memory Read
0000001 XXXXX A 90 A10 A8 A3 A1 A2 A0
0000001 XXXXX A 91 A10 A8 A3 A1 A2 A0
Figure 12. HOLD Operation [2]
- Figure shows HOLD operation for input mode and output mode.
each byte to experience one endurance cycle through the loop. Table 6. Time to Reach Endurance Limit for Repeating
Document Number: 001-86150 Rev. *A Page 11 of 20 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. DC voltage applied to outputs Transient voltage (< 20 ns) on Package power dissipation Surface mount lead soldering DC output current (1 output at a time, 1s duration) .... 15 mA Electrostatic Discharge Voltage Operating Range Range Ambient Temperature (TA) VDD Automotive-E –40 C to +125 C 4.5 V to 5.5 V Over the Operating Range Parameter Description Test Conditions Min Typ [5] Max Unit VDD Power supply 4.5 5.0 5.5 V IDD VDD supply current SCK toggling between VDD – 0.3 V and VSS, other inputs VSS or VDD – 0.3 V. SO = Open. fSCK = 1 MHz – – 0.3 mA fSCK = 1 5 M H z ––3 m A ISB VDD standby current CS = VDD. All other inputs VSS or VDD. TA = 85 °C – – 10 A TA = 125 °C – – 30 A ILI Input leakage current V SS < VIN < VDD –– ± 1 A ILO Output leakage current V SS < VOUT < VDD –– ± 1 A VIH Input HIGH voltage 0.75 × V DD –V DD + 0.3 V VIL Input LOW voltage – 0.3 – 0.25 × V DD V VOH Output HIGH voltage I OH = –2 mA V DD – 0.8 – – V VOL Output LOW voltage I OL = 2 mA – – 0.4 V VHYS [5] Input Hysteresis (CS and SCK pin) 0.05 × V DD –– V Notes 3. Typical values are at 25 °C, V DD = VDD(typ). Not 100% tested. 4. This parameter is characterized but not 100% tested.
Document Number: 001-86150 Rev. *A Page 12 of 20 AC Test Conditions Data Retention and Endurance Parameter Description Test condition Min Max Unit TDR Data retention T A = 125 C 11000 – Hours TA = 105 C1 1 – Y e a r s TA = 85 C 121 – NVC Endurance Over operating temperature 10 13 – Cycles Example of an F-RAM Life Time in an AEC-Q100 Automotive Application An application does not operate under a steady temperature for the entire usage life time of the application. Instead, it is often expected to operate in multiple temperature environments throughout the application’s usage life time. Accordingly, the retention specification for F-RAM in applications often needs to be calculated cumulatively. An example calculation for a multi-temperature thermal profiles is given below. Tempeature T Time Factor t Acceleration Factor with respect to Tmax A [5] Profile Factor P Profile Life Time L (P) T1 = 125 C t1 = 0.1 A1 = 1 8.33 > 10.46 YearsT2 = 105 C t2 = 0.15 A2 = 8.67 T3 = 85 C t3 = 0.25 A3 = 95.68 T4 = 55 C t4 = 0.50 A4 = 6074.80 Capacitance Parameter [6] Description Test Conditions Max Unit CO Output pin capacitance (SO) T A = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF CI Input pin capacitance 6p F Thermal Resistance Parameter Description Test Conditions 8-pin SOIC Unit JA Thermal resistance (junction to ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA / JESD51. 147 C/W JC Thermal resistance (junction to case) 47 C/W Notes 5. Where k is the Boltzmann constant 8.617 × 10-5 eV/K, Tmax is the highest temperature specified for the product, and T is any temperature within the F-RAM product specification. All temperatures are in Kelvin in the equation. 6. This parameter is characterized but not 100% tested. A LT Ea T--- 1 P 1
Document Number: 001-86150 Rev. *A Page 13 of 20 AC Switching Characteristics Over the Operating Range Parameters [7] Description Min Max UnitCypress Parameter Alt. Parameter fSCK – SCK Clock frequency 0 15 MHz tCH – Clock HIGH time 30 – ns tCL – Clock LOW time 30 – ns tCSU tCSS Chip select setup 10 – ns tCSH tCSH Chip select hold 10 – ns tOD [8, 9] tHZCS Output disable time – 25 ns tODV tCO Output data valid time – 25 ns tOH – Output hold time 0 – ns tD – Deselect time 80 – ns tR [10, 11] – Data in rise time – 50 ns tF [10, 11] – Data in fall time – 50 ns tSU tSD Data setup time 5 – ns tH tHD Data hold time 5 – ns tHS tSH HOLD setup time 10 – ns tHH tHH HOLD hold time 10 – ns tHZ [8, 9] tHHZ HOLD LOW to HI-Z – 25 ns tLZ [9] tHLZ HOLD HIGH to data active – 20 ns Notes 7. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 12. 8. t OD and tHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 9. This parameter is characterized and not 100% tested. 10. Rise and fall times measured between 10% and 90% of waveform. 11. These parameters are guaranteed by design and are not tested.
Figure 15. Power Cycle Timing
- Slope measured at any point on VDD waveform.
Document Number: 001-86150 Rev. *A Page 16 of 20 Ordering Code Definitions
Ordering Information
Diagram Package Type Operating Range FM25C160B-GA 51-85066 8-pin SOIC Automotive-E FM25C160B-GATR 51-85066 8-pin SOIC All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Option: blank = Standard; TR = Tape and Reel Temperature Range: A = Automotive-E (–40 C to +125 C) Package Type: G = 8-pin SOIC; DG = 8-pin TDFN Die revision: B Density: 160 = 16-Kbit Voltage: C = 3.0 V to 3.6 V SPI F-RAM Cypress 25FM C 160 B A G- TR
Figure 16. 8-pin SOIC (150 Mils) Package Outline, 51-85066
Document Number: 001-86150 Rev. *A Page 18 of 20 Acronyms Document Conventions Units of MeasureAcronym Description AEC Automotive Electronics Council CPHA Clock Phase CPOL Clock Polarity EEPROM Electrically Erasable Programmable Read-Only Memory EIA Electronic Industries Alliance I/O Input/Output JEDEC Joint Electron Devices Engineering Council JESD JEDEC Standards LSB Least Significant Bit MSB Most Significant Bit F-RAM Ferroelectric Random Access Memory RoHS Restriction of Hazardous Substances SPI Serial Peripheral Interface SOIC Small Outline Integrated Circuit Symbol Unit of Measure °C degree Celsius Hz hertz kHz kilohertz K kilohm Kbit kilobit kV kilovolt MHz megahertz A microampere s microsecond mA milliampere ms millisecond ns nanosecond ohm % percent pF picofarad V volt W watt
Document Number: 001-86150 Rev. *A Page 19 of 20 Document History Page Document Title: FM25C160B, 16-Kbit (2 K × 8) Serial (SPI) Automotive F-RAM Document Number: 001-86150 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 3912930 GVCH 02/25/2013 New spec. *A 4227185 GVCH 01/23/2014 Converted to Cypress standard format Updated Maximum Ratings table - Removed Moisture Sensitivity Level (MSL) - Added junction temperature and latch up current Updated Data Retention and Endurance table Added “Example of an F-RAM Life Time in an AEC-Q100 Automotive Applica- tion” table Added footnote 5 Added Thermal Resistance table Removed Package Marking Scheme (top mark) Removed Ramtron revision history Completing Sunset Review
Document Number: 001-86150 Rev. *A Revised January 23, 2014 Page 20 of 20 All products and company names mentioned in this document may be the trademarks of their respective holders. FM25C160B © Cypress Semiconductor Corporation, 2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypres s. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a ma lfunction or failure may reasonably be expe cted to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subj ect to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to t he materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.co m/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress. com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cyp ress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless PSoC® Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support