FM25040B-GX

FM25040B_V01 CYPRESS | Alldatasheet

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Features

■ 4-Kbit ferroelectric random access memory (F-RAM) logically organized as 512 × 8 ❐ High-endurance 100 trillion (1014) read/writes ❐ 151-year data retention (See the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Advanced high-reliability ferroelectric process ■ Very fast serial peripheral interface (SPI) ❐ Up to 20 MHz frequency ❐ Direct hardware replacement for serial flash and EEPROM ❐ Supports SPI mode 0 (0, 0) and mode 3 (1, 1) ■ Sophisticated write protection scheme ❐ Hardware protection using the Write Protect (WP) pin ❐ Software protection using Write Disable instruction ❐ Software block protection for 1/4, 1/2, or entire array ■ Low power consumption ❐ 250 A active current at 1 MHz ❐ 4 A (typ) standby current ■ Voltage operation: VDD = 4.5 V to 5.5 V ■ Industrial temperature: –40 C to +85 C ■ 8-pin small outline integrated circuit (SOIC) package ■ Restriction of hazardous substances (RoHS) compliant Functional Description The FM25040B is a 4-Kbit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes similar to a RAM. It provides reliable data retention for 151 years while eliminating the complexities, overhead, and system level reliability problems caused by serial flash, EEPROM, and other nonvolatile memories. Unlike serial flash and EEPROM, the FM25040B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array immediately after each byte is successfully transferred to the device. The next bus cycle can commence without the need for data polling. In addition, the product offers substantial write endurance compared with other nonvolatile memories. The FM25040B is capable of supporting 14 read/write cycles, or 100 million times more write cycles than EEPROM. These capabilities make the FM25040B ideal for nonvolatile memory applications requirin g frequent or rapid writes. Examples range from data collection, where the number of write cycles may be critical, to demanding industrial controls where the long write time of serial flash or EEPROM can cause data loss. The FM25040B provides substantial benefits to users of serial EEPROM or flash as a hardwa re drop-in replacement. The FM25040B uses the high-speed SPI bus, which enhances the high-speed write capability of F-RAM technology. The device specifications are guaranteed ov er an industrial temperature range of –40 C to +85 C. For a complete list of related documentation, click here. Errata: The Write Enable Latch (WEL) bit in the Status Register of FM25040B part doesn’t clear after executing the memory write (WRITE) operation at memory location(s) from 0x100 to 0x1FF. For more information, see Errata on page 19. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Instruction Decoder Clock Generator Control Logic Write Protect Instruction Register Address Register Counter 512 x 8 F-RAM Array Data I/ O Register Nonvolatile Status Register WP CS HOLD SCK SOSI Logic Block Diagram

Figure 1. 8-pin SOIC pinout activates the SCK signal. A falling edge on CS must occur before every opcode. be any value between 0 and 20 MHz and may be interrupted at any time. and is ignored at other times. It should always be driven to a valid logic level to meet IDD specifications. times including when HOLD is LOW. Data transitions are driven on the falling edge of the serial clock. on page 7. This pin must be tied to VDD if not used. VSS Power supply Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device.

1. SI may be connected to SO for a single pin data interface .

Document Number: 001-86145 Rev. *J Page 4 of 22 Functional Overview The FM25040B is a serial F-RAM memory. The memory array is logically organized as 512 × 8 bits and is accessed using an industry standard serial peripheral interface (SPI) bus. The functional operation of the F-RAM is similar to serial flash and serial EEPROMs. The major difference between the FM25040B and a serial flash or EEPROM with the same pinout is the F-RAM’s superior write performance, high endurance, and low power consumption. Memory Architecture When accessing the FM25040B, the user addresses 512 locations of eight data bits each. These eight data bits are shifted in or out serially. The addresses are accessed using the SPI protocol, which includes a chip select (to permit multiple devices on the bus), an opcode including the upper address bit, and a word address. The word address consist of the lower 8-address bits. The complete address of 9 bits specifies each byte address uniquely. Most functions of the FM25040B are either controlled by the SPI interface or handled by on-board circuitry. The access time for the memory operation is essentially zero, beyond the time needed for the serial protocol. Th at is, the memory is read or written at the speed of the SPI bus. Unlike a serial flash or EEPROM, it is not necessary to poll the device for a ready condition because writes occur at bus speed. By the time a new bus transaction can be shifted into the device, a write operation is complete. This is explained in more detail in the interface section. Note The FM25040B contains no power management circuits other than a simple internal power-on reset circuit. It is the user’s responsibility to ensure that V DD is within datasheet tolerances to prevent incorrect operation. It is recommended that the part is not powered down with chip enable active. Serial Peripheral Interface – SPI Bus The FM25040B is a SPI slave device and operates at speeds up to 20 MHz. This high-speed serial bus provides high-performance serial communication to a SPI master. Many common microcontrollers have hardware SPI ports allowing a direct interface. It is quite simple to emulate the port using ordinary port pins for microcon trollers that do not. The FM25040B operates in SPI Mode 0 and 3. SPI Overview The SPI is a four-pin interface with Chip Select (CS), Serial Input (SI), Serial Output (SO), and Serial Clock (SCK) pins. The SPI is a synchronous serial interface, which uses clock and data pins for memory access and supports multiple devices on the data bus. A device on the SPI bus is activated using the CS pin. The relationship between chip select, clock, and data is dictated by the SPI mode. This device supports SPI modes 0 and 3. In both of these modes, data is clocked into the F-RAM on the rising edge of SCK starting from the first rising edge after CS goes active. The SPI protocol is controlled by opcodes. These opcodes specify the commands from the bus master to the slave device. After CS is activated, the first byte transferred from the bus master is the opcode. Following the opcode, any addresses and data are then transferred. The CS must go inactive after an operation is complete and before a new opcode can be issued. The commonly used terms in the SPI protocol are as follows: SPI Master The SPI master device controls the operations on a SPI bus. An SPI bus may have only one master with one or more slave devices. All the slaves share the same SPI bus lines and the master may select any of the slave devices using the CS pin. All of the operations must be initiated by the master activating a slave device by pulling the CS pin of the slave LOW. The master also generates the SCK and all the data transmission on SI and SO lines are synchronized with this clock. SPI Slave The SPI slave device is activated by the master through the Chip Select line. A slave device gets the SCK as an input from the SPI master and all the communicat ion is synchronized with this clock. An SPI slave never initiates a communication on the SPI bus and acts only on the instruction from the master. The FM25040B operates as an SPI slave and may share the SPI bus with other SPI slave devices. Chip Select (CS) To select any slave device, the master needs to pull down the corresponding CS pin. Any instruction can be issued to a slave device only while the CS pin is LOW. When the device is not selected, data through the SI pin is ignored and the serial output pin (SO) remains in a high-impedance state. Note A new instruction must begin with the falling edge of CS . Therefore, only one opcode can be issued for each active Chip Select cycle. Serial Clock (SCK) The Serial Clock is generated by the SPI master and the communication is synchronized with this clock after CS goes LOW. The FM25040B enables SPI modes 0 and 3 for data communication. In both of these modes, the inputs are latched by the slave device on the rising edge of SCK and outputs are issued on the falling edge. Therefore, the first rising edge of SCK signifies the arrival of the first bit (MSB) of a SPI instruction on the SI pin. Further, all data inputs and outputs are synchronized with SCK. Data Transmission (SI/SO) The SPI data bus consists of two lines, SI and SO, for serial data communication. SI is also referred to as Master Out Slave In (MOSI) and SO is referred to as Master In Slave Out (MISO). The

Bits 0 and 4-7 are fixed at ‘0’; none of these bits can be modified. the software write-protection f eatures and are nonvolatile bits. The WEL flag indicates the state of the Write Enable Latch. WREN and WRDI commands, respectively. inactive and the WREN command has been issued. Table 5 summarizes the write protection conditions. therefore, clears the Write Enable Latch. Table 2. Status Register Table 3. Status Register Bit Definition Bit 0 Don’t care This bit is non-writable and always returns ‘0’ upon read. Bit 1 (WEL) Write Enable Latch WEL indicates if the device is write enabled. This bit defaults to ‘0’ (disabled) on power-up. Bit 2 (BP0) Block Protect bit ‘0’ Used for block protection. For details, see Table 4. Bit 3 (BP1) Block Protect bit ‘1’ Used for block protection. For details, see Table 4. Bit 4-7 Don’t care These bits are non-writable and always return ‘0’ upon read. Table 4. Block Memory Write Protection Table 5. Write Protection

0 X Protected Protected Protected

and CS can toggle during a hold state. Figure 10. Memory Write (WREN not shown) Figure 11. Memory Read

0000 A8 01 A7 A6 A5 A4 A3 A10 A2 A0

0000 A8 01 A7 A6 A5 A4 A3 A11 A2 A0

Figure 12. HOLD Operation[2]

1. Figure shows HOLD operation for input mode and output mode.

each byte to experience one endurance cycle through the loop. Table 6. Time to Reach Endurance Limit for Repeating

Document Number: 001-86145 Rev. *J Page 11 of 22 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Maximum accumulated storage time Ambient temperature DC voltage applied to outputs Transient voltage (< 20 ns) Package power Surface mount lead DC output current (1 output at a time, 1s duration) .... 15 mA Electrostatic Discharge Voltage [3] Operating Range Range Ambient Temperature (TA) VDD Industrial –40 C to +85 C 4.5 V to 5.5 V Over the Operating Range Parameter Description Test Conditions Min Typ [4] Max Unit VDD Power supply 4.5 5.0 5.5 V IDD VDD supply current SCK toggling between VDD – 0.3 V and V SS, other inputs VSS or VDD – 0.3 V. SO = Open. fSCK = 1 MHz – – 0.25 mA fSCK = 20 MHz – – 4 mA ISB VDD standby current CS = VDD. All other inputs VSS or VDD.– 4 1 0 A ILI Input leakage current V SS < VIN < VDD –– ± 1 A ILO Output leakage current V SS < VOUT < VDD –– ± 1 A VIH Input HIGH voltage 0.7 × V DD –V DD + 0.3 V VIL Input LOW voltage – 0.3 – 0.3 × V DD V VOH Output HIGH voltage I OH = –2 mA V DD – 0.8 – – V VOL Output LOW voltage I OL = 2 mA – – 0.4 V VHYS [5] Input Hysteresis (CS and SCK pin) 0.05 × VDD –– V Notes 3. Electrostatic Discharge voltages specifie d in the datasheet are the JEDEC standard limits used for qualifying the device. To know the maximum value device passes for, please refer to the device qualification report available on the website. 4. Typical values are at 25 °C, V DD = VDD(typ). Not 100% tested. 5. This parameter is characterized but not 100% tested.

Document Number: 001-86145 Rev. *J Page 12 of 22 AC Test Conditions Data Retention and Endurance Parameter Description Test condition Min Max Unit TDR Data retention T A = 85 C1 0 – Y e a r s TA = 75 C3 8 – TA = 65 C 151 – NVC Endurance Over operating temperature 10 14 – Cycles Capacitance Parameter [6] Description Test Conditions Max Unit CO Output pin capacitance (SO) T A = 25 C, f = 1 MHz, VDD = VDD(typ) 8 pF CI Input pin capacitance 6p F Thermal Resistance Parameter Description Test Conditions 8-pin SOIC Unit JA Thermal resistance (junction to ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/JESD51. 148 C/W JC Thermal resistance (junction to case) 48 C/W Note 6. This parameter is characterized but not 100% tested.

Document Number: 001-86145 Rev. *J Page 13 of 22 AC Switching Characteristics Over the Operating Range Parameters [7] Description Min Max UnitCypress Parameter Alt. Parameter fSCK – SCK Clock frequency 0 20 MHz tCH – Clock HIGH time 22 – ns tCL – Clock LOW time 22 – ns tCSU tCSS Chip select setup 10 – ns tCSH tCSH Chip select hold 10 – ns tOD [8, 9, 10] tHZCS Output disable time – 20 ns tODV tCO Output data valid time – 20 ns tOH – Output hold time 0 – ns tD – Deselect time 60 – ns tR [11, 12] – Data in rise time – 50 ns tF [11, 12] – Data in fall time – 50 ns tSU tSD Data setup time 5 – ns tH tHD Data hold time 5 – ns tHS tSH HOLD setup time 10 – ns tHH tHH HOLD hold time 10 – ns tHZ [8, 9] tHHZ HOLD LOW to HI-Z – 20 ns tLZ [9] tHLZ HOLD HIGH to data active – 20 ns Notes 7. Test conditions assume a signal transition time of 5 ns or less, timing reference levels of 0.5 × VDD, input pulse levels of 10% to 90% of VDD, and output loading of the specified IOL/IOH and 30 pF load capacitance shown in AC Test Conditions on page 12. 8. t OD and tHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 9. This parameter is characterized but not 100% tested. 10. For clock high time t CH < 35 ns, the parameter tODV is extended such that tCH + tODV < 65 ns. 11. Rise and fall times measured between 10% and 90% of waveform. 12. These parameters are guaranteed by design and are not tested.

Figure 15. Power Cycle Timing

1. Slope measured at any point on VDD waveform.

Document Number: 001-86145 Rev. *J Page 16 of 22 Ordering Code Definitions

Ordering Information

agram Package Type Operating Range FM25040B-G 51-85066 8-pin SOIC Industrial FM25040B-GTR 51-85066 8-pin SOIC All these parts are Pb-free. Contact your local Cypress sales representative for availability of these parts. Option: X = blank or TR blank = Standard; TR = Tape and Reel Package Type: G = 8-pin SOIC Die revision: B Density: 040 = 4-Kbit SPI F-RAM Cypress 25FM 040 B - X G

Figure 16. 8-pin SOIC (150 Mils) Package Outline, 51-85066

Document Number: 001-86145 Rev. *J Page 18 of 22 Acronyms Document Conventions Units of MeasureAcronym Description AEC Automotive Electronics Council CPHA Clock Phase CPOL Clock Polarity EEPROM Electrically Erasable Programmable Read-Only Memory EIA Electronic Industries Alliance I/O Input/Output JEDEC Joint Electron Devices Engineering Council JESD JEDEC Standards LSB Least Significant Bit MSB Most Significant Bit F-RAM Ferroelectric Random Access Memory RoHS Restriction of Hazardous Substances SPI Serial Peripheral Interface SOIC Small Outline Integrated Circuit Symbol Unit of Measure °C degree Celsius Hz hertz kHz kilohertz K kilohm Kbit kilobit kV kilovolt MHz megahertz A microampere s microsecond mA milliampere ms millisecond ns nanosecond  ohm % percent pF picofarad V volt W watt

Document Number: 001-86145 Rev. *J Page 19 of 22 Errata This section describes the errata for the 4Kb SPI F-RAM (512 × 8, SPI) products. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Compare this document with th e device datasheet for complete functional differences. Contact your local Cypress Sales Represent ative if you have questions. You can also send your related queries directly to FRAM@cypress.com. Part Numbers Affected Qualification Status Production parts. Errata Summary The following table defines the errata applicability. 1. The Write Enable Latch (WEL) bit in the Status Register of FM25040B part doesn’t clear after executing the memory write (WRITE) operation at memory location(s) from 0x100 to 0x1FF. ■ Problem Definition As per the FM25040B datasheet “sending the WREN opcode causes the internal Write Enable Latch (WEL) to be set. A flag bit in the status register, called WEL, indicates the state of the latch. WEL=1 indicates that writes are permitted. Attempting to write the WEL bit in the status register has no effect. Completing any write operation will automatically clear the write-enable latch and will prevent further writes without another WREN command”. However, in the FM25040B part, the WEL bit doesn’t clear automat ically after writing at any me mory location(s) from 0x100 to 0x1FF. That means, after completing the write cycle with the opcode byte 0x0A, WEL bit in status register is still set and hence a further write can be issued without sending the WREN opcode. Part Number Device Characteristics FM25040B 512 × 8, 4.5 V to 5.5 V, single power supply, serial (SPI) interface F-RAM in 8-pin SOIC package. Items Part Number Silicon Revision Fix Status The Write Enable Latch (WEL) bit in the Status Register of FM25040B part doesn’t clear after executing the memory write (WRITE) operation at memory location(s) from 0x100 to 0x1FF. FM25040B-G FM25040B-GTR Rev *A None. This behavior is applicable to all listed parts in the production.

Document Number: 001-86145 Rev. *J Page 20 of 22 Status Register Status Register Bit Definition The internal state machine of FM25040B is intended to clea r the WEL bit after executing wr ite opcodes (WRITE and WRSR). However, as explained above, the WEL doesn’t clear when executing the memory write (WRITE) at location/s from 0x100 to 0x1FF. The 4Kb memory requires 9 address bits to map the entire memory array (512 × 8). To optimize the command cycle and to maintain the compatibility with the industry standard 4Kb SPI EEPROMs, the MSB of the address (9th bit) in the 4Kb device is embedded into write (WRITE) and read (READ) opcodes as shown below. For address range – 0x00 to 0xFF: WRITE opcode – 0000 A010 = 0x0000 0010 (or 0x02 in hex, A = ‘0’) READ opcode – 0000 A011 = 0x0000 0011 (or 0x03 in hex, A = ‘0’) For address range – 0x100 to 0x1FF: WRITE opcode – 0000 A010 = 0x0000 1010 (or 0x0A in hex, A = ‘1’) READ opcode – 0000 A011 = 0x0000 1011 (or 0x0B in hex, A = ‘1’) Due to a logic bug in the FM25040B state machine, the opcode byte 0x0A does not trigger clearing of WEL bit, hence the WEL bit remains set even after executing the memory write at address location/s from 0x100 to 0x1FF. ■ Parameters Affected None. ■ Trigger Condition(S) Execute the Write Enable command (WREN) followed by the write command (WRITE) to memory address range 0x100 to 0x1FF. ■ Scope of Impact None. It only allows a subsequent write (WRITE or WRSR) without sending a prior WREN command. ■ Workaround To ensure that the WEL bit is cleared after every write, the SPI host controller can issue the Write Disable (WRDI) opcode at the end of every write cycle (after CS goes high). The WRDI command clears the WEL (if set) and disables all writes until the WEL is set by sending the WREN opcode before initiating a new write operation. ■ Fix Status There is no fix planned and all the FM25040B part in production will continue with the above errata.

Document Number: 001-86145 Rev. *J Page 21 of 22 Document History Page Document Title: FM25040B, 4-Kbit (512 × 8) Serial (SPI) F-RAM Document Number: 001-86145 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 3902952 GVCH 02/25/2013 New spec. *A 3924523 GVCH 03/07/2013 Updated Power Cycle Timing: Changed minimum value of tPU parameter from 10 ms to 1 ms. *B 3994285 GVCH 05/14/2013 Added Appendix A - Errata for FM25040B. *C 4045438 GVCH 06/30/2013 All errata items are fixed and the errata is removed. *D 4226124 GVCH 01/24/2014 Converted to Cypress standard format. Updated Maximum Ratings: - Removed Moisture Sensitivity Level (MSL). - Added junction temperature and latch up current. Updated Data Retention and Endurance: - Added data retention value at 65 C and 75 C temperature. Added Thermal Resistance. Removed Package Marking Scheme (top mark). Removed Ramtron revision history. Completing Sunset Review. *E 4306361 GVCH 03/12/2014 Updated Document History Page: Fixed typo (Changed Document Number from 001-86146 to 001-86145). *F 4564960 GVCH 11/10/2014 Updated Functional Description: Added “For a complete list of related documentation, click here.” at the end. *G 4878519 ZSK / PSR 08/10/2015 Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Updated Package Diagram: spec 51-85066 – Changed revision from *F to *G. Updated to new template. *H 5397011 GVCH 08/09/2016 Updated Serial Peripheral Interface – SPI Bus: Updated WREN - Set Write Enable Latch: Updated description (Added note regarding Errata). Updated Package Diagram: spec 51-85066 – Changed revision from *G to *H. Added Errata. Updated to new template. *I 5606081 GVCH 01/27/2017 Updated Maximum Ratings: Updated Electrostatic Discharge Voltage (in compliance with AEC-Q100 standard): Changed value of “Human Body Model” from 3.5 kV to 2 kV. Changed value of “Charged Device Model” from 1.25 kV to 500 V. Removed “Machine Model” related information. Updated to new template. Completing Sunset Review. *J 5701943 GVCH 04/19/2017 Updated Maximum Ratings: Added Note 3 and referred the same note in “Electrostatic Discharge Voltage”. Updated to new template.

Document Number: 001-86145 Rev. *J Revised April 19, 2017 Page 22 of 22 FM25040B © Cypress Semiconductor Corporation, 2013–2017. This document is the property of Cypress Semiconductor Corporation and its subs idiaries, including Spansion LLC ("Cypress"). This document, including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the Software is prohibited. TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. Cypress is not liable, in whol e or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from or related to all Uninte nded Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products. Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products ARM® Cortex® Microcontrollers cypress.com/arm Automotive cypress.com/automotive Clocks & Buffers cypress.com/clocks Interface cypress.com/interface Internet of Things cypress.com/iot Memory cypress.com/memory Microcontrollers cypress.com/mcu PSoC cypress.com/psoc Power Management ICs cypress.com/pmic Touch Sensing cypress.com/touch USB Controllers cypress.com/usb Wireless Connectivity cypress.com/wireless PSoC® Solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Forums | WICED IOT Forums | Projects | Video | Blogs | Training | Components Technical Support cypress.com/support