FM24CL64B CYPRESS | Alldatasheet
Document overview
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Technical content
Features
64K bit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits High Endurance 1014 Read/Writes 38 year Data Retention NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 1 MHz maximum bus frequency Direct hardware replacement for EEPROM Supports legacy timing for 100 kHz & 400 kHz Low Power Operation 2.7V-3.6V Operation 100 A Active Current (100 kHz) 3 A (typ.) Standby Current Industry Standard Configuration Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC and TDFN Packages
Description
The FM24CL64B is a 64-kilobit nonvolatile memory employing an advanced f erroelectric process. A ferroelectric random access memory or F-RAM is nonvolatile and performs reads and writes like a RAM. It provide s reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problem s caused by EEPROM and other nonvolatile memories. The FM 24CL64B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM 24CL64B is capable of supporting 10 14 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM 24CL64B ideal for nonvolatile memory applicat ions requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM 24CL64B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop -in repla cement. The FM24CL64B is available in an industry stan dard 8 - pin SOIC package and uses a familiar two -wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration VSS VDD WP SCL SDA Pin Names Function A0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage
Ordering Information
FM24CL64B-G “Green”/RoHS 8-pin SOIC FM24CL64B-GTR “Green”/RoHS 8-pin SOIC, Tape & Reel FM24CL64B-DG “Green”/RoHS 8-pin TDFN FM24CL64B-DGTR “Green”/RoHS 8-pin TDFN, Tape & Reel VSS VDD WP SCL SDA Top View
Figure 1. FM24CL64B Block Diagram open-drain and is intended to be wire -OR’d with other devices on the two -wire bus. driver includes slope control for falling edges. A pull-up resistor is required. incorporates a Schmitt trigger input for noise immunity.
zero beyond the time needed for the serial protocol. more detail in the interface section below. vulnerable to noise during much of the cycle. users but is described in this section. device on the bus that is being controlled is a slave. The FM24CL64B always is a slave device. Figure 2. Typical System Configuration
Rev. 3.0 Jan. 2012 Page 8 of 13 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +5.0V VIN Voltage on any pin with respect to VSS -1.0V to +5.0V and VIN < VDD+1.0V * TSTG Storage Temperature -55C to +125C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 4kV 1.25kV 300V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD =2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 2.7 3.3 3.65 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 100 170 300 ISB Standby Current 3 6 A 2 ILI Input Leakage Current ±1 A 3 ILO Output Leakage Current ±1 A 3 VIL Input Low Voltage -0.3 0.3 VDD V VIH Input High Voltage 0.7 VDD VDD + 0.3 V VOL Output Low Voltage @ IOL = 3.0 mA 0.4 V RIN Address Input Resistance (WP, A2-A0) For VIN = VIL (max) For VIN = VIH (min) VHYS Input Hysteresis 0.05 VDD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is strong (40K) when the input voltage is below VIL and weak (1M) when the input voltage is above VIH.
Rev. 3.0 Jan. 2012 Page 9 of 13 AC Parameters (TA = -40 C to + 85 C, VDD =2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 s tHIGH Clock High Period 4.0 0.6 0.4 s tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 s tBUF Bus Free Before New Transmission 4.7 1.3 0.5 s tHD:STA Start Condition Hold Time 4.0 0.6 0.25 s tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 s tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 s tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to bo th read and write operations. 1 The speed-related specifications are guaranteed characteristic points along a continuous curve of operation from DC to 1 MHz. 2 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 3V) Symbol Parameter Max Units Notes CI/O Input/Output capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing VDD min.VDD SDA,SCL tVR tPDtPU tVF Power Cycle Timing (TA = -40C to +85C, VDD = 2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU Power Up (VDD min) to First Access (Start condition) 10 - ms tPD Last Access (Stop condition) to Power Down (VDD min) 0 - s tVR VDD Rise Time 30 - s/V 1 tVF VDD Fall Time 30 - s/V 1 Notes 1. Slope measured at any point on VDD waveform.
Rev. 3.0 Jan. 2012 Page 10 of 13 AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0.1 VDD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 VDD Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant datasheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tS U:S DA Start tR tF Stop Start tB UF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DA T tS U:DAT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention Symbol Parameter Min Max Units Notes TDR @ +85ºC 10 - Years @ +80ºC 19 - Years @ +75ºC 38 - Years 3.6V Output 1100 100 pF
Rev. 3.0 Jan. 2012 Page 11 of 13 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 0.40 1.27 0.19 0.25 - 8 Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXXX= part number, P= package type (G=SOIC) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24CL64B, “Green” SOIC package, Year 2010, Work Week 47 FM24CL64BG A00002G1 RIC1047 XXXXXXXP RLLLLLLL RICYYWW
Rev. 3.0 Jan. 2012 Page 12 of 13 8-pin TDFN (4.0mm x 4.5mm body, 0.95mm pitch) Pin 1 4.00 ±0.1 4.50 ±0.1 0.75 ±0.05 0.40 ±0.05 0.95 0.20 REF. Pin 1 ID 0.0 - 0.05
2.85 REF
3.60 ±0.10 2.60 ±0.10 Exposed metal pad. Do not connect to anything except Vss. 4.30 0.45 0.95 Recommended PCB Footprint 0.40 2.70 3.70 0.30 ±0.1 Note: All dimensions in millimeters. Legend: R=Ramtron, G=”green” TDFN package, XXXX=base part number LLLL= lot code, YY=year, WW=work week Example: “Green” TDFN package, FM24CL64B, Lot 0003, Industrial temperature, Year 2011, Work Week 07 R4L64B 0003 1107 RGXXXX LLLL YYWW
Rev. 3.0 Jan. 2012 Page 13 of 13
Revision History
1.0 11/10/2010 Initial Release 1.1 12/20/2010 Added 4x4.5mm DFN package. 1.2 2/15/2011 Added ESD ratings. Updated DFN package marking. Changed t PU and t VF spec limits. 3.0 1/6/2012 Changed to Production status. Changed tVF spec.