FM24C64B

FM24C64B_13 CYPRESS | Alldatasheet

Document overview

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Technical content

Features

64K bit Ferroelectric Nonvolatile RAM Organized as 8,192 x 8 bits High Endurance 1 Trillion (1012) Read/Writes

38 Year Data Retention

NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 1 MHz maximum bus frequency Direct hardware replacement for EEPROM Supports legacy timing for 100 kHz & 400 kHz Low Power Operation 5V operation 100 A Active Current (100 kHz) A (typ.) Standby Current Industry Standard Configuration Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC (-G)

Description

The FM 24C64B is a 64 -kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the co mplexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM 24C64B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has b een successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling . The FM 24C64B is capable of supporting 10 12 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM 24C64B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can c ause data loss. The combination of features allows more frequent data writes with less overhead for the system. The FM24C64B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop -in replacement. The FM24C64B is available in an industry standard 8-pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration VSS VDD WP SCL SDA Pin Names Function A0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage

Ordering Information

FM24C64B-G “Green”/RoHS 8-pin SOIC FM24C64B-GTR “Green”/RoHS 8-pin SOIC, Tape & Reel

Figure 1. FM24C64B Block Diagram edges. A pull-up resistor is required. input also incorporates a Schmitt trigger input for improved noise immunity. all addresses may be written. This pin is pulled down internally.

Figure 4. Slave Address requires two bytes. The first is the MSB (upper byte). a single read or write operation. bits from the master and then send an Acknow ledge. counter will wrap from 1FFFh to 0000h. write ca n occur immediately following a write. (VSS) will deactivate this feature.

Document Number: 001-84454 Rev. *B Page 8 of 15 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +7.0V VIN Voltage on any signal pin with respect to VSS -1.0V to +7.0V and VIN < VDD+1.0V * TSTG Storage Temperature -55 C to + 125 C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 4kV 1.25kV 200V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational secti on of this specificat ion is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 100 200 400 A A A ISB Standby Current 4 10 A 2 ILI Input Leakage Current ±1 A 3 ILO Output Leakage Current ±1 A 3 VIL Input Low Voltage -0.3 0.3 VDD V VIH Input High Voltage 0.7 VDD VDD + 0.3 V VOL Output Low Voltage @ IOL = 3 mA 0.4 V RIN Input Resistance (WP, A2-A0) For VIN = VIL (max) For VIN = VIH (min) K M VHYS Input Hysteresis 0.05 VDD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is strong (40K ) when the input voltage is below VIL and much weaker (1M when the input voltage is above VIH.

Document Number: 001-84454 Rev. *B Page 9 of 15 AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz tLOW Clock Low Period 4.7 1.3 0.6 s tHIGH Clock High Period 4.0 0.6 0.4 s tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 s tBUF Bus Free Before New Transmission 4.7 1.3 0.5 s tHD:STA Start Condition Hold Time 4.0 0.6 0.25 s tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 s tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 1 tF Input Fall Time 300 300 100 ns 1 tSU:STO Stop Condition Setup 4.0 0.6 0.25 s tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/output capacitance (SDA) 8 pF 1 CIN Input capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing VDD min.VDD SDA,SCL tVR tPDtPU tVF Power Cycle Timing (TA = -40 C to +85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU Power Up (VDD min) to First Access (Start condition) 10 - ms tPD Last Access (Stop condition) to Power Down (VDD min) 0 - s tVR VDD Rise Time 30 - s/V 1 tVF VDD Fall Time 30 - s/V 1 Notes 1. Slope measured at any point on VDD waveform.

Document Number: 001-84454 Rev. *B Page 10 of 15 AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0.1 VDD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 VDD Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specific ations are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIG H 1/fSCL tLO W tSP tSP Acknowledge tHD:DAT tSU:DAT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention Symbol Parameter Min Max Units Notes TDR @ +85ºC 10 - Years @ +80ºC 19 - Years @ +75ºC 38 - Years 5.5V Output 1700 100 pF

Document Number: 001-84454 Rev. *B Page 11 of 15 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 0.40 1.27 0.19 0.25 - 8 Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXXX= part number, P= package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24C64B, “Green” SOIC package, Year 2010, Work Week 47 FM24C64B-G A00002G1 RIC1047 XXXXXXX-P LLLLLLL RICYYWW

Document Number: 001-84454 Rev. *B Page 12 of 15

Revision History

1.0 11/10/2010 Initial Release 1.1 12/20/2010 Changed VIH (max) to VDD+0.3V. 1.2 2/7/2011 Added ESD ratings. 1.3 2/15/2011 Changed tPU and tVF spec limits. 3.0 1/6/2012 Changed to Production status. Changed tVF spec. Updated WP pin description.

Document Number: 001-84454 Rev. *B Page 13 of 15 Errata All errata for this product are fixed effective date code 1 148 (YY=11, WW= 48). For more information refer to datasheet 001-84454 Rev. *A or contact Cypress Technical Support at http://www.cypress.com/support.

Document Number: 001-84454 Rev. *B Page 14 of 15 Document History Document Title: FM24C64B 64Kb Serial 5V F-RAM Memory Document Number: 001-84454 Revision ECN Orig. of Change Submission Date Description of Change ** 3902204 GVCH 02/25/2013 New Spec *A 3996669 GVCH 05/13/2013 Added Appendix A - Errata for FM24C64B *B 4045469 GVCH 06/30/2013 All errata items are fixed and the errata is removed.

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