FM21L16-60-TGTR

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Features

■ 2-Mbit ferroelectric random access memory (F-RAM) logically organized as 128 K × 16 ❐ Configurable as 256 K × 8 using UB and LB ❐ High-endurance 100 trillion (1014) read/writes ❐ 151-year data retention (see the Data Retention and Endurance table) ❐ NoDelay™ writes ❐ Page mode operation to 30-ns cycle time ❐ Advanced high-reliability ferroelectric process ■ SRAM compatible ❐ Industry-standard 128 K × 16 SRAM pinout ❐ 60-ns access time, 110-ns cycle time ■ Advanced features ❐ Software-programmable block write-protect ■ Superior to battery-backed SRAM modules ❐ No battery concerns ❐ Monolithic reliability ❐ True surface mount solution, no rework steps ❐ Superior for moisture, shock, and vibration ■ Low power consumption ❐ Active current 8 mA (typ) ❐ Standby current 90 A (typ) ❐ Sleep mode current 5 A (max) ■ Low-voltage operation: VDD = 2.7 V to 3.6 V ■ Industrial temperature: –40 C to +85 C ■ 44-pin thin small outline package (TSOP) Type II ■ Restriction of hazardous substances (RoHS) compliant Functional Overview The FM21L16 is a 128 K × 16 nonvolatile memory that reads and writes similar to a standard SRAM. A ferroelectric random access memory or F-RAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 151 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and high write endurance make the F-RAM superior to other types of memory. The FM21L16 operation is similar to that of other RAM devices and therefore, it can be used as a drop-in replacement for a standard SRAM in a system. Re ad and write cycles may be triggered by CE or simply by changing the address. The F-RAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM21L16 ideal for nonvolatile memory applications requiring frequent or rapid writes. The FM21L16 includes a low voltage monitor that blocks access to the memory array when V DD drops below V DD min. The memory is protected against an inadvertent access and data corruption under this condition. The device also features software-controlled write prot ection. The memory array is divided into 8 uniform blocks, each of which can be individually write protected. The device is available in a 400-mil, 44-pin TSOP-II surface mount package. Device specifications are guaranteed over the industrial temperature range –40 °C to +85 °C. For a complete list of related documentation, click here. Address Latch & Write Protect CE Control Logic WE Block & Row Decoder A I/O Latch & Bus Driver OE DQ

16 K x 16 block 16 K x 16 block

A . . . Column Decoder . . . UB, LB ZZ 16-0 16-2 A1-0 15-0 Logic Block Diagram Not recommended for new designs.

Figure 1. 44-pin TSOP II pinout address lines A1–A0 may be used for page mode read and write operations. DQ15–DQ0 Input/Output Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array. available. Deasserting OE HIGH tristates the DQ pins. UB Input Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH. LB Input Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH. condition. ZZ must be HIGH for a normal read/write operation. If unused, tie ZZ pin to VDD. VSS Ground Ground for the device. Must be connected to the ground of the system. VDD Power supply Power supply input to the device. NC No connect No connect. This pin is not connected to the die. Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 4 of 22 Device Operation The FM21L16 is a word wide F-RAM memory logically organized as 131,072 × 16 and accessed using an industry-standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation, which provides high-speed access to addresses within a page (row). Access to a different page requires that either CE transitions LOW or the upper address (A 16–A2) changes. See the Functional Truth Table on page 17 for a complete description of read and write modes. Memory Operation Users access 131,072 memory locations, each with 16 data bits through a parallel interface. The F-RAM array is organized as eight blocks, each having 4096 rows. Each row has four column locations, which allow fast access in page mode operation. When an initial address is latched by the falling edge of CE subsequent column locations may be accessed without the need to toggle CE . When CE is deasserted HIGH, a pre-charge operation begins. Writes occur immediately at the end of the access with no delay. The WE pin must be toggled for each write operation. The write data is stored in the nonvolatile memory array immediately, which is a feature unique to F-RAM called NoDelay writes. Read Operation A read operation begins on the falling edge of CE . The falling edge of CE causes the address to be latched and starts a memory read cycle if WE is HIGH. Data becomes available on the bus after the access time is met. When the address is latched and the access completed, a new access to a random location (different row) may begin while CE is still LOW. The minimum cycle time for random addresses is tRC. Note that unlike SRAMs, the FM21L16's CE -initiated access time is faster than the address access time. The FM21L16 will drive the data bus when OE and at least one of the byte enables (UB , LB) is asserted LOW. The upper data byte is driven when UB is LOW, and the lower data byte is driven when LB is LOW. If OE is asserted after the memory access time is met, the data bus will be driven with valid data. If OE is asserted before completing the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven to the bus. When OE is deasserted HIGH, the data bus will remain in a HI-Z state. Write Operation In the FM21L16, writes occur in the same interval as reads. The FM21L16 supports both CE and WE controlled write cycles. In both cases, the address A16–A2 is latched on the falling edge of CE. In a CE -controlled write, the WE signal is asserted before beginning the memory cycle. That is, WE is LOW when CE falls. In this case, the device begins the memory cycle as a write. The FM21L16 will not drive the data bus regardless of the state of OE as long as WE is LOW. Input data must be valid when CE is deasserted HIGH. In a WE -controlled write, the memory cycle begins on the falling edge of CE. The WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if OE is LOW; however, it will be HI-Z when WE is asserted LOW. The CE- and WE-controlled write timing cases are shown in the page 14. Write access to the array begins on the falling edge of WE after the memory cycle is initiated. The write access terminates on the rising edge of WE or CE , whichever comes first. A valid write operation requires the user to meet the access time specification before deasserting WE or CE. The data setup time indicates the interval during which data cannot change before the end of the write access (rising edge of WE or CE). Unlike other nonvolatile memory technologies, there is no write delay with F-RAM. Because the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The F-RAM array is organized as eight blocks, each having 4096 rows. Each row has four column-address locations. Address inputs A 1–A0 define the column address to be accessed. An access can start on any column address, and other column locations may be accessed without the need to toggle the CE pin. For fast access reads, after the first data byte is driven to the bus, the column address inputs A 1–A0 may be changed to a new value. A new data byte is then driven to the DQ pins no later than tAAP, which is less than half the initial read access time. For fast access writes, the first write pulse defines the first write access. While CE is LOW, a subsequent write pulse along with a new column address provides a page mode write access. Pre-charge Operation The pre-charge operation is an in ternal condition in which the memory state is prepared for a new access. Pre-charge is user-initiated by driving the CE signal HIGH. It must remain HIGH for at least the minimum pre-charge time, tPC. Pre-charge is also activated by changing the upper addresses, A16–A2. The current row is first closed before accessing the new row. The device automatically detects an upper order address change, which starts a pre-charge operation. The new address is latched and the new read data is valid within the t AA address access time; see Figure 9 on page 13. A similar sequence occurs for write cycles; see Figure 14 on page 14 . The rate at which random addresses can be issued is tRC and tWC, respectively. Sleep Mode The device incorporates a sleep mode of operation, which allows the user to achieve the lowest power supply current condition. It enters a low-power sleep mode by asserting the ZZ pin LOW. Read and write operations must complete before the ZZ pin going LOW. When ZZ is LOW, all pins are ignored except the ZZ pin. When ZZ is deasserted HIGH, there is some time delay (tZZEX) before the user can access the device. If sleep mode is not used, the ZZ pin should be tied to VDD. Not recommended for new designs.

Figure 3. Write-Protect State Machine Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 9 of 22 Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. These user guidelines are not tested. Maximum accumulated storage time Ambient temperature Voltage applied to outputs Transient voltage (< 20 ns) on Package power dissipation capability (T Surface mount Pb soldering DC output current (1 output at a time, 1s duration) .... 15 mA Static discharge voltage Human Body Model ( Charged Device Model (JEDEC Std JESD22-C101-D) .... 800 V Operating Range Range Ambient Temperature (TA) VDD Industrial –40 C to +85 C 2.7 V to 3.6 V Over the Operating Range Parameter Description Test Conditions Min Typ [2] Max Unit VDD Power supply voltage 2.7 3.3 3.6 V IDD VDD supply current V DD = 3.6 V, CE cycling at min. cycle time. All inputs toggling at CMOS levels (0.2 V or V DD – 0.2 V), all DQ pins unloaded. –8 1 2 m A ISB Standby current VDD = 3.6 V, CE at VDD, All other pins are static and at CMOS levels (0.2 V or V DD – 0.2 V), ZZ is HIGH TA = 25 C– 9 0 1 5 0 µ A TA = 85 C– –2 7 0 µ A IZZ Sleep mode current V DD = 3.6 V, ZZ is LOW, all other inputs at CMOS levels (0.2 V or VDD – 0.2 V). TA = 25 C ––5 µ A TA = 85 C ––8 µ A ILI Input leakage current V IN between VDD and VSS –– + 1µ A ILO Output leakage current V OUT between VDD and VSS –– + 1µ A VIH Input HIGH voltage 2.2 – V DD + 0.3 V VIL Input LOW voltage – 0.3 – 0.6 V VOH1 Output HIGH voltage I OH = –1.0 mA 2.4 – – V VOH2 Output HIGH voltage I OH = –100 µA VDD – 0.2 – – V VOL1 Output LOW voltage I OL = 2.1 mA – – 0.4 V VOL2 Output LOW voltage I OL = 100 µA – – 0.2 V Note 2. Typical values are at 25 °C, V DD = VDD (typ). Not 100% tested. Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 10 of 22 AC Test Conditions Data Retention and Endurance Parameter Description Test condition Min Max Unit TDR Data retention TA = 85 C 10 – Years TA = 75 C3 8 – TA = 65 C1 51 – NVC Endurance Over operating temperature 1014 – Cycles Capacitance Parameter Description Test Conditions Max Unit CI/O Input/Output capacitance (DQ) T A = 25 C, f = 1 MHz, VDD = VDD(Typ) 8 pF CIN Input capacitance 6p F CZZ Input capacitance of ZZ pin 8 pF Thermal Resistance Parameter Description Test Conditions 44-pin TSOP II Unit JA Thermal resistance (junction to ambient) Test conditions follow standard test methods and procedures for measuring thermal impedance, in accordance with EIA/JESD51. 102 C/W JC Thermal resistance (junction to case) 22 C/W Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 11 of 22 AC Switching Characteristics Over the Operating Range Parameters [3] Description Min Max UnitCypress Parameter Alt Parameter SRAM Read Cycle tCE tACE Chip enable access time – 60 ns tRC – Read cycle time 110 – ns tAA – Address access time – 110 ns tOH tOHA Output hold time 20 – ns tAAP – Page mode address access time – 25 ns tOHP – Page mode output hold time 5 – ns tCA – Chip enable active time 60 10,000 ns tPC – Pre-charge time 50 – ns tBA tBW UB, LB access time – 20 ns tAS tSA Address setup time (to CE LOW) 0– ns tAH tHA Address hold time (CE Controlled) 60 – ns tOE tDOE Output enable access time – 15 ns tHZ [4, 5] tHZCE Chip Enable to output HI-Z – 10 ns tOHZ [4, 5] tHZOE Output enable HIGH to output HI-Z – 10 ns tBHZ [4, 5] tHZBE UB, LB HIGHHIGH to output HI-Z – 10 ns Notes 3. Test conditions assume a signal transition time of 3 ns or less, timing reference levels of 0.5 × V DD, input pulse levels of 0 to 3 V, output loading of the specified IOL/IOH and load capacitance shown in AC Test Conditions on page 10. 4. t HZ, tOHZ and tBHZ are specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 5. This parameter is characterized but not 100% tested. Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 12 of 22 SRAM Write Cycle tWC tWC Write cycle time 110 – ns tCA – Chip enable active time 60 10,000 ns tCW tSCE Chip enable to write enable HIGH 60 – ns tPC – Pre-charge time 50 – ns tPWC – Page mode write enable cycle time 25 – ns tWP tPWE Write enable pulse width 16 – ns tAS tSA Address setup time (to CE LOW) 0 – ns tASP – Page mode address setup time (to WE LOW) 8 – ns tAHP – Page mode address hold time (to WE LOW) 15 – ns tWLC tPWE Write enable LOW to chip disabled 25 – ns tBLC tBW UB, LB LOW to chip disabled 25 – ns tWLA – Write enable LOW to A16-2 change 25 – ns tAWH – A16-2 change to write enable HIGH 110 – ns tDS tSD Data input setup time 14 – ns tDH tHD Data input hold time 0 – ns tWZ [6, 7] tHZWE Write enable LOW to output HI-Z – 10 ns tWX [7] – Write enable HIGH to output driven 10 – ns tWS [8] – Write enable to CE LOW setup time 0 – ns tWH [8] – Write enable to CE HIGH hold time 0 – ns AC Switching Characteristics (continued) Over the Operating Range Parameters [3] Description Min Max UnitCypress Parameter Alt Parameter Notes 6. t WZ is specified with a load capacitance of 5 pF. Transition is measured when the outputs enter a high impedance state. 7. This parameter is characterized but not 100% tested. 8. The relationship between CE and WE determines if a CE- or WE-controlled write occurs. The parameters tWS and tWH are not tested. Not recommended for new designs.

Figure 15. Page Mode Write Cycle Timing

1. UB and LB to show byte enable and byte masking cases.

Not recommended for new designs.

Figure 16. Power Cycle and Sleep Mode Timing

1. Slope measured at any point on the VDD waveform.
2. Cypress cannot test or characterize all VDD power ramp profiles. The behavior of the internal circuits is difficult to predict when VDD is below the level of a transistor

threshold voltage. Cypress strongly recommends that VDD power up faster than 100 ms through the range of 0.4 V to 1.0 V. Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 17 of 22 Functional Truth Table CE WE A16-2 A1-0 ZZ Operation [14, 15] X X X X L Sleep Mode H X X X H Standby/Idle L H H V V V V H H Read L H No Change Change H Page Mode Read L H Change V H Random Read L L L V V V V H H CE -Controlled Write[15] L ↓ VVH W E -Controlled Write [15, 16] L ↓ No Change V H Page Mode Write [17] L X X X X X X H H Starts pre-charge Byte Select Truth Table WE OE LB UB Operation [18] H H X X Read; Outputs disabled XHH H L H L Read upper byte; HI-Z lower byte L H Read lower byte; HI-Z upper byte L L Read both bytes L X H L Write upper byte; Mask lower byte L H Write lower byte; Mask upper byte L L Write both bytes Notes 14. H = Logic HIGH, L = Logic LOW, V = Valid Data, X = Don't Care, ↓ = toggle LOW, ↑ = toggle HIGH. 15. For write cycles, data-in is latched on the rising edge of CE or WE, whichever comes first. 16. WE-controlled write cycle begins as a Read cycle and then A16-2 is latched. 17. Addresses A1-0 must remain stable for at least 10 ns during page mode operation. 18. Assumes CE is LOW and ZZ is HIGH for all cases.The UB and LB pins may be grounded if 1) the system does not perform byte writes and 2) the device is not configured as a 256 K x 8. Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 18 of 22 Ordering Code Definitions

Ordering Information

Access time (ns) Ordering Code Package Diagram Package Type Operating Range

60 FM21L16-60-TG 51-85087 44-pin TSOP II Industrial

All the above parts are Pb-free. Option: blank = Standard; TR = Tape and Reel Package Type: TG = 44-pin TSOP II Access Time: 60 ns I/O Width: × 16 Voltage: 2.7 V to 3.6 V 2-Mbit Parallel F-RAM Cypress 21FM L 16 - 60 - TG TR Not recommended for new designs.

Figure 17. 44-pin TSOP Package Outline, 51-85087 Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 20 of 22 Acronyms Document Conventions Units of MeasureAcronym Description CPU Central Processing Unit CMOS Complementary Metal Oxide Semiconductor EIA Electronic Industries Alliance F-RAM Ferroelectric Random Access Memory I/O Input/Output MCU Microcontroller Unit MPU Microprocesser Unit RoHS Restriction of Hazardous Substances R/W Read and Write SRAM Static Random Access Memory TSOP Thin Small Outline Package Symbol Unit of Measure °C degree Celsius Hz hertz kHz kilohertz k kilohm MHz megahertz A microampere F microfarad s microsecond mA milliampere ms millisecond M megaohm ns nanosecond  ohm % percent pF picofarad V volt W watt Not recommended for new designs.

Document Number: 001-86191 Rev. *D Page 21 of 22 Document History Page Document Title: FM21L16, 2-Mbit (128 K × 16) F-RAM Memory Document Number: 001-86191 Rev. ECN No. Orig. of Change Submission Date Description of Change ** 3912933 GVCH 02/25/2013 New spec *A 4191807 GVCH 11/14/2013 Added watermark as “Not recommended for new designs.” *B 4274811 GVCH 03/11/2014 Typo fixed: Changed da tasheet status from “Preliminary to Final” Converted to Cypress standard format Updated Maximum Ratings table - Removed Moisture Sensitivity Level (MSL) - Added junction temperature and latch up current Updated Data Retention and Endurance table Added Thermal Resistance table Typo error fixed: Updated Address range from A17-A0 to A16-A0 for Figure 12 and Figure 13 Removed Package Marking Scheme (top mark) *C 4574376 GVCH 11/19/2014 Added related documentation hyperlink in page 1. *D 4879990 ZSK / PSR 08/11/2015 Updated Maximum Ratings: Removed “Maximum junction temperature”. Added “Maximum accumulated storage time”. Added “Ambient temperature with power applied”. Updated to new template. Not recommended for new designs.

Document Number: 001-86191 Rev. *D Revised August 11, 2015 Page 22 of 22 All products and company names mentioned in this document may be the trademarks of their respective holders. FM21L16 © Cypress Semiconductor Corporation, 2013-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subj ect to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to t he materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless PSoC® Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support Not recommended for new designs.