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Issue Date: Oct. 01, 2008 MR27V6441L 64M–Word × 1–Bit Serial Production Programmed ROM (P2ROM) GENERAL DESCRIPTION The MR27V6441L is a 64 Mbit Production Programmed Read-Only Memory, which is configured as 67,108,864 word × 1-bit. The MR27V6441L supports a simple read operation using a single 3.3V power supply and a Serial Peripheral Interface (SPI) compatible serial bus. The MR27V6441L have data programmed and have functions tested at LAPIS Semiconductor factory. (Using the DC pins for the programming function is NOT allowed.)
FEATURES
PIN CONFIGURATION (TOP VIEW)· 67,1 08,864-word × 1-bit configuration
- +3.0 V to 3.6 V power supply
- Access time 33 MHz serial clock (FAST-READ)
20 MHz serial clock (READ)
- Read Identification Instruction
- Active read current 30 mA MAX (FAST-READ) 20 mA MAX (READ)
- Standby current 50 µA MAX
- Serial Clock Input and Data Input/Output
- Input Data Format 1-byte command code, 3-byte address, 1-byte dummy (FAST-READ) 1-byte command code, 3-byte address (READ) PACKAGES
- MR27V6441L-xxxMP 16-pin plastic SOP (P-SOP16-375-1.27-K) PIN DESCRIPTIONS Pin name Functions #CS Chip Select SI Serial Data Input SO Serial Data Output SCLK Clock Input VCC Power supply voltage VSS Ground DC Don’t care ( 0v - Vcc ) <for reference> Program power supply voltage Vpp under Programming operation NC No connection 16SOP NC VCC NC DC NC NC #CS SO SCLK SI 2 NC 3 NC 4 NC 5 NC 6 VSS 7 NC 8
Command Read Array (byte) Note 1st 03[H] 1 2nd AD1 2 3rd AD2 2 4th AD3 2 Action N byte read out until #CS goes high 3 Note: 1. The 1 st command 03[H] is a Read command 2. AD1 to AD3 are address input data 3. Data output Details of Command are shown as follows. 1-byte command code READ: 0 0 0 0 0 0 1 1 3-byte address AD1: X A22 A21 A20 A19 A18 A17 A16 AD2: A15 A14 A13 A12 A11 A10 A9 A8 AD3: A7 A6 A5 A4 A3 A2 A1 A0 Note: X: Dummy bit
FAST-READ COMMAND DEFINITION Command Read Array (byte) Note 1st 0B[H] 1 2nd AD1 2 3rd AD2 2 4th AD3 2 5th X 3 Action N byte read out until #CS goes high 4 Note: 1. The 1 st command 0B[H] is a Read command 2. AD1 to AD3 are address input data 3. X is a dummy cycle 4. Data output Details of Command are shown as follows. 1-byte command code FAST-READ: 0 0 0 0 1 0 1 1 3-byte address AD1: X A22 A21 A20 A19 A18 A17 A16 AD2: A15 A14 A13 A12 A11 A10 A9 A8 AD3: A7 A6 A5 A4 A3 A2 A1 A0 Note: X: Dummy bit
READ IDENTIFICATION COMMAND DEFINITION Command Read Array (byte) Note 1st 9F[H] 1 Action 3 byte read out 2 Note: 1. The 1 st command 9F[H] is a Read Identification command 2. Identification output Details of Command are shown as follows. 1-byte command code RDID 1 0 0 1 1 1 1 1 IDENTIFICATION DEFINITION Device Identification Manufacturer Identification Type Capacity AE[H] 41[H] 15[H]
- Command “03h” or “0Bh” makes this LSI become and keep active mode until next #CS High. 2. Incorrect command makes this LSI become and keep standby mode until next #CS Low. In standby mode, SO pin is High-Z. COMMAND DESCRIPTION 1. Read Array This command consists of the 4-byte code. The 1 st code is a command which decides if the device becomes standby or active mode. The 1st code “03h”activates the device. The 2nd code to the 4th code are address. 2. Fast-Read Array This command consists of the 5-byte code. The 1 st code is a command which decides if the device becomes standby or active mode. The 1st code “0Bh”activates the device. The 2nd code to the 4th code are address. The 5th code is a dummy cycle. 3. Read Identification Array This command consists of the 1-byte code. The 1 st code is a command which decides if the device becomes standby or active mode. The 1st code “9Fh”activates the device. 4. Standby When #CS is high , the device is put in standby mode at the next rising edge of SCLK. Maximum standby current is 50uA. When the above-mentioned 1 st code is incorrect command , the device is put in standby mode at the next rising edge of SCLK. DATA SEQUENCE The data is serially sent out through SO pin, synchronized with the falling edge of SCLK. Meanwhile input data is also serially read in through SI pin, synchronized with the rising edge of SCLK. The bit sequence for both input and output data are bit7 (MSB) first, bit6, bit5, …, and bit0(LSB). ADDRESS SEQUENCE The address assignment is described at the COMMAND DEFINITION on page 2 or 3.
Parameter Symbol Condition Value Unit Storage temperature Tstg — –55 to 125 °C Input voltage VI –0.5 to VCC+0.5 V Output voltage VO –0.5 to VCC+0.5 V Power supply voltage VCC relative to VSS –0.5 to 5 V Power dissipation per package PD Ta = 25°C 1.0 W Output short circuit current IOS — 10 mA RECOMMENDED OPERATING CONDITIONS (Ta = 0 to 70°C) Parameter Symbol Condition Min. Typ. Max. Unit Operating temperature under bias Ta 0 — 70 °C VCC power supply voltage VCC 3.0 — 3.6 V Input “H” level VIH 2.4 — VCC+0.5∗ V Input “L” level VIL VCC = 3.0 to 3.6 V –0.5∗∗ — 0.6 V Voltage is relative to VSS. ∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns. PIN CAPACITANCE (VCC = 3.3 V, Ta = 25°C, f = 1 MHz) Parameter Symbol Condition Min. Typ. Max. Unit Input C IN1 V I = 0 V — — 10 Output C OUT V O = 0 V — — 10 DC C DC V I = 0 V — — 200 pF
ELECTRICAL CHARACTERISTICS
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C) Parameter Symbol Condition Min. Typ. Max. Unit Input leakage current ILI V I = 0 to VCC — — 10 μA Output leakage current ILO V O = 0 to VCC — — 10 μA ICCSC #CS = VCC — — 50 μA VCC power supply current (Standby) ICCST #CS = VIH — — 1 mA VCC power supply current (Read) ICC1 #CS = VIL f=20MHz — — 20 mA VCC power supply current (Fast-Read) ICC1F #CS = VIL f=33MHz — — 30 mA Input “H” level VIH — 2.4 — VCC+0.5∗ V Input “L” level VIL — –0.5∗∗ — 0.6 V Output “H” level VOH I OH = –100 μA 2.4 — — V Output “L” level VOL I OL = 500 μA — — 0.4 V Voltage is relative to VSS. ∗ : Vcc+1.5V(Max.) when pulse width of overshoot is less than 10ns. ∗∗ : -1.5V(Min.) when pulse width of undershoot is less than 10ns.
(VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C) Parameter Symbol Condition Min. Max. Unit Clock frequency tSCLK — — 33 MHz Clock high time tSKH — 12 — ns Clock low time tSKL — 12 — ns Clock rise time tR — — 3 ns Clock fall time tF — — 3 ns #CS lead clock time tCSA — 10 — ns #CS setup time tCS — 10 — ns #CS lag clock time tCSB — 5 — ns #CS hold time tCH — 5 — ns #CS high time tCSH — 80 — ns SI setup time tDS — 5 — ns SI hold time tDH — 10 — ns Access time tAA — — 15 ns SO hold time tDOH — 0 — ns SO floating time tDOZ — — 10 ns READ (VCC = 3.3 V ± 0.3 V, Ta = 0 to 70°C) Parameter Symbol Condition Min. Max. Unit Clock frequency tSCLK — — 20 MHz Clock high time tSKH — 20 — ns Clock low time tSKL — 20 — ns Clock rise time tR — — 5 ns Clock fall time tF — — 5 ns #CS lead clock time tCSA — 10 — ns #CS setup time tCS — 10 — ns #CS lag clock time tCSB — 5 — ns #CS hold time tCH — 5 — ns #CS high time tCSH — 80 — ns SI setup time tDS — 5 — ns SI hold time tDH — 10 — ns Access time tAA — — 15 ns SO hold time tDOH — 0 — ns SO floating time tDOZ — — 10 ns Measurement conditions Output load Input signal level 0 V/Vcc Output Input timing reference level 0.3Vcc/0.7Vcc O utput load 30 pF 30 pF (Including scope and jig) Output timing reference level 0.5Vcc
TIMING CHART (READ CYCLE) Serial Data Input/Output Timing Incorrect command makes this LSI become and keep standby mode until next #CS rising edge. In standby mode, SO pin is High-Z. SI BIT 7 BIT 6 B IT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0SI SCLK #CS Standby Timing SO Hi-Z 1st byte = incorrect code Standby Standby tDOZ tSKH tSKL tCSA tR tF #CS SO BIT 7 BIT 6 BIT 0 BIT 7 BIT 0 tCYC tDS tDH tAA tDOH tCSH tCSB BIT 6 tCS tCH SCLK SI
R ead Array Timing Waveform Not 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 4th byte. SI BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 SI SCLK #CS SO BIT 3 BIT 2 B IT 1 BIT 0 BIT 7 Hi-Z (N-1)th data output Nth data output (N+1)th data output SI BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 SI SCLK #CS SO Hi-Z 1st data output BIT 1 B IT 0 BIT 7 BIT 6 BIT 5 4th byte AD3 1st data output 2nd data output Do en’t Car *note2 #CS SI BIT 7 BIT 6 B IT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0SI SCLK SO Hi-Z 1st byte Command BIT 7 BIT 6 B IT 5 BIT 4 2nd byte AD1 BIT 3 *note1 10/
Fast Read Array Timing Waveform Note: 1. Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 5 th byte. SI BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 6 BIT 5 BIT 4 SI SCLK #CS SO BIT 3 BIT 2 B IT 1 BIT 0 BIT 7 Hi-Z (N-1)th data output Nth data output (N+1)th data output SI BIT 1 BIT 0 B IT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 SI SCLK #CS SO Hi-Z 1st data output BIT 1 B IT 0 B IT 7 BIT 6 BIT 5 5th byte DUMMY 1st data output 2nd data output Do en’t Car *note2 #CS SI BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0SI SCLK SO Hi-Z 1st byte Command BIT 7 BIT 6 B IT 5 BIT 4 2nd byte AD1 BIT 3 *note1 11/
Identification Timing Waveform Note: . Input data are latched at SCLK-rising edge. 2. Data-output starts at SCLK-falling edge in bit0 of the 1st byte. #CS SI BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0SI SCLK SO Hi-Z 1st byte Command B B IT 7 BIT 6 IT 5 BIT 4 BIT 3 Manufacturer Identification *note1 Do e n’t Car *note2 SI BIT 1 BIT 0 BIT 2 SI SCLK #CS SO Device Identification BIT 1 B IT 0BIT15 BIT14 BIT13 Do en’t Car tCSB Hi-Z 12/
(Unit: mm) No tes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 13/
REVISION HISTORY
No. Date Previous Edition Current Edition
Description
FEDR27V6441L-02-01 Oct. 28, 2005 – – Final edition 1 1 1 PIN DESCRIPTIONS DC: Don’t care (H or L or Open) -- > Don’t care ( 0v - Vcc ) 6 6 PIN CAPACITANCE C IN1 12 pF --- > 10 pF MAX COUT 12 pF --- > 10 pF MAX FEDR27V6441L-02-02 Nov. 9, 2006 8 8 AC Characteristics FAST-READ & READ t CS 5 ns -- > 10 ns Min tDS 2 ns -- > 5 ns Min tDOZ 8 ns -- > 10 ns Max FAST-READ t R 0.1 V/ns Min -- > 3 ns Max tF 0.1 V/ns Min -- > 3 ns Max READ t R 0.1 V/ns Min -- > 5 ns Max tF 0.1 V/ns Min -- > 5 ns Max 2 2 3-byte address (0 to 3FFF[H]) --> 3-byte address 3 3 3-byte address (0 to 3FFF[H]) --> 3-byte address FEDR27V6441L-02-03 Mar. 16, 2007 13 13 Replaced package diagram FEDR27V6441L-002-03 Oct. 1, 2008 – – Changed company logo and name to OKI SEMICONDUCTOR 14/
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