DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 27
Technical content
Issue Date: Jan 29, 2009 ML9460 Common Driver for Dot Matrix STN Liquid Crystal Display 1. Product Overview
1.1 General Description
The ML9460 is a 240-output common driver for driving a dot matrix LCD panel. It enables switching between 240 outputs and 200 outputs and 160 outputs and 120 outputs. The ML9460 is used in combination with the segment driver ML9461B.
1.2 Features
240-channel common driver Display duty: Up to 1/240 LCD drive voltage: 43 V max. Operating voltage: 2.5 to 5.5 V Intermediate voltage Interface Built-in alternating signal generation circuit; pin programmable Built-in display OFF control circuit Can switch output modes: 240-output mode/200-output mode/160-output mode/120-output mode Clock cycle time: 245 ns min. @ 4.5 V 330 ns @ 2.5 V Package Au Bump Chip Product name: ML9460CVWA TCP Product name: ML9460ADVVA
LAPIS Semiconductor ML9460 2. Pin Description
2.1 Pin Description
name I/O Polarity Descripiton Initial value Handling when not used Attribute Remarks VDD — — Logic power supply pin — — Power VSS — — Logic power supply pin — — VSS V2L V2R — — Power supply pins for liquid crystal drive level output. Selective level. — — Power V2L and V2R are connected internally with each other. MV2L MV2R — — Power supply pins for liquid crystal drive level output. Selective level. — — Power MV2L and MV2R are connected internally with each other. VCL VCR — — Power supply pins for liquid crystal drive level output. Nonselective level. — — Power VCL and VCR are connected internally with each other. YSCL I Shift clock input pin. Data is shifted in on the falling edge of the shift clock YSCL of the shift register. Low — CLK FR I/O — Input-output pin for alternating signal for liquid crystal drive output Low — Digital See Sections 4.1.1, “Liquid Crystal Drive Circuit,” and 4.2.1, “Timing of Connection with the Segment Driver.” FRWS0 FRWS1 FRWS2 FRWS3 FRWS4 I — Alternating signal (FR signal) period setting pins. Specify the number of lines with an integer from 2 to 31. For operation using an external alternating signal, set the number of lines to 0. Tied High or Low — Digital See Sections 4.1.4, “Alternating Signal Generation Circuit.” SEL1 SEL2 I — Liquid crystal drive output pin switching pins Tied High or Low — Digital See Sections 4.1.1, “Liquid Crystal Drive Circuit,” and 4.1.3, “Bidirectional Shift Register.” DIO1 DIO2 I/O — Serial I/O (shift register data input-output) pins Tied High or Low — Digital See Section 4.1.3, “Bidirectional Shift Register.” FRRES I Negative Pin for initializing the counter for the alternating signal generation circuit. Setting this pin to “L” level sets initializes the altemating signal(FR signal) circuit. A “H” level FRRES is normally used. Low — Digital DSPOF I Negative A “L” level on this pin sets each of the liquid crystal drive outputs O1–O240 to the VC level. No internal register will be cleared. Low — Digital DSPMS I — Pin for selecting the method of processing the DSPOF signal internally Tied High or Low — Digital See Section 4.1.5, “Control Circuit.”
LAPIS Semiconductor ML9460 Pin name I/O Polarity Descripiton Initial value Handling when not used Attribute Remarks DOC O Negative DISPOFF signal output pin Low — Digital See Sections 4.1.5, “Control Circuit,” and 4.2.3, “DOC Signal Waveforms.” SHL I — Shift direction switching pin. Switches the shift direction of the shift register. Tied High or Low — Digital See Section 4.1.3, “Bidirectional Shift Register.” O1 to O240 O — Liquid crystal drive output pins. When the VDD voltage is input to the DSPOF pin, one of the three levels (V2, MV2, VC) is selected and output according to the combination of the FR signal and display data. Pins that are made disabled by the SEL1 and SEL2 pins will output the nonselective level signal (VC). Analog See Section 4.1.1, “Liquid Crystal Drive Circuit.” Note: In the initial value column, - A dash “—” for an input pin indicates that the initial value is Don’t Care. - A dash “—” for an output pin indicates that the initial value is undefined.
LAPIS Semiconductor ML9460
2.2 Inupt and Output Configuration
Applicable to pins YSCL, FRWS0～4,SEL1,SEL2, FRRES,DSPOF,DSPMS, and SHL. Applicable to pins FR,DIO1,and DIO2. Applicable to pins DOC. Applicable to pins O1～240.
LAPIS Semiconductor ML9460 3. Block Diagram Level Shifter X1–X240 Bidirectional Shift Register V2R VCR Liquid Crystal Drive Circuit V2L MV2L VCL VDD VSS O1–O240 FR FRWS0 FRWS1 FRWS2 FRWS3 FRWS4 FRRES Alternating Signal Generation Circuit DIO2 SHL SEL1 SEL2 DSPMS DSPOF DIO1 DOC YSCL Control Circuit X1 X2 X239 X240 O1 O2 O239 O240 MV2R
LAPIS Semiconductor ML9460 4. Functional Description
4.1 Internal Blocks
4.1.1 Liquid Crystal Drive Circuit
The liquid crystal drive circuit outputs three levels for liquid crystal drive. One of the three liquid crystal drive levels (V2, MV2, VC) is selected and output according to the combination of data stored n the shift register circuit and FR, as shown below. FR Display data DSPOF Output level * * "L" VC *: Don't care The number of output pins is set by the SEL1 and SEL2 settings, as shown below. SEL1 SEL2 Number of output pins "H" "H" 240 outputs (O1, O2, O3, , O239, O240) "H" "L" 200 outputs (O21, O22, O23, , O219, O220) "L" "H" 160 outputs (O41, O42, O43, , O199, O200) "L" "L" 120 outputs (O61, O62, O63, , O179, O180) Pins that are made disabled by the SEL1 and SEL2 pins will output the nonselective level signal (VC) synchronized with the FR signal.
4.1.2 Level Shifter
e level shifter converts 5 V signals to high-voltage signals used for liquid crystal drive by multiplying the voltage.
4.1.3 Bidirectional Shift Register
e device is equipped with a 240-bit bidirectional shift register, where the first line signals that are input from the DIO1 and DIO2 pins are shifted sequentially. The shift direction is deterrmined by the SHL pin setting. Relationship between SHL, DIO1, and DIO2 SHL DIO1 DIO2 "H" Serial output Serial input "L" Serial input Serial output
LAPIS Semiconductor ML9460 Relationship between SEL1/SEL2 and Shift Direction SHL SEL1 SEL2 Shift direction "H"
4.1.4 Alternating Signal Generation Circuit
e alternating signal generation circuit generates the a lternation signal fro liquid crystal display (FR signal). Alternating is enabled by setting each pin from FRWS0 to FRWS4 to VDD or VSS. When inputting alternating signals externally, alternating is enabled by setting all the pins from FRWS0 to FRWS4 to VSS. Number of lines FRWS4 FRWS3 FRWS2 FRWS1 FRWS0 Line alternating waveform FR pin status Remarks 0 0 0 0 0 0 — Input 1 0 0 0 0 1 1 line alternated (*1) 2 0 0 0 1 0 2 lines alternated 3 0 0 0 1 1 3 lines alternated ~ 31 1 1 1 1 1 31 lines alternated Output *1: This setting is prohitited.
4.1.5 Control Circuit
ed on the DSPMS pin status, the control circuit processes the DSPOF signal internally and outputs the generated signal to the DOC signal. DSPMS DSPOF signal and internal processing "H" The liquid crystal output is set to the VC level during the “L” period of the DSPOF signal. "L" Holds the liquid crystal output at the VC level until 16 frames of data are input to DIO1 and DIO2 after a level change from "L" "H" on the DSPOF signal. DSPMS DOC Outputs "L" while the DSPOF signal is at “L”. "H" Outputs "H" while the DSPOF signal is at “H”. "L" Even if the DSPOF signal level changes from "L" "H", a "L" level is output until 16 frames of data are input to DIO1 and DIO2.
LAPIS Semiconductor ML9460
4.2 Timing Diagram
4.2.1 Timing of Connection with the Segment Driver
Input signal FR is latched at the rise of input signal YSCL and is propagated to the liquid crystal drive circuit at the next fall of YSCL. The DATA signal that is input from the DIO1 and DIO2 pins is latched at the fall of the YSCL signal and propagated to the liquid crystal drive circuit. The liquid crystal drive signal level (V2, MC, MV2) is determined by the operation between the FR signal propagated to the liquid crystal drive circuit and the DATA signal. When using output of the FR signal through the FR signal generation circuit, connect the FR signal to the FR pin of the ML9461B directly. The FR signal inside of the LSI is processed by delaying it by two YSCL signals for the FR signal output from the common driver. Timing Diagram when the FR pin is configured as input Y S C L DATA D1 D2 D3 FR M1 M2 M3 DATA D1 D2 D3 FR M1 M2 M3 Operation between D1 and M1 Operation between D2 and M2 Operation between D3 and M3 Timing Diagram when the FR pin is configured as output Y S C L DATA D1 D2 D3 FR M1 M2 M3 DATA D1 D2 D3 FR M1 M2 M3 Operation between D1 and M1 Operation between D2 and M2 Operation between D3 and M3 Input signal O1–O240 pin outputs Liquid crystal drive circuit (LSI internal signal) Input signal O1–O240 pin outputs Output signal Liquid crystal drive circuit (LSI internal signal)
LAPIS Semiconductor ML9460
4.2.2 Driver Output Waveform
Common voltage Peirod of normal display DISPOFF period V2 (21.75 V) VDD (3.3 V) VC (1.75 V) VSS (0.0 V) MV2 (–18.25 V)
4.2.3 DOC Signa
When DSPMS = “H” DSPOF DOC When DSPMS = “L” DSPOF 1 2 3 4 14 15 16 D I O 1 , D I O 2 DOC
LAPIS Semiconductor ML9460
4.2.4 Timing Waveforms of AC Characteristics
(during input) DIO1 DIO2 (during output) FR (during output) O1–O240 Y S C L FR (during input) tf VDD 0.7 VDD 0.3 tCWL tCWH tCYC tr tDS tDH VDD 0.7 VDD 0.3 VOH VOL tDD tFPD VOH VOL 0.8 V2 tpd VDD 0.7 VDD 0.3 tFRS tFRH VDD 0.7VDD 0.7 VDD 0.3VDD 0.3 0.2 V2 0.2 VMV2 0.8 VMV2
LAPIS Semiconductor ML9460 DSPOF DIO1 DIO2 (during input) DOC O1–O240 (DSPMS=H) O1–O240 (DSPMS=L) FRRES tDOC1 tDOC2 VDD 0.3 VDD 0.7 VDD 0.3 tDISP VDD 0.3 tFRRES VDD 0.3 0.2 V2 0.2 VMV2 tpdOFF1 0.8 V2 0.8 VMV2 tpdON1 0.2 V2 0.2 VMV2 tpdOFF2 0.8 V2 0.8 VMV2 tpdON2 VDD 0.7 VDD 0.3
LAPIS Semiconductor ML9460
4.2.5 Alternating Waveforms
L1="H", SEL2="H"(240Output), SHL="H", FR Signal Internal generation, 3 lines inverted YSCL DIO2(Input) FR(Output)
2 Clock Delay
FR(Internal) DSPOF Shift register Q240 DIO1(Output) O240 VC MV2 1Frame (240Lines) 240Lines VC MV2 VC MV2 VC MV2 VC MV2
LAPIS Semiconductor ML9460 SEL1="H", SEL2="H"(240Output), SHL="H", FR Signal Internal generation, 3 lines inverted YSCL DIO2(Input) FR(Output) FR(Latch) FR(Internal) DSPOF Shift Register Q240 DIO1(Output) O240 VC MV2 1Frame (240Lines) 240Lines VC MV2 VC MV2 VC MV2 VC MV2
LAPIS Semiconductor ML9460 5. Power Supply System
5.1 Power Supply Group
X1–X240 Bidirectional Shift Register Liquid Crystal Drive Circuit O1–O240 Alternating Signal Generation CircuitControl Circuit X1 X2 X239 X240 O1 O2 O239 O240 V2L VCL MV2L MV2R VCR V2R VDD VSS This LSI does completely separate Liquid crystal drive voltage and Operating voltage on its circuit architecture. Please do an anti-noise measure on a panel so that anoise Liquid crystal drive voltage does not round it in Operating voltage.
LAPIS Semiconductor ML9460
5.2 Power-On/Shutdown Sequence
5.2.1 Power-On Sequence
- A pply power to (1)VSS–VDD, (2)VSS–V2, (3)VC, and (4)MV2 in this order. Then, input the VSS potential to the DSPOF pin. 2. The O1–O240 pins forcibly outputs the VC level by the DISPOFF function. 3. Even if an input signal is disturbed immediately after VDD is applied, priority is given to the DISPOFF function. 4. Input the predetermined signal(s) to initialize the registers in the driver. In this case, take at least one frame for the initialization period. 5. Input the VDD voltage to the DSPOF pin to release the DISPOFF function. At this point, the levels of the MV2, V2, and VC pin must have reached their respective predetermined potentials.
5.2.2 Shutdown Sequence
- T h e DSPOF pin must remain set to the VSS potential. 2. Shut down the power supplies for liquid crystal in the order of (1)VSS–V2, (2)VC, and (3)MV2. 3. Reduce the voltage of VDD and the levels of the input signals to the VSS potential. At this point, the V2 and VC pin must completely drop to 3 V or lower. V D D V C M V 2 DSPOF Input signal, clock, data, etc. Signal uncertain period Initialization period (1 frame or more) "V2" " V C " "VC" O1–O240 "MV2" 0 ms 0 ms 0 ms 0m s 2.5V 0 ms 0 ms 2.5V0 V 0 V 0 V 0 V 0 V 0 V 0 ms 0 V
LAPIS Semiconductor ML9460 6. Electrical Specifications
6.1 Absolute Maximum Ratings
VSS = 0V Parameter Symbol Condition Rating Unit Applicable pins Logic circuit V DD Tj = –30°C to +75°C –0.3 to +7.0 V VDD V2 Tj = –30°C to +75°C –0.3 to +25.0 V V2L, V2R VMV2 Tj = –30°C to +75°C –22.5 to +0.3 V MV2L, MV2R Power supply voltage liquid crystal drive circuit V M-VMV2 Tj = –30°C to +75°C –0.3 to +45.0 V V2L,V2R,MV2L, MV2R Input voltage (1) Vt1 Tj = –30°C to +75°C –0.3 to V DD+0.3 V DIO1, DSPOF, SHL, FR, FRWS0, FRWS1, FRWS2, FRWS3, FRWS4, FRRES, SEL1, SEL2, YSCL, DSPMS, DIO2 Input voltage (2) V2 Tj = –30°C to +75°C –0.3 to +25.0 V V2L, V2R Input voltage (3) VMV2 Tj = –30°C to +75°C –22.5 to +0.3 V MV2L, MV2R Input voltage (4) VC Tj = –30°C to +75°C –0.3 to +5.0 V VCL, VCR Output current/output short-circuit current IO Tj = –30°C to +75°C 10 mA FR, DIO1, DIO2, DOC, O1–O240 Junction temperature Tj — –55 to +110 °C — Storate temperature range Tstg — –55 to +110 °C —
LAPIS Semiconductor ML9460
6.2 Recommended Operating Conditions (Guaranteed Operating Range)
VSS = 0V, V2VMV2 = 15 to 43V, Tj = 30 to +75°C Range Parameter Symbol Condition Min. Typ. Max. Unit Applicable pins Logic circuit V DD — 2.5 — 5.5 V VDD V2 — 8.8 — 24 V V2L, V2R Power supply voltage liquid crystal drive circuit VMV2 — –21.5 — –4 V MV2L, MV2R “H” Input voltage V IH — 0.7VDD — V DD V “L” Input voltage V IL — 0 — 0.3VDD V DIO1, DSPOF, SHL, FR, DSPMS, FRWS0, FRWS1, FRWS2, FRWS3, FRWS4, FRRES, YSCL, SEL1, SEL2, DOC, DIO2 liquid crystal drive Input voltage (1) V2 — 8.8 — 24 V V2L, V2R liquid crystal drive Input voltage (2) VMV2 — –21.5 — –4 V MV2L, MV2R liquid crystal drive Input voltage (3) VC — 0 — 3.5 V VCL, VCR VDD=5V (*1) — 4 MHz YSCL Operating frequency f CK VDD=3V (*1) — 3 MHz YSCL Operating temperature (Tj) Topr — –30 — 75 °C — Load condition 1 C L1 — — — 30 pF DIO1, DIO2 Load condition 2 C L2 — — — 100 pF DOC, O1–O240 Input rise waveform t r — — — 30 ns YSCL Input fall waveform t f — — — 30 ns YSCL Clock “High” period t CWH — 20 — — ns YSCL Clock “Low” period t CWL — 250 — — ns YSCL Data setup time t DS — 70 — — ns DIO1, DIO2, YSCL Data hold time tDH — 10 — — ns DIO1, DIO2, YSCL FR setup time tFRS — 20 — — ns FR, YSCL FR hold time tFRH — 20 — — ns FR, YSCL “—” indicates that no particular value is specified. *1: 5kHz is specified for the test condition. Note: Insert bypass capacitors by referring to the Application Circuit described later so that power supplies will be stabilized. It is recommended that 0.1 F CA capacitors (JIS (Japanese Industrial Standards) FJ(F) equivalent) be used.
LAPIS Semiconductor ML9460
6.3 DC Characteristics
VDD = 2.5 to 5.5V, V SS = 0V, V 2VMV2 = 15 to 43V, Tj = –30 to +75°C No. Parameter Symbol Condition Min. Typ. Max. Unit Applicable pins 1 “H” level input voltage VIH — V DD0.7 — V DD V 2 “L” level input voltage V IL — 0 — V DD0.3 V DIO1, DSPOF, SHL, FR, DSPMS, FRWS0, FRWS1, FRWS2, FRWS3, FRWS4, FRRES, YSCL, SEL1, SEL2, DIO2 3 “H” level output voltage V OH I OH = 0.4mA V DD0.4 — — V 4 “L” level output voltage VOL I OL = 0.4mA — — 0.4 V FR, DIO1, DIO2, DOC
5 Supply current (1) I CC1
VDD = 3.3V V2VMV2 = 40V fYSCL = 19.2kHz f FR = 1.5kHz 240-output mode Ta = 25°C No load — 10 40 A VDD
6 Supply current (2) I CC2
VDD = 5.0V V2VMV2 = 40V fYSCL = 19.2kHz fFR = 1.5kHz 240-output mode Ta = 25°C No load — 20 50 A VDD
7 Supply current (3) I CC3
VDD = 3.3V V2VMV2 = 40V fYSCL = 19.2kHz fFR = 1.5kHz 240-output mode Ta = 25°C No load — 25 50 A V2
8 Static supply current I DDS Ta = 25°C — — 10 A VDD
9 Input leakage
current 1 IIL1 V IN = VDD to VSS –5 — 5 A DIO1, DSPOF, SHL, FR, DSPMS, FRWS0, FRWS1, FRWS2, FRWS3, FRWS4, FRRES, YSCL, SEL1, SEL2, DIO2
10 Input leakage
current 2 IIL2 — –25 — 25 A VCL, VCR VON = 0.5V V2 = 21.75V VMV2 = –18.25V VC = 1.75V — 0.7 2.0 k O1–O240
11 ON resistance
ON VON = 0.5V V2 = 11.75V VMV2 = –8.25V VC = 1.75V — 1.2 3.3 k O1–O240 Values in the Typ. column are for reference only. “—” indicates that no particular value is specified.
LAPIS Semiconductor ML9460
6.4 AC Characteristics
6.4.1 AC Characteristics 1
VDD = 2.5 to 4.5V, VSS = 0V, V2 = 21.5V, VC = 0V, VMV2 =-21.5V, Tj = –30 to +75°C No. Parameter Symbol Condition Min. Typ. Max. Unit Applicable pins
1 Clock cycle time t CYC — 330 — — ns YSCL
2 YSCL “H” level width t CWH — 20 — — ns YSCL
3 YSCL “L” level width t CWL — 250 — — ns YSCL
4 YSCL rise time tr — — — 30 ns YSCL
5 YSCL fall time tf — — — 30 ns YSCL
6 Data setup time t DS — 70 — — ns DIO1, DIO2,
7 Data hold time t DH — 10 — — ns DIO1, DIO2,
8 Data output delay
DD (*1) — — 200 ns DIO1, DIO2, YSCL
9 FR output delay time t FRD (*1) — — 140 ns FR, YSCL
10 FR setup time t FRS — 20 — — ns FR, YSCL
11 FR hold time tFRH — 20 — — ns FR, YSCL
DSPMS = H (*2) — — 200 ns DSPOF, DOC
12 DOC output delay
DSPMS = L (*2) — — 1500 ns DSPOF, DOC
13 DOC output delay
time 2 tDOC2 (*2) — — 300 ns DIO1, DIO2, DOC tpdFF1 DSPMS = H (*2) — — 1200 ns DSPOF, O1 to O240 14 Common output delay time from DSPOF fall tpdOFF2 DSPMS = L (*2) — — 2500 ns DSPOF, O1 to O240
15 Common output delay
pdON1 DSPMS = H (*2) — — 1200 ns DSPOF, O1 to O240
16 Common output delay
time from DIO fall tpdON2 DSPMS = L (*2) — — 1200 ns DIO1, DIO2, O1 to O240
17 DSPOF “L” level width
(*3) tDISP DSPMS = L 100 — — ns DSPOF
18 FRRES “L” level width
(*3) tFRRES — 100 — — ns FRRES Values in the Typ. column are for reference only. “—” indicates that no particular value is specified.
LAPIS Semiconductor ML9460 V DD = 4.5 to 5.5V, VSS = 0V, V2 = 21.5V, VC = 0V, VMV2 =-21.5V, Tj = –30 to +75°C No. Parameter Symbol Condition Min. Typ. Max. Unit Applicable pins
1 Clock cycle time tCYC — 245 — — ns YSCL
2 YSCL “H” level width t CWH — 15 — — ns YSCL
3 YSCL “L” level width t CWL — 170 — — ns YSCL
6 Data setup time t DS — 50 — — ns DIO1, DIO2,
7 Data hold time tDH — 10 — — ns DIO1, DIO2,
8 Data output delay time t DD (*1) — — 150 ns DIO1, DIO2,
9 FR output delay time t FRD (*1) — — 100 ns FR, YSCL
10 FR setup time tFRS — 15 — — ns FR, YSCL
11 FR hold time tFRH — 15 — — ns FR, YSCL
DSPMS = H (*2) — — 140 ns DSPOF, DOC
12 DOC output delay time 1 tDOC1
DSPMS = L (*2) — — 1000 ns DSPOF, DOC
13 DOC output delay time 2 tDOC2 (*2) — — 200 ns DIO1, DIO2, DOC
tpdOFF1 DSPMS = H (*2) — — 700 ns DSPOF, O1 to O240 14 Common output delay time from DSPOF fall tpdOFF2 DSPMS = L (*2) — — 2000 ns DSPOF, O1 to O240 pdON1 DSPMS = H (*2) — — 700 ns DSPOF, O1 to O240 time from DIO fall tpdON2 DSPMS = L (*2) — — 700 ns DIO1, DIO2, O1 to O240
17 DSPOF “L” level
width(*3) tDISP DSPMS = L 100 — — ns DSPOF
18 FRRES “L” level
width(*3) tFRRES — 100 — — ns FRRES Values in the Typ. column are for reference only. “—” indicates that no particular value is specified.
LAPIS Semiconductor ML9460
6.4.2 AC Characteristics 2
VDD = 2.5 to 4.5V, VSS = 0V, V2 = 21.5V, VC = 0V, VMV2 =-21.5V, Tj = –30 to +75°C No. Parameter Symbol Condition Min. Typ. Max. Unit Applicable pins 1 Output delay time t pd (*2) — — 1.2 s O1–O240, FR “—” indicates that no particular value is specified.
6.4.3 AC Characteristics 3
VDD = 4.5 to 5.5V, VSS = 0V, V2 = 21.5V, VC = 0V, VMV2 =-21.5V, Tj = –30 to +75°C No. Parameter Symbol Condition Min. Typ. Max. Unit Applicable pins 1 Output delay time t pd (*2) — — 0.7 s O1–O240, FR “—” indicates that no particular value is specified. *1: Load condition *2: Load condition *3: If any signal whose pulse width is shorter than this value, the device may not operate normally. 30 pF 100 pF
LAPIS Semiconductor ML9460 7. PAD CONFIGURATION
7.1 Pad Coordinates (Au Bump Chip: ML9460CVWA)
No. Pad name x-coordinate y-coordinate No. Pad name x-coordinate y-coordinate No. Pad name x-coordinate y-coordinate No. Pad name x-coordinate y-coordinate 4 V2L -5738 -604.2 84 YSCL 3779 -604.2 164 O183 3125 606.3 244 O103 -875 606.3 5 V2L -5672 -604.2 85 YSCL 3845 -604.2 165 O182 3075 606.3 245 O102 -925 606.3 30 FRWS3 -2663 -604.2 110 O237 5825 606.3 190 O157 1825 606.3 270 O77 -2175 606.3 31 FRWS3 -2597 -604.2 111 O236 5775 606.3 191 O156 1775 606.3 271 O76 -2225 606.3 67 DSPOF 2078 -604.2 147 O200 3975 606.3 227 O120 -25 606.3 307 O40 -4025 606.3 68 DSPOF 2144 -604.2 148 O199 3925 606.3 228 O119 -75 606.3 308 O39 -4075 606.3 Note: Leave DUMMY pads open.
LAPIS Semiconductor ML9460 No. Pad name x-coordinate y-coordinate No. Pad name x-coordinate y-coordinate No. Pad name x-coordinate y-coordinate 321 O26 -4725 606.3 331 O16 -5225 606.3 341 O6 -5725 606.3 322 O25 -4775 606.3 332 O15 -5275 606.3 342 O5 -5775 606.3 323 O24 -4825 606.3 333 O14 -5325 606.3 343 O4 -5825 606.3 324 O23 -4875 606.3 334 O13 -5375 606.3 344 O3 -5875 606.3 325 O22 -4925 606.3 335 O12 -5425 606.3 345 O2 -5925 606.3 326 O21 -4975 606.3 336 O11 -5475 606.3 346 O1 -5975 606.3 327 O20 -5025 606.3 337 O10 -5525 606.3 347 DUMMY -6025 606.3 328 O19 -5075 606.3 338 O9 -5575 606.3 348 DUMMY -6075 606.3 329 O18 -5125 606.3 339 O8 -5625 606.3 330 O17 -5175 606.3 340 O7 -5675 606.3 Note: Leave DUMMY pads open. b b b=45.0μm Alignment Mark② Center Coordinate (6074.4, -588.1) Mark size a a a a a a a=15.0μm Alignment Mark① Center Coordinate (-6074.4, -588.1) Mark size Alignment Mark Information X Y (0,0) Die No. No.1 No.348 No.105 No.104 Alignment Mark ① Alignment Mark ② Chip Size 12.59mm × 1.50mm Chip Thickness 625 μm
LAPIS Semiconductor ML9460
7.2 Pin Configuration (TCP: ML9460ADVVA)
NC ： NC ： V2L ： VCL ： MV2L ： NC ： NC ： NC ： NC ： DIO2 ： FR ： FRRESB ： FRWS4 ： FRWS3 ： FRWS2 ： FRWS1 ： FRWS0 ： VDD ： SEL2 ： SEL1 ： DOCB ： DSPOFB ： NC ： SHL ： VSS ： YSCL ： NC ： DSPMS ： DIO1 ： NC ： MV2R ： VCR ： V2R ： NC ： NC O238 O239 O240 DUMMY DUMMY DUMMY OKIML9460A DVVA 24 240 The drawing shown does not specify the exact outline of the TCP;it only specifies the pin layout. T.B.D
LAPIS Semiconductor ML9460 8. Application Circuit (With External Components Connected) ML9460 YSCL FRRES DSPOF DS PMS DOC FR FRWS0–FRWS4 V2L, V2R VCL, VCR MV2L, MV2R SHL DIO1 VSS VDD Power supply circuit VLCD VDD VC MV2 MV1 GND DI O2 O1–O240 LCD Panel 320 3(RGB) 240 1/240 duty O1–O320 ML9461B (No.1)SH L EIO2 SEL1 VSS VD D FR LP SCL D0–D7 DMS DSPOF VCL,VCR MV1L,MV1R V1 L,V1R EIO1 O1–O320 ML9461B (No.2) O1–O320 ML9461B (No.3) Controller LP SCL D0 –D7 DSPOF FLM FRWS0–4 COM1 COM2 COM239 COM240 SEG 960 SEG 959 SEG SEG CA CA CA CA CB CB CB FR LP SCL D0–D7 DMS DSPOF VCL,VCR MV1L,MV1R V1 L,V1R SHL EIO2 SEL1 VSS VD D SH L EIO2 SEL1 VSS VDD FR LP SCL D0–D7 DMS DSPOF VCL,VCR MV1L,MV1R V1L,V1R EIO1 EIO1 Insert a capacitor CA,CB specified in the Recommended Operating Conditions (Guaranteed Operating Range). It is recommended that 0.1 F CA capacitors (JIS (Japanese Industrial Standards) FJ(F) equivalent) be used.
LAPIS Semiconductor ML9460
Revision History
Document No. Date Previous Edition Current Edition
Description
PEDL9460-01 May 21, 2007 – – Preliminary edition 1 1 1 Au Bump Chip product name DVWA→CVWA 13 13 Additional comment. – 23 Additional 7.2 Pin Configuration. PEDL9460-02 Dec 5, 2007 23 24 Changed Application Circuit. – – Changed to OKI Semiconductor’s format PEDL9460-03 Dec 17,2008 1,7,24 1,7,24 ML9461→ML9461B – – Final edition 1 2 2 Additional comment for FRRES pin – 4 Additional FEDL9460-01 Jan 29,2009 22 23 Additional Alignment Mark Information
LAPIS Semiconductor ML9460 NOTICE No copying or reproduction of this document, in part or in whole, is permitted without the consent of LAPIS Semiconductor Co., Ltd. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing LAPIS Semiconductor's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from LAPIS Semiconductor upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, LAPIS Semiconductor shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. LAPIS Semiconductor does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by LAPIS Semiconductor and other parties. LAPIS Semiconductor shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-a utomation equipment, communication devices, electronic appliances and amusement devices). The Products specified in this document are not designed to be radiation tolerant. While LAPIS Semiconductor always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. LAPIS Semiconductor shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or no t in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (suc h as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). LAPIS Semiconductor shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law. Copyright 2009 - 2011 LAPIS Semiconductor Co., Ltd.