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Issue Date: May. 15, 2009 ML9289-xx Vacuum fluorescent display tube controller driver GENERAL DESCRIPTION The ML9289-xx is an alphanumeric type vacuum fluorescent display (VFD) tube controller driver IC which can display alphanumeric characters, symbols, and bar charts. Vacuum fluorescent display tube drive signals are generated by serial data sent from a micro-controller. A display system is easily realized by internal ROM and RAM for character display. -01 is available as a general-purpose code. Custom codes are provided on customer’s request.
FEATURES
Logic power supply (V DD) : 3.3 V10% or 5.0 V10% Vacuum fluorescent display tube driving power supply (V DISP) : 20V to 42V VFD driver output current (VFD driver output can be connected directly to the VFD tube. No pull-down resistor is required.)
- Segment driver (SEG1–16) : –6 mA (V DISP = 42 V)
- Segment driver (AD1, 2) : –15 mA (V DISP = 42 V)
- Grid driver (COM1–16) : –30 mA (V DISP = 42 V) Content of display
- CGROM : 16 segments 240 types (character data)
- CGRAM : 16 segments 16 types (character data)
- ADRAM : 16 (display digit) 2 bits (symbol data)
- DCRAM : 16 (display digit) 8 bits (register for character data display) Display control function
- Display digits : 1 to 16 digits
- Display duty (brightness adjustment) : 16 stages
- All display lights ON/OFF Four interfaces with microcontroller: DA, CS, CP, RESET Instruction executable with 1 byte (excluding data write for each RAM) Built-in oscillation circuit (resistor & capacitor connected externally) Package options: AL-Pad Chip (ML9289-xxWA) 44-pin plastic QFP (QFP44-P-910-0.80-2K) (ML9289-xxGA) 48-pin plastic TQFP (TQFP48-P-0707-0.50-K) (ML9289-xxTB)
16w 8b CGR AM 16w 16b ADRAM 16w 2b 8 bit Shift Register Command Decoder Control Circuit Timing Generator 1 Oscillator Timing Generator 2 Digit Control Duty Control Grid Driver AD Driver Segment Driver Write Address Counter Read Address Counter Address Selector CGROM 240w16b
PIN CONFIGURATION (TOP VIEW) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 AD2 AD1 VDISP DA CP SEG16 SEG15 SEG14 SEG13 SEG12 GND SEG11 COM12 COM13 COM14 COM15 CO M16 GND V DISP OSC0 VDD RESET CS SEG10 SEG9 SEG8 SEG7 44-Pin Plastic QFP
N.C N.C N.C N.C CS N.C: No-Connection pin 48-Pin Plastic TQFP
Chip Size: 2.30 3.20 mm Chip Thickness: 280 ±30 m Pad Size: Metal 90 90 m, PV Pad hole 70 70 m Y X 33 22 Pad Coordinates Pad No Symbol X ( m) Y ( m) Pad No Symbol X ( m) Y ( m)
1 SEG7 -638 -1465 23 COM12 811 1465
2 SEG8 -522 -1465 24 COM13 567 1465
3 SEG9 -406 -1465 25 COM14 323 1465
4 SEG10 -290 -1465 26 COM15 79 1465
5 SEG11 -174 -1465 27 COM16 -165 1465
6 GND -39 -1465 28 GND -435 1465
7 SEG12 91 -1465 29 VDISP -575 1465
8 SEG13 207 -1465 30 OSC0 -715 1465
9 SEG14 323 -1465 31 VDD -855 1465
10 SEG15 439 -1465 32 RESET -1015 1465
11 SEG16 555 -1465 33 CS -1015 1225
12 COM1 1015 -1308 34 CP -1015 985
13 COM2 1015 -1064 35 DA -1015 745
14 COM3 1015 -820 36 VDISP -1015 415
15 COM4 1015 -576 37 AD1 -1015 196
16 COM5 1015 -332 38 AD2 -1015 65
17 COM6 1015 -88 39 SEG1 -1015 -123
18 COM7 1015 156 40 SEG2 -1015 -253
19 COM8 1015 400 41 SEG3 -1015 -383
20 COM9 1015 644 42 SEG4 -1015 -513
21 COM10 1015 888 43 SEG5 -1015 -643
22 COM11 1015 1132 44 SEG6 -1015 -773
Symbol Type Connects to Description 28–38, 40–44 31-41, 43-47 SEG1–16 O VFD tube anode electrode VFD tube anode electrode drive output. Directly connected to the VFD tube and no pull-down resistor is required. I OH > –6 mA 1–16 1-11, 14-18 COM1–16 O VFD tube grid electrode VFD tube grid electrode drive output. Directly connected to the VFD tube and no pull-down resistor is required. I OH > –30 mA 26, 27 29,30 AD1–2 O VFD tube anode electrode VFD tube anode electrode drive output. Directly connected to the VFD tube and no pull-down resistor is required. I OH > –15 mA 18, 25 20,28 V DISP 20 22 V DD 17,39 19,42 GND — Power supply The voltage supply between VDD and GND is for the power supply for the internal logic. The voltage supply between V DISP and GND is for the power supply for driving the VFD tube. Apply power to VDD first, then to VDISP. 24 27 DA I Microcontroller Serial data input pin. Data is input from the LSB. 23 26 CP I Microcontroller Shift clock input pin. Serial data is shifted in on a rising edge of CP when CS pin is “L” level. 22 25 CS I Microcontroller Chip select input pin. Serial data transfer is enabled when CS pin is “L” level. 21 23 RESET l Microcontroller Reset input. Setting this pin to “Low” initializes all the functions. Initial status is as follows. Pin for RC oscillation. Resistors and capacitors are connected externally and constants vary depending on the VDD voltage used. The target oscillation frequency is 2MHz. 19 21 OSC0 I/O C 1, R1 OSC0 R1C1 (RC oscillator circuit) *Refer to the Application Circuit. - 12,13, 24,48 N.C - Open No-Connection pin.
Parameter Symbol Condition Rating Unit Supply Voltage (1) V DD — –0.3 to +6.5 V Supply Voltage (2) V DISP — –0.3 to +45 V Input Voltage V lN — –0.3 to VDD+0.3 V Power Dissipation P D Ta 25C 44-pin plastic QFP 541 mW Storage Temperature TSTG — –55 to +150 C lO1 COM1–16 –40 to 0.0 mA lO2 AD1–2 –20 to 0.0 mA Output Current IO3 SEG1–16 –10 to 0.0 mA RECOMMENDED OPERATING CONDITIONS-1 When the unit power supply voltage is 5.0 V (typ.) Parameter Symbol Condition Min. Typ. Max. Unit Supply Voltage (1) V DD — 4.5 5.0 5.5 V Supply Voltage (2) V DISP — 20 — 42 V High Level Input Voltage V IH All input pins except OSC0 0.7 V DD — — V Low Level Input Voltage V IL All input pins except OSC0 — — 0.3 V DD V CP frequency f C — — — 2.0 MHz Self-oscillation frequency f OSC R 1 = 8.2 k5%, C1 = 82 pF5% 1.4 2.0 2.6 MHz Frame Frequency fFR DIGIT = 1 to16, R1 = 8.2 k5%, C1 = 82 pF5% 170 244 318 Hz Top 44-pin plastic QFP –40 — 85 Operating Temperature Tj AL-Pad Chip –40 — 105 C RECOMMENDED OPERATING CONDITIONS-2 When the unit power supply voltage is 3.3 V (typ.) Parameter Symbol Condition Min. Typ. Max. Unit Supply Voltage (1) V DD — 3.0 3.3 3.6 V Supply Voltage (2) V DISP — 20 — 42 V High Level Input Voltage V IH All input pins except OSC0 0.8 V DD — — V Low Level Input Voltage V IL All input pins except OSC0 — — 0.2 V DD V CP frequency f C — — — 2.0 MHz Self-oscillation frequency f OSC R 1 = 6.8 k5%, C1 = 82 pF5% 1.4 2.0 2.6 MHz Frame Frequency fFR DIGIT = 1 to 16, R1 = 6.8 k5%, C1 = 82 pF5% 170 244 318 Hz Top 44-pin plastic QFP –40 — 85 Operating Temperature Tj AL-Pad Chip –40 — 105 C
ELECTRICAL CHARACTERISTICS
(VDD=5.0V10%, V DISP=42V, Ta=–40to+85C, unless otherwise specified) Parameter Symbol Applied pin Condition Min. Max. Unit High Level Input Voltage VIH CS, CP, DA, RESET — 0.7 V DD — V Low Level Input Voltage VIL CS, CP, DA, RESET — — 0.3 VDD V High Level Input Current IIH CS, CP, DA, RESET VIH = VDD –1.0 1.0 A Low Level Input Current IIL CS, CP, DA, RESET VIL = 0V –1.0 1.0 A VOH1 COM1–16 IOH1 = –30mA V DISP – 1.5 — V VOH2 AD1–2 I OH2 = –15mA V DISP – 1.5 — V High Level Output Voltage VOH3 SEG1–16 I OH3 = –6mA VDISP– 1.5 — V Low Level Output Voltage V OL1 COM1–16 AD1–2 SEG1–16 — — 1.0 V IDD1 Duty = 15/16 Digit =1–16 All output lights ON — 3 mA IDD2 VDD fOSC =
2 MHz,
no load Duty = 0/16 Digit = 1–8 All output lights OFF — 3 mA IDISP1 Duty = 15/16 Digit =1–16 All output lights ON — 1 mA Supply Current IDISP2 VDISP fOSC = no load Duty = 0/16 Digit = 1–8 All output lights OFF — 0.1 mA
(VDD=3.3V10%, V DISP=42V, Ta=–40to+85C, unless otherwise specified) Parameter Symbol Applied pin Condition Min. Max. Unit High Level Input Voltage VIH CS, CP, DA, RESET — 0.8 V DD — V Low Level Input Voltage VIL CS, CP, DA, RESET — — 0.2 VDD V High Level Input Current IIH CS, CP, DA, RESET VIH = VDD –1.0 1.0 A Low Level Input Current IIL CS, CP, DA, RESET VIL = 0V –1.0 1.0 A VOH1 COM1–16 IOH1 = –30mA V DISP – 1.5 — V VOH2 AD1–2 I OH2 = –15mA V DISP– 1.5 — V High Level Output Voltage VOH3 SEG1–16 I OH3 = –6mA VDISP – 1.5 — V Low Level Output Voltage V OL1 COM1–16 AD1–2 SEG1–16 — — 1.0 V IDD1 Duty = 15/16 Digit =1–16 All output lights ON — 2 mA IDD2 VDD fOSC = no load Duty = 0/16 Digit = 1–8 All output lights OFF — 2 mA IDISP1 Duty = 15/16 Digit =1–16 All output lights ON — 1 mA Supply Current IDISP2 VDISP fOSC = no load Duty = 0/16 Digit = 1–8 All output lights OFF — 0.1 mA
(VDD=5.0V10%, VDISP=42V, Ta=–40to+85C, unless otherwise specified) Parameter Symbol Condition Min. Max. Unit CP Frequency f C — — 2.0 MHz CP Pulse Width t CW — 250 — ns DA Setup Time tDS — 250 — ns DA Hold Time tDH — 250 — ns CS Setup Time t CSS — 250 — ns CS Hold Time t CSH R 1 = 8.2 k5%, C1 = 82 pF5% 16 — s CS Wait Time t CSW — 250 — ns Data Processing Time t DOFF R 1 = 8.2 k5%, C1 = 82 pF5% 8 — s RESET Pulse Width t WRES — 250 — ns RESET Time tRSON — 250 — ns DA Wait Time tRSOFF — 250 — ns tR t R = 20 to 80% — 2.0 s All Driver Output Slew Rate tF Cl = 100 pF tF = 80 to 20% — 2.0 s AC Characteristics-2 (VDD=3.3V10%, VDISP=42V, Ta=–40 to+85C, unless otherwise specified) Parameter Symbol Condition Min. Max. Unit CP Frequency f C — — 2.0 MHz CP Pulse Width t CW — 250 — ns DA Setup Time tDS — 250 — ns DA Hold Time tDH — 250 — ns CS Setup Time t CSS — 250 — ns CS Hold Time t CSH R 1 = 6.8 k5%, C1 = 82 pF5% 16 — s CS Wait Time t CSW — 250 — ns Data Processing Time t DOFF R 1 = 6.8 k5%, C1 = 82 pF5% 8 — s RESET Pulse Width t WRES — 250 — ns RESET Execution Time tRSON — 250 — ns DA Wait Time tRSOFF — 250 — ns tR t R = 20 to 80% — 2.0 s All Driver Output Slew Rate tF Cl = 100 pF tF = 80 to 20% — 2.0 s
1) Data Input Timing Symbol V DD = 3.3 V 10% V DD = 5.0 V 10% VIH 0.8 VDD 0.7 VDD VIL 0.2 VDD 0.3 VDD CS CP DA tCSS tDS tDH tDOFF tCW tCW tCSH tCSW VALID VALID VALID VALID VIH VIH fC VIL VIL VIH VIL 2) Data Input Timing VDD RESET DA tRSON tWRES
0.8 VDD
0.5 VDD
3) Output Timing All driver outputs tFtR 0.8 VDISP
0.2 VDISP
4) Digit Output Timing (16-Digit, 15/16-Duty) COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 COM16 AD1-2 SEG1-16 GND t1 = 1024T t2 = 60T t3 = 4T Frame cycle Display timing Blank timing VDISP GND VDISP T = 8 (fos c = 2.0 MHz, t1= 4.096 ms) (fos c = 2.0 MHz, t2 = 240 s) (fos c = 2.0 MHz, t3 = 16 s) fOS C
Command LSB First byte MSB LSB Second byte MSB B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
1 DCRAM data write X0 X1 X2 X3 1 0 0 0 C0 C1 C2 C3 C4 C5 C6 C7
C0 C1 C2 C3 C4 C5 C6 C7 2nd byte
2 CGRAM data write X0 X1 X2 X3 0 1 0 0
C8 C9 C10 C11 C12 C13 C14 C15 3rd byte
3 ADRAM data write X0 X1 X2 X3 1 1 0 0 C0 C1 * * * * * *
4 Display duty set D0 D1 D2 D3 1 0 1 0
5 Number of digits set K0 K1 K2 K3 0 1 1 0
6 All display lights
ON/OFF L H * * 1 1 1 0 O t h e r s ( t e s t m o d e ) * : Don’t care Xn : Address setting for each RAM Cn : Character code setting for each RAM Dn : Display duty setting Kn : Setting of the number of display digits H : All display lights ON setting L : All display lights OFF setting When data is written to RAM (DCRAM, CGRAM, and ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and subsequent bytes. Note: The test mode is used for inspection before shipment. It is not a user function. Positional Relationship Between SEGn and ADn (one digit) SEG1 SEG2 SEG3 C2SEG4C3 SEG5 SEG6 SEG7C6 SEG8C7 C14 SEG15 C10 SEG11 C11 SEG12 C13SEG14 SEG10 C15 SEG16 SEG13C12 SEG9C8 C0–7: Corresponds to the 2nd byte of the CGRAM data write command. C8–15: Corresponds to the 3rd byte of the CGRAM data write command.
Data Transfer Method and Command Write Method Display control command and data are written by an 8-bit serial transfer. Write timing is shown in the figure below. Setting the CS pin to “Low” level enables a data transfer. Data is 8 bits and is sequentially input into the DA pin from LSB (LSB first). As shown in the figure below, data is read by the shift register at the rising edge of the shift clock, which is input into the CP pin. If 8-bit data is input, internal load signals are automatically generated and data is written to each register and RAM. Therefore it is not necessary to input load signals from the outside. Setting the CS pin to “High” disables data transfer. Data input from the point when the CS pin changes from “High” to “Low” is recognized in 8-bit units. *1 When data is written to RAM (DCRAM, CGRAM, ADRAM) continuously, addresses are internally incremented automatically. Therefore it is not necessary to specify the 1st byte to write RAM data for the 2nd and subsequent bytes. Reset Function Res et is executed when the RESET pin is set to “L”, (when turning power on, for example) and initializes all functions. Initial status is as follows. Be sure to execute the reset operation when turning power on and set again according to “Setting Flowchart” after reset. tDOFF LSB CS CP MSB 1st byte LSB MSB 2nd byte Command and address data tCSH LSB MSB 3rd byte Character code data of the next address Character code dataWhen data is written to DCRAM(*1) DA B0 B1 B2 B3 B4 B5 B6 B7 B0 B1 B2 B3B4 B5 B6 B7 B0 B1 B2 B3 B4 B5 B6 B7
Description of Commands and Functions 1. “DCRAM data write” command (Specifies the address of DCRAM and writes the character code of CGROM and CGRAM.) DCRAM (Data Control RAM) has a 4-bit address to store character codes of CGROM and CGRAM. A character code specified by DCRAM is converted to an alphanumeric character pattern via CGROM or CGRAM. The DCRAM can store 16 characters worth of character codes. [Command format] X0 X1 X2 X3 1 0 0 0 B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) LSB MSB C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) LSB MSB : Setup and DCRAM address in the write mode of DCRAM data are specified. (Example: Specify DCRAM address 0H.) : Specify character code of CGROM and CGRAM. (It is written into DCRAM address 00H.) To specify the character code of CGROM and CGRAM to the next address continuously, specify only character code as follows. Since the address of DCRAM is automatically incremented, address specification is unnecessary. C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (3rd) LSB MSB C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (4th) LSB MSB : Specify character code of CGROM and CGRAM. (It is written into DCRAM address 1H.) : Specify character code of CGROM and CGRAM. (It is written into DCRAM address 2H.) B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (17th) LSB MSB C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (18th) LSB MSB : Specify character code of CGROM and CGRAM. (It is written into DCRAM address FH.) : Specify character code of CGROM and CGRAM. (It is rewritten into DCRAM address 0H.) C0 C1 C2 C3 C4 C5 C6 C7 X0 (LSB) to X3 (MSB): DCRAM address (4 bits: 16 characters worth) C0 (LSB) to C7 (MSB): Character code of CGROM and CGRAM (8 bits: 256 characters worth)
[Relationship between DCRAM addresses setup and COM positions] HEX X0 X1 X2 X3 COM position H E XX 0X 1X 2X 3 COM position 0 0 0 0 0 COM1 8 0 0 0 1 COM9 1 1 0 0 0 COM2 9 1 0 0 1 COM10 2 0 1 0 0 COM3 A 0 1 0 1 COM11 3 1 1 0 0 COM4 B 1 1 0 1 COM12 4 0 0 1 0 COM5 C 0 0 1 1 COM13 5 1 0 1 0 COM6 D 1 0 1 1 COM14 6 0 1 1 0 COM7 E 0 1 1 1 COM15 7 1 1 1 0 COM8 F 1 1 1 1 COM16
- “CGRAM data write” command (Specifies the address of CGRAM and writes character pattern data.) CGRAM (Character Generator RAM) has a 4-bit address to store alphanumeric character patterns. A character pattern stored in CGRAM can be displayed by specifying the character code (address) by DCRAM. The addresses of CGRAM are assigned to 00H to 0FH (All the other addresses are the CGROM addresses). The CGRAM can store 16 types of character patterns. [Command format] C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (2nd) LSB MSB : Specify 1st-column data. (It is written into CGRAM address 00H.) C8 C9 C10 C11 C12 C13 C14C15 B0 B1 B2 B3 B4 B5 B6 B7 3rd byte (3rd) LSB MSB : Specify 2nd-column data. (It is written into CGRAM address 00H.) X0 X1 X2 X3 0 1 0 0 B0 B1 B2 B3 B4 B5 B6 B7 1st byte (1st) LSB MSB : Setup and CGRAM address in the write-in mode of CGRAM data are specified. (Example: Specify CGRAM address 00H.) To specify character pattern data continuously to the next address, specify only character pattern data as follows. Since the address of CGRAM is automatically incremented, address specification is unnecessary. Data from the 2nd to 6th byte (character pattern) is regarded as one data item taken together, so 250ns s is sufficient for t DOFF time between bytes. C0 C1 C2 C3 C4 C5 C6 C7 B0 B1 B2 B3 B4 B5 B6 B7 2nd byte (4th) LSB MSB C8 C9 C10 C11 C12 C13 C14C15 B0 B1 B2 B3 B4 B5 B6 B7 3rd byte (5th) LSB MSB Specify 1st-column data. (It is written into CGRAM address 01H.) Specify 2nd-column data. (It is written into CGRAM address 01H.) X0 (LSB) to X3 (MSB): CGRAM address (4 bits: 16 characters worth) C0 (LSB) to C15 (MSB): Character data of CGRAM (16 bits: 16 outputs per digit)
[Positional relationship between CGRAM addresses setup and CGROM addresses] HEX X0 X1 X2 X3 CGROM address H E XX 0X 1X 2X 3 CGROM address 0 0 0 0 0 RAM00 8 0 0 0 1 RAM08 1 1 0 0 0 RAM01 9 1 0 0 1 RAM09 2 0 1 0 0 RAM02 A 0 1 0 1 RAM0A 3 1 1 0 0 RAM03 B 1 1 0 1 RAM0B 4 0 0 1 0 RAM04 C 0 0 1 1 RAM0C 5 1 0 1 0 RAM05 D 1 0 1 1 RAM0D 6 0 1 1 0 RAM06 E 0 1 1 1 RAM0E 7 1 1 1 0 RAM07 F 1 1 1 1 RAM0F Refer to the ROM Code Tables attached later in this document. Positional Relationship Between CGROM and CGRAM outputs SEG1 SEG2 SEG3 SEG4 C4SEG5C5 SEG6 SEG7C6 SEG8C7 C14 SEG15 C10 SEG11 C11SEG12C13SEG14 SEG10 C15 SEG16 SEG13C12 SEG9C8 C0–7: Corresponds to the 2nd byte of the CGRAM data write command. C8–15: Corresponds to the 3rd byte of the CGRAM data write commnad. *On CGROM A CGROM (Character Generator ROM) has an 8-bit address to generate alphanumeric type matrix character patterns. It has a capacity of 240 x 16 bits and can store 240 types of character patterns.
- “ADRAM data write” command (Specifies the address of ADRAM and writes symbol data) ADRAM (Additional Data RAM) has a 2-bit address to store symbol data. Symbol data specified by ADRAM is directly output without CGROM and CGRAM. (The ADRAM can store two types of symbol patterns for each digit.) The terminal to which the contents of ADRAM are output can be used as a cursor. [Command format] B0 B1 B2 B3 B4 B5 B6 B72nd byte (2nd) LSB MSB : Specify symbol data. (Example: Specify ADRAM address 0H.) X0 X1 X2 X3 1 1 0 0 B0 B1 B2 B3 B4 B5 B6 B71st byte (1st) LSB MSB : Setup and DCRAM address in the write-in mode o f DCRAM data are specified. (Example: Specify ADRAM address 0H.) To specify symbol data continuously to the next address, specify only symbol data as follows. Since the address of ADRAM is automatically incremented, address specification is unnecessary. B0 B1 B2 B3 B4 B5 B6 B72nd byte (3rd) LSB MSB : Specify symbol data. (It is written into ADRAM address 1H.) B0 B1 B2 B3 B4 B5 B6 B7 LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 LSB MSB B0 B1 B2 B3 B4 B5 B6 B7 LSB MSB 2nd byte (4th) 2nd byte (17th) 2nd byte (18th) Specify symbol data. (It is written into ADRAM address 2H.) Specify symbol data. (It is written into ADRAM address FH.) Specify symbol data. (It is rewritten into ADRAM address 0H.) X0 (LSB) to X3 (MSB) : ADRAM address (4 bits: 16 characters worth) C0 (LSB) to C1 (MSB) : Symbol data (2 bits: 2 symbols per digit) * : Don’t care [Relationship between ADRAM addresses setup and COM positions] HEX X0 X1 X2 X3 COM positions H E XX 0X 1X 2X 3 COM positions 0 0 0 0 0 COM1 8 0 0 0 1 COM9 1 1 0 0 0 COM2 9 1 0 0 1 COM10 2 0 1 0 0 COM3 A 0 1 0 1 COM11 3 1 1 0 0 COM4 B 1 1 0 1 COM12 4 0 0 1 0 COM5 C 0 0 1 1 COM13 5 1 0 1 0 COM6 D 1 0 1 1 COM14 6 0 1 1 0 COM7 E 0 1 1 1 COM15 7 1 1 1 0 COM8 F 1 1 1 1 COM16
- “Display duty set” command (Writes display duty value into the duty cycle register.) For display duty, brightness can be adjusted in 16 stages using 4-bit data. When power is turned on or when the RESET signal is input, the duty cycle register value is “0”. Always execute this command before turning the display on, then set a desired duty value. [Command format] D0 D1 D2 D3 1 0 1 0 B0 B1 B2 B3 B4 B5 B6 B7 1st byte LSB MSB : setup and duty value in display duty specification mode are specified. D0 (LSB) to D3 (MSB) : Display duty data (4 bits: 16 stages worth) [Relation between setup data and controlled COM duty] HEX D0 D1 D2 D3 COM duty HEX D0 D1 D2 D3 COM duty 0 0 0 0 0 0/16 8 0 0 0 1 8/16 1 1 0 0 0 1/16 9 1 0 0 1 9/16 2 0 1 0 0 2/16 A 0 1 0 1 10/16 3 1 1 0 0 3/16 B 1 1 0 1 11/16 4 0 0 1 0 4/16 C 0 0 1 1 12/16 5 1 0 1 0 5/16 D 1 0 1 1 13/16 6 0 1 1 0 6/16 E 0 1 1 1 14/16 7 1 1 1 0 7/16 F 1 1 1 1 15/16 * The state when power is turned on or when the RESET signal is input.
- “Number of display digits set” command (Writes the number of display digits into the number-of-display-digits register.) For the number of display digits, 1 to 16 digits can be specified using 4-bit data. When power is turned on or when a RESET signal is input, the number-of-display-digits register value is “0”. Always execute this command before turning the display on, then set a desired value. [Command format] K0 K1 K2 K3 0 1 1 0 B0 B1 B2 B3 B4 B5 B6 B7 1st byte LSB MSB : Setup in display digits specification mode and digits value is specified. K0 (LSB) to K3 (MSB) : Data of the number of display digits (4 bits: 16 digits worth) [Relation between data to be set and the number of digits of COM to be controlled] HEX K0 K1 K2 K3 No. of digits of COM H E X K 0K 1K 2K 3 No. of digits of COM 0 0 0 0 0 COM1–16 8 0 0 0 1 COM1–8 1 1 0 0 0 COM1 9 1 0 0 1 COM1–9 2 0 1 0 0 COM1–2 A 0 1 0 1 COM1–10 3 1 1 0 0 COM1–3 B 1 1 0 1 COM1–11 4 0 0 1 0 COM1–4 C 0 0 1 1 COM1–12 5 1 0 1 0 COM1–5 D 1 0 1 1 COM1–13 6 0 1 1 0 COM1–6 E 0 1 1 1 COM1–14 7 1 1 1 0 COM1–7 F 1 1 1 1 COM1–15 * The state when power is turned on or when the RESET signal is input.
- “All display lights ON” and “All display lights OFF” commands (Turns the entire display ON and OFF, respectively.) All display lights ON is used primarily for display testing. All display lights OFF is primarily used for display blink and to prevent false display upon power-on. [Command format] L H * * 1 1 1 0 B0 B1 B2 B3 B4 B5 B6 B7 1st byte LSB MSB : Select all display lights ON or OFF and specif y their operation. L: All display lights OFF H: All display lights ON * : Don’t Care [Data to be setup and display state of SEG and AD] L H Display state of SEG and AD 0 0 Normal display 1 0 Sets all outputs to Low * The state when power is turned on or when RESET signal is input 0 1 Sets all outputs to High 1 1 Sets all outputs to High * Priority is given to the All display lights ON command.
(Power applying included) Setup of the number display digits Setup of display duty CGRAM CGRAM character code Another RAM to be set? Release all display lights OFF mode ADRAM ADRAM character code DCRAM data write mode (including address setting) DCRAM character code DCRAM character code write ended? * Select a RAM to be used. * Display operation active Address is incremented automatically NO NO NO YES YES YES YES End of Setting NO Apply VDISP * Status of all outputs byRESET signal input Apply VDD All display lights OFF data write mode (including address setting) data write mode (including address setting) Address is incremented automatical ly Address is incremented automatically ADRAM character code write ended? CGRAM character code write ended? Power-off Flowchart Display operation active Turn off VDD Turn off VDISP
To prevent the IC from malfunctioning, turn on the logic power supply first, and then turn on the driver power supply when applying power. Also, for power-off, turn off the driver power supply first, then turn off the logic power supply. [Voltage] [Time] VDD Terminal Voltage VDISP Terminal Voltage >2.0μSec >2.0μSec
VDD COM1-16SEG1-16AD1-2VDD GND GND VDISP OSC0 DA CP CS Output port VDD VDISP ZD Alphanumeric fluorescent display tubes GRID (DIGIT) ANODE (SEGMENT) ANODE (SEGMENT) Heater transformer VDD GNDGND VDD Notes: 1. The V DD voltage depends on the power supply voltage of the microcontroller used. Adjust the value of the constants R1 and C1 to the power supply voltage used. 2. The V DISPvoltage depends on the vacuum fluorescent display tube used. Adjust the value of the constants R 2 and ZD to the voltage used. Reference data Shown below is a chart showing the V DISP voltage vs. output current of each driver. Care must be taken that the entire power consumption will not exceed the power dissipation. –30 –25 –20 –15 –10 17 22 27 32 37 42 Output Current (mA) VDISP Voltage VDISP Voltage vs. Output Current of Each Driver COM1–COM16 (Condition: VOH = VDISP –1.5 V) AD1–AD2 (Condition: VOH = VDISP–1.5 V) SEG1–SEG16 (Condition: VOH = VDISP–1.5 V) (V)
*ROM CODE is the character set for SEG1 to SEG16. *00000000b(00h) to 00001111b(0Fh) are the CGRAM addresses MSB LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
0000 RAM0
0001 RAM1
0010 RAM2
0011 RAM3
0100 RAM4
0101 RAM5
0110 RAM6
0111 RAM7
1000 RAM8
1001 RAM9
1010 RAMA
1011 RAMB
1100 RAMC
1101 RAMD
1110 RAME
1111 RAMF
16 Segment 14 Segment 7 Segment
16 Segment design 14 Segment design 7 Segment design
0000 0001 0010 0011 0100 0101 0110 0111 0001 0010 0011 0100 0111 LSB 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 RAM0 RAM1 RAM2 RAM3 RAM4 RAM5 RAM6 RAM7 RAM8 RAM9 RAMA RAMB RAMC RAMD RAME RAMF
QFP44-P-910-0.80-2K Package material Epoxy resin Lead frame material 42 alloy Pin treatment Sn/Pb Package weight (g) 0.41 TYP. 5 Rev. No./Last Revised 5/Nov. 20, 2002 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's SEMICONDUCTOR’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit: mm)
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact ROHM's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit: mm)
REVISION HISTORY
No. Date Previous Edition Current Edition
Description
FEDL9289-01 May 15, 2009 Final edition 1
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