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Issue Date: Nov., 26, 2002 ML9212 32-Bit Duplex/Triplex (1/2 duty / 1/3 duty) VF Controller/Driver with Digital Dimming GENERAL DESCRIPTION The ML9212 is a full CMOS controller/driver for Duplex or Triplex (1/2 duty or 1/3 duty) vacuum fluorescent display tube. It consists of a 32-segment driver multiplexed to drive up to 96 segments, and 10-bit digital dimming circuit. ML9212 features a selection of a master mode and a slave mode, and therefore it can be used to expand segments for the VFD driver with keyscan and A/D converter function. ML9212 provides an interface with a microcontroller only by three signal lines: DATA IN, CLOCK and CS.
FEATURES
Logic supply voltage (VDD) : 4.5 to 5.5 V Driver supply voltage (VDISP) : 8 to 18 V Duplex/Triplex (1/2 duty / 1/3 duty) selectable DUP/ TRI = 1/2 duty selectable at “H” level DUP/ TRI = 1/3 duty selectable at “L” level Number of display segments Max. 64-segment display (during 1/2 duty mode) Max. 96-segment display (during 1/3 duty mode) Master/Slave selectable M/ S = Master mode selectable at “H” level M/ S = Slave mode selectable at “L” level Interface with a microcontroller Three lines: CS, CLOCK, and DATA IN 32-segment driver outputs : I OH = –5 mA at VOH = VDISP–0.8 V (SEG1 to 22) (can be directly connected to VFD tube : I OH = –10 mA at VOH = VDISP–0.8V (SEG23 to 32) and require no external resisters) : I OL = 500 A at VOL = 2 V (SEG1 to 32) 3-grid pre-driver outputs : I OH = –5.0 mA at VOH = VDISP–0.8 V (require external drivers) I OL = 10 mA at VOL = 2 V Logic outputs : I OH = –200 A at VOH = VDD–0.8 V I OL = 200 A at VOL = 0.8 V Built-in digital dimming circuit (10-bit resolution) Built-in oscillation circuit (external R and C) Built-in Power-On-Reset circuit Package options: 56-pin plastic QFP (QFP56-P-910-0.65-2K)(ML9212GA)
LAPIS Semiconductor ML9212 BLOCK DIAGRAM Timing Generator DIM OUT SYNC OUT1 SYNC OUT2 DIM IN SYNC IN1 SYNC IN2 M/S DUP/TRI OSC Control Out1-32 32 bit Shift Register In1-10 Dimming Latch Out1-10 10 bit Digital Dimming POR OSC0 CS CLOCK DATA IN Out1-3 3 bit Shift Register PORPOR POR Out1-32 Segment Latch3 in1-32 3HOut1-32 Segment Latch2 in1-32 2HOut1-32 Segment Latch1 in1-32 1H Mode Select in1-3 POR 0H 4H Power On Reset VDD L-GND POR Out1-32 96 to 32 Segment Control in1-32 in1-32in1-32
32 Segment DriverVDISP
3 Grid Pre Driver
GRID2 GRID3 GRID1 SEG32SEG1 PORPORPOR
LAPIS Semiconductor ML9212 PIN CONFIGURATION (TOP VIEW) NC: No connection (OPEN) 56-pin Plastic QFP SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 GRID1 GRID2 GRID3 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 VDISP SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 D-GND SEG18 DIM IN SYNC IN 1 SYNC IN 2 CS CLOCK DATA IN L-GND NC OSC0
12 D-GND
14 VDD
24 DUP/TRI
25 M/S
26 SYNC OUT 2
27 SYNC OUT 1
28 DIM OUT
31 SEG2
30 SEG1
47 SEG17
46 SEG16
45 SEG15
44 SEG14
43 VDISP
LAPIS Semiconductor ML9212 PIN DESCRIPTIONS Symbol Pin Type Description VDISP 43, 56 — Power supply pins for VFD driver circuit. 43 pin and 56 pin should be connected externally. VDD 14 — Power supply pin for logic drive. D-GND 12, 49 — L-GND 21 — D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. 12 pin, 21 pin and 49 pin should be connected externally. SEG1 to 22 30 to 42, 44 to 48, 50 to 53 O Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. l OHL –5 mA SEG23 to 32 1 to 8, 54, 55 O Segment (anode) signal output pins for a VFD tube. These pins can be directly connected to the VFD tube. External circuit is not required. l OHL –10 mA GRID1 to 3 9, 10, 11 O Inverted Grid signal output pins. For pre-driver, the external circuit is required. l OL 10 mA CS 18 I Chip select input pin. Data is not transferred when CS is set to a Low level. CLOCK 19 I Shift clock input pin. Serial data shifts at the rising edge of the CLOCK. DATA IN 20 I Serial data input pin (positive logic). Data is input to the shift register at the rising edge of the CLOCK signal. DUP/TRl 24 I Duplex/Triplex operation select input pin. Duplex (1/2 duty) operation is selected when this pin is set to VDD. Triplex (1/3 duty) operation is selected when this pin is set to L-GND. M/S 25 I Master/Slave mode select input pin. Master mode is selected when this pin is set to VDD. Slave mode is selected when this pin is set to L-GND. DIM IN 15 I Dimming pulse input. When the slave mode is selected, the pulse width of the all segment output are controlled by a input pulse width of DIM IN. Connect this pin to the master side DIM OUT pin at the slave mode. When the master mode is selected, the input level of this pin is ignored and the pulse width of the all grids and segment outputs are controlled by a built-in 10-bit dimming circuit. Connect this pin to V DD or L-GND at the master mode.
LAPIS Semiconductor ML9212 Symbol Pin Type Description SYNC IN 1, 2 16, 17 I Synchronous signal input. When the slave mode is selected, connect these pins to the master side SYNC OUT 1, and 2 pins. When the master mode is selected, the input level of these pins are ignored. Connect these pins to V DD or L-GND at the master mode. DIM OUT 28 O Dimming pulse output. Connect this pin to the slave side DIM IN pin. SYNC OUT 1, 2 26, 27 O Synchronous signal output. Connect these pins to the slave side SYNC IN 1, and 2 pins. OSC0 23 I/O RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details refer to ELECTRICAL CHARACTERISTICS. NC 13,22,29 - OPEN pins. ABSOLUTE MAXIMUM RATING Parameter Symbol Condition Ratings Unit Driver Supply Voltage V DISP — –0.3 to +20 V Logic Supply Voltage V DD — –0.3 to +6.5 V Input Voltage VIN — –0.3 to VDD+0.3 V Power Dissipation PD Ta 105°C 233 mW Storage Temperature T STG — –55 to +150 °C Io1 SEG1 to 22 –10.0 to +2.0 mA Io2 SEG23 to 32 –20.0 to +2.0 mA Io3 GRID1 to 3 –10.0 to +20.0 mA Output Current Io4 DIM OUT, SYNC OUT1, SYNC OUT2 –2.0 to +2.0 mA RECOMMENDED OPERATING CONDITIONS Parameter Symbol Condition Min. Typ. Max. Unit Driver Supply Voltage V DISP — 8.0 13.0 18.0 V Logic Supply Voltage V DD — 4.5 5.0 5.5 V High Level Input Voltage V IH All inputs except OSC0 0.8V DD — — V Low Level Input Voltage V IL All inputs except OSC0 — — 0.2V DD V Clock Frequency fC — — — 2.0 MHz VDD OSC0 R C
LAPIS Semiconductor ML9212 Parameter Symbol Condition Min Typ. Max. Unit Oscillation Frequency f OSC R = 10 k±5%, C = 27 pF±5% 2.2 3.3 4.4 MHz 1/3 duty 179 269 358 Frame Frequency f FR R = 10 k±5%, C = 27 pF±5% 1/2 duty 268 403 538 Hz Operating Temperature T OP — –40 — +105 °C
LAPIS Semiconductor ML9212
ELECTRICAL CHARACTERISTICS
Ta = –40 to +105°C, V DISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter Symbol Applied pin Condition Min. Max. Unit High Level Input Voltage V IH *1) — 0.8V DD — V Low Level Input Voltage V IL *1) — — 0.2V DD V High Level Input Current I IH *1) V IH = VDD –1.0 +1.0 A Low Level Input Current I IL *1) V IL = GND –1.0 +1.0 A VOH1 SEG1-22 lOH1 = –5 mA V DlSP – 0.8 — V VOH2 SEG23-32 lOH2 = –10 mA V DlSP – 0.8 — V VOH3 GRID1-3 VDISP = 9.5V lOH3 = –5 mA V DlSP – 0.8 — V High Level Output Voltage VOH4 *2) VDD = 4.5 V lOH4 = –200 AV DD – 0.8 — V VOL1 SEG1-22 lOL1 = 500 A — 2.0 V VOL2 SEG23-32 lOL2 = 500 A — 2.0 V VOL3 GRID1-3 VDlSP = 9.5V lOL3 = 10 mA — 2.0 V Low Level Output Voltage VOL4 *2) VDD = 4.5 V lOL4 = 200 A — 0.8 V IDISP V DISP — 100 uA Supply Current IDD V DD R = 10 k±5%, C = 27 pF±5% no load — 5.0 mA *1) CS, CLOCK, DATA IN, DIM IN, SYNC IN 1, SYNC IN 2, M/S, DUP/TRI *2) DIM OUT, SYNC OUT 1, SYNC OUT 2
LAPIS Semiconductor ML9212 AC Characteristics Ta = –40 to +105°C, V DISP = 8.0 to 18.0 V, VDD = 4.5 to 5.5 V Parameter Symbol Condition Min. Max. Unit Clock Frequency fC — — 2.0 MHz Clock Pulse Width tCW — 200 — ns Data Setup Time tDS — 200 — ns Data Hold Time tDH — 200 — ns CS Off Time tCSL — 20 — s CS Setup Time (CS-Clock) tCSS — 200 — ns CS Hold Time (Clock-CS) tCSH — 200 — ns CS Wait Time tRSOFF — 400 — ns tR t R = 20% to 80% — 2.0 s Output Slew Rate Time tF CL = 100 pF tF = 80% to 20% — 2.0 s VDD Rise Time tPRZ Mounted in a unit — 100 s VDD Off Time tPOF Mounted in a unit, V DD = 0.0 V 5.0 — ms TIMING DIAGRAM Data Input Timing Reset Timing Driver Output Timing CS CLOCK DATA IN tDS t DH tCSS –0.8VDD –0.2VDD –0.8VDD –0.2VDD –0.8VDD –0.2VDD 1/fC tCW tCW tCSH tCSL VALID VALID VALID VALID VDD CS tPOFtPRZ tRSOFF –0.8VDD –0.0 V –0.8VDD –0.0 V –0.8VDISP –0.2VDISP SEG1-32, GRID1-3 tR tRtF
LAPIS Semiconductor ML9212 Output Timing (Duplex Operation) *1bit time = 4/f OSC Solid line : The dimming data is 1016/1024 at the master mode Dotted line : The dimming data is 64/1024 at the master mode Output Timing (Triplex Operation) *1bit time = 4/f OSC Solid line : The dimming data is 1016/1024 at the master mode Dotted line : The dimming data is 64/1024 at the master mode 1016 bit times 1016 bit times1016 bit times GRID1 VDISP D-GND GRID2 VDISP D-GND GRID3 SEG1-32 VDISP D-GND DIM OUT L-GND SYNC OUT1 L-GND SYNC OUT2 L-GND VDISP D-GND 2048 bit times(1 display cycle) 8 bit times8 bit times 8 bit times 64 bit times 64 bit times 64 bit times 1016 bit times 1016 bit times 1016 bit times GRID1 GRID2 GRID3 SEG1-32 DIM OUT SYNC OUT1 SYNC OUT2 3072 bit times(1 display cycle) 8 bit times8 bit times 8 bit times 64 bit times 64 bit times 64 bit times VDD VDD VDD VDISP D-GND VDISP D-GND VDISP D-GND L-GND L-GND L-GND VDISP D-GND VDD VDD VDD
LAPIS Semiconductor ML9212 FUNCTIONAL DESCRIPTION Power-on Reset Wh en power is turned on, ML9212 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: The contents of the shift registers and latches are set to “0”. The digital dimming duty cycle is set to “0”. All segment outputs are set to Low level. GRID1 outputs are set to Low level. GRID2 to 3 outputs are set to High level. Data Transfer Method Data can be tran sferred between the rising edge and the next falling edge of chip select input. The mode data, segment data and dimming data are written by a serial transfer method. The serial data is input to the shift register at the rising edge of a shift clock pulse. The mode data (M0 to M2) must be transferred after the segment data and dimming data succeedingly. When the chip select input falls, an internal LOAD signal is automatically generated and data is loaded to the latches. Function Mode Fun ction mode is selected by the mode data (M0 to M2). The relation between function mode and mode data is as follows: FUNCTION DATA FUNCTION MODE OPERATING MODE M0 M1 M2
0 Segment Data for GRID1-3 Input 0 0 0
1 Segment Data for GRID1 Input 1 0 0
2 Segment Data for GRID2 Input 0 1 0
3 Segment Data for GRID3 Input 1 1 0
4 Digital Dimming Data Input 0 0 1
Segment Data Input [Function Mode: 0 to 3] ML9212 receiv es the segment data when function mode 0 to 3 are selected. The same segment data is transferred to the 3 segment data latches corresponding to GRID1 to 3 at the same time when the function mode 0 is selected. The segment data is transferred to only one segment data latch corresponding to the specified GRID when the function mode is 1, 2 or 3 is selected. Segment output (SEG1 to 32) becomes High level (lightning) when the segment data (S1 to S32) is set to “1”. [Data Format] Input Data : 35 bits Segment Data : 32 bits Mode Data : 3 bits Bit 1 2 3 4 29 30 31 32 33 34 35 Input DATA S1 S2 S3 S4 S29 S30 S31 S32 M0 M1 M2 (3 bits) Segment Data (32 bits) Mode Data
LAPIS Semiconductor ML9212 [Bit correspondence between segment output and segment data] SEG n 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Segment data S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 SEG n 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Segment data S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 Digital Dimming Data Input [Function Mode: 4] ML9212 receiv es the digital dimming data when function mode 4 is selected. The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. The 10-bit digital dimming data is input from LSB. [Data Format] Input Data : 13 bits Digital Dimming Data : 10 bits Mode Data : 3 bits Bit 1 2 3 4 5 6 7 8 9 10 11 12 13 Input DATA D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 M0 M1 M2 (LSB) Dimming Data (MSB) D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Duty Cycle 0 0 0 0 0 0 0 0 0 0 0/1024 1 0 0 0 0 0 0 0 0 0 1/1024 1 1 1 0 1 1 1 1 1 1 1015/1024 0 0 0 1 1 1 1 1 1 1 1016/1024 1 0 0 1 1 1 1 1 1 1 1016/1024 1 1 1 1 1 1 1 1 1 1 1016/1024 Master Mode Mast er Mode is selected when M/S pin is set at High level. The master mode operation is as follows: The input levels of DIM IN, SYNC IN1 and SYNC IN2 are ignored, and these pins should be connected to L-GND or VDD. The pulse width of GRID1 to 3 and SEG1 to 32 are controlled by the internal digital dimming circuit. The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by the internal timing generator. Digital Dimming Data (10 bits) Mode Data (3 bits) LSB MSB
LAPIS Semiconductor ML9212 Slave Mode Slave Mode is selected when M/S pin is set at Low level. The slave mode operation is as follows: The internal dimming circuit is ignored. The pulse width of SEG1 to 32 are controlled by the pulse width of DIM IN signal. The segment Latch1 to 3 corresponding to GRID1 to 3 are selected by SYNC IN1 and SYNC IN2 signals. The output levels of GRID1 to 3 are set at High level. The output levels of DIM OUT, SYNC OUT1 and SYNC OUT2 are set at Low level. [Correspondence between SYNC IN1, 2 and Segment Latch1 to 3] [Correspondence between DIM IN and SEG1 to 32] SYNC IN 1 SYNC IN 2 Segment Latch GRID DIM IN SEG1 to 32 0 0 No No 0 Low 1 0 Latch1 GRID1 1 High 0 1 Latch2 GRID2 Note: Low: Lights OFF 1 1 Latch3 GRID3 High: Lights ON
LAPIS Semiconductor ML9212 APPLICATION CIRCUITS 1. Circuit for the duplex VFD t ube wi th 128 segments (2 Grid 64 Anode) (MASTER) ML9212 (SLAVE) VDISP VDD D-GND L-GND OSC 0 CLOCK DATA IN CS DIM IN SYNC IN 2 SYNC IN 1 DIM OUT SYNC OUT1 SYNC OUT2 GRID2 GRID1 GRID3 SEG1 SEG32 Duplex VF Tube Microcontroller M/S DUP/TRI Ef GND R C S2 S3 S62 S64 S63 VDD GND GND VDD VDISP ML9212 VDD D-GND L-GND CLOCK CS DIM IN SYNC IN 2 SYNC IN 1 DIM OUT SYNC OUT1 GRID2 GRID1 GRID3 SEG1 SEG32 M/S DUP/TRI GND R C VDD GND DATA IN SYNC OUT2 VDISP OSC 0
LAPIS Semiconductor ML9212 2. Circuit for the triplex VFD tube with 192 segments (3 Grid 64 A node) Triplex VF Tube Ef S2 S3 S62 S64 S63 (MASTER) ML9212 (SLAVE) VDISP VDD D-GND L-GND DATA IN DIM IN SYNC IN 2 SYNC IN 1 DIM OUT SYNC OUT1 SYNC OUT2 GRID2 GRID3 SEG1 SEG32 M/S DUP/TRI GND R C GND ML9212 VDD D-GND L-GND DIM IN SYNC IN 1 DIM OUT GRID2 GRID1 GRID3 SEG1 SEG32 M/S DUP/TRI GND R C VDD GND DATA IN SYNC OUT2 GRID1 OSC 0 CLOCK CS SYNC OUT1 VDISP SYNC IN 2 CLOCK CS OSC 0 Microcontroller GND VDD VDISP
LAPIS Semiconductor ML9212 NOTES ON TURNING POWER ON/OFF Connect L-GND and D-GND externally to be an equal potential voltage. To avoid wrong operations, turn on the driver power supply after turning on the logic power supply. Conversely, turn off the logic power supply after tuning off the driver power supply. [Voltage] [Time] VDD VDISP
LAPIS Semiconductor ML9212
REVISION HISTORY
No. Date Previous Edition Current Edition
Description
FEDL9212-01 Nov., 26, 2002 – – Final edition 1
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