FEDL630Q464-01

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Issue Date: Oct. 26, 2016 ML630Q464/Q466 Ultra Low Power 32-bit Microcontroller ■ GENERAL DESCRIPTION This LSI is a high -performance low power 32 -bit microcontroller. Equipped with a 32 -bit CPU core Cortex TM-M0+, it implements a 128 KB flash memory, 16 KB RAM, rich peripheral circuits, such as USB Full speed device, synchronous serial port, UART, I2C bus interface, supply voltage level detect circuit, RC oscillation type A/D converter, successive approximation type A/D converter, and LCD driver . The Flash ROM that is installed as program memory achieves low -voltage low -power consumption operation (read operation) is most suitable for battery-driven applications. ■ FEATURES

• CP U − 32-bit RISC CPU (CPU name: ARM CortexTM-M0+) − Thumb®/Thumb®-2 instruction supported − Serial Wire Debug Port − Minimum instruction execution time 30.5 µs (@32.768 kHz system clock) 41.7ns (@24 MHz system clock)
• Internal memory − Re-writing the program memory area by software − Number of segments Product name Flash memory S RAM Program area Data area ML630Q464 64KB (16K × 32bit) 2KB (0.5K × 32bit) 8KB (2K × 32bit) ML630Q466 128KB (32K × 32bit) 2KB (0.5K × 32bit) 16KB (4K × 32bit)
• I nterrupt controller (NVIC) − 1 non-maskable interrupt source (Internal source: 1) − 31 maskable interrupt sources (Internal sources: 30, External sources: 1) − Priority level (4-level) can be set for each interrupt
• DMA controller (DMAC) − 2 channels − Enable to allocate multiple DMA transfer request sources for each channel. − Channel priority: fixed mode/round robin mode − DMA transfer mode: cycle steal mode/burst mode − DMA request type: software requests/hardware requests − Maximum transfer count: 65,536 − Data transfer size: 8 bits/16 bits/32 bits − Transfer request source: SSIOF, UART, UARTF, I2CF, RC-ADC, SA-ADC
• Time base counter (TBC) − Low-speed time base counter ×1 channel
• 1 kHz Timer − 10 Hz / 1 Hz interrupt function

• Timers (TMR) − 8 bits × 8 channels (Timer0-7: 16-bit x 4 configuration available by using Timer0-1 or Timer2-3, Timer4-5, Timer6-7) − Selection of one shot timer mode is possible − External clock can be selected as timer clock.
• Function Timers (FTM) − 16-bit × 4 channels − Equipped with the timer/capture/PWM functions using a 16-bit counter − An event trigger (external pin input interrupt or timer interrupt request) can control start/stop/clear of the timer (however , th e minimum pulse width of pin input is timer clock 3φ) − 1 to 64 dividing of LSCLK/OSCLK/HSCLK/external input selectable as timer clock − Two types of PWM with the same period and different duties and complementary PWM with the dead time set can b e o utput.
• Real Time Clock (RTC) − 1 channels (99 years calendar, alarm, revision of the clock)
• Watchdog timer (WDT) − Non-maskable interrupt and reset − Free running − Overflow period: 4 types selectable (125ms, 500ms, 2s, and 8s when LSCLK = 32.768 kHz)
• Synchronous serial port (SSIOF/SSIO) − without FIFOs (SSIO) : 1 channel − with 16-byte transmits and receives FIFOs (SSIOF) : 1 channel − Master/slave selectable − LSB first/MSB first selectable − Clock polarity (data out at rising edge and data in at falling edge/data out at falling edge and data in at rising edge) selectable − 8-bit length/16-bit length selectable − Initial clock level (High start/Low start) selectable − supports slave-select signal (only SSIOF)
• UART (UARTF/UART) − without FIFOs (UART) : 1channel − with 16-byte transmits and receives FIFOs (UARTF) :1 channels − Full duplex buffer system − Communication speed: Settable within the range of 2400bps to 115200bps. − Programmable interface (data length, parity, stop bits selectable)
• I2C bus interface (I2CF/I2C) − without FIFOs(I2C) :1 channel − with 16-byte transmits and receives FIFOs (I2CF) : 1 channels − Master/slave function (only I2CF) − Fast mode (400 kHz), standard mode (100 kHz)
• USB full-speed device − Compliant with Universal Serial Bus (USB) − Full speed (12 Mbps) 1 port. − End points: 5 or 6 − Supports all data transfer types (control transfer, bulk transfer, interrupt transfer, isochronous transfer). − Built-in SOF generation and CRC5/16 generation functions − Access size to data transfer FIFOs: 8 bits/16 bits/32 bits
• General-purpose ports (PORT) − Input/output port × 38 channels (including secondary or tertiary or quaternary or quinary functions). (ML630Q464 and ML630Q466: including LCD com/seg ports ( each 20 ports ))

• RC oscillation type A/D converter (RC-ADC) − Time division × 2 channels − Starting by trigger of Timer/FTM function. − 24-bit counter
• Successive approximation type A/D converter (SA-ADC) − Input × 12 channels − 12-bit A/D converter − Starting by trigger of Timer/FTM function. − Capacitive touch sense function
• Analog Comparator (CMP) − Input × 2ch − Common mode input voltage: 0.2V to VDD－0.2V − Input offset voltage: 30mV(max) − Interrupt allow edge selection and sampling selection
• Voltage Level Supervisor (VLS) − Threshold voltages: One of 64 levels − Acuraccy: ±3% − Interrupt or Reset generation are slectable − Voltage measurement with voltage input pin or VDD pin
• Low Level Detector(LLD) − Judgment Voltage: 1.8V±0.2V − Can be used as low level detection reset.
• LCD driver − Maximun 400 dots (50 segment x 8 common) − 1/1 to 1/8 duty − 1/2, 1/3 bias (built-in bias generation circuit) − Frame frequency selecable − Bias voltage multiplying clock selectable (5 types) − Contrast adjustment (32 steps) − 4 operating mode: LCD drive stop, LCD display, all LCDs on, all LCDs off − Programmable display allocation function
• Random number generator (RANDOM) − Generates 8-bit random numbers
• AES − 128-bit Common key − Supports key sizes of 128, 192, and 256 bits − Supports ECB, CBC, and CTR modes
• Reset − Reset by the RESET_N pin input − Reset by power-on detection − Reset by overflow of watchdog timer (WDT) − Reset by threshold detection in Voltage Level Supervisor(VLS) − Reset by low level detection in Low Level Detector(LLD) − Reset by the low-speed crystal oscillation stop detection − Reset by SYSRESETREQ of CortexTM-M0+ (software reset)

• Clock − Low-speed clock: − Crystal oscillation (32.768 kHz) − Built-in RC oscillation (32.768kHz) − High-speed clock: − PLL (24 MHz) generated from Crystal oscillation (32.768 kHz) − Built-in RC oscillation (16MHz)
• Power management − HALT mode: Instruction execution by CPU is suspended. All peripheral circuits can keep in operating states. − HALT-H mode: Instruction execution by CPU is suspended . Stop of high- speed oscillation auto matically. All peripheral circuits can keep in operating states. − DEEP-HALT mode: Instruction execution by CPU is suspended . Some peripheral circuits(Timer, LTBC etc.) can keep in operating states. − ULTRA-DEEP-HALT mode: Instruction execution by CPU is s uspended. Some peripheral circuits(Timer, LTBC etc.) can keep in operating states, at VDD>2.5V. − STOP mode: Stop of low -speed oscillation and high -speed oscillation (Operations of CPU and peripheral circuits are stopped.) − Clock gear: The frequency of hi gh-speed system clock can be changed by software (1/1, 1/2, 1/4, 1/8,1/16,1/32 of the oscillation clock) − Block Control Function: Power down (reset registers and stop clock supply) the circuits of unused peripherals.
• Guaranteed operating range − Operating temperature (ambient) : −40°C to +85°C − Operating voltage: VDD = 1.8V to 3.6V
• Supply current (Typ) − High-speed operation (24 MHz) : 250uA/MHz − ULTRA-DEEP-HALT : 0.80uA
• Package − 100-pin plastic TQFP − Tray ML630Q464- xxxTBZWAX ML6 30Q466-xxxTBZWAX

Figure 1. ML630Q464/Q466 Block Diagram

8 Timer

4 Function

■ PIN CONFIGURATION F igure 2. Pin Layout of ML630Q464/Q466

■ PIN LIST PIN No. .Reset State Primary Function Secondary Function Tertiary Function Quaternary Function Quinary Function Pin name I/O Pin name I/O pin name I/O pin name I/O pin name I/O

78 Pull-up

77 Pull-up

76 Pull-up

75 Pull-down

95 Hi-Z

I/O IN0 I SOUT0 O RXDF0 I – –

96 Hi-Z

I/O CS0 O SIN0 I TXDF0 O – –

97 Hi-Z

I/O RCT0 O SCK0 I/O TMOUT0 O – –

98 Hi-Z

I/O RS0 O – – TMOUT1 O – –

99 Hi-Z

100 Hi-Z

91 Hi-Z

I/O IN1 I SOUTF0 O – – – –

92 Hi-Z

I/O CS1 O SINF0 I – – – –

93 Hi-Z

I/O RS1 O SCKF0 I/O TMOUT2 O – –

94 Hi-Z

I/O RT1 O SSF0 I/O TMOUT3 O – –

82 Hi-Z

I/O SDAF0 I/O SOUT0 O – – – –

83 Hi-Z

I/O SCLF0 I/O SIN0 I – – – –

84 Hi-Z

I/O RXDF0 I SCK0 I/O TMOUT4 O – –

85 Hi-Z

I/O TXDF0 O 32kCLKO O TMOUT5 O – –

86 Hi-Z

I/O SDA1 I/O SOUTF0 O – – – –

87 Hi-Z

I/O SCL1 O SINF0 I – – – –

88 Hi-Z

I/O RXD0 I SCKF0 I/O TMOUT6 O – –

89 Hi-Z

I/O TXD0 O SSF0 I/O TMOUT7 O – – 13 to Low Level

9 Hi-Z

8 Hi-Z

7 Hi-Z

6 Hi-Z

49 Hi-Z

I/O SDAF0 I/O SOUT0 O – – SEG34 O

No. .Reset State Primary Function Secondary Function Tertiary Function Quaternary Function Quinary Function Pin name I/O Pin name I/O pin name I/O pin name I/O pin name I/O

50 Hi-Z

I/O SCLF0 I/O SIN0 I – – SEG35 O

51 Hi-Z

I/O RXDF0 I SCK0 I/O TMOUT8 O SEG36 O

52 Hi-Z

I/O TXDF0 O 32kCLKO O TMOUT9 O SEG37 O

53 Hi-Z

EXI44 I/O SDA1 I/O SOUTF0 O – – SEG38 O

54 Hi-Z

EXI45 I/O SCL1 O SINF0 I – – SEG39 O

55 Hi-Z

I/O RXD0 I SCKF0 I/O TMOUTA O SEG40 O

56 Hi-Z

I/O TXD0 O SSF0 I/O TMOUTB O SEG41 O

57 Hi-Z

EXI50 I/O SDAF0 I/O SOUT0 O – – SEG42 O

58 Hi-Z

EXI51 I/O SCLF0 I/O SIN0 I – – SEG43 O

59 Hi-Z

EXI52 I/O RXDF0 I SCK0 I/O TMOUTC O SEG44 O

60 Hi-Z

EXI53 I/O TXDF0 O 32kCLKO O TMOUTD O SEG45 O

61 Hi-Z

EXI54 I/O SDA1 I/O SOUTF0 O – – SEG46 O

62 Hi-Z

EXI55 I/O SCL1 O SINF0 I – – SEG47 O

63 Hi-Z

I/O RXD0 I SCKF0 I/O TMOUTE O SEG48 O

64 Hi-Z

I/O TXD0 O SSF0 I/O TMOUTF O SEG49 O

66 Hi-Z

67 Hi-Z

69 Low

■ PIN DESCRIPTION In the table below indicates the functional pin description. The pin name represents the function pin name of the primary function of each terminal, The pin mode represents the set of mode register of Port Control. (1st:primary function, 2nd:secondary function, 3rd: tertiary function, 4th: quaternary function, 5th:quinary function) Pin name I/O Description LSI pin name Pin mode Logic System RESET_N I Reset input pin. When this pin is set to a “L” level, system reset mode is set and the internal section is initialized. When this pin is set to a “H” level subsequently, program execution starts. A pull-up resistor is internally connected. RESET_N – L BRMP I Remapping control input (for firmware update) Based on the BRMP pin setting at the time of the reset release, Bank0 is remapped. BRMP – H XT0 I Crystal connection pin for low-speed clock. Capacitors CDL and CGL are connected across this pin and VSS as required. XT0 – – XT1 O XT1 – – 32kCLKO O Low-speed clock output pin P33,P43,P53 2nd General-purpose input/output port P00-P05 I/O General-purpose input/output port. P00-P05 1st – P20-P23 I/O General-purpose input/output port. P20-P23 1st – P30-P37 I/O General-purpose input/output port. P30-P37 1st – P40-P47 I/O General-purpose input/output port. P40-P47 1st – P50-P57 I/O General-purpose input/output port. P50-P57 1st – P60-P63 I/O General-purpose input/output port. P60-P63 1st – External interrupt EXI00-05 EXI20-23 EXI30-37 EXI40-47 EXI50-57 EXI60-63 I External maskable interrupt input pins. It is possible, for each bit, to specify whether the interrupt is enabled and select the interrupt edge by software. P00-P05 P20-P23 P30-P37 P40-P47 P50-P57 P60-P63 1st H/L LED LED O N-channel open drain output pins to drive LED. P34,P35,P40,P41 1st – UART TXD0 O UART data output pin. P37,P47,P57 2nd – RXD0 I UART data input pin. P36,P46,P56 2nd – TXDF0 O UARTF with FIFO data output pin. P01,P33,P43,P53 2nd – RXDF0 I UARTF with FIFO data input pin. P00,P32,P42,P52 2nd – I2C bus interface SDA1 I/O I2C1 data input/output pin. This pin has an NMOS open drain output. When using this pin as a function of the I2C, externally connect a pull-up resistor. P34,P44,P54 2nd – SCL1 O I2C1 clock output pin. This pin has an NMOS open drain output. When using this pin as a function of the I2C, externally connect a pull-up resistor. P35,P45,P55 2nd – SDAF0 I/O I2CF0 data input/output pin. This pin has an NMOS open drain output. When using this pin as a function of the I2C, externally connect a pull-up resistor. P30,P40,P50 2 nd – SCLF0 I/O I2CF0 clock input/output pin. This pin has an NMOS open drain output. When using this pin as a function of the I2C, externally connect a pull-up resistor. P31,P41,P51 2 nd –

/37 Pin name I/O Description LSI pin name Pin mode Logic Synchronous serial SCK0 I/O Synchronous serial (SSIO) clock input/output pin. P02,P32,P42,P52 3rd – SIN0 I Synchronous serial (SSIO) data input pin. P01,P31,P41,P51 3rd – SOUT0 O Synchronous serial (SSIO) data output pin. P00,P30,P40,P50 3rd – SCKF0 I/O Synchronous serial with FIFO (SSIOF) clock input/output pin. P22,P36,P46,P56 3rd – SINF0 I Synchronous serial with FIFO (SSIOF) data input pin. P21,P35,P45,P55 3rd – SOUTF0 O Synchronous serial with FIFO (SSIOF) data output pin. P20,P34,P44,P54 3rd – SSF0 I/O Synchronous serial with FIFO (SSIOF) select input/output pin. P23,P37,P47,P57 3rd L FTM TMOUT0-9 TMOUTA-F O FTM output pin. P02,P03,P22,P23 P32,P33,P36,P37 P42,P43,P46,P47 P52,P53,P56,P57 4th – TMCKI0-7 I External clock input pin for FTM. P42,P43,P46,P47 P36,P37,P56,P57 1st – RC oscillation type A/D converter IN0 I Oscillation input pin of Channel 0. P00 2 nd – CS0 O Reference capacitor connection pin of Channel 0. P01 2nd – RS0 O Reference resistor connection pin of Channel 0. P03 2nd – RT0 O Resistor sensor connection pin for measurement of Channel 0. P04 2nd – RCT0 O Resistor/capacitor sensor connection pin of Channel 0 for measurement. P02 2nd – RCM O RC oscillation monitor pin. P05 2nd – IN1 I Oscillation input pin of Channel 1. P20 2nd – CS1 O Reference capacitor connection pin of Channel 1. P21 2nd – RS1 O Reference resistor connection pin of Channel 1. P22 2 nd – RT1 O Resistor sensor connection pin for measurement of Channel 1. P23 2 nd – Successive approximation type A/D converter VREF I Reference power supply pin for successive approximation type A/D converter. VREF – – AIN0-11 I Analog input for successive approximation type A/D converter. (AIN0-3) P32-35, (AIN4-7) P20-23, (AIN8-11) P00-03 1st – Analog comparator CMP0P I Comparator0 Non-inverted input pin. P30 1st – CMP0M I Comparator0 Inverted input pin. P31 1st – CMP1P I Comparator1 Non-inverted input pin. P32 1 st – CMP1M I Comparator1 Inverted input pin. P33 1 st – USB FS Device DP I/O USB dev D+ pin. DP – – DM I/O USB dev D- pin. DM – – PUCTL O USB dev pull-up control PUCTL – – DEBUG Interface SWC I Serial clock of Serial Wire Debug Port SWC – – SWD I/O Serial I/O data of Serial Wire Debug Port SWD – –

/37 Pin name I/O Description LSI pin name Pin mode Logic Power supply VSS – Negative power supply pin. VSS – – VDD – Positive power supply pin. VDD – – VDDL – Positive power supply pin (internally generated) for internal logic. Capacitors CL is connected between this pin and VSS. VDDL – – VHF – Positive power supply pin (internally generated) for built-in halver circuit. Capacitor CVH is connected between this pin and VSS. VHF – – CH1 – CH2 – Capacitor pins of built-in halver circuit CH1 – CH2 – – LCD driver COM0 – COM3 – Common pins of LCD driver COM0 – COM3 – – COM4 – COM7 – Common pins of LCD driver P60-P63 2 nd – SEG0 – SEG33 – Segment pins of LCD driver SEG0 – SEG33 – – SEG34 – SEG49 – Segment pins of LCD driver P40-P47 P50-P57 5th – C1 – C2 – Capacitor pins of built-in generation bias circuit C1 – C2 – – VL1 – VL3 – Reference voltage input pins of built-in bias generation circuit VL1 – VL3 – –

/37 ■ TERMINATION OF UNUSED PINS Table 1 shows methods of terminating the unused pins. Table 1 Termination of Unused Pins Pin Recommended pin termination RESET_N open BRMP Connect a pull-down resistor. SWC Connect a pull-up resistor. SWD Connect a pull-up resistor. VREF Connect to VDD P00 to P05 open P20 to P23 open P30 to P37 open P40 to P47 open P50 to P57 open P60 to P63 open COM0 to COM3 open SEG0 to SEG33 open DP, DM, PUCTL open VL1, VL2, VL3 open C1, C2 open ote] For unused input ports or unused input/output ports, if the corresponding pins are configured as high- impedance inputs and left open, the supply current may become excessively large. Therefore, it is recommended to configure those pins as either inputs with a pull-down resistor/pull-up resistor or outputs.

/37 ■ Electrical Characteristics

• ABSOLUTE MAXIMUM RATINGS （VSS=0V） Parameter Symbol Condition Rating Unit Power supply voltage 1 V DD Ta=25°C -0.3 to +4.6 V Power supply voltage 2 V DDL Ta=25°C -0.3 to +2.0 V Power supply voltage 3 V L1-3 Ta=25°C -0.3 to +6.0 V Input voltage(P00-P05, P20-P23, P30-P35, SWC, SWD, BRMP, RESET_N, DP, DM) VIN Ta=25°C -0.3 to VDD+0.3 V Input voltage (5 V tolerant) P50-P57, P60-P63) VINT Ta=25°C -0.3 to +6.0 V Output voltage 1 V OUT1 Ta=25°C -0.3 to VDD+0.3 V Output voltage 2 (COM0 to COM7 SEG0 to SEG49) VOUT2 Ta=25°C -0.3 to VL1-3+0.3 V Output current 1 I OUT1 Ta=25°C -12 to +11 mA Output current 2 I OUT2 Ta=25°C -12 to +20 mA Power dissipation PD Ta=25°C 0.9 W Storage temperature T STG – -55 to +150 °C

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• RECOMMENDED OPERATING CONDITIONS （VSS=0V） Parameter Symbol Condition Range Unit Operating temperature (Ambience) TOP – -40 to +85 °C Operating voltage V DD – 1.8 to 3.6 V Reference voltage V REF – 1.8 to VDD V Operating frequency (CPU) fOP – LSCLK:32.768k HSCLK:500k to 24M Hz Low speed crystal oscillation frequency fXTL – 32.768k Hz Low speed crystal oscillation external capacitor 1 CDL Using VT-200-FL(from SII） 6.8 to 12 pF CGL 6.8 to 12 Low speed crystal oscillation external capacitor 2 CDL Using DT-26(from Daishinku) 12 to 16 pF CGL 12 to 16 Low speed crystal *1 oscillation external capacitor 3 CDL Using VT-200-F(from SII） 12 to 22 pF CGL 12 to 22 VDDL external capacitor *2 C L ESR ≦500mΩ 2.2 ± 30% µF VL1,2,3pin external capacitor Ca,b,c – 1.0 ± 30% µF C1-C2 external capacitor C12 – 1.0 ± 30% µF CH1, CH2 external capacitor CH12 – 1.0 ± 30% µF VHF external capacitor CHF – 1.0 ± 30% µF *1 : Please use this crystal except DEEPHALT mode because this LSI may not be functioning at DEEPHALT mode with the crystal. Please evaluate the matching when other crystal oscillator/ceramic oscillator is used. *2：Please evaluate on user’s conditions, put on CL0( = 0.1uF) if necessary.

/37

• Operating Conditions of Flash Memory （VSS= 0V） Parameter Symbol Condition Range Unit Operating temperature (Ambience) TOP Data area : write/erase -40 to +85 °C Program area : write/erase 0 to +40 °C Operating voltage Write time VDD Write/erase 1.8 to 3.6 V CEPD Data area (1,024B x 2) 10,000 times CEPP Program area 100 times Erase unit – Block erase Program area 8 KB Data area 2 Sector erase 1 KB Erase time(Maximum) – Block erase/Sector erase 100 ms Write unit – – 1 word (4 byte) –

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• AC characteristics (Oscillation, reset) *1 : Mean value of 1024 cycle. *2 : Guarantee value at the time of the shipment. *3 : Except DeepHALT mode and Ultra-DeepHALT mode. (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless other wise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. Low speed crystal oscillation start time TXTL – – – 2 s Low speed built-in RC oscillation frequency*1*2*3 fLCR Ta=25°C Typ -1.5% 32.768 Typ +1.5% kHz Ta=-40 to 85°C typ-5% 32.768 typ+5% High speed build-in RC oscillation frequency*1*2 fHCR Ta=25°C typ -1% 16 typ +1% MHz Ta=-40 to 85°C typ -5% 16 typ +5% PLL frequency f PLL f XTL=32.768kHz typ -0.25% 24 typ +0.25% MHz Low speed crystal oscillation stop detection time TSTOP – – 600 – µs Reset pulse width PRST – 200 – – µs Reset noise elimination pulse width PNRST – – – 0.3 µs Power-on reset activation power rise time TPOR – – – 10 ms PRST RESET_N External reset sequence VDD 0.9*VDD 0.3*VDD VDD 0.9*VDD 0.1*VDD TPOR Power on reset sequence PRST 0.3*VDD 0.3*VDD

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• DC Characteristics (IDD) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating*1 Unit Measuring c ircuit Min. Typ. Max. Power consumption 1 IDD1 CPU is Stopped Low/High-speed oscillation is stopped Ta=25°C – 0.70 2.5 µA Ta=-40 to 85°C – – 28 Power consumption 2 IDD2-1 ULTRA-DEEP-HALT mode *3*4 (LBTC function) Low-speed crystal oscillating (32.768kHz) High-speed oscillation is stopped. 2.5V≦VDD Ta=25°C – 0.80 2.5 µA Ta=-40 to 85°C – – 20 IDD2-2 DEEP-HALT mode *3*4 (LBTC function) Low-speed crystal oscillating (32.768kHz) High-speed oscillation is stopped. µA Ta=-40 to 85°C – – 28 Power consumption 3 IDD3 HALT mode *3*4 (LTBC function) Low-speed crystal oscillating (32.768kHz) High speed oscillation is stopped. Ta=25°C – 2.2 5.0 µA Ta=-40 to 85°C – – 32 Power consumption 4 IDD4 CPU Low-speed *2*4 Low-speed crystal oscillating High speed oscillation is stopped. Ta=25°C – 9.0 14 µA Ta=-40 to 85°C – – 45 Power consumption 5 IDD5 CPU High-speed(16MHz) *2*4 High-speed Built-in RC oscillating Ta=25°C – 3.8 5.0 mA Power consumption 5 IDD5 CPU High-speed(24MHz) *2*4 High-speed PLL oscillating Ta=25°C – 6.0 7.0 mA *1：typ.rating is VDD=3.0V *2：at CPU activity rate =100%（No HALT state） *3 : using 32.768KHz crystal oscillator VT-200-FL (from SII)(CGL/CDL＝12pF) using 32.768KHz crystal oscillator DT-26(from Daishinku)(CGL/CDL＝12pF） *4 : CLKCON valid bits are “0”, RSTCON valid bits are “1”

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• DC Characteristics (VLS) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. VLS judge voltage (VDD=fall) VVLS VLSLV[5:0] = 00H*1 Typ. -3% 1.200 Typ. +3% V 1 VLSLV[5:0] = 01H*1 1.225 VLSLV[5:0] = 02H*1 1.250 VLSLV[5:0] = 03H*1 1.275 VLSLV[5:0] = 04H*1 1.300 VLSLV[5:0] = 05H*1 1.325 VLSLV[5:0] = 06H*1 1.350 VLSLV[5:0] = 07H*1 1.375 VLSLV[5:0] = 08H*1 1.400 VLSLV[5:0] = 09H*1 1.425 VLSLV[5:0] = 0AH*1 1.450 VLSLV[5:0] = 0BH*1 1.475 VLSLV[5:0] = 0CH*1 1.500 VLSLV[5:0] = 0DH*1 1.525 VLSLV[5:0] = 0EH*1 1.550 VLSLV[5:0] = 0FH*1 1.575 VLSLV[5:0] = 10H*1 1.600 VLSLV[5:0] = 11H*1 1.625 VLSLV[5:0] = 12H*1 1.650 VLSLV[5:0] = 13H*1 1.675 VLSLV[5:0] = 14H*1 1.700 VLSLV[5:0] = 15H*1 1.725 VLSLV[5:0] = 16H*1 1.750 VLSLV[5:0] = 17H*1 1.775 VLSLV[5:0] = 18H 1.800 VLSLV[5:0] = 19H 1.825 VLSLV[5:0] = 1AH 1.850 VLSLV[5:0] = 1BH 1.875 VLSLV[5:0] = 1CH 1.900 VLSLV[5:0] = 1DH 1.925 VLSLV[5:0] = 1EH 1.950 VLSLV[5:0] = 1FH 1.975 VLSLV[5:0] = 20H 2.000 VLSLV[5:0] = 21H 2.050 VLSLV[5:0] = 22H 2.100 VLSLV[5:0] = 23H 2.150 VLSLV[5:0] = 24H 2.200 VLSLV[5:0] = 25H 2.250 VLSLV[5:0] = 26H 2.300 VLSLV[5:0] = 27H 2.350 VLSLV[5:0] = 28H 2.400 VLSLV[5:0] = 29H 2.450 VLSLV[5:0] = 2AH 2.500 VLSLV[5:0] = 2BH 2.550 VLSLV[5:0] = 2CH 2.600

/37 VLSLV[5:0] = 2DH Typ. -3% 2.650 Typ. +3% V VLSLV[5:0] = 2EH 2.700 VLSLV[5:0] = 2FH 2.750 VLSLV[5:0] =30H 2.800 VLSLV[5:0] = 31H 2.850 VLSLV[5:0] = 32H 2.900 VLSLV[5:0] = 33H 2.950 VLSLV[5:0] = 34H 3.000 VLSLV[5:0] = 35H 3.050 VLSLV[5:0] = 36H 3.100 VLSLV[5:0] = 37H 3.150 VLSLV[5:0] = 38H 3.200 VLSLV[5:0] = 39H 3.250 VLSLV[5:0] = 3AH 3.300 VLSLV[5:0] = 3BH 3.350 VLSLV[5:0] = 3CH 3.400 VLSLV[5:0] = 3DH 3.450 VLSLV[5:0] = 3EH 3.500 VLSLV[5:0] = 3FH 3.550 VVLS Hysteresis width (VDD=rise) HVLS – VVLS X 1.0% VVLS X 2.7% VVLS X 4.5% V VLSLV[3:0] are bits of the VLSCON register to change detection voltage level. *1: Setable only at the time of select to VVLSP pin.

• D C characteristics (LLD) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. LLD judge Voltage VLLR – 1.60 1.80 2.00 V 1
• D C/AC characteristics (Analog comparator) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. Common Input voltage range VCMPIN – 0.2 – VDD -0.2 V

1 Input offset voltage VCMPOF – -30 – 30 mV

time TCMP CMPP- CMPM =40mV – – 2 µs

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• DC characteristics (LCD Driver) (VDD=1.8 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. VL1 voltage VL1 VDD = 3.0V, Tj = 25°C V LCN[4:0] = 10H 1.21 1.26 1.31 LCN[4:0] = 11H 1.23 1.28 1.33 LCN[4:0] = 12H 1.25 1.30 1.35 LCN[4:0] = 13H 1.27 1.32 1.37 LCN[4:0] = 14H 1.29 1.34 1.39 LCN[4:0] = 15H 1.31 1.36 1.41 LCN[4:0] = 16H 1.33 1.38 1.43 LCN[4:0] = 17H 1.35 1.40 1.45 LCN[4:0] = 18H 1.37 1.42 1.47 LCN[4:0] = 19H 1.39 1.44 1.49 LCN[4:0] = 1AH 1.41 1.46 1.51 LCN[4:0] = 1BH 1.43 1.48 1.53 LCN[4:0] = 1CH 1.45 1.50 1.55 LCN[4:0] = 1DH 1.47 1.52 1.57 LCN[4:0] = 1EH 1.49 1.54 1.59 LCN[4:0] = 1FH 1.51 1.56 1.61 VL1 temperature deviation*1 ∆VL1 VDD = 3.0V – −0.06 – %/°C VL1 voltage dependency*1 ∆VL1 VDD = 1.8 to 3.6V – 5 20 mV/V VL2 voltage VL2 VDD = 3.0V, Tj = 25°C 1MΩ load (VL3−VSS) Typ. −10% VL1×2 Typ. +4% V VL3 voltage VL3 Typ. −10% VL1×3 Typ. +4% LCD bias voltage generation time TBIAS – – – 600 ms *1:VL1 can not exceed VDD level. The maximum VL1 becomes VDD level when the VL1 calculated by the temperature deviation and voltage dependency is going to exceed the VDD level. *2: 1/3 bias only.

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• DC characteristics (VOHL, IOHL) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85 °C, unless otherwise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. Output voltage 1 P30-P37, P40-P47, P50-P57,, P60-P63, SWD,PUCTL) VOH1 IOH=-1.0mA VDD -0.5 – – V 2 VOL1 IOL=+0.5mA – – 0.4 Output voltage 2 ( P34, P35, P40, P41 ) (LED mode is selected) VOL2 2.7V ≤VDD ≤3.6V IOL=+5.0mA – – 0.6 IOL=+2.0mA – – 0.4 Output voltage 3 (P30, P31, P34, P35, P40, P41, P44, P45, P50, P51, P54, P55 ) (I2C mode is selected) VOL3 IOL3= +3mA (I2Cspec) (VDD ≥2V) – – 0.4 Output voltage 4 ( P30, P31, P34, P35, P40, P41, P44, P45, P50, P51, P54, P55 ) (I2C mode is selected) VOL4 IOL4= +2mA(I2Cspec) (VDD < 2V) – – VDD ×0.2 Output voltage 5 (COM0～7) (SEG00～49) (LCD mode is selected) VOH5 1/3bias, IOH5=-0.02mA, VL1=1.2V VL3 -0.2 – – VOM5 1/3bias, IOM5=+0.02mA, VL1=1.2V – – VL2 +0.2 VOM5S 1/3bias, IOM5S=-0.02mA, VL1=1.2V VL2 -0.2 – – VOML5 1/3bias, IOML5=+0.02mA, VL1=1.2V – – VL1 +0.2 VOML5S 1/3bias, IOML5S=-0.02mA, VL1=1.2V VL1 -0.2 – – VOL5 1/3bias, IOL5=+0.02mA, VL1=1.2V – – 0.2 Output voltage 5 (COM0～7) (SEG00～49) (LCD mode is selected) VOH5 1/2bias, IOH5=-0.01mA, VL1=1.4V VL3 -0.3 ― ― VOM5 1/2bias, IOM5=+0.01mA, VL1=1.4V ― ― VL2 +0.3 VOM5S 1/2bias, IOM5S=-0.01mA, VL1=1.4V VL2 -0.3 ― ― VOML5 1/2bias, IOML5=+0.01mA, VL1=1.4V ― ― VL1 +0.3 VOML5S 1/2bias, IOML5S=-0.01mA, VL1=1.4V VL1 -0.3 ― ― VOL5 1/2bias, IOL5=+0.01mA, VL1=1.4V ― ― 0.3

/37 Output leak 1 ( P00-P05, P20-P23, P30-P37, P40-P47, P50-P57, P60-P63, SWD,PUCTL ) IOOH1 VOH=VDD (at high impedance) – – +1 µA 3 IOOL1 VOL=VSS (at high impedance) -1 – –

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• DC characteristics (IIHL) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. Input current 1 (RESET_N) IIH1 VIH1=VDD – – 1 µA 4 IIL1 VIL1=VSS -900 -3 00 -20 Input current 3 (P00-P05, P20-P23, P30-P37, P40-P47, P50-P57, P60-P63, SWC, SWD, BRMP) IIH3 VIH3=VDD (at pull down) 1 15 200 IIL3 VIL3=VSS (at pull up) -200 -15 -1 IIH3Z VIH3=VDD (at high impedance) – – 1 IIL3Z VIL3=VSS (at high impedance) -1 – – Input current 4 (P36, P37, P40-P47, P50-P57, P60-P63) IIH4Z VIH4=5.0V (at high impedance) – – 1 *1：typ.rating is VDD=3.0V, Ta=25°C
• DC characteristics (VIHL) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, u nless otherwise specified) Parameter Symbol Condition Rating Unit Measuring circuit Min. Typ. Max. Input voltage 1 (RESET_N, SWD, SWC, BRMP, P00-P05, P20-P23, P30-P37, P40-P47, P50-P57, P60-P63 ) VIH1 – 0.7 ×VDD – V DD V 5 VIL1 – 0 – 0.3 ×VDD Input terminal capacitance (RESET_N, SWD, SWC, BRMP, P00-P05, P20-P23, P30-P37, P40-P47, P50-P57, P60-P63 ) CIN f=10kHz Vrms=50mV Ta=25°C – – 10 pF –

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• DC characteristics (USB) (VDD=3.0 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating*1 Unit Measu ring circuit Min. Typ. Max. Differential input sensitivity V DI Absolute value of the difference between the DP and DM pins 0.2 - - V Differential common mode range V CM Includes VDI range 0.8 - 2.5 V Single end input threshold voltage VSE - 0.8 - 2.0 V High level output voltage VOH 15k W RL is connected to GND 2.8 - - V Low level output voltage VOL 1.5k W RL to 3.6 V - - 0.3 V Hi-Z state input/output leakage current ILO 0 V < VIN < 3.3 V -10 10 uA Driver output resistance ZDRV Steady state 28 44 Ω

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• MEASURING CIRCUITS MEASURING CIRCUIT1 M EASURING CIRCUIT 2 Input pins V VDD VDDL VL1 VL2 VL3 VSS VIL Output pins (*1) Input logic circuit to determine the specified measuring conditions. (*2) Measured at the specified output pins. (*2) (*1) VIH XT0 XT1 32.768kHz crystal A VDD VDDL V CL VL1 Ca VL2 Cb VL3 Cc VSS C1 C12 CV CDL CGL CV : 1µF CL : 2.2µF Ca,Cb,Cc : 1µF C12 : 1µF CGL : 12pF CDL :12pF 32.768kHz crystal oscilation: (DT-26 from Daishinku)

/37 M EASURING CIRCUIT 3 MEASURING CIRCUIT 4 MEASURING CIRCUIT 5 VDD VDDL VL1 VL2 VL3 VSS VIH VIL Input pins Output pins (*1) *1: Input logic circuit to determine the specified measuring conditions. Waveform monitoring A VDD VDDL VL1 VL2 VL3 VSS *3: Measured at the specified output pins. Input pins Output pins (*3) Input pins A VDD VDDL VL1 VL2 VL3 VSS VIH VIL Output pins *1: Input logic circuit to determine the specified measuring conditions. *2: Measured at the specified output pins. (*2) (*1)

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• AC characteristics (USB) (VDD=3.0 to 3.6V, VSS=0V, Ta=-40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Applied pin Min. Typ. Max. Rise time (*1) TR CL = 50 pF 4 – 20 ns DP, DM Fall time (*1) TF CL = 50 pF 4 – 20 ns Output signal crossover voltage VCRS CL = 50 pF 0.8 – 2 .5 V Data rate TDRATE Average bit rate (12Mbps ±0.25%) 11.97 – 12.03 Mbps * 1: TR and TF: Rise time and fall time between 10% and 90% of the pulse amplitude, respectively

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• AC charctoristics (synchronous serial port) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Conditon Rating Unit Min. Typ. Max. SCK input cycle (slave mode) tSCYC High-speed oscillation is not active 10 – – µs High-speed oscillation is active 500 – – ns SCK output cycle (master mode) tSCYC – – SCK* 1 – s SCK input pulse width (slave mode) tSW High-speed oscillation is not active 4 – – µs High-speed oscillation is active 200 – – ns SCK output pulse width (master mode) tSW – tSCYC ×0.4 tSCYC ×0.5 tSCYC ×0.6 s SOUT output delay time (slave mode) tSD – – – 180 ns SOUT output delay time (master mode) tSD – – – 80 ns SIN input Setup time (slave mode) tSS – 50 – – ns SIN input Setup time (master mode) tSS – 130 – – ns SINinput Hold time tSH – 50 – – ns *1 : The clock period which is selected by the below registers(min:250ns@ regularly, min:500ns@P02,P22 is used) In case of SSIO : S0CK2 -0 of serial port 0 mode register(SIO0MOD). In case of SSIOF : SF0BR9-0 of SIOF0 port register(SF0BRR) tSD SCK0/SCKF0 ("0" during transmission/reception) SIN0/SINF0 SOUT0/SOUTF0 tSD tSS tSH tSW tSCYC tSW SCK0/SCKF0 ("1" during transmission/reception)

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• AC characteristics（I2C Bus interface : Standard mode 100kHz） (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Min. Typ. Max. SCL clock frequency fSCL – 0 – 100 kHz SCL hold time (Start/restart condition) tHD:STA – 4.0 – – µs SCL”L” level time tLOW – 4.7 – – µs SCL”H” level time tHIGH – 4.0 – – µs SCL setup time (restart condition) tSU:STA – 4.7 – – µs SDA setup time tSU:DAT – 0.25 – – µs SDA setup time (stop condition) tSU:STO – 4.0 – – µs Bus-free time tBUF – 4.7 – – µs
• A C characteristics（I2C bus interface : fast mode 400kHz） (VDD=1.8 to 3.6V, V SS=0V, Ta= -40 to +85°C, unless otherwise specified) Parameter Symbol Condition Rateing Unit Min. Typ. Max. SCL clock frequency fSCL – 0 – 400 kHz SCLhold time (start/restart condition) tHD:STA – 0.6 – – µs SCL”L” level time tLOW – 1.3 – – µs SCL”H” level time tHIGH – 0.6 – – µs SCL setup time (restart condition) tSU:STA – 0.6 – – µs SDA setup time tSU:DAT – 0.1 – – µs SDA setup time (stop condition) tSU:STO – 0.6 – – µs Bus-free time tBUF – 1.3 – – µs *1: Only at the time of SYSCLK=16MHz or 24MHz SCL SDA Start condition Restart condition Stop condition tBUF tHD:STA tLOW tHIGH tSU:STA tHD:STA tSU:DAT tSU:STO

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• AC characteristics (RC-ADC) (VDD=1.8 to 3.6V, VSS=0V, Ta=-40~+85°C, unless otherwise specified ) Parameter Symbol Condition Rating unit Min. Typ. Max. Resister for oscillation RS0,RS1,RT0, RT0-1,RT1 – 1 – 400 k Ω Oscillation freqency VDD = 3.0V CVR=820pF CS=560pF fOSC1_0 Resister for oscillation =1kΩ – 528 – kHz fOSC2_0 Resister for oscillation =10kΩ – 59 – kHz fOSC3_0 Resister for oscillation =100kΩ – 5.9 – kHz RS to RT oscillation frequency ratio *1 VDD = 3.0V CVR=820pF CS=560pF Kf1_0 RT0, RT0-1, RT1=1kΩ 8.225 8.94 9.655 – Kf2_0 RT0, RT0-1, RT1=10kΩ 0.99 1 1.01 – Kf3_0 RT0, RT0-1, RT1=100kΩ 0.093 0.101 0.109 – *1：Kfx is the ratio of the oscillation frequency by the sensor resistor to the oscillation frequency by the reference resistor on the same conditions. Kfx = fOSCX (RT0-CS0 oscillation) fOSCX (RT0-1-CS0 oscillation) fOSCX (RT1-CS1 oscillation) fOSCX (RS0-CS0 oscillation) , fOSCX (RS0-CS0 oscillation) , fOSCX (RS1-CS1 oscillation) ( x = 1, 2, 3 ) M easuring circuit 【Note】 ・Please have the shortest layout for the common node (wiring patterns which are connected to the external capacitors, resistors and IN0/IN1 pin), including CVR0/CVR1. Especially, do not have long wire between IN0/IN1 and RS0/RS1. The coupling capacitance on the wires may occur incorrect A/D conversion. Also, please do not have signals which may be a source of noise around the node. ・When RT0/RT1 (Thermistor and etc.) requires long wiring due to the restricted placement, please shield the signal by VSS(GND). ・Please make wiring to components (capacitor, resisteor and etc.) necessory for objective measurement. Wiring to reserved components may affect to the A/D conversion operation by noise the components itself may have. VDD VDDL CL1 CL0 VSS CV RT0, RT0-1, RT1: 1kΩ/10kΩ/100kΩ RS0, RS1: 10kΩ CS0, CT0, CS1: 560pF CVR0, CVR1: 820pF RCM Measure frequency (fOSCX) Input pins VIH VIL (*1) Input logic circuit to determine the specified measuring conditions. CS0 RT0 IN1 CS1 RS1 RT1 CS0 RS0 RS0 RCT0 RT0-1 CT0 RT0 CS1 RS1 RT1 IN0 CVR0 CVR1 (*1)

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• AC characteristics (Low speed clock output) (VDD=1.8 to 3.6V, V SS=0V, Ta= -40~+85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Min. Typ. Max. Clock output frequency tclk – – 32.768 – kHz

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• E lectrical Characteristics of SA-ADC (VDD=1.8 to 3.6V, V SS=0V, Ta= -40~+85°C, unless otherwise specified) Parameter Symbol Condition Rating Unit Min. Typ. Max. Resolution n – – 12 – bit Integral non-linearity error INL LSB 1.8V ≤ VREF < 2.2V (using Low-speed clock) −10 – +10 Differential non-linearity error DNL 1.8V ≤ VREF < 2.2V (using Low-speed clock) −9 – +9 Zero-scale error V OFF 1.8V ≤ VREF < 2.2V (using Low-speed clock) −10 – +10 Full-scale error FSE 1.8V ≤ VREF < 2.2V (using Low-speed clock) −10 – +10 Input impidance RI – – – 5k Ω Reference voltage V REF – 1.8 – V DD V Conversion time t CONV Using High-speed clock(max. 4MHz) – 170 – clk Using Low-speed clock – 16 – Measuring circuit A VDD VSS - RI ≤ 5kΩ AIN 0.47μF 10μF VREF 1μF Reference Voltage

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• Power-on and shutdown Procedures In case of power-on or shutdown of VDD, the procedures and constraints are shown as following. Note: If VDDL level is 100mV or more over, reset the IC by RESET_N pin after power-on. 0.9*VDD 0.1*VDD TPOR Power down/on and power on reset sequence (VSS = 0) VDD VDDL (VSS = 0) 30mV or less 100mV or less

APPLICATION CIRCUIT EXAMPLE *: Make a decision the parameters after evaluating on user’s conditions when designing circuits for mass production. CV : 1uF* CL : 2.2uF CL0 : open* CGL,CDL : 12 to 16pF* Ca~Cc : 1uF* C12 : 1uF* CH12 : 1uF* CVH : 1uF* CAV : 1uF* RS0, RS1 : 10 KΩ CS0, CS1 : 560 pF CVR0, CVR1 : 820 pF RT0, RT1 : Thermistor (103AT/Semitec) XL : DT-26, Daishinku P30/SDAF0 P35 /LED P31/SCLF0 P34 /LED P32 (Output) LED SDA Vcc SCL I2C EEPROM A0 A1 A2 CAV VREF XT0 XT1 XL CGL CDL 32.768KHz Xtal ML630Q464/ Q466 CL CL0 VDDL Vss P00/IN0 P01/CS0 P03/RS0 P04/RT0 P02/RCT0 CS0 RS0 RT0 P05/RCM P20/IN1 P21/CS1 P22/RS1 P23/RT1 CS1 RS1 RT1 WP Vss VL1 VL3 VL2 C1 C2 RESET_N SWC SWD VHF CH1 CH2 C12 Ca Cb Cc CH12 CVH VDD CV 3.3V RESET_N CVR0 CVR1

/37 PACKAGE DIMENSIONS ML630Q464/Q466 PACK AG E DIMENSIONS Figure B-1 TQFP100 N otes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions(reflow method, temperature and times).

/37 RE VISION HISTORY Document No. Date Page Description Previous Edition Current Edition FEDL630Q464-01 Oct. 26. 2016 - - Final Edition

/37 Notes 1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors ca n b reak down and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail -safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrat e t he standard usage and op erations of the Products.The peripheral conditions must be taken into account when designin g c ircuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS S emiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. A V/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ships, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semico nductor shall have no responsibility for any damages or injury arising from non -compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information co ntained in this document. However, LAPIS Semiconductor does not warrant that such information is error -free and LAPIS Semiconductor shall hav e n o responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please contact a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in whole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Cop yright 2016 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/