DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 44
Technical content
Issue Date : April 27, 2016 MSM56V16161N 2-Bank×524,288-Word×16-Bit SYNCHRONOUS DYNAMIC RAM
DESCRIPTION
The MSM56V16161N is a 2-Bank 524,288-word 16-bit Synchronous dynamic RAM. The device operates at 3.3V . The inputs and outputs are LVTTL compatible.
FEATURES
Organization 2Bank x 524,288Word x 16Bit Address Size 2,048Row x 256Column Power Supply VCC (Core) 3.3V0.3V Power Supply VCCQ (I/O) 3.3V0.3V Interface LVTTL compatible Operating Frequency Max. 166MHz (Speed Rank 6) Operating Temperature 0 to 70°C Function Standard SDRAM command interface /CAS Latency 2, 3 Burst Length 1, 2, 4, 8, Full page Burst Type Sequential, Interleave Write Mode Burst, Single Refresh Auto-Refresh, 4,096cycle/64ms (0°C Ta 70°C), Self-Refresh Package 50-Pin Plastic TSOP(II) (Cu frame) (P-TSOP(2)50-400-0.80-ZK) PRODUCT FAMILY Family Max. Frequency Access Time (Max.) tAC2 tAC3 MSM56V16161N -6 166MHz 5.4ns 5.4ns MSM56V16161N -7 143MHz 5.4ns 5.4ns MSM56V16161N -75 133MHz 5.4ns 5.4ns MSM56V16161N -10 100MHz 6ns 6ns
PIN CONFIGURATION (TOP VIEW) Pin Name Function Pin Name Function CLK System Clock UDQM, LDQM Data Input / Output Mask /CS Chip Select DQi Data Input / Output CKE Clock Enable VCC Power Supply (3.3V) A0 to A10 Address VSS Ground (0V) A11 Bank Select Address VCCQ Data Output Power Supply (3.3V) /RAS Row Address Strobe VSSQ Data Output Ground (0V) /CAS Column Address Strobe NC No Connection /WE Write Enable Note : The same power supply voltage must be provided to every VCC pin . The same power supply voltage must be provided to every VCCQ pin. The same GND voltage level must be provided to every VSS pin and VSSQ pin. 50-Pin Plastic TSOP(II) 7 44 A11 A10 VSSQ VCCQ VCCQ VSS NC UDQM NC /WE /CAS /RAS /CS LDQM CLK CKE 9 38 DQ0 DQ1 VCC VCCQ VSS VCCQ DQ12 DQ11 DQ10 VSSQ DQ5 VSSQ DQ6 DQ7 DQ2 DQ3 DQ4 DQ9 DQ8 DQ13 DQ15 DQ14 VSSQ 26 25 VCC
CLK Clock (Input) Fetches all inputs at the “H” edge. CKE Clock Enable (Input) Masks system clock to deactivate the subsequent CLK operation. If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is deactivated. CKE should be asserted at least one cycle prior to a new command. /CS Chip Select (Input) Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE and UDQM, LDQM. /RAS Row Address Strobe (Input) Functionality depends on the combination with other signals. For detail, see the function truth table. /CAS Column Address Strobe (Input) Functionality depends on the combination with other signals. For detail, see the function truth table. /WE Write Enable (Input) Functionality depends on the combination with other signals. For detail, see the function truth table. A11 Bank Address (Input) Slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. A0 to A10 Row & column multiplexed. (Input) Row address : RA0 – RA10 Column Address : CA0 – CA7 DQ0 to DQ15 3-state Data Bus (Input/Output) UDQM, LDQM DQ Mask (Input) Masks the read data of two clocks later when DQM are set “H” at the “H” edge of the clock signal. Masks the write data of the same clock when DQM are set “H” at the “H” edge of the clock signal. UDQM controls DQ7 to DQ15, LDQM controls DQ0 to DQ7. VCC, VSS Power Supply (Core), Ground (Core) The same power supply voltage must be provided to every VCC pin. The same GND voltage level must be provided to every VSS pin. VCCQ, VSSQ Power Supply (I/O), Ground (I/O) The same power supply voltage must be provided to every VCCQ pin. The same GND voltage level must be provided to every VSSQ pin. NC No Connection
ELECTRICAL CHARACTERISTICS
Parameter Symbol Value Unit Voltage on Input/Output Pin Relative to VSS VIN, VOUT –0.5 to VCC+0.5 V VCC Supply Voltage VCC –0.5 to 4.6 V VCCQ Supply Voltage VCCQ –0.5 to 4.6 V Power Dissipation (Ta=25°C) PD 1000 mW Short Circuit Output Current IOS 50 mA Storage Temperature Tstg –55 to 150 °C Operating Temperature Topr 0 to 70 °C Notes: 1. Permanent device damage may occur if Absolute Maximum Ratings are exceeded. 2. Functional operation should be restricted to recommended operating condition. 3. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. 4. The voltages are referenced to VSS. Recommended Operating Conditions (1/2) Ta= 0 to 70C Parameter Symbol Min. Typ. Max. Unit Note Power Supply Voltage (Core) VCC 3.0 3.3 3.6 V 1 Power Supply Voltage (I/O) VCCQ 3.0 3.3 3.6 V 1 Ground VSS, VSSQ 0 0 0 V Notes: 1. The voltages are referenced to VSS 2. The power supply voltages should input stable voltage. The power supply voltages should not input oscillated voltage. If voltages Recommended Operating Conditions (2/2) Ta= 0 to 70C Parameter Symbol Min. Max. Unit Note Input High Voltage VIH 2.0 VCC + 0.3 V 1, 2 Input Low Voltage VIL 0.3 0.8 V 1, 3 Notes: 1. The voltages are referenced to VSS. 2. The input voltage is VCC + 0.5V when the pulse width is less than 20ns (the pulse width is with respect to the point at which VCC is applied). 3. The input voltage is 0.5V when the pulse width is less than 20ns (the pulse width respect to the point at which VSS and VSSQ are applied).
Ta = 25°C, VCC＝VCCQ＝3.3V, f＝1MHz Parameter Symbol Min. Max. Unit Input Capacitance (CLK) CCLK 4 pF Input Capacitance (A0 to A11, /RAS, /CAS, /WE, /CS, CKE, UDQM, LDQM) CIN 5 pF Input/Output Capacitance (DQ0 to DQ15) COUT 6.5 pF DC Characteristics (Input/Output) When Output Driver Strength=100%, 50%, 25% Ta= 0 to 70°C VCC = VCCQ = 3.0V~3.6V Parameter Symbol Condition Min. Max. Unit Output High Voltage VOH IOH = 2mA 2.4 V Output Low Voltage VOL IOL = 2mA 0.4 V Input Leakage Current ILI 0V VIN VCCQ 10 10 µA Output Leakage Current ILO 10 10 µA Note : The voltages are referenced to VSS. When Output Driver Strength=12.5% Ta= 0 to 70°C VCC = VCCQ = 3.0V~3.6V Parameter Symbol Condition Min. Max. Unit Output High Voltage VOH IOH = 0.5mA 2.4 V Output Low Voltage VOL IOL = 0.5mA 0.4 V Input Leakage Current ILI 0V VIN VCCQ 10 10 µA Output Leakage Current ILO 10 10 µA Note : The voltages are referenced to VSS.
DC Characteristics (Power Supply Current) Ta= 0 to 70°C VCC = VCCQ = 3.0V~3.6V Parameter Symbol Condition MSM56V16161N Unit Note -6 -7 -75 -10 Bank CKE Others Max. Max. Max. Max. Average Power Supply Current (Operating) ICC1 One Bank Active CKE VIH tCC = Min. tRC = Min. No Burst 120 100 90 70 mA 1, 2 Power Supply Current (Standby) ICC2 Both Banks Precharge CKE VIH tCC = Min. 50 40 35 30 mA 3 Average Power Supply Current (Clock Suspension) ICC3S Both Banks Active CKE VIL tCC = Min. 3 3 3 3 mA 2 Average Power Supply Current (Active Standby) ICC3 One Bank Active CKE VIH tCC = Min. 50 45 40 35 mA 3 Power Supply Current (Burst) ICC4 Both Banks Active CKE VIH tCC = Min. 160 140 130 100 mA 1, 2 Power Supply Current (Auto-Refresh) ICC5 One Bank Active CKE VIH tCC = Min. tRC = Min. 160 140 130 100 mA 2 Average Power Supply Current (Self-Refresh) ICC6 Both Banks Precharge CKE VIL tCC = Min. 2 2 2 2 mA Average Power Supply Current (Power Down) ICC7 Both Banks Precharge CKE VIL tCC = Min. 2 2 2 2 mA Notes: 1. Measured with outputs open. 2. The address and data can be changed once or left unchanged during one cycle. 3. The address and data can be changed once or left unchanged during two cycles.
AC Characteristics (1/2) Ta= 0 to 70°C VCC = VCCQ = 3.0V~3.6V Note1,2 Parameter Symbol MSM56V16161N Unit Note -6 -7 -75 -10 Clock Cycle Time CL=3 tCC3 6 7 7.5 10 ns CL=2 tCC2 10 10 10 10 ns Access Time from Clock CL=3 tAC3 5.4 5.4 5.4 6 ns 3,4 CL=2 tAC2 5.4 5.4 5.4 6 ns 3,4 Clock High Pulse Time tCH 2 2 2.5 3 ns 4 Clock Low Pulse Time tCL 2 2 2.5 3 ns 4 Input Setup Time tSI 2 2 2 2 ns Input Hold Time tHI 1 1 1 1 ns Output Low Impedance Time from Clock tOLZ 2 2 2 2 ns Output High Impedance Time from Clock tOHZ 5.4 5.4 5.4 6 ns Output Hold from Clock tOH 2 2 2 2 ns 3 Random Read or Write Cycle Time tRC 60 60 65 70 ns RAS Precharge Time tRP 18 20 20 20 ns RAS Pulse Width tRAS 42 105 42 105 45 105 50 105 ns /RAS to /CAS Delay Time tRCD 18 18 20 20 ns Write Recovery Time tWR 2 2 2 2 Cycle 6 /RAS to /RAS Bank Active Delay Time tRRD 10 10 15 20 ns Refresh Time tREF 64 64 64 64 ms 5 Power-down Exit setup Time tPDE tSI+1CLK tSI+1CLK tSI+1CLK tSI+1CLK ns Refresh cycle Time tRCA 60 60 65 70 ns
AC Characteristics (2/2) Ta= 0 to 70°C VCC = VCCQ = 3.0V~3.6V Note1,2 Parameter Symbol MSM56V16161N Unit Note -6 -7 -75 -10 /CAS to /CAS Delay Time (Min.) lCCD 1 1 1 1 Cycle Clock Disable Time from CKE lCKE 1 1 1 1 Cycle Data Output High Impedance Time from UDQM, LDQM lDOZ 2 2 2 2 Cycle Dada Input Mask Time from UDQM, LDQM lDOD 0 0 0 0 Cycle Data Input Mask Time from Write Command lDWD 0 0 0 0 Cycle Data Output High Impedance Time from Precharge Command lROH CL CL CL CL Cycle Active Command Input Time from Mode Register Set Command Input (Min.) lMRD 2 2 2 2 Cycle Write Command Input Time from Output lOWD 2 2 2 2 Cycle Notes: 1. AC measurements assume that tT = 1ns,. 2. Test condition Parameter Test Condition Unit Input voltage for AC measurement 2.4 0.4 V Transition Time for AC measurement tT＝1 ns Reference level for timing of input signal (tT1ns) 1.4 V Reference level for timing of input signal (tT>1ns) VIH Min. VIL Max. V Reference level for timing of output signal 1.4 V 3. Output load. 4. If tT is longer than 1ns, then the reference level for timing of input signals is VIH and VIL. 5. It is necessary to operate auto-refresh 4096 cycles within tREF. 6. If tCC is longer than 20ns, the spec of tWR (min.) is 20ns (1 cycle). Output Z=50 30pF (External Load) 1.4V 50
- Apply power and attempt to maintain CKE=”H” and other pins are NOP condition at the input. 2. Maintain stable power, stable clock and NOP input condition for a minimum of 200 s. 3. Issue precharge commands for all banks of the devices. 4. Issue mode register set command to initialize the mode register. 5. Issue extended mode register set command to initialize the extended mode register. 6. Issue 2 or more auto-refresh commands. Note 1: (4), (5) or (6): in no special order. 2. (5) can be omitted. When it is omitted, it becomes default settings. 3. Carry out an initialization sequence after each input terminal reaches a regulation voltage when other input terminals were the undefined setup input (High -Z) at the CKE= "H" time. And, the undefined setup input per iod of the CKE= "H" time can't hold data. It becomes more effective than writing data after the initialization sequence. Mode Register Set Command (MRS) The mode register stores the data for controlling the various operating modes. It programs the /CAS latency, burst type, burst length and write mode. The default value of the mode register is not defined, therefore the mode register must be written after power up to operate the SDRAM. The mode register is written by mode register set command MRS. The state of address pins A0 to A 10 in the same cycle as MRS is the data written in the mode register. Refer to the table for specific codes for various /CAS latencies, burst type, burst length and write mode. Extended Mode Register Set Command (EMRS) The extended mode register stores the data for controlling output driver strength. The default value of the extended mode register is defined. Therefore the mode register must be written after power up to operate the SDRAM. The extended mode register is writ ten by extended mode register set command EMRS. The state of address pins A 0 to A10 in the same cycle as EMRS is the data written in the extended mode register. Refer to the table for Extended Mode Register Set Address Keys. MRS CLK n-1 n CKE H X /CS X (Idle) L /RAS L /CAS L /WE L A11 X 0 A0 to A10 V V V: The value of mode register set EMRS CLK n-1 n CKE H X /CS X (Idle) L /RAS L /CAS L /WE L A11 X 1 A0 to A10 V V V: The value of extended mode register set
Mode Register Field Table To Program Mode Write Burst Mode /CAS Latency Burst Type Burst Length A9 WM A6 A5 A4 CL A3 BT A2 A1 A0 BT = 0 BT = 1
0 Burst 0 0 0 Reserved 0 Sequential 0 0 0 1 1
1 Single 0 0 1 Reserved 1 Interleave 0 0 1 2 2
1 0 0 Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved 1 1 1 Full Page Reserved Notes: 1. 1. Objects are all family products. 2. A11 should stay “0” during mode set cycle. 3. A7, A8 and A10 should stay “0” during mode set cycle. 4. Don’t set address keys of “Reserved”. Extended Mode Register Set Address Keys Output Driver Strength A6 A5 DS 0 0 Full (Default) 0 1 1/2 1 0 1/8 1 1 1/4 Notes: 1. A11 should stay “1” during mode set cycle. 2. A0 to A4, A7 to A10 should stay “0” during mode set cycle. 3. If don’t set EMRS, DS is set to default (Full).
Output Driver Characteristics (1/2) Ta＝0°C~+70°C, VCC,VCCQ＝3.0V~3.6V Output Driver Strength=Full (Default) Output Driver Strength=1/2 min. max. typ. min. max. typ. min. max. typ. min. max. typ.
Output Driver Characteristics (2/2) Ta＝0°C~+70°C, VCC,VCCQ＝3.0V~3.6V Output Driver Strength=1/4 Output Driver Strength=1/8 min. max. typ. min. max. typ. max. min. typ. max. min. typ.
Burst operation is the operation to continuously increase a column address inputted during read or write command. The upper bits select a column address block, Access order in column address block Start Address (Lower bit) Burst Type BT=Sequential BT=Interleave Burst Length BL=2 0 0, 1 0, 1 1 1, 0 1, 0 BL=4 A1 A0 0 0 0, 1, 2, 3 0, 1, 2, 3 0 1 1, 2, 3, 0 1, 0, 3, 2 1 0 2, 3, 0, 1 2, 3, 0, 1 1 1 3, 0, 1, 2 3, 2, 1, 0 BL=8 A2 A1 A0 BL=Full Page (256) A0 to A7 0 0, 1… 255 Non Support Yn Yn, Yn+1… 255, 0… …Yn-1
This SDRAM is organized as four independent banks of 524,288 words x 16 bits memory arrays. The A11 input is latched at the time of assertion of /RAS and /CAS to select the bank to be used for operation. The bank address A11 is latched at bank active, read, write, mode register s et and precharge operations. Activate The bank activate command is used to select a random row in an idle bank. By asserting low on /RAS and /CS with desired row and bank address, a row access is initiated. The read or write operation can occur afte r a time delay of tRCD(min) from the time of bank activation. Precharge The precharge operation is performed on an active bank by precharge command (PRE) with valid A11 of the bank to be precharged. The precharge command can be asserted anytime after tRAS(min) is satisfied from the bank active command in the desired bank. All bank can precharged at the same time by using precharge all command (PALL). Asserting low on /CS, /RAS and /WE with high on A10 after all banks have satisfied t RAS(min) requirement, performs precharge on al banks. At the end of t RP after performing precharge to all banks, all banks are in idle state. Bank Address A11 Bank 0 A 1 B ACT CLK n-1 n CKE H X /CS X (Idle) L /RAS L /CAS H /WE H A11 X BA A0 to A10 X RA BA: Bank Address RA: Row Address (Page) PALL CLK n-1 n CKE H X /CS X (Page Open) L /RAS L /CAS H /WE L A11 X X A10 X 1 A0 to A9 X X PRE CLK n-1 n CKE H X /CS X (Page Open) L /RAS L /CAS H /WE L A11 X BA A10 X 0 A0 to A9 X X BA: Bank Address
Write / Write with Auto-Precharge The write command is used to write data into the SDRAM on consecutive clock cycles in adjacent address depending on burst length and burst sequence. By asserting low on /CS, /CAS and /WE with valid column address, a write burst is initiated. The data inputs are provided for the initial address in the same clock cycle as the burst write command. The input buffer is deselected at the end of the burst length, even through the internal writing can be completed yet. The writing can be completed by issuing a burst read and DQM for blocking data inputs or burst write in the same or another active bank. The burst stop command is valid at every burst length. Write Cycle WRTA CLK n-1 n CKE H X /CS X (Page Open) L /RAS H /CAS L /WE L A11 X BA A10 X 1 A9, A8 X X A0 to A7 X CA DQ X D-in BA: Bank Address CA: Column Address D-in: Data inputs WRT CLK n-1 n CKE H X /CS X (Page Open) L /RAS H /CAS L /WE L A11 X BA A10 X 0 A9, A8 X X A0 to A7 X CA DQ X D-in BA: Bank Address CA: Column Address D-in: Data inputs WRT WRT WRTA PRE PRE ACT ACT ACT ACT ACT D0 D1 D2 D3 tRAS tRP tRP tRAS tWR tRP tWR Auto Precharge Start Page Open D0 D1 D2 D3 CLK CL=2 or 3, BL=1 or WM=Single Command DQ CL=2 or 3, BL=4, WM=Burst Command DQ CL=2 or 3, BL=4, WM=Burst Command DQ Valid Burst Data In Valid Single Data In tRCD tRCD
Read / Read with Auto-Precharge The read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The read command is issued b y asserting low on /CS and /CAS with /WE being high on the positive edge of the clock. The bank must be active for at least tRCD(min) before the read command is issued. The first output appears in /CAS latency number of clock cycles after the issue of read command. The burst length, burst sequence and latency from the read command are determined by the mode register that is already programmed. Read Cycle RDA CLK n-1 n CKE H X /CS X (Page Open) L /RAS H /CAS L /WE H A11 X BA A10 X 1 A9, A8 X X A0 to A7 X CA DQ X X BA: Bank Address CA: Column Address RD CLK n-1 n CKE H X /CS X (Page Open) L /RAS H /CAS L /WE H A11 X BA A10 X 0 A9, A8 X X A0 to A7 X CA DQ X X BA: Bank Address CA: Column Address RD RD PRE PRE ACT ACT ACT ACT tRAS tRP tRP tRAS tRP Auto Precharge Start Page Open Q1 Q2 Q3 Q0 Q1 Q2 Q3 RDA Q0 Q1 Q2 Q3 tRP Auto Precharge Start RDA Q0 Q1 Q2 Q3 CLK CL=2, BL=4 Command DQ CL=3, BL=4 Command DQ CL=2, BL=4 Command DQ CL=3, BL=4 Command DQ Page Open /CAS Latency (CL) = 2 /CAS Latency (CL) = 3 Valid Burst Data Out Valid Burst Data Out tRCD tRCD ACT ACT
When a new write command is issued to same bank during write cycle or another active bank, current burst write is terminated and new burst write start. When a new write command is issued to another bank during a write with auto-precharge cycle, current burst is terminated and a new write command start. Then, current bank is precharged after specified time. Don’t issue a new write command to same bank during write with auto-precharge cycle. Write / Write interrupt cycle Da0 Db0 Db1 Dc0 Dc1 Dc2 Dc3 tCCD tCCD WRTa WRTb WRTc WRTA DA0 WRTA DB0 DA1 DB1 DB2 DB3 ACT A ACT B A B tWR + 1clk tRP Auto Precharge Burst Write Burst Interrupt, Write Recovery Row Active Burst Write Auto Precharge Write Recovery Row Active tWR tRP tCCD tRRD CLK CL=2 or 3, BL=4, WM=Burst Command DQ CL=2 or 3, BL=4, WM=Burst Command DQ CL=2 or 3, BL=4, WM=Burst Command Bank Address Bank A Internal State Bank B Internal State DQ WRTa WRTAb Da0 Db0 Db1 Db2 Db3 tCCD tWR ACT tRP Auto Precharge Start Row Active Da1
When a new read command is issued to same bank during read cycle or another active bank, current burst read is terminated after the cycle same as /CAS latency and new burst read start. When a new read command is issued to another bank during a read with auto -precharge cycle, current burst is terminated after the cycle same as /CAS latency and a new read command start. Then, current bank is precharged after specified time. Don’t issue a new read command to same bank during read with auto-precharge cycle. Read / Read interrupt cycle RDa Qa0 Qb0 Qb1 Qc0 Qa0 Qb1 Qb2 RDb Qc1 RDc Qc2 Qc3 tCCD High-Z RDa Qb0 tCCD tCCD Qb3 ACT tRP RDAb High-Z Auto Precharge Start CLK CL=2, BL=4 Command DQ CL=3, BL=4 Command DQ CL=2, BL=4 Command Bank Address Bank A Internal State Bank B Internal State DQ RDA RDA QA0 QA1 A B QB0 QB1 QB2 QB3 Auto Precharge Burst Read Burst Interrupt Row Active Burst Read Auto Precharge Row Active ACT A ACT B Row Active tCCD tRRD tRP + 1clk tRP Qa1
When a new read command is issued to same bank during write cycle or another active bank, current burst write is terminated and new burst read start. When a new read command is issued to another bank during a write with auto-precharge cycle, current burst is terminated and a new read command start. Then, current bank is precharged after specified time. Don ’t issue a new read command to same bank during write with auto -precharge cycle. DQ must be hi-Z till 1 or more clock from first read data. Write / Read interrupt cycle Qb1 Qb2 RDb Qb3 tCCD High-Z WRTa Da0 WRTa tCCD Da0 Da1 Qb1 Qb2 Qb3 High-Z Auto Precharge Start tRP RDAb ACT Invalid Data Input Invalid Data Input Qb0 Qb0 WRTA RDA ACT A B tCCD CLK CL=3, BL=4, WM=Burst Command DQ CL=2, BL=4, WM=Burst Command DQ CL=2, BL=4, WM=Burst Command Bank Address Bank A Internal State Bank B Internal State DQ Burst Write tWR + 1clk Burst Interrupt, Write Recovery Auto Precharge tRP ACT Row Active Row Active Auto Precharge DA0 DA1 tRP A B Invalid Data Input QB1 QB2 QB3 High-Z QB0 Burst Read tRRD Row Active
When a new write command is issued to same bank during read cycle or another active bank, current burst read is terminated and new burst write start. When a new write command is issued to another bank during a read with auto-precharge cycle, current burst is terminated and a new write command start. Then, current bank is precharged after specified time. Don ’t issue a new write command to sa me bank during read with auto -precharge cycle. DQ must be Hi-Z till 1 or more clock from new write command. Therefore, DQM must be high till 3 clocks from new write command. Read / Write interrupt cycle Qa0 Db0 RDa Db1 WRTb Db2 Db3 High-Z QA0 DB0 RDA DB1 WRTA DB2 DB3 High-Z tOWD tOWD CLK CL=3, BL=4, WM=Burst Command DQM DQ CL=2, BL=4, WM=Burst Command Bank Address Bank A Internal State Bank B Internal State DQM DQ A B Burst Read Auto Precharge Row Active Burst Interrupt ACT A Row Active Burst Write Auto Precharge Write Recovery tWR tRP + 1clk
When a burst stop command is issued during read cycle, current burst read is terminated. The DQ is to Hi -Z after the cycle same as /CAS latency and page keep open. When a burst stop command is issued during write cycle, current burst write is terminated. The input data is ignored after burst stop command. Don ’t issue burst stop command during read with auto-precharge cycle or write with auto-precharge cycle. Read / Burst Stop cycle Write / Burst Stop cycle BST CLK n-1 n CKE H X /CS X (Burst) L /RAS H /CAS H /WE L A11 X X A0 to A10 X X RD Q0 Q1 Q2 Q0 Q2 BST High-Z RD High-Z CLK CL=2, BL=4~Full Command DQ CL=3, BL=4~Full Command DQ BST WRT D0 D1 D2 BST High-Z Invalid Data Input CLK CL=2 or 3, BL=4~Full, WM=Burst Command DQ
When a precharge command is issued to the same bank during read cycle or precharge all command is issued, current burst read is terminated and DQ is to Hi -Z after the cycle same as /CAS latency. The objected bank is precharged. When a precharge command is issued to the same bank during write cycle or precharge all command is issued, current burst write is terminated and the objected bank is precharged. The input data after precharge command is ignored. Read / Precharge Break cycle Write / Precharge Break cycle PRE Q0 Q1 RD CLK CL=2, BL=4~Full Command DQ CL=3 BL=4~Full Command DQ tRAS tRP High-Z Q0 Q2 RD High-Z PRE ACT tRCD ACT ACT tRAS tRP ACT tRCD PRE D0 D1 WRT あ tRAS tRP ACT tRCD ACT Invalid Data Input CLK CL=2, BL=4~Full Command DQM DQ CL=3, BL=4~Full Command DQM DQ ACT PRE D0 D1 WRT あ tRAS tRP tRCD ACT tWR tWR
DQM masks input / output data at every byte. UDQM controls DQ8 to DQ15 and LDQM controls DQ0 to DQ7. During read cycle, DQM mask output data after 2 clocks. During write cycle, DQM mask input data at same clock. Read / DQM Function Write / DQM Function QU0 RD QU1 High-Z QU4 QU6 QU7 QL0 QL3 QL4 QL6 QL7 High-Z High-Z High-Z High-Z High-Z CLK CL=3, BL=8 Command UDQM DQ8 to DQ15 LDQM DQ0 to DQ7 DU0 WRT DU1 DU4 DU6 DU7 DL0 DL3 DL4 DL6 DL7 Invalid Data Input CLK CL=2 or 3, BL=8 Command UDQM DQ8 to DQ15 LDQM DQ0 to DQ7
The read / write operation can be stopped by CKE temporaril y. When CKE is set low, the next clock is ignored. When CKE is set low during read cycle, the burst read is stopped temporarily and the current output data is kept. When CKE is set high, burst read is resumed. When CKE is set low during write cycle, the bu rst write is stopped temporarily. When CKE is set high, burst write is resumed. Read / Clock Suspend Write / Clock Suspend CLK CL=2 or 3, BL=8 CKE Command DQ WRT D1 D2 D4 D5 Invalid Data Input D3 D6 Suspend C L B L C K E C o m m Suspend RD Q2 Q4 Q3 Q1 CLK CL=2, BL=8 CKE Command DQ Q5 Suspend Suspend Valid Data Output
The data of memory cells are maintained by refresh operation. The refresh operation is to activate all row addresses within a refresh time. The method that row addresses are activated by activate and precharge command is called RAS only refresh cycle. This method needs to input row address with activate command. But, auto-refresh and self refresh don’t need to input address. Because, row addresses are generated in SDRAM automatically. Auto Refresh All memory area is refreshed by 4,096 times refresh command REF. The refresh command REF can be entered only wh en all the banks are in an idle state. SDRAM is in idle state after refresh cycle time tRCA. Auto-Refresh Cycle Intensive Refresh 4,096 times refresh command can be entered every refresh time tREF. Dispersed Refresh Refresh command can be entered every 15.6s (tREF 64ms / 4,096 cycles). REF CLK n-1 n CKE H H /CS X (Idle) L /RAS L /CAS L /WE H A11 X X A0 to A10 X X CLK Command REF PALL REF ACT tRP tRCA tRCA REF x 4,096 CLK State Read or Write Auto Refresh Read or Write Auto Refresh REF x 4,096 tREF=64ms tREF=64ms CLK State R/W REF 4,096 times tREF=64ms R/W REF R/W REF R/W REF 15.6µs REF 15.6µs 15.6µs
When read or write is not operated in the long period, self refresh can reduce power consumption for refresh operation. Refresh operation is controlled automatically by refresh timer and row address counter during self refresh mode. All signals except CKE are ignored and data bus DQ is set Hi-Z during self refresh mode. When CKE is set to high level, self refresh mode is finished. Then, CLK must be operated before 1 clock or more. And, maintain NOP condition within a period of tRCA(Min.) after CKE is set to be high level. Self Refresh Cycle Notes : 1. When intensive refresh is used, 4,096 times refresh must be issued before and after the self refresh. CLK CKE Command REF tRCA Self Refresh tRCA SREF REF SREF CLK n-1 n CKE H L /CS X (Idle) L /RAS L /CAS L /WE H A11 X X A0 to A10 X X
SDRAM can be set to low power consumption condition with CKE function. CKE is reflected at 1 clock later regardless /CAS latency. When CKE is set to low level, SDRAM go into power down mode. All signals except CKE are ignored and DQ is set to High impedance in this state. When CKE is set to high level, SDRAM exit power down mode. Then, Clock must be resumed before 1 or more clocks. Power Down Signal Condition in Power Down Mode Signal Input to SDRAM Output from SDRAM CLK Don’t Care CKE “L” level /CS,/RAS, /CAS, /WE Don’t Care A0 to A10, A11 Don’t Care DQ0 to DQ15 Don’t Care High-Z UDQM,LDQM Don’t Care VCC,VCCQ,VSS,VSSQ Power Supply Notes : 1. “Don’t Care” means high or low level input. Active Power Down Mode RD Write Cycle Q0 Q1 D2 D3 D1 New Command High-Z Q2 Q3 Q1 Auto Precharge Start Page Open Stand-by Power Down Mode High-Z REF New Command Precharge Stand-by / Idle CLK CL=2, BL=4, Case 1 CKE Command DQ CL=2, BL=4, Case 2 CKE Command DQ
FUNCTION TRUTH TABLE (Table 1) (1/3) Current State *1 /CS /RAS /CAS /WE ADDR Command Action Idle H X X X X NOP NOP L H H X X NOP/BST NOP L H L H BA, CA, A10 RD/RDA ILLEGAL *2 L H L L BA, CA, A10 WRT/WRTA ILLEGAL *2 L L H H BA, RA ACT Row Active L L H L BA, A10 PRE/PALL NOP *3 L L L H X REF Auto-Refresh or Self-Refresh *4 L L L L V, A11=0 MRS Mode Register Set *4 L L L L V, A11=1 EMRS Extended Mode Register Set *4 Row Active H X X X X NOP NOP L H H X X NOP/BST NOP L H L H BA, CA, A10 RD/RDA Read / Read auto Precharge *5 L H L L BA, CA, A10 WRT/WRTA Write / Write auto Precharge *5 L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL Precharge L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL Read H X X X X NOP Continue Row Active after Burst ends L H H H X NOP Continue Row Active after Burst ends L H H L X BST Term Burst --> Row Active L H L H BA, CA, A10 RD/RDA Term Burst, start new Burst Read L H L L BA, CA, A10 WRT/WRTA Term Burst, start new Burst Write L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL Term Burst, execute Row Precharge L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL Write H X X X X NOP Continue Row Active after Burst ends L H H H X NOP Continue Row Active after Burst ends L H H L X BST Term Burst --> Row Active L H L H BA, CA, A10 RD/RDA Term Burst, start new Burst Read L H L L BA, CA, A10 WRT/WRTA Term Burst, start new Burst Write L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL Term Burst, execute Row Precharge L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL
FUNCTION TRUTH TABLE (Table 1) (2/3) Current State *1 /CS /RAS /CAS /WE ADDR Command Action Read with Auto Precharg e H X X X X NOP Continue Burst to End and enter Row Precharge L H H H X NOP Continue Burst to End and enter Row Precharge L H H L X BST ILLEGAL L H L H BA, CA, A10 RD/RDA ILLEGAL *7 L H L L BA, CA, A10 WRT/WRTA ILLEGAL *7 L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL ILLEGAL *8 L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL Write with Auto Precharge H X X X X NOP Continue Burst to End and enter Row Precharge L H H H X NOP Continue Burst to End and enter Row Precharge L H H L X BST ILLEGAL L H L H BA, CA, A10 RD/RDA ILLEGAL *7 L H L L BA, CA, A10 WRT/WRTA ILLEGAL *7 L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL ILLEGAL *8 L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL Precharge H X X X X NOP Idle after tRP L H H H X NOP Idle after tRP L H H L X BST ILLEGAL L H L H BA, CA, A10 RD/RDA ILLEGAL *2 L H L L BA, CA, A10 WRT/WRTA ILLEGAL *2 L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL ILLEGAL *3 L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL Write Recovery H X X X X NOP Row Active after tWR L H H H X NOP Row Active after tWR L H H L X BST ILLEGAL L H L H BA, CA, A10 RD/RDA ILLEGAL *2 L H L L BA, CA, A10 WRT/WRTA ILLEGAL *2 L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL ILLEGAL *8 L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL
FUNCTION TRUTH TABLE (Table 1) (3/3) Current State *1 /CS /RAS /CAS /WE ADDR Command Action Write Recovery in Auto Precharge H X X X X NOP enter Row Precharge after tWR L H H H X NOP enter Row Precharge after tWR L H H L X BST ILLEGAL L H L H BA, CA, A10 RD/RDA ILLEGAL *7 L H L L BA, CA, A10 WRT/WRTA ILLEGAL *7 L L H H BA, RA ACT ILLEGAL *6 L L H L BA, A10 PRE/PALL ILLEGAL *8 L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL Auto Refresh H X X X X NOP Idle after tRCA L H H H X NOP Idle after tRCA L H H L X BST ILLEGAL L H L H BA, CA, A10 RD/RDA ILLEGAL L H L L BA, CA, A10 WRT/WRTA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL ILLEGAL L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL Mode Register Access H X X X X NOP Idle after tMRD L H H H X NOP Idle after tMRD L H H L X BST ILLEGAL L H L H BA, CA, A10 RD/RDA ILLEGAL L H L L BA, CA, A10 WRT/WRTA ILLEGAL L L H H BA, RA ACT ILLEGAL L L H L BA, A10 PRE/PALL ILLEGAL L L L H X REF ILLEGAL L L L L X MRS/EMRS ILLEGAL ABBREVIA TIONS ADDR = Address RA = Row Address BA = Bank Address CA = Column Address NOP = No OPeration command V = Value of Mode Register Set Notes : 1. All inputs are enabled when CKE is set high for at least 1 cycle prior to the inputs. 2. RD/RDA or WRT/WRTA command to same bank is forbidden. But RD/RDA or WRT/WRTA command to activated page in another bank is valid after tRCD(min.). 3. PRE command to another activated bank is valid. PALL command is valid to only activated bank. 4. Illegal if any bank is not idle. 5. RD/RDA or WRT/WRTA command to activated bank is valid after tRCD(min.) from ACT command. 6. Activate command to the same bank is forbidden. But activate command to another bank in idle state is valid. 7. RD/RDA or WRT/WRTA command to same bank is forbidden. But RD/RDA or WRT/WRTA command to activated page in another bank is valid. 8. PRE to same bank is forbidden. PRE to ano ther bank must be issued after tRAS(min.). PALL command is forbidden. 9. Write recovery states means a period from last data to the time that tWR(min.) passed.
FUNCTION TRUTH TABLE for CKE (Table 2) Current State n-1 CKE n-1 CKE n /CS n /RAS n /CAS n /WE n ADDR n Action All Banks Idle (ABI) H H X X X X X Refer to Table 1 H L H X X X X Enter Power Down H L L H H H X Enter Power Down H L L H H L X ILLEGAL H L L H L X X ILLEGAL H L L L H H BA, RA Enter Active Power Down after Activate H L L L H L X ILLEGAL H L L L L H X Enter Self Refresh *2 H L L L L L BA, V Enter Power Down after MRS L X X X X X X INVALID Self Refresh H X X X X X X INVALID L H H X X X X Exit Self Refresh --> ABI *3 L H L H H H X Exit Self Refresh --> ABI *3 L H L H H L X ILLEGAL L H L H L X X ILLEGAL L H L L X X X ILLEGAL L L X X X X X NOP (Maintain Self Refresh) Power Down H X X X X X X INVALID L H X X X X X Exit Power Down --> ABI *4 L L X X X X X NOP (Continue Power Down) Active Power Down H X X X X X X INVALID L H X X X X X Exit Active Power Down --> Row Active *4 L L X X X X X NOP (Continue Active Power Down) Row Active H H X X X X X Refer to Table 1 H L H X X X X Enter Active Power Down H L L H H H X Enter Active Power Down H L L H H L X ILLEGAL H L L H L X X Clock Suspension (Refer to Table 1) H L L L H X X Clock Suspension (Refer to Table 1) H L L L L X X ILLEGAL L X X X X X X INVALID Any State Other than Listed Above H H X X X X X Refer to Table 1 H L X X X X X Begin Clock Suspend Next Cycle L H X X X X X Enable Clock of Next Cycle L L X X X X X Continue Clock Suspension ABBREVIA TIONS ADDR = Address RA = Row Address BA = Bank Address NOP = No OPeration command V = Value of Mode Register Set ABI = All Banks Idle *Notes : 1. Deep Power Down can be entered only when all the banks are in an idle state. 2. Self Refresh can be entered only when all the banks are in an idle state. 3. tRCA must be set after exit self refresh. 4. New command is enabled in the next clock.
CKE CKE CKE CKE CKE CKE CKE CKE Write Read CKE CKE Burst Stop Read Write Burst Stop Read Write Precharge Read with Auto Precharge Write AP Write AP Read AP Read AP Write with Auto Precharge Precharge Precharge CKE CKE Active Refresh Self Refresh Exit MRS Precharge Command / input signal Auto Sequence EXTENDED MODE REGISTER SET EMRS
Synchronous Characteristics Note : The object of input are CKE, A0 to A11 /CS, /RAS, /CAS, /WE,UDQM to LDQM and DQ0 to DQ15 (input). Power on Sequence Notes : 1. It is advisable that UDQM and LDQM are set to high for set DQ to high impedance during power on sequence. tT > 1ns tT ≤ 1ns High-Z tCL tCH tCC2/3 tSI tHI tSI tHI tOHZ tOH tOH High-Z tAC2/3 tAC2/3 1.4V Input * CLK DQ Output High-Z tCL tCH tCC2/3 tSI tHI tSI tHI tOHZ2/3 tOH tOH tAC2/3 tAC2/3 Valid High Valid Low Valid High Valid Low Valid High Valid Low High-Z Valid High Valid Low VIH VIL VIH VIL VOH VOL Transition Time tT1ns Transition Time tT1ns 1.4V 1.4V tOLZ tOLZ VCC, VCCQ CLK Command (/CS, /RAS, /CAS, /WE) Address UDQM,LDQM DQ0 to DQ15 NOP PALL NOP 200µs Max. Min. 0V Stable Clock Input Initialize High-Z (NOP) Don't Care Don't Care *1
Notes : 1. V = Value of mode register, Rx = Row Address, Bx = Bank Address = NOP command or High or Low 2. It is advisable that UDQM to LDQM are set to be high level for setting DQ to high impedance during power on sequence. Mode Register Set cycle Notes : 1. V = Value of mode register, Rx = Row Address, Bx = Bank Address = NOP command or High or Low CLK CKE Command (/CS, /RAS, /CAS,/WE) Address A10 A11 UDQM,LDQM DQ0 to 15 Ra V Ba tRP PALL MRS EMRS REF REF ACT High V Ra 200µs tMRD tMRD tRCA tRCA High-Z Don't Care *2 CLK CKE Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM,LDQM DQ0 to 15 Ra tRP MRS EMRS ACT V tMRD tMRD tRCA High-Z PRE REF SREF V Ra tRAS Ba Ba tRC tSI
Burst Write Cycle (BL=4, WM=Burst) Notes : 1. Rx = Row Address, Cx = Column Address, Bx = Bank Address = NOP command or High or Low level, CKE = High level Burst Read Cycle (BL=4) Notes : 1. Rx = Row Address, Cx = Column Address, Bx = Bank Address = NOP command or High or Low level, CKE = High level CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM (CL=2) DQ0 to 15 (CL=2) UDQM, LDQM (CL=3) DQ0 to 15 (CL=3) Qa0 Qa2 Qa3 Qa2 Qa3 Qb0 Qb0 RD RD Ca Cb PRE Bb Rb Ba Bb Ba Bb tRAS tRP tRCD tRAS tRC tAC2 tOH ACT Rb Ra Ba ACT Ra tRCD Qa0 tAC2 tOH CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM (CL=2, 3) DQ0 to 15 (CL=2, 3) tOLZ tOHZ tOLZ tOHZ tAC3 tOH tOLZ tOHZ tAC3 tOH tOLZ tOHZ Qa1 Qa1 PRE Da0 Da2 Db0 ACT Ra Ra Ba WRT ACT WRT Ca Rb Cb PRE Bb PRE Rb Ba Bb Ba Bb tRC tRAS tRP tRAS tRCD tRCD tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI tSI tHI Da1 tWR tWR
Bank Interleave Write with Auto Precharge Cycle (CL=2, BL=4, WM=Burst) Notes : 1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address = NOP command or High or Low level, CKE = High level Bank Interleave Read with Auto Precharge Cycle (CL=2, BL=4) Notes : 1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address = NOP command or High or Low level, CKE = High level CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM DQ0 to 15 CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM DQ0 to 15 QAa0 QAa1 QAa2 QAa3 ACT RAa RAa A RDA ACT CAa RAb CAb A RAb A A B B tRC (Bank-A) tRAS (Bank-A) tRP (Bank-A) tRCD tRCD CBa ACT B RBa RBa RDA QBa0 QBa1 QBa2 QBa3 RDA ACT RDA RBb CBb RBb B QAb0 QAb1 QAb2 tRCD tRCD tRAS (Bank-B) tRP (Bank-B) tRC (Bank-B) tAC2 tOH tOLZ tOHZ tAC2 tOH DAa0 DAa2 ACT RAa RAa A WRTA ACT CAa RAb CAb A RAb A A B B tRC (Bank-A) tRAS (Bank-A) tRP (Bank-A) tRCD tRCD tSI tHI tSI tHI CBa ACT B RBa RBa WRTA DBa0 DBa2 DBa3 WRTA ACT WRTA RBb CBb RBb B DAb0 DAb2 DBb0 tRCD tRCD tRAS (Bank-B) tRP (Bank-B) tRC (Bank-B) tWR tWR tSI tHI tSI tHI DAa1 DAa3 DBa1 DAb1 DAb3
Burst Read Single Write Cycle (CL=2, BL=4,WM=Single) Notes : 1.RXx = Row Address, CXx = Column Address, X = Bank, x = Address = NOP command or High or Low level, CKE = High level Random Column Read / Write Cycle (CL=3, BL=2, 4, 8, Full Page) Notes : 1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address = NOP command or High or Low level, CKE = High level, = Invalid Data Input CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM DQ0 to 15 QAa0 QAb0 CAa A ACT CAc B A tRRD CAb QAc0 QAd0 DBa0 tOWD tAC3 tOLZ tOH WRT DAf0 QBc0 tCCD RD RD RD CAd RBa A A A B RD PRE RD WRT ACT RD WRT WRT RD RD RAb CBa CAe CBb CAf CBc CAg CBd CAh RBa A B B A A B A A DBb0 DAe0 tAC3 tOLZ tCCD tCCD tCCD tCCD tCCD tCCD tCCD tCCD tCCD tRP (Bank-A) tRCD (Bank-B) (Bank-A=Active) tRCD (Bank-A) tOH RAb tSI tHI tOHZ CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM,LDQM DQ0 to 15 QAa0 QAa1 ACT RAa RAa A RD ACT CAb A A B tRCD tRCD CBa B RBa QAa2 QAa3 DBa CBb B tOWD tAC2 tOLZ tOH WRT WRT RD DBb QAb0 tAC2 tOLZ tOH RBa tCCD tSI tHI tSI tHI tOHZ2 tCCD CAa
Burst Stop Read / Write Cycle (BL=Full Page, WM=Burst) Notes : 1. Cx = Column Address, Bx = Bank Address = NOP command or High or Low level, CKE = High level, = Invalid Data Input Precharge Break Read / Write Cycle (BL=Full Page, WM=Burst) Notes : 1. RXx = Row Address, CXx = Column Address, X = Bank, x = Address = NOP command or High or Low level, CKE = High level, = Invalid Data Input CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM (CL=2) DQ0 to 15 (CL=2) UDQM, LDQM (CL=3) DQ0 to 15 (CL=3) CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM (CL=2) DQ0 to 15 (CL=2) UDQM, LDQM (CL=3) DQ0 to 15 (CL=3) Qa0 Ca Ba tWR Db0 tOWD tAC2 tOLZ tOH RD BST Cb Ba WRT BST Dbn-1 Dbn PRE Ba tSI tHI tOHZ Qa0 tWR Qan-2 Db0 tOWD tAC3 tOLZ tOH Dbn-1 tSI tHI tOHZ Qa1 Qan-1 Db1 Qan Qan-1 Db1 Qan Ca Ba RD PRE Cb Ba WRT PRE Ba Qa0 tWR Db0 tOWD tAC2 tOLZ tOH tSI tHI tOHZ Qa0 tWR Db0 tOWD tAC3 tOLZ tSI ACT Ba Rb Rb Ba tRP tRAS tRCD tOH Qan-1 Qan Qan-2 Dbn-1 Dbn-1 tOHZ Qan-1 Qan tHI Db1 Db1 Qa1 Dbn
Byte Read / Byte Write Cycle (CL=2, BL=8, WM=Burst) Notes : 1. Cx = Column Address, Bx = Bank Address = NOP command or High or Low level, CKE = High level, = Invalid Data Input Clock Suspend Read / Write Cycle (CL=3, BL=4, WM=Burst) Notes : 1. Cx = Column Address, Bx = Bank Address = NOP command or High or Low level, CKE = High level, = Invalid Data Input CLK CKE Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM DQ0 to 15 RD WRT Ca Cb Ba Ba Qa0 Db1 Db2 Qa1 Db3 tSI tHI tSI tHI tAC3 tOLZ tOH tSI tHI tOHZ tOWD CLK Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM DQ8 to 15 LDQM DQ0 to 7 RD WRT Ca Cb Ba Ba Qa0 Db0 Db1 Qa1 Qa4 Qa5 Db4 Db5 Qa0 Db0 Db2 Qa2 Qa4 Qa5 Db4 Db5 tOHZ tOLZ tSI tHI tSI tHI Qa3 Qa2 Db0
Notes : 1. Rx = Row Address, Bx = Bank Address = NOP command or High or Low level, CKE = High level, = Invalid Data Input Self Refresh Cycle Notes : 1. Rx = Row Address, Bx = Bank Address = High or Low level CLK CKE Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM DQ0 to 15 PALL REF REF REF ACT High Ra Ba High-Z tRP tRCA tRCA tRCA CLK CKE Command (/CS, /RAS, /CAS, /WE) Address A10 A11 UDQM, LDQM DQ0 to 15 PALL SREF ACT Ra Ba High-Z tRP tRCA NOP Don't Care NOP Self Refresh Ra Ra tSI tSI 1clk
Notes : 1. Rx = Row Address, Bx = Bank Address = High or Low level CLK CKE Command (/CS, /RAS, /CAS,/WE) Address A10 A11 UDQM, LDQM DQ0 to 15 ACT ACT Rb Bb High-Z Active Power Down Rb tSI tSI 1clk Don't Care NOP PRE NOP tSI Don't Care NOP NOP Power Down 1clk 1clk tSI Ra Ba Ra Ba 1clk
Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact a ROHM sales office for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). (Unit: mm) NOTES: 1. LEAD WITH DOES NOT INCLUDE TRIM OFFSET. 2. PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION, DIEPAD SUPPORT PROTRUSION AND CAVITY OFFSET BETWEEN TOP AND BOTTOM CAVITY. 3. THE SEATING PLANE IS THE SURFACE WHICH THE PACKAGE IS MOUNTED ON AND GETS IN CONTACT WITH.
REVISION HISTORY
Document No. Date Page Description Previous Edition Current Edition FEDD56V16161N-01 April 27, 2016 – – Final edition 1
1) The information contained herein is subject to change without notice. 2) Although LAPIS Semiconductor is continuously working to improve product reliability and quality, semiconductors can break dow n and malfunction due to various factors. Therefore, in order to prevent personal injury or fire arising from failure, please take safety measures such as complying with the derating characteristics, implementing redundant and fire prevention designs, and utilizing backups and fail -safe procedures. LAPIS Semiconductor shall have no responsibility for any damages arising out of the use of our Products beyond the rating specified by LAPIS Semiconductor. 3) Examples of application circuits, circuit constants and any other information contained herein are provided only to illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. 4) The technical information specified herein is intended only to show the typical functions of the Products and examples of application circuits for the Products. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of LAPIS Semiconductor or any third party with respect to the information contained in this document; therefore LAPIS Semiconductor shall have no responsibility whatsoever for any dispute, concerning such rights owned by third parties, arising out of the use of such technical information. 5) The Products are intended for use in general electronic equipment (i.e. A V/OA devices, communication, consumer systems, gaming/entertainment sets) as well as the applications indicated in this document. 6) The Products specified in this document are not designed to be radiation tolerant. 7) For use of our Products in applications requiring a high degree of reliability (as exemplified below), please contact and consult with a LAPIS Semiconductor representative: transportation equipment (i.e. cars, ship s, trains), primary communication equipment, traffic lights, fire/crime prevention, safety equipment, medical systems, servers, solar cells, and power transmission systems. 8) Do not use our Products in applications requiring extremely high reliability, such as aerospace equipment, nuclear power control systems, and submarine repeaters. 9) LAPIS Semiconductor shall have no responsibility for any damages or injury arising from non -compliance with the recommended usage conditions and specifications contained herein. 10) LAPIS Semiconductor has used reasonable care to ensure the accuracy of the information contained in this document. However, LAPIS Semiconductor does not warrant that such information is error -free and LAPIS Semiconductor shall have no responsibility for any damages arising from any inaccuracy or misprint of such information. 11) Please use the Products in accordance with any applicable environmental laws and regulations, such as the RoHS Directive. For more details, including RoHS compatibility, please conta ct a ROHM sales office. LAPIS Semiconductor shall have no responsibility for any damages or losses resulting non-compliance with any applicable laws or regulations. 12) When providing our Products and technologies contained in this document to other countries, you must abide by the procedures and provisions stipulated in all applicable export laws and regulations, including without limitation the US Export Administration Regulations and the Foreign Exchange and Foreign Trade Act. 13) This document, in part or in wh ole, may not be reprinted or reproduced without prior consent of LAPIS Semiconductor. Copyright 2016 LAPIS Semiconductor Co., Ltd. 2-4-8 Shinyokohama, Kouhoku-ku, Yokohama 222-8575, Japan http://www.lapis-semi.com/en/