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Publication Number 21504 Revision E Amendment 5 Issue Date November 2, 2006 Am29F800B Data Sheet The following document contains information on Spansion memory products. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary. For More Information Please contact your local sales office for additional information about Spansion memory solutions.

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This Data Sheet states AMD’s current technical specifications regarding the Product described herein. This Data Sheet may be revised by subsequent versions or modifications due to changes in technical specifications. Publication# 21504 Rev: E Amendment: 5 Issue Date: November 2, 2006 Am29F800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 5.0 Volt-only, Boot Sector Flash Memory DISTINCTIVE CHARACTERISTICS ■ Single power supply operation — 5.0 Volt-only operation for read, erase, and program operations — Minimizes system level requirements ■ Manufactured on 0.32 µm process technology — Compatible with 0.5 µm Am29F800 device ■ High performance — Access times as fast as 55 ns ■ Low power consumption (typical values at

5 MHz)

— 1 µA standby mode current — 20 mA read current (byte mode) — 28 mA read current (word mode) — 30 mA program/erase current ■ Flexible sector architecture — One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and fifteen 64 Kbyte sectors (byte mode) — One 8 Kword, two 4 Kword, one 16 Kword, and fifteen 32 Kword sectors (word mode) — Supports full chip erase — Sector Protection features: A hardware method of locking a sector to prevent any program or erase operations within that sector — Sectors can be locked via programming equipment Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically preprograms and erases the entire chip or any combination of designated sectors — Embedded Program algorithm automatically writes and verifies data at specified addresses ■ Minimum 1,000,000 program/erase cycles per sector guaranteed ■ 20-year data retention at 125°C — Reliable operation for the life of the system ■ Package option — 48-pin TSOP — 44-pin SO — 48-ball FBGA — Known Good Die (KGD) (see publication number 21631) ■ Compatibility with JEDEC standards — Pinout and software compatible with single- power-supply Flash — Superior inadvertent write protection ■ Data# Polling and toggle bits — Provides a software method of detecting program or erase operation completion ■ Ready/Busy# pin (RY/BY#) — Provides a hardware method of detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends an erase operation to read data from, or program data to, a sector that is not being erased, then resumes the erase operation ■ Hardware reset pin (RESET#) — Hardware method to reset the device to reading array data

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The Am29F800B is an 8 Mbit, 5.0 volt-only Flash memory organized as 1,048,576 bytes or 524,288 words. The device is offered in 44-pin SO, 48-pin TSOP, and 48-ball FBGA packages. The device is also available in Known Good Die (KGD) form. For more information, refer to publication number 21631. The word-wide data (x16) appears on DQ15–DQ0; the byte-wide (x8) data appears on DQ7–DQ0. This device is designed to be programmed in-system with the stan dard system 5.0 volt V CC supply. A 12.0 V V PP is not required for write or erase operations. The device can also be programmed in standard EPROM program mers. This device is manufactured using AMD’s 0.32 µm process technology, and offers all the features and ben efits of the Am29F800, which was manufactured using 0.5 µm process technology. The standard device offers access times of 55, 70, 90, and 120 ns, allowing high speed microprocessors to operate without wait states. To eliminate bus contention the device has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device requires only a single 5.0 volt power sup- ply for both read and write functions. Internally gener - ated and regulated voltages are provided for the program and erase operations. The device is entirely command set compatible with the JEDEC single-power-supply Flash standard . Com- mands are written to the command register using stan- dard microprocessor write timings. Register contents serve as input to an internal state-machine that con - trols the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. Device erasure occurs by executing the erase com - mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device is ready to read array data or accept another command. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write opera - tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem - ory. This can be achieved via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A sys tem reset would thus also reset the device, enabling the system microprocessor to read the boot-up firmware from the Flash memory. The system can place the device into the standby mode . Power consumption is greatly reduced in this mode. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability and cost effective ness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The data is programmed using hot electron injection.

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Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29F800B Speed Option VCC = 5.0 V ± 10% -55 -70 -90 -120 Max access time, ns (tACC) 55 70 90 120 Max CE# access time, ns (tCE) 55 70 90 120 Max OE# access time, ns (tOE) 30 30 35 50 Input/Output Buffers X-Decoder Y-Decoder Chip Enable Output Enable Logic Erase Voltage Generator PGM Voltage Generator TimerVCC Detector State Control Command Register VCC VSS WE# BYTE# CE# OE# STB STB DQ0–DQ15 (A-1) Sector Switches RY/BY# RESET# Data Latch Y-Gating Cell Matrix Address LatchA0–A18

November 2, 2006 21504E5 Am29F800B 5 DATA SHEET CONNECTION DIAGRAMS This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for more information. A15 A18 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin TSOP—Standard Pinout RY/BY# A18 A17 CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC SO

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This device is also available in Known Good Die (KGD) form. Refer to publication number 21631 for more information. Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCA18NCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 FBGA Top View, Balls Facing Down

November 2, 2006 21504E5 Am29F800B 7 DATA SHEET PIN CONFIGURATION A0–A18 = 19 addresses DQ0–DQ14 = 15 data inputs/outputs DQ15/A-1 = DQ15 (data input/output, word mode), A-1 (LSB address input, byte mode) BYTE# = Selects 8-bit or 16-bit mode CE# = Chip enable OE# = Output enable WE# = Write enable RESET# = Hardware reset pin, active low RY/BY# = Ready/Busy# output VCC = +5.0 V single power supply (see Product Selector Guide for device speed ratings and voltage supply tolerances) VSS = Device ground NC = Pin not connected internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A18 CE# OE# WE# RESET# BYTE# RY/BY#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed by a combination of the elements below. Valid Combinations Valid Combinations list configurations planned to be sup - ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29F800B T -70 E C TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-Free Package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-Free Package E = Extended (–55 °C to +125°C) K = Extended (–55 °C to +125°C) with Pb-Free Package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) S = 44-Pin Small Outline Package (SO 044) WB = 48-Ball Fine Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 9 mm package (FBB048) This device is also available in Known Good Die (KGD) form. See publication number 21536 for more information. SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29F800B

8 Megabit (1 M x 8-Bit/512K x 16-Bit) CMOS Flash Memory

5.0 Volt-only Read, Program and Erase

AM29F800BT -55, AM29F800BB-55 EC, EI, EE, ED, EF , EK SC, SI, SE, SD, SF , SK AM29F800BT -70, AM29F800BB-70 AM29F800BT -90, AM29F800BB-90 AM29F800BT -120, AM29F800BB-120 Valid Combinations for FBGA Packages Order Number Package Marking AM29F800BT -55, AM29F800BB-55 WBC, WBI, WBE, WBD, WBF , WBK F800BT55V, F800BB55V C, I, E, D, F, K AM29F800BT -70, AM29F800BB-70 F800BT70V, F800BB70V AM29F800BT -90, AM29F800BB-90 F800BT90V, F800BB90V AM29F800BT -120, AM29F800BB-120 F800BT12V, F800BB12V

each of these operations in further detail. Table 1. Am29F800B Device Bus Operations Note: See the sections on Sector Group Protection and Temporary Sector Unprotect for more information. an input for the LSB (A-1) address function. data upon device power-up, or after a hardware reset. command register contents are altered.

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tions” section for details on erasing a sector or the en - tire chip, or suspending/resuming the erase operation. After the system writes the autoselect command se - quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter - nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the “Autoselect Mode” and “Autoselect Command Sequence” sections for more information. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The “AC Characteristics” section contains timing specification tables and timing diagrams for write operations. Program and Erase Operation Status During an erase or program operation, the system may check the status of the operation by reading the status bits on DQ7–DQ0. Standard read cycle timings and I CC read specifications apply. Refer to “Write Operation Status” for more information, and to each AC Charac - teristics section for timing diagrams. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde pendent of the OE# input. The device enters the CMOS standby mode when CE# and RESET# pins are both held at V CC ± 0.5 V. (Note that this is a more restricted voltage range than V IH.) The device enters the TTL standby mode when CE# and RESET# pins are both held at V IH. The device re- quires standard access time (tCE) for read access when the device is in either of these standby modes, before it is ready to read data. The device also enters the standby mode when the RE- SET# pin is driven low. Refer to the next section, “RE- SET#: Hardware Reset Pin”. If the device is deselected during erasure or program - ming, the device draws active current until the operation is completed. In the DC Characteristics tables, I CC3 represents the standby current specification. RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the system drives the RESET# pin low for at least a period of t RP, the device immediately terminates any operation in progress, tristates all data output pins, and ignores all read/write attempts for the duration of the RESET# pulse. The device also resets the internal state ma chine to reading array data. The operation that was in- terrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at V IL, the device enters the TTL standby mode; if RESET# is held at V SS ± 0.5 V, the device enters the CMOS standby mode. The RESET# pin may be tied to the system reset cir - cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm ware from the Flash memory. If RESET# is asserted during a program or erase oper- ation, the RY/BY# pin remains a “0” (busy) until the in- ternal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo - rithms). The system can read data t RH after the RE - SET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state.

Table 2. Am29F800BT Top Boot Block Sector Address Table

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Table 3. Am29F800BB Bottom Boot Block Sector Address Table through the command register.

Table 4. Am29F800B Autoselect Codes (High Voltage Method) L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care. The device is shipped with all sectors unprotected. AMD representative for details. “Autoselect Mode” for details. ously protected sectors to change data in-system. shows the timing waveforms, for this feature. Figure 1. Temporary Sector Unprotect Operation

  1. All protected sectors unprotected.
  2. All previously protected sectors are protected once

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The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to the Command Defi nitions table). In addition, the following hardware data protection measures prevent accidental erasure or pro gramming, which might otherwise be caused by spuri - ous system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not ac - cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent uninten - tional writes when VCC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = V IL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or se - quences into the command register initiates device op- erations. The Command Definitions table defines the valid register command sequences. Writing incorrect address and data values or writing them in the im proper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the “AC Characteristics” section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. The device is also ready to read array data after completing an Embedded Program or Em bedded Erase algorithm. After the device accepts an Erase Suspend command, the device enters the Erase Suspend mode. The sys tem can read array data using the standard read tim - ings, except that if it reads at an address within erase- suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See “Erase Sus - pend/Erase Resume Commands” for more information on this mode. The system must issue the reset command to re-en - able the device for reading array data if DQ5 goes high, or while in the autoselect mode. See the “Reset Com- mand” section, next. See also “Requirements for Reading Array Data” in the “Device Bus Operations” section for more information. The Read Operations table provides the read parame- ters, and Read Operation Timings diagram shows the timing diagram. Reset Command Writing the reset command to the device resets the de- vice to reading array data. Address bits are don’t care for this command. The reset command may be written between the se - quence cycles in an erase command sequence before erasing begins. This resets the device to reading array data. Once erasure begins, however, the device ig nores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in a program command sequence be - fore programming begins. This resets the device to reading array data (also applies to programming in Erase Suspend mode). Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data (also applies to autoselect during Erase Suspend). If DQ5 goes high during a program or erase operation, writing the reset command returns the device to read ing array data (also applies during Erase Suspend).

and determine whether or not a sector is protected. mers and requires VID on address bit A9. mode (or 02h in byte mode) returns the device code. autoselect mode and return to reading array data. formation on these status bits. ing array data, to ensure data integrity. Figure 2. Program Operation ments for the chip erase command sequence.

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Any commands written to the chip during the Embed - ded Erase algorithm are ignored. Note that a hardware reset during the chip erase operation immediately ter - minates the operation. The Chip Erase command se - quence should be reinitiated once the device has returned to reading array data, to ensure data integrity. The system can determine the status of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. See “Write Operation Status” for information on these status bits. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. Figure 3 illustrates the algorithm for the erase opera - tion. See the Erase/Program Operations tables in “AC Characteristics” for parameters, and to the Chip/Sector Erase Operation Timings for timing waveforms. Sector Erase Command Sequence Sector erase is a six bus cycle operation. The sector erase command sequence is initiated by writing two un- lock cycles, followed by a set-up command. Two addi - tional unlock write cycles are then followed by the address of the sector to be erased, and the sector erase command. The Command Definitions table shows the address and data requirements for the sec tor erase command sequence. The device does not require the system to preprogram the memory prior to erase. The Embedded Erase algo- rithm automatically programs and verifies the sector for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or tim ings during these operations. After the command sequence is written, a sector erase time-out of 50 µs begins. During the time-out period, additional sector addresses and sector erase com mands may be written. Loading the sector erase buffer may be done in any sequence, and the number of sec tors may be from one sector to all sectors. The time be- tween these additional cycles must be less than 50 µs, otherwise the last address and command might not be accepted, and erasure may begin. It is recommended that processor interrupts be disabled during this time to ensure all commands are accepted. The interrupts can be re-enabled after the last Sector Erase command is written. If the time between additional sector erase commands can be assumed to be less than 50 µs, the system need not monitor DQ3. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must rewrite the command sequence and any additional sector addresses and commands. The system can monitor DQ3 to determine if the sector erase timer has timed out. (See the “DQ3: Sector Erase Timer” section.) The time-out begins from the rising edge of the final WE# pulse in the command sequence. Once the sector erase operation has begun, only the Erase Suspend command is valid. All other commands are ignored. Note that a hardware reset during the sector erase operation immediately terminates the op eration. The Sector Erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. When the Embedded Erase algorithm is complete, the device returns to reading array data and addresses are no longer latched. The system can determine the sta tus of the erase operation by using DQ7, DQ6, DQ2, or RY/BY#. Refer to “Write Operation Status” for informa- tion on these status bits. Figure 3 illustrates the algorithm for the erase opera - tion. Refer to the Erase/Program Operations tables in the “AC Characteristics” section for parameters, and to the Sector Erase Operations Timing diagram for timing waveforms. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to in- terrupt a sector erase operation and then read data from, or program data to, any sector not selected for erasure. This command is valid only during the sector erase operation, including the 50 µs time-out period during the sector erase command sequence. The Erase Suspend command is ignored if written during the chip erase operation or Embedded Program algo rithm. Writing the Erase Suspend command during the Sector Erase time-out immediately terminates the time-out period and suspends the erase operation. Ad dresses are “don’t-cares” when writing the Erase Sus- pend command. When the Erase Suspend command is written during a sector erase operation, the device requires a maximum of 20 µs to suspend the erase operation. However, when the Erase Suspend command is written during the sector erase time-out, the device immediately ter minates the time-out period and suspends the erase operation. After the erase operation has been suspended, the system can read array data from or program data to any sector not selected for erasure. (The device “erase suspends” all sectors selected for erasure.) Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sec tors produces status da ta on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2 together, to determine if a sector is actively erasing or is erase-suspended. See “Write Operation Status” for information on these status bits. After an erase-suspended program operation is com - plete, the system can once again read array data within non-suspended sectors. The system can determine the status of the program operation using the DQ7 or

  1. See the appropriate Command Definitions table for erase
  2. See “DQ3: Sector Erase Timer” for more information.

Figure 3. Erase Operation

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Table 5. Am29F800B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A18–A12 uniquely select any sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or autoselect data, all bus cycles
  4. Data bits DQ15–DQ8 are don’t cares for unlock and
  5. Address bits A18–A11 are don’t cares for unlock and

command cycles, unless SA or PA required.

  1. No unlock or command cycles required when reading array data.
  2. The Reset command is required to return to reading array

high (while the device is providing status data).

  1. The fourth cycle of the autoselect command sequence is a
  2. The data is 00h for an unprotected sector and 01h for a

“Autoselect Command Sequence” for more information.

  1. The system may read and program in non-erasing sectors, or
  2. The Erase Resume command is valid only during the Erase

90 X00 01Byte AAA 555 AAA

55 SA 30Byte AAA 555 AAA AAA 555

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RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data (including during the Erase Suspend mode), or is in the standby mode. Table 6 shows the outputs for RY/BY#. The timing dia- grams for read, reset, program, and erase shows the relationship of RY/BY# to other signals. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the command sequence (prior to the program or erase op eration), and during the sector erase time-out. During an Embedded Program or Erase algorithm op - eration, successive read cycles to any address cause DQ6 to toggle. (The system may use either OE# or CE# to control the read cycles.) When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 tog gles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unpro tected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter - mine whether a sector is acti vely erasing or is erase- suspended. When the device is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When the device enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on “DQ7: Data# Polling”). If a program address falls within a protected sector, DQ6 toggles for approximately 2 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro gram algorithm is complete. The Write Operation Status table shows the outputs for Toggle Bit I on DQ6. Refer to Figure 5 for the toggle bit algorithm, and to the Toggle Bit Timings figure in the “AC Characteristics” section for the timing diagram. The DQ2 vs. DQ6 figure shows the differences be tween DQ2 and DQ6 in graphical form. See also the subsection on “DQ2: Toggle Bit II”. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era sure. (The system may use either OE# or CE# to con - trol the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era sure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 5 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the “DQ6: Toggle Bit I” subsection. Refer to the Toggle Bit Timings figure for the toggle bit timing diagram. The DQ2 vs. DQ6 figure shows the dif ferences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 5 for the following discussion. When - ever the system initially begins reading toggle bit sta - tus, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, a system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The sys tem can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped tog gling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not complete the operation successfully, and

22 Am29F800B 21504E5 November 2, 2006

Table 6. Write Operation Status

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “DQ5: Exceeded Timing Limits” for more information.

24 Am29F800B 21504E5 November 2, 2006

Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifcations are tested with VCC = VCCmax 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Not 100% tested. 5. I CC3 = 20 µA max at extended temperature (>+85°C) Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET Input Load Current VCC = VCC max; A9 = OE# = RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, f = 5 MHz, Byte Mode 19 40 mA CE# = VIL, OE# = VIH, f = 5 MHz, Word Mode 19 50 mA ICC2 VCC Active Write Current (Notes 2, 3 and 4) CE# = VIL, OE# = VIH 36 60 mA ICC3 VCC Standby Current (Notes 2, 5) CE#, OE#, and RESET# = VIH, 0.4 1 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 2.0 VCC + 0.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V VOH Output High Voltage IOH = –2.5 mA, VCC = VCC min 2.4 V VLKO Low VCC Lock-Out Voltage (Note 4) 3.2 4.2 V

November 2, 2006 21504E5 Am29F800B 25 DATA SHEET DC CHARACTERISTICS CMOS Compatible Notes: 1. I CC active while Embedded Erase or Embedded Program is in progress. 2. Maximum I CC specifcations are tested with VCC = VCCmax 3. Not 100% tested. Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9, OE#, RESET Input Load Current VCC = VCC max, A9 = OE# = RESET = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Note 2) CE# = VIL, OE# = VIH, f = 5 MHz Byte Mode 20 40 mA CE# = VIL, OE# = VIH, f = 5 MHz Word Mode 28 50 mA ICC2 VCC Active Write Current (Notes 1, 2, 3) CE# = VIL, OE# = VIH 30 50 mA ICC3 VCC Standby Current (Note 2) CE# and RESET# = VCC±0.5 V, OE# = VIH 0.3 5 µA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 5.0 V 11.5 12.5 V VOL Output Low Voltage IOL = 5.8 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.5 mA, VCC = VCC min 0.85 VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 V VLKO Low VCC Lock-Out Voltage (Note 3) 3.2 4.2 V

26 Am29F800B 21504E5 November 2, 2006

Table 7. Test Specifications Figure 8. Test Setup Diodes are IN3064 or equivalents.

November 2, 2006 21504E5 Am29F800B 27 DATA SHEET AC CHARACTERISTICS Read Operations Notes: 1. Not 100% tested. 2. See Figure 8 and Table 7 for test specifications. Parameter

Description

JEDEC Std Test Setup -55 -70 -90 -120 Unit tAVAV tRC Read Cycle Time (Note 1) Min 55 70 90 120 ns tAVQV tACC Address to Output Delay CE# = VIL OE# = VIL Max 55 70 90 120 ns tELQV tCE Chip Enable to Output Delay OE# = VIL Max 55 70 90 120 ns tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 20 20 20 30 ns tGHQZ tDF Output Enable to Output High Z (Note 1) Max 20 20 20 30 ns tOEH Output Enable Hold Time (Note 1) Read Min 0 ns Toggle and Data# Polling Min 10 ns tAXQX tOH Output Hold Time From Addresses, CE# or OE#, Whichever Occurs First (Note 1) Min 0 ns tCE Outputs WE# Addresses CE# OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tOE

0 VRY/BY#

RESET# tDF tOH Figure 9. Read Operations Timings

28 Am29F800B 21504E5 November 2, 2006

Figure 10. RESET# Timings

30 Am29F800B 21504E5 November 2, 2006

Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter JEDEC Std -55 -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tWLAX tAH Address Hold Time Min 45 45 45 50 ns tDVWH tDS Data Setup Time Min 25 30 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 45 50 ns tWHWL tWPH Write Pulse Width High Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 7 µs Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 30 30 35 50 ns

Figure 13. Program Operation Timings

  1. PA = program address, PD = program data, D OUT is the true data at the program address.
  2. Illustration shows device in word mode.

32 Am29F800B 21504E5 November 2, 2006

Note: SA = Sector Address. VA = Valid Address for reading status data. Figure 14. Chip/Sector Erase Operation Timings

34 Am29F800B 21504E5 November 2, 2006

Figure 17. DQ2 vs. DQ6 Figure 18. Temporary Sector Unprotect Timing Diagram

November 2, 2006 21504E5 Am29F800B 35 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description -55 -70 -90 -120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 55 70 90 120 ns tAVEL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 45 50 ns tDVEH tDS Data Setup Time Min 25 30 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tOES Output Enable Setup Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 30 35 45 50 ns tEHEL tCPH CE# Pulse Width High Min 20 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 7 µs Word Typ 12 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 1 sec

36 Am29F800B 21504E5 November 2, 2006

  1. PA = Program Address, PD = Program Data, SA = Sect or Address, DQ7# = Complement of Data Input, DOUT = Array Data.
  2. Figure indicates the last two bus cycles of the command sequence, with the device in word mode.

Figure 19. Alternate CE# Controlled Write Operation Timings

November 2, 2006 21504E5 Am29F800B 37 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 5.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 4.5 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 5.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 3) Unit Comments Sector Erase Time 1.0 8 s Excludes 00h programming prior to erasure (Note 4)Chip Erase Time (Note 2) 19 s Byte Programming Time 7 300 µs Excludes system level overhead (Note 5) Word Programming Time 12 500 µs Chip Programming Time (Note 2) Byte Mode 7.2 21.6 s Word Mode 6.3 18.6 s Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF Parameter Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Ye a r s 125°C 20 Ye a r s

38 Am29F800B 21504E5 November 2, 2006

SO 044—44-Pin Smal l Outline Package Dwg rev AC; 10/99

November 2, 2006 21504E5 Am29F800B 39 DATA SHEET PHYSICAL DIMENSIONS (continued) TS 048—48-Pin Standard Pin out Thin Small Outline Package (TSOP) Dwg rev AA; 10/99

40 Am29F800B 21504E5 November 2, 2006

PHYSICAL DIMENSIONS (continued) FBB048—48-Ball Fine-Pitch Ball Grid Array (FBGA) 6 x 9 mm package Dwg rev AF; 10/99

42 Am29F800B 21504E5 November 2, 2006

REVISION SUMMARY (Continued) Revision D (January 1999) Distinctive Characteristics Added the 20-year data retention subbullet. Optional Processing: Deleted “B = Burn-in”. DC Characteristics—TTL/NMOS Compatible ILIT: Added OE# and RESET to the Description column. Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5 V” in the Test Conditions column. ILO , I CC1 , I CC2 : Deleted “V CC = V CC max” in Test Conditions. ICC3: Added Note 4, “I CC3 = 20 µA max at extended temperatures (>+85°C)”. DC Characteristics— CMOS Compatible ILIT: Added OE# and RESET to the Description column. Changed “A9 = 12.5 V” to “A9 = OE# = RESET = 12.5 V” in the Test Conditions column. ICC1 , I CC2 , I CC3 : Deleted “V CC = V CCmax”; added Note 2 “Maximum I CC specifications are tested with VCC = VCCmax”. Revision D+1 (March 23, 1999) Command Definitions table Corrected SA definition in legend; range should be A18–A12. In Note 4, A17 should be A18. Revision D+2 (July 2, 1999) Global Added references to availability of device in Known Good Die (KGD) form. Revision E (November 16, 1999) AC Characteristics—Figure 13. Program Operations Timing and Figure 14. Chip/Sector Erase Operations Deleted tGHWL and changed OE# waveform to start at high. Physical Dimensions Replaced figures with more detailed illustrations. Revision E+1 (August 4, 2000) Global Added FBGA package. Revision E+2 (June 4, 2004) Added Pb-Free OPNs. Revision E3 (December 22, 2005) Global Deleted reverse TSOP package option and 150 ns speed option. Revision E4 (May 19, 2006) Added “Not recommended for new designs” note. AC Characteristics Changed tBUSY specification to maximium value. Revision E5 (November 2, 2006) Deleted “Not recommended for new designs” note. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion Inc. will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor devices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners. Copyright © 2004–2006 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.