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Document overview
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Technical content
Features
Drives Two N-MOSFETs Adaptive Shoot-Through Protection 0.5ΩΩΩΩΩ On-Resistance, 4A Sink Current Capability Supports High Switching Frequency Tri-State PWM Input for Power Stage Shutdown Output Disable Function Integrated Boost Switch Low Bias Supply Current VCC POR Feature Integrated Small 8-Lead WDFN Package RoHS Compliant and Halogen Free
Applications
Core Voltage Supplies for Intel ® / AMD ® Mobile Microprocessors High Frequency Low Profile DC/DC Converters High Current Low Output Voltage DC/DC Converters High Input Voltage DC/DC Converters High Voltage Synchronous Rectified Buck MOSFET Driver for Notebook Computer General Description The RT9610B is a high frequency, dual MOSFET driver specifically designed to drive two power N-MOSFETS in a synchronous-rectified buck converter topology. It is especially suited for mobile computing applications that require high efficiency and excellent thermal performance. This driver, combined with Richtek's series of multi-phase Buck PWM controllers, provides a complete core voltage regulator solution for advanced microprocessors. The drivers are capable of driving a 3nF load with fast rising/falling time and fast propagation delay. This device implements bootstrapping on the upper gates with only a single external capacitor. This reduces implementation complexity and allows the use of higher performance, cost effective, N-MOSFETs. Adaptive shoot through protection is integrated to prevent both MOSFETs from conducting simultaneously. The RT9610B is available in WDFN-8L 2x2 package.
Ordering Information
Note : Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Pin Configuration (TOP VIEW) WDFN-8L 2x2 EN BOOT PHASE VCC LGATE GND PWM UGATE GND RT9610B Package Type QW : WDFN-8L 2x2 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Marking Information 20 : Product Code W : Date Code20W
DS9610B-07 August 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1 EN Enable pin. When low, both UGATE and LGATE are driven low and the normal operation is disabled. 2 PHASE Switch node. Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. This pin provides a return path for the upper gate driver. 3 UGATE Upper gate drive output. Connect to the gate of high side power N-MOSFET.
4 BOOT
Floating bootstrap supply pin for upper gate drive. Connect the bootstrap capacitor between this pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. 5 PWM Control input for driver. The PWM signal can enter three distinct states during operation. Connect this pin to the PWM output of the controller. 9 (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 7 LGATE Lower gate drive output. Connect to the gate of the low side power N-MOSFET. 8 VCC Input supply pin. Connect this pin to a 5V bias supply. Place a high quality bypass capacitor from this pin to GND. Functional Block Diagram Shoot-Through Protection BOOT UGATE PHASE POR VCC R R Tri-State DetectPWM EN Control Logic LGATE GND VCCVCC
DS9610B-07 August 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Operation POR (Power On Reset) POR block detects the voltage at the VCC pin. When the VCC pin voltage is higher than POR rising threshold, the POR pin output voltage (POR output) is high. POR output is low when VCC is not higher than POR rising threshold. When the POR pin voltage is high, UGATE and LGATE can be controlled by PWM input voltage. If the POR pin voltage is low, both UGATE and LGATE will be pulled to low. Tri-State Detect When both POR output and EN pin voltages are high, UGATE and LGATE can be controlled by PWM input. There are three PWM input modes which are high, low, and shutdown state. If PWM input is within the shutdown window, both UGATE and LGATE outputs are low. When PWM input is higher than its rising threshold, UGATE is high and LGATE is low. When PWM input is lower than its falling threshold, UGATE is low and LGATE is high. Control Logic Control logic block detects whether high side MOSFET is turned off by monitoring (UGATE - PHASE) voltages below 1.1V or PHASE voltage below 2V. To prevent the overlap of the gate drives during the UGATE pulls low and the LGATE pulls high, low side MOSFET can be turned on only after high side MOSFET is effectively turned off. Shoot-Through Protection Shoot-through protection block implements the dead-time when both high side and low side MOSFETs are turned off. With shoot-through protection block, high side and low side MOSFETs are never turned on simultaneously. Thus, shoot-through between high side and low side MOSFETs is prevented.
DS9610B-07 August 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Electrical Characteristics
Recommended Operating Conditions (Note 4) (VCC = 5V, T A = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit VCC Supply Current Quiescent Current IQ PWM Pin Floating, V EN = 3.3V -- 80 -- A Shutdown Current ISH DN V EN = 0V, PWM = 0V, VCC = 5V -- 0 5 A VPORH VCC POR Rising -- 4.2 4.5 V VPORL VCC POR Falling 3.5 3.84 -- V VCC Power On Reset (POR) VPORH YS Hysteresis -- 360 -- mV Absolute Maximum Ratings (Note 1) PHASE to GND UGATE to PHASE LGATE to GND Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3)
DS9610B-07 August 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Internal BOOT Switch Internal Boost Switch On Resistance RBOOT VCC to BOOT, 10mA -- -- 80 PWM Input VPWM = 5V -- 174 -- Input Current I PWM VPWM = 0V -- 174 -- PWM Tri-State Rising Threshold VPWMH V CC = 5V 3.5 3.8 4.1 V PWM Tri-State Falling Threshold VPWML V CC = 5V 0.7 1 1.3 V Tri-State Shutdown Hold-off Time tSHD_Tri V CC = 5V 100 175 250 ns EN Input Logic-High V ENH V CC = 5V 2 -- -- EN Input Voltage Logic-Low V ENL V CC = 5V -- -- 0.48 V Switching Time UGATE Rise Time t UGATEr V CC = 5V, 3nF Load -- 8 -- ns UGATE Fall Time t UGATEf V CC = 5V, 3nF Load -- 8 -- ns LGATE Rise Time t LGATEr V CC = 5V, 3nF Load -- 8 -- ns LGATE Fall Time t LGATEf V CC = 5V, 3nF Load -- 4 -- ns UGATE Turn-Off Propagation Delay tPDLU V CC = 5V, Outputs Unloaded -- 35 -- ns LGATE Turn-Off Propagation Delay tPDLL V CC = 5V, Outputs Unloaded -- 35 -- ns UGATE Turn-On Propagation Delay tPDHU V CC = 5V, Outputs Unloaded -- 20 -- ns LGATE Turn-On Propagation Delay tPDHL V CC = 5V, Outputs Unloaded -- 20 -- ns UGATE/LGATE Tri-State Propagation Delay tPTS V CC = 5V, Outputs Unloaded -- 35 -- ns Output UGATE Driver Source Resistance RUGATEsr 100mA Source Current -- 1 -- UGATE Driver Source Current I UGATEsr V UGATE VPHASE = 2.5V -- 2 -- A UGATE Driver Sink Resistance R UGATEsk 100mA Sink Current -- 1 -- UGATE Driver Sink Current I UGATEsk V UGATE VPHASE = 2.5V -- 2 -- A LGATE Driver Source Resistance RLGATEsr 100mA Source Current -- 1 -- LGATE Driver Source Current I LGATEsr V LGATE = 2.5V -- 2 -- A LGATE Driver Sink Resistance R LGATEsk 100mA Sink Current -- 0.5 -- LGATE Driver Sink Current I LGATEsk V LGATE = 2.5V -- 4 -- A
DS9610B-07 August 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution recommended. The human body mode is a 100pF capacitor is charged through a 1.5k Ω resistor into each pin. Note 4. The device is not guaranteed to function outside its operating conditions. Timing Diagram PWM LGATE UGATE tPDLL 90% 1.5V 1.5V tPDHU tPDLU tPDHL 90% 1.5V 1.5V VCC PWM GND BOOT UGATE PHASE LGATE RT9610B 1µF Q1VCC 1µF PWM 1µH 2.2µH VCORE EN C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 VINVBAT 3.3nF 2.2 Chip Enable
DS9610B-07 August 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Operating Characteristics Dead Time UGATE PHASE LGATE UGATE - PHASE (5V/Div) Time (20ns/Div) VIN = 19V, PWM Falling, No Load Dead Time UGATE PHASE (5V/Div) LGATE UGATE - PHASE Time (20ns/Div) VIN = 19V, PWM Rising, No Load PWM Rising Edge UGATE (20V/Div) PHASE (20V/Div) PWM (5V/Div) LGATE (5V/Div) Time (20ns/Div) VIN = 19V, No Load PWM Falling Edge UGATE (20V/Div) PHASE (20V/Div) PWM (5V/Div) LGATE (5V/Div) Time (20ns/Div) VIN = 19V, No Load Driver Disable UGATE (20V/Div) PHASE (20V/Div) EN (5V/Div) LGATE (5V/Div) Time (1 μs/Div) VIN = 19V, No Load Driver Enable UGATE (20V/Div) PHASE (20V/Div) EN (5V/Div) LGATE (5V/Div) Time (1 μs/Div) VIN = 19V, No Load
DS9610B-07 August 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Short Pulse UGATE PHASE LGATE UGATE - PHASE (5V/Div) Time (20ns/Div) VIN = 19V, Start Up Dead Time UGATE PHASE LGATE UGATE - PHASE (5V/Div) Time (20ns/Div) VIN = 19V, PWM Falling, Full Load Dead Time UGATE PHASE LGATE UGATE - PHASE (5V/Div) Time (20ns/Div) VIN = 19V, PWM Rising, Full Load
DS9610B-07 August 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Application Information
Supply Voltage and Power On Reset The RT9610B is designed to drive both high side and low side N-MOSFETs through an externally input PWM control signal. Connect 5V to VCC to power on the RT9610B. A minimum 1 μF ceramic capacitor is recommended to bypass the supply voltage. Place the bypassing capacitor physically near the IC. The power on reset (POR) circuit monitors the supply voltage at the VCC pin. If VCC exceeds the POR rising threshold voltage, the controller resets and prepares for operation. UGATE and LGATE are held low before VCC is above the POR rising threshold. Enable and Disable The RT9610B includes an EN pin for sequence control. When the EN pin rises above the V ENH trip point, the RT9610B begins a new initialization and follows the PWM command to control the UGATE and LGATE. When the EN pin falls below the V ENL trip point, the RT9610B shuts down and keeps UGATE and LGATE low. Three State PWM Input After initialization, the PWM signal takes over the control. The rising PWM signal first forces the LGATE signal low and then allows the UGATE signal to go high right after a non-overlapping time to avoid shoot through current. In contrast, the falling PWM signal first forces UGATE to go low. When the UGATE or PHASE signal reach a predetermined low level, LGATE signal is then allowed to go high. Non-overlap Control To prevent the overlap of the gate drives during the UGATE pull low and the LGATE pull high, the non-overlap circuit monitors the voltages at the PHASE node and high side gate drive (UGATE-PHASE). When the PWM input signal goes low, UGATE begins to pull low (after propagation delay). Before LGATE can pull high, the non-overlap protection circuit ensures that the monitored (UGATE- PHASE) voltages have gone below 1.1V or phase voltage is below 2V. Once the monitored voltages fall below the threshold, LGATE begins to turn high. By waiting for the voltages of the PHASE pin and high side gate drive to fall below their threshold, the non-overlap protection circuit ensures that UGATE is low before LGATE pulls high. Also to prevent the overlap of the gate drives during LGATE pull low and UGATE pull high, the non-overlap circuit monitors the LGATE voltage. When LGATE go below 1.1V, UGATE is allowed to go high. Driving Power MOSFETs The DC input impedance of the power MOSFET is extremely high. The gate draws the current only for few nano-amperes. Thus once the gate has been driven up to “ON” level, the current could be negligible. However, the capacitance at the gate to source terminal should be considered. It requires relatively large currents to drive the gate up and down rapidly. It is also required to switch drain current on and off with the required speed. The required gate drive currents are calculated as follows. L Cgs1Cgd1 Igd1 Igs1 Ig1 VOUT VIN GND Cgs2 Ig2 Igd2 Igs2 Cgd2 Figure1. Equivalent Circuit and Associated Waveforms t t Vg2 Vg1 VPHASE +5V
DS9610B-07 August 2016www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. W-Type 8L DFN 2x2 Package Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.200 0.300 0.008 0.012 D 1.950 2.050 0.077 0.081 D2 1.000 1.250 0.039 0.049 E 1.950 2.050 0.077 0.081 E2 0.400 0.650 0.016 0.026 e 0.500 0.020 L 0.300 0.400 0.012 0.016 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options D E A L be SEE DETAIL A Outline Dimension