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Technical content
Features
Support Connected Shutdown Mode for Ultrabook CCRCOT Control with 100ns Load Step Response PWM Maximum Duty Ratio > 98% 5V to 25V Input Voltage Range 2V to 5.5V Output Voltage Range 5V LDO with 100mA Output Current Internal Frequency Setting with 300kHz @ VIN =12V Internal Soft-Start and Soft-Discharge 4700ppm/°°°°°C RDS(ON) Current Sensing Independent Switcher Enable Control Built-In OVP/UVP/OCP/OTP Synchronous DC-DC Step-Down Controller with 5V LDO
Applications
Notebook and Sub-Notebook Computers System Power Supplies 3-Cell and 4-Cell Li+ Battery-Powered Devices
Ordering Information
Note : *Empty means Pin1 orientation is Quadrant 1 Richtek products are : RoHS compliant and compatible with the current require- ments of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. RT6550A Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Pin 1 Orientation* (2) : Quadrant 2, Follow EIA-481-D Marking Information 6W=YM DNN 6W= : Product Code YMDNN : Date Code Pin Configuration (TOP VIEW) WDFN-10L 3x3 EN CS LDO5 VO_DIS LGATE PHASE UGATE VIN BOOT FB GND
DS6550A-00 September 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Pin Description Pin No. Pin Name Pin Function 1 EN Enable control input. 2 CS Current limit setting. Connect a resistor to GND to set the threshold for synchronous RDS(ON) sense. The GND - PHASE current limit threshold is 1/8th the voltage seen at CS over a 0.2V to 2V range. There is an internal 10 A current source from LDO5 to CS. 3 FB Feedback voltage input. Connect FB to a resistive voltage divider from VOUT to GND to adjust output from 2V to 5.5V. 4 VO_DIS Output discharge function. 5 LDO5 5V linear regulator output. LDO5 is also the supply voltage for the low-side MOSFET and analog supply voltage for the device. 6 VIN Power input for 5V LDO regulator and buck controller. 7 BOOT Bootstrap supply for high-side gate driver. Connect to an external capacitor according to the typical application circuit. 8 UGATE High-side gate driver output. UGATE swings between PHASE and BOOT. 9 PHASE Switch node of MOSFETs. PHASE is the internal lower supply rail for the UGATE high-side gate driver. PHASE is also the current sense input. 10 LGATE Low-side gate driver output. LGATE swings between GND and LDO5. (Exposed Pad) GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation.
DS6550A-00 September 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Functional Block Diagram Operation The RT6550A includes constant on-time synchronou step- down controller and linear regulator. Buck Controller In normal operation, the high-side N-MOSFET is turned on when the output is lower than VREF, and is turned off after the internal one-shot timer expires. While the high- side N-MOSFET is turned off, the low-side N-MOSFET is turned on to conduct the inductor current until next cycle begins. Soft-Start For internal soft-start function, an internal current source charges an internal capacitor to build the soft-start ramp voltage. The output voltage will track the internal ramp voltage during soft-start interval. Current Limit The current limit circuit employs an unique “valley” current sensing algorithm. If the magnitude of the current sense signal at PHASE is above the current limit threshold, the PWM is not allowed to initiate a new cycle. Thus, the current to the load exceeds the average output inductor current, the output voltage falls and eventually crosses the under-voltage protection threshold, inducing IC shutdown. Over-Voltage Protection (OVP) and Under-Voltage Protection (UVP) The channel output voltage is continuously monitored for over-voltage and under-voltage conditions. When the output voltage exceeds over-voltage threshold (113% of VOUT), UGATE goes low and LGATE is forced high; when it is less than 52% of reference voltage, under-voltage protection is triggered and then both UGATE and LGATE gate drivers are forced low. The controller is latched until EN is reset or LDO5 is re-supplied. LDO5 The LDO5 can be power on by EN. The linear regulator LDO5 provides 5V regulated output. Driver Logic VIN FB TON Generator Control & Protection Logic PWM CMP Soft Start & Slew Rate Control PWM 113% VREF Power On Reset 52% VREF Enable LogicEN OVP UVP CS 10µA X(1/8) Current limit VREF BOOT UGATE PHASE LGATE GND LDO5 VO_DIS Shutdown Discharge LDO5 LDO5 Over- Temperature Protection Short during CCM +
DS6550A-00 September 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Absolute Maximum Ratings (Note 1) BOOT to GND BOOT to PHASE PHASE to GND UGATE to GND UGATE to PHASE LGATE to GND Power Dissipation, PD @ TA = 25°C Package Thermal Resistance (Note 2) ESD Susceptibility (Note 3) Recommended Operating Conditions (Note 4)
DS6550A-00 September 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Parameter Symbol Test Conditions Min Typ Max Unit Input Supply VIN Power On Reset V IN_POR Rising Threshold -- 4.6 4.9 V Falling Threshold 3.2 3.7 -- VIN Shutdown Supply Current IVIN_SBY Buck Controller Off, V EN = GND -- 20 35 A VIN Quiescent Current I VIN UGATE / LGATE Floating, VIN = 12V, No Switching -- 420 750 A Buck Controllers Output and FB Voltage FB Valley Trip Voltage V FB CCM Operation 1.98 2 2.02 V VO_DIS Discharge Current IDCHG V VO_DIS = 0.5V 10 45 -- mA PHASE Discharge Current IDCHG_LX V PHASE = 0.5V 5 8 -- mA Switching Frequency Switching Frequency f SW V IN = 12V, VOUT = 5V 240 300 360 kHz Minimum Off-Time t OFF(MIN) V FB = 1.9V -- 200 275 ns Soft-Start Soft-Start Time t SS V OUT Ramp-up Time -- 0.9 -- ms Current Sense CS Source Current I CS V CS = 1V 9 10 11 A CS Current Temperature Coefficient TCICS In Comparison with 25°C -- 4700 -- ppm/ C Internal Regulator LDO5 Output Voltage V LDO5 VIN = 12V, No Load 4.9 5 5.1 V VIN > 7V, ILDO5 < 100mA 4.8 5 5.1 VIN > 5.5V, ILDO5 < 35mA 4.8 5 5.1 VIN > 5V, ILDO5 < 20mA 4.5 4.75 5.1 LDO5 Output Current I LDO5 V LDO5 = 4.5V, VIN = 7.4V 100 175 -- mA UVLO LDO5 UVLO Threshold V UVLO5 Rising Edge -- 4.3 4.6 V Falling Edge 3.7 3.9 4.1 Fault Detection OVP Trip Threshold V OVP FB with Respect to Internal Reference 109 113 117 % OVP Propagation Delay -- 1 -- s UVP Trip Threshold V UVP UVP Detect, FB Falling Edge 47 52 57 % UVP Shutdown Blanking Time tSHDN_UVP From EN Enable -- 1.3 -- ms
Electrical Characteristics
(VIN = 12V, VEN = 3.3V, VCS = 2V, No Load, TA = 25°C, unless otherwise specified)
DS6550A-00 September 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Note 1. Stresses beyond those listed “Absolute Maximum Ratings ” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θ JA is measured under natural convection (still air) at T A = 25 °C with the component mounted on a high effective- thermal-conductivity four-layer test board on a JEDEC 51-7 thermal measurement standard. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Parameter Symbol Test Conditions Min Typ Max Unit Thermal Shutdown Thermal Shutdown T SD -- 150 -- °C Logic Inputs EN Threshold Voltage VEN_H SMPS On 1.6 -- -- V VEN_L SMPS Off -- -- 0.4 Internal Boost Switch Internal Boost Switch On-Resistance RBOOST LDO5 to BOOT -- 80 -- Power MOSFET Drivers UGATE On-Resistance R UGATE High State, VBOOT VUGATE = 0.25V, VBOOT VPHASE = 5V -- 3 -- Low State, VUGATE VPAHSE = 0.25V, VBOOT VPHASE = 5V -- 2 -- LGATE On-Resistance R LGATE High State, VLDO5 VLGATE = 0.25V, VLDO5 = 5V -- 3 -- Low State, VLGATE GND = 0.25V -- 1 -- Dead-Time t D LGATE Rising -- 20 -- ns UGATE Rising -- 30 --
DS6550A-00 September 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Typical Application Circuit C6 5V RT6550A VIN6 PHASE LGATE BOOT UGATE FB VIN 10µF8 C3R15.2V to 25V LC4 0.1µF R4 0 15k 10k VO_DIS 4 10µF EN1 VOUT
0 R3 0
10µF Enable BSC0909 NS R5* C5* 3.3µH 220µF C8* 11 (Exposed Pad)GND Off On * : Optional LDO55 1µF CS2 82k
DS6550A-00 September 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Quiescent Current vs. Input Voltage 200 210 220 230 240 250 260 270 280 290 300 5 9 13 17 21 25 Input Voltage (V) Quiescent Current (μA) VLDO5 vs. ILDO5 5.000 5.005 5.010 5.015 5.020 5.025 5.030 0 20 40 60 80 100 ILDO5 (mA) VLDO5 (V) Output Voltage vs. Output Current 4.96 4.97 4.98 4.99 5.00 5.01 5.02 0.001 0.01 0.1 1 10 Output Current (A) Output Voltage (V) Switching Frequency vs. Input Voltage 100 200 300 400 500 5 9 13 17 21 25 Input Voltage (V) Switching Frequency (kHz) 1 Switching Frequency vs. Output Current 100 150 200 250 300 350 400 450 0.001 0.01 0.1 1 10 Output current (A) Switching frequency(kHz Typical Operating Characteristics VEN = 1/4 V IN VIN = 11.1V VIN = 7.4V VIN = 19V VEN = 1/4 V IN IOUT = 6A VEN = 1/4 V IN VIN = 20.5V VIN = 14.8V VIN = 11.1V VIN = 7.4V VEN = 1/4 VIN, VIN = 12V VEN = 1/4 VIN, VFB = 2.2V, No Switching Efficiency vs. Output current 100 0123456789 Output current (A) Efficiency (%) VEN = 1/4 V IN VIN = 7.4V VIN = 11.1V VIN = 14.8V VIN = 20.5V
DS6550A-00 September 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. VIN = 12V, VEN = 5V, No Load Power On from EN Time (400 μs/Div) VEN (5V/Div) VOUT (5V/Div) VLDO5 (5V/Div) Power Off from EN Time (2ms/Div) VIN = 12V, VEN = 5V, No Load VEN (5V/Div) VOUT (5V/Div) VLDO5 (5V/Div) Load Transient Response Time (40 μs/Div) IOUT (5A/Div) VOUT (100mV/Div) VEN = 1/4 VIN, VIN = 12V, IOUT = 0A to 6A UGATE (20V/Div) LGATE (5V/Div) OVP Time (40 μs/Div) VEN = 1/4 VIN, VIN = 12V, No Load VOUT (2V/Div) UGATE (20V/Div) LGATE (5V/Div) UVP Time (400 μs/Div) VEN = 1/4 VIN, VIN = 12V, No Load VOUT (2V/Div) UGATE (20V/Div) LGATE (5V/Div) IOUT (5A/Div) VOUT IOUT
DS6550A-00 September 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation.
Application Information
The RT6550A is a low quiescent, Mach ResponseTM DRVTM mode synchronous Buck controller targeted for Ultrabook system power supply solutions. Richtek's Mach Response TM technology provides fast response to load steps. The topology solves the poor load transient response timing problems of fixed frequency current mode PWMs, and avoids the problems caused by widely varying switching frequencies in CCR (constant current ripple) constant on-time PWM schemes. A special adaptive on- time control trades off the performance and efficiency over wide input voltage range. The RT6550A includes 5V (LDO5) linear regulators. The LDO5 linear regulator steps down the battery voltage to supply internal circuitry and gate drivers. The synchronous switch gate drivers are directly powered by LDO5. PWM Operation The Mach Response TM DRVTM mode controller relies on the output filter capacitor's Effective Series Resistance (ESR) to act as a current sense resistor, so that the output ripple voltage provides the PWM ramp signal. Referring to the RT6550A's Function Block Diagram, the synchronous high-side MOSFET is turned on at the beginning of each cycle. After the internal one-shot timer expires, the MOSFET will be turned off. The pulse width of this one- shot is determined by the converter's input output voltages to keep the frequency fairly constant over the entire input voltage range. Another one-shot sets a minimum off-time (200ns typ.). The on-time one-shot will be triggered if the error comparator is high, the low-side switch current is below the current limit threshold, and the minimum off- time one-shot has timed out. PWM Frequency and On-time Control For each specific input voltage range, the Mach Response TM control architecture runs with pseudo constant frequency by feed forwarding the input and output voltage into the on-time one-shot timer. The high-side switch on-time is inversely proportional to the input voltage as measured by V IN and proportional to the output voltage. The inductor ripple current operating point remains relatively constant, resulting in easy design methodology and predictable output voltage ripple. The RT6550A adaptively changes the operation frequency according to the input voltage. Higher input voltage usually comes from an external adapter, so the RT6550A operates with higher frequency to have better performance. Lower input voltage usually comes from a battery, so the RT6550A operates with lower switching frequency for lower switching losses. For a specific input voltage range, the switching cycle period is given by : For 5V VOUT, IN IN V2 . 0 2 5Period (usec.) = V3 . 7 9 where the VIN is in volt. The on-time guaranteed in the Electrical Characteristics table is influenced by switching delays in the external high-side power MOSFET. Forced-CCM Mode The low noise, forced-CCM mode disables the zero- crossing comparator, which controls the low side switch on-time. This causes the low side gate-drive waveform to become the complement of the high side gate-drive waveform. This in turn causes the inductor current to reverse at ligt loads as the PWM loop to maintain a duty ratio V OUT/VIN. The benefit of forced-CCM mode is to keep the switching frequency fairly constant, but it comes at a cost : The no-load battery current can be up to 10mA, depending on the external MOSFETs. Linear Regulators (LDO5) The RT6550A includes 5V (LDO5) linear regulators. The regulator can supply up to 100mA for external loads. Bypass LDO with 1 μF (min) to 4.7 μF (max), and the recommended value is 1μF ceramic capacitor. Current Limit Setting The RT6550A has cycle-by-cycle current limit control and the OCP function only operation at CCM , it is disabled at FCCM in order to reduce quiescent current. The current limit circuit employs an unique “valley” current sensing algorithm. If the magnitude of the current sense signal at
DS6550A-00 September 2016www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. UVLO Protection The RT6550A has LDO5 under-voltage lock out protection (UVLO). When the LDO5 voltage is lower than 3.9V (typ.), both switch power supply is shut off. This is a non-latch protection. Output Over-Voltage Protection (OVP) The output voltage can be continuously monitored for over- voltage condition. If the output voltage exceeds 13% of its set voltage threshold, the over-voltage protection is triggered and the LGATE low-side gate drivers is forced high. This activates the low-side MOSFET switch, which rapidly discharges the output capacitor and pulls the output voltage downward. The RT6550A is latched once OVP is triggered and can only be released by either toggling EN or cycling VIN. There is a 1μs delay built into the over-voltage protection circuit to prevent false transition. Note that latching LGATE high will cause the output voltage to dip slightly negative due to previously stored energy in the LC tank circuit. For loads that cannot tolerate a negative voltage, place a power Schottky diode across the output to act as a reverse polarity clamp. If the over-voltage condition is caused by a shorted in high-side switch, turning the low-side MOSFET on 100% will create an electrical shorted circuit between the battery and GND to blow the fuse and disconnecting the battery from the output. Output Under-Voltage Protection (UVP) The output voltage can be continuously monitored for under- voltage condition. If the output is less than 52% (typ.) of its set voltage threshold, the under-voltage protection will be triggered and then both UGATE and LGATE gate drivers will be forced low. The UVP is ignored for at least 1.3ms (typ.) after a start-up or a rising edge on EN. Toggle EN or cycle VIN to reset the UVP fault latch and restart the controller. Thermal Protection The RT6550A features thermal shutdown to prevent damage from excessive heat dissipation. Thermal shutdown occurs when the die temperature exceeds 150°C. All internal circuitries are turned off during thermal shutdown. The RT6550A triggers thermal shutdown while input voltage on VIN and drawing current from LDO5 are too high. Discharge Mode (Soft Discharge) When EN is low the output under-voltage fault latch is set, the output discharge mode will be triggered. During discharge mode, an internal switch creates a path for discharging the output capacitors' residual charge to GND. Shutdown Mode When VIN exceeds POR threshold and EN < 0.4V, the RT6550A operate in shutdown mode, and PWM contoller is OFF state. For the RT6550A, LDO5 is OFF and approximately consumes 17μA of input current. Power-Up Sequencing and On/Off Controls (EN) EN controls the power-up sequencing of the Buck converter. The 0.4V falling edge threshold on EN can be used to detect a specific analog voltage level and to shutdown the device. Once in shutdown, the 1.6V rising edge threshold activates, providing sufficient hysteresis for most applications.
©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Figure 6. Derating Curve of Maximum Power Dissipation the average inductor current. The calculation above shall serve as a general reference. considered when improving transient response. on the maximum power dissipation.
DS6550A-00 September 2016 www.richtek.com ©Copyright 2016 Richtek Technology Corporation. All rights reserved. is a registered trademark of Ric htek Technology Corporation. Layout Considerations Layout is very important in high frequency switching converter design. Improper PCB layout can radiate excessive noise and contribute to the converter’s instability. Certain points must be considered before starting a layout with the RT6550A. Place the filter capacitor close to the IC, within 12mm (0.5 inch) if possible. Keep current limit setting network as close as possible to the IC. Routing of the network should avoid coupling to high- voltage switching node. Connections from the drivers to the respective gate of the high-side or the low-side MOSFET should be as short as possible to reduce stray inductance. Use 0.65mm (25 mils) or wider trace. All sensitive analog traces and components such as FB, PGOOD, and should be placed away from high voltage switching nodes such as PHASE, LGATE, UGATE, or BOOT nodes to avoid coupling. Use internal layer(s) as ground plane(s) and shield the feedback trace from power traces and components. Place ground terminal of VIN capacitor(s), VOUT capacitor(s), and Source of low-side MOSFETs as close to each other as possible. The PCB trace of PHASE node, which connects to Source of high-side MOSFET, Drain of low-side MOSFET and high voltage side of the inductor, should be as short and wide as possible.
DS6550A-00 September 2016www.richtek.com Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnish ed by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringeme nts of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of R ichtek or its subsidiaries. Outline Dimension Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e 0.500 0.020 L 0.350 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package 1 122 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. DETAIL A Pin #1 ID and Tie Bar Mark Options D E A L be SEE DETAIL A