DS42514

DS42514 AMD | Alldatasheet

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This document contains information on a product under development at Advanced Micro Devices. The information is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed product without notice. Publication# 23756 Rev: B Amendment/2 Issue Date: March 15, 2001 Refer to AMD’s Website (www.amd.com) for the latest information. DS42514 Stacked Multi-Chip Package (MCP) Flash Memory and SRAM Am29DL163D Bottom Boot 16 Megabit (2 M x 8-Bit/1 M x 16-Bit) CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory and 4 Mbit (512 K x 8-Bit/ 256 K x 16-Bit) Static RAM DISTINCTIVE CHARACTERISTICS MCP Features I Power supply voltage of 2.7 to 3.3 volt I High performance — 85 ns maximum access time I Package — 69-Ball FBGA I Operating Temperature — –25°C to +85°C Flash Memory Features ARCHITECTURAL ADVANTAGES I Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank — Zero latency between read and write operations I Secured Silicon (SecSi) Sector: Extra 64 KByte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed I Zero Power Operation — Sophisticated power management circuits reduce power consumed during inactive periods to nearly zero I Bottom boot block I Manufactured on 0.23 µm process technology I Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS I High performance — 85 ns access time — Program time: 7 µs/word typical utilizing Accelerate function I Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode I Minimum 1 million write cycles guaranteed per sector I 20 Year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES I Data Management Software (DMS) — AMD-supplied software manages data programming and erasing, enabling EEPROM emulation — Eases sector erase limitations I Supports Common Flash Memory Interface (CFI) I Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank I Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles I Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES I Any combination of sectors can be erased I Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion I Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to reading array data I WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing I Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotect allows changing data in protected sectors in-system SRAM Features I Power dissipation — Operating: 50 mA maximum — Standby: 7 µA maximum I CE1#s and CE2s Chip Select I Power down features using CE1#s and CE2s I Data retention supply voltage: 1.5 to 3.3 volt I Byte data control: LB#s (DQ0–DQ7), UB#s (DQ8–DQ15)

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The Am29DL163 is a 16 megabit, 3.0 volt-only flash memory device, organized as 1,048,576 words of 16 bits each or 2,097,152 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data ap- pears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 85 ns. The device is offered in a 69-ball FBGA package. Standard control pins— chip enable (CE#f), write en- able (WE#), and output enable (OE#)— control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. The Am29DL163D has 4 Mb in Bank 1 and 12 Mb in Bank 2. The Secured Silicon (SecSi) Sector is an extra 64 Kbit sector capable of being permanently locked by AMD or customers. The SecSi Sector Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable. This way, customer lockable parts can never be used to re- place a factory locked part. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number). Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplified, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode. The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes.

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Figure 12. Input Waveforms and Measurement Figure 13. Timing Diagram for Alternating Figure 16. CIOf Timings for Read Operations . 39 Figure 17. CIOf Timings for Write Operations. . 39 Figure 19. Accelerated Program Timing Figure 20. Chip/Sector Erase Operation Figure 21. Back-to-back Read/Write Cycle Figure 22. Data# Polling Timings (During Figure 23. Toggle Bit Timings (During Figure 25. Temporary Sector/Sector Block Figure 26. Sector/Sector Block Protect and Figure 27. Flash Alternate CE#f Controlled Figure 28. SRAM Read Cycle— Address Figure 30. SRAM Write Cycle— WE# Control . . 51 Figure 31. SRAM Write Cycle— CE1#s Control. 52 Figure 32. SRAM Write Cycle— UB#s and Figure 33. CE1#s Controlled Data Retention Figure 34. CE2s Controlled Data Retention

Standard Voltage Range: VCC = 2.7–3.3 V Flash Memory SRAM Max Access Time (ns) 85 85 CE# Access (ns) 85 85 OE# Access (ns) 35 45 VSS /VSSQVCC s/VCCQ RESET# WE# CE#f OE# CE1#s VSSVCC f RY/BY# LB#s UB#s CIOf WP#/ACC CE2s SA CIOs

4 Mbit

16 Mbit

DQ0 to DQ15/A–1 DQ0 to DQ15/A–1 DQ0 to DQ15/A–1 A0 to A19 A0 to A19 A0 to A19 A–1 A0 to A17

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FLASH MEMORY BLOCK DIAGRAM VCC VSS Upper Bank AddressA0–A19 RESET# WE# CE# CIOf DQ0 –DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# CIOf DQ0 –DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address Status Control A0–A19 A0–A19 A0–A19A0–A19 DQ0 –DQ15 DQ0 –DQ15

Special Handling Instructions for FBGA Package Special handling is required for Flash Memory prod- ucts in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro- mised if the package body is exposed to temperatures above 150 °C for prolonged periods of time. NC NC NC NC NC DQ8 DQ14 CE1#s LB#s WP#/ACC WE# A8 A11 B3B1 B4 B5 B6 B7 B8 A6 UB#s RESET# CE2s A19 A12 A15 C2 C3 C4 C5 C6 C7 C8 C9 A5 A18 RY/BY# NC A9 A13 NC D2 D3 D4 D5 D6 D7 D8 D9 A1 A4 A17 A10 A14 NC E1 E10E2 E3 E4 E7 E8 E9 VSS DQ1A0 DQ6 SA A16 F1 F10F3 F4F2 F7 F8 F9 CE#f DQ0 OE# DQ9 DQ3 DQ4 DQ13 DQ15/A -1 CIOf G2 G3 G4 G5 G6 G7 G8 G9 DQ10 VCC f VCC s DQ12 DQ7 V SS H2 H3 H4 H5 H6 H7 H8 H9 DQ2 DQ11 CIOs DQ5 J3 J8J4 J5 J6 J7 NC NC NC A1 A5 A6 NC A10 NC NC NC K1 K5 K6 NC K10 SRAM only Shared Flash only 69-Ball FBGA Top View

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A0–A17 = 18 Address Inputs (Common) A–1, A18–A19 = 3 Address Inputs (Flash) SA = Highest Order Address Input (SRAM) Byte mode DQ0 –DQ15 = 16 Data Inputs/Outputs (Common) CE#f = Chip Enable (Flash) CE#s = Chip Enable (SRAM) OE# = Output Enable (Common) WE# = Write Enable (Common) RY/BY# = Ready/Busy Output UB#s = Upper Byte Control (SRAM) LB#s = Lower Byte Control (SRAM) CIOf = I/O Configuration (Flash) CIOf = V IH = Word mode (x16), CIOf = VIL = Byte mode (x8) CIOs = I/O Configuration (SRAM) CIOs = VIH = Word mode (x16), CIOs = VIL = Byte mode (x8) RESET# = Hardware Reset Pin, Active Low WP#/ACC = Hardware Write Protect/ Acceleration Pin (Flash) V CC f = Flash 3.0 volt-only single power sup- ply (see Product Selector Guide for speed options and voltage supply tolerances) V CC s = SRAM Power Supply VSS = Device Ground (Common) NC = Pin Not Connected Internally LOGIC SYMBOL

ORDERING INFORMATION

This section describes the requirements and use of the device bus operations, which are initiated through the internal command register. The command register itself does not occupy any addressable memory loca- tion. The register is a latch used to store the commands, along with the address and data informa- tion needed to execute the command. The contents of the register serve as inputs to the internal state ma- chine. The state machine outputs dictate the function of the device. Tables 1 through 3 lists the device bus operations, the inputs and control levels they require, and the resulting output. The following subsections de- scribe each of these operations in further detail. 16 or 8 DQ0 –DQ15 A0–A17 CE#f OE# WE# RESET# UB#s RY/BY# WP#/ACC SA A–1, A18–A19 LB#s CIOf CIOs CE1#s CE2s Valid Combination Order Number Package Marking DS42514 DS42514

Table 1. Device Bus Operations— Flash Word Mode, CIOf = VIH; SRAM Word Mode, CIOs = VCC

1. Other operations except for those indicated in this column are inhibited.

IL, CE1#s = VIL and CE2s = VIH at the same time.

1. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

0.3 V HH i g h - Z H i g h - Z

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Table 2. Device Bus Operations— Flash Word Mode, CIOf = VIH; SRAM Byte Mode, CIOs = VSS

1. Other operations except for those indicated in this column are inhibited.

IL, CE1#s = VIL and CE2s = VIH at the same time.

1. Don’t care or open LB#s or UB#s.
2. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

0.3 V H High-Z High-Z

Table 3. Device Bus Operations— Flash Byte Mode, CIOf = VIL; SRAM Byte Mode, CIOs = VSS

1. Other operations except for those indicated in this column are inhibited.

IL, CE1#s = VIL and CE2s = VIH at the same time.

1. Don’t care or open LB#s or UB#s.
2. If WP#/ACC = VIL , the boot sectors will be protected. If WP#/ACC = VIH the boot sectors protection will be removed.

If WP#/ACC = VACC (9V), the program time will be reduced by 40%.

1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector protection

Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

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The CIOf pin controls whether the device data I/O pins operate in the byte or word configuration. If the CIOf pin is set at logic ‘1’, the device is in word configura- tion, DQ0–DQ15 are active and controlled by CE# and OE#. If the CIOf pin is set at logic ‘0’, the device is in byte configuration, and only data I/O pins DQ0–DQ7 are active and controlled by CE# and OE#. The data I/O pins DQ8–DQ14 are tri-stated, and the DQ15 pin is used as an input for the LSB (A-1) address function. Requirements for Reading Array Data To read array data from the outputs, the system must drive the CE#f and OE# pins to V IL. CE#f is the power control and selects the device. OE# is the output con- trol and gates array data to the output pins. WE# should remain at V IH. The CIOf pin determines whether the device outputs array data in words or bytes. The internal state machine is set for reading array data upon device power-up, or after a hardware reset. This ensures that no spurious alteration of the memory content occurs during the power transition. No com- mand is necessary in this mode to obtain array data. Standard microprocessor read cycles that assert valid addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Flash Read-Only Opera- tions table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE#f to V IL, and OE# to VIH. For program operations, the CIOf pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facil- itate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 5–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7 –DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively.

state, independent of the OE# input. modes, before it is ready to read data. standby current specification. data is latched and always available to the system. automatic sleep mode current specification. the RESET# pin returns to VIH. rameters and to Figure 15 for the timing diagram. Table 4. Device Bank Division

64 Kbyte/32 Kword

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Table 5. Sector Addresses for Bottom Boot Sector Devices Table 6. SecSi Sector Addresses for Bottom Boot Devices

accessed in-system through the command register. mand Sequence section for more information. Table 7. Bottom Boot Sector/Sector Block The device is shipped with all sectors unprotected. a top-boot-configured device. sectors were last set to be protected or unprotected. tor/Sector Block Protection and Unprotection”.

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Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP#/ACC = VIL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

Note: The term “sector” in the figure applies to both sectors and sector blocks. Figure 2. In-System Sector/Sector Block Protect and Unprotect Algorithms

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SecSi (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector is 64 Kbytes in length, and uses a SecSi Sector Indicator Bit to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi Sector Indicator Bit permanently set to a “1.” The customer-lockable version is shipped with the unprotected, allowing cus- tomers to utilize the that sector in any manner they choose. The customer-lockable version has the SecSi Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents customer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with a random, se- cure ESN only In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN in the lowest addressable memory area at addresses 00000h–00007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot device the starting address of the ESN will be at the bottom of the lowest 8 Kbyte boot sector at ad- dresses F8000h –F8007h in word mode (or 1F0000h–1F000Fh in byte mode). Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array by 64 Kbytes. The SecSi Sector can be read, programmed, and erased as often as required. Note that the acceler- ated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: I Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector. I Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection”. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way. Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 12 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low V CC Write Inhibit When V CC is less than VLKO , the device does not ac- cept any write cycles. This protects data during VCC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subse- quent writes are ignored until V CC is greater than VLKO . The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO .

or WE# do not initiate a write cycle. cally reset to reading array data on power-up. interfaces for long-term compatibility. an Embedded Program or embedded erase algorithm. vice to the autoselect mode. AMD representative for copies of these documents. Table 8. CFI Query Identification String

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Table 9. System Interface String Table 10. Device Geometry Definition

Table 11. Primary Vendor-Specific Extended Query The number of sectors in Bank 2 is device dependent.

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Writing specific address and data commands or se- quences into the command register initiates device operations. Table 12 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- quence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#f, whichever happens later. All data is latched on the rising edge of WE# or CE#f, whichever hap- pens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Flash Read-Only Operations table provides the read parameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank entered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to read- ing array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 12 shows the address and data requirements. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: I A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. I A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. I A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 5–6 for valid sector addresses). The system must write the reset command to return to reading array data (or erase-suspend-read mode if the bank was previously in Erase Suspend).

Enter SecSi Sector/Exit SecSi Sector Command Sequence The system can access the SecSi Sector region by is- suing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system issues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to nor- mal operation. Table 12 shows the address and data requirements for both command sequences. See also “SecSi (Secured Silicon) Sector Flash Memory Re- gion” for further information. Note that a hardware reset (RESET#=V IL) will reset the device to reading array data. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the CIOf pin. Programming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cy- cles, followed by the program set-up command. The program address and data are written next, which in turn initiate the Embedded Program algorithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the pro- grammed cell margin. Table 12 shows the address and data requirements for the byte program command sequence. When the Embedded Program algorithm is complete, that bank then returns to reading array data and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to reading array data, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read will show that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 12 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. The first cycle must contain the bank address and the data 90h. The second cycle need only contain the data 00h. The bank then returns to the reading array data. The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 3 illustrates the algorithm for the program oper- ation. Refer to the Flash Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

24 DS42514

Figure 3. Program Operation section for information on these status bits. array data, to ensure data integrity. ings during these operations. quence and any additional addresses and commands. DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. Note:See Table 12 for program command sequence.

26 DS42514

Table 12. DS42514 Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE#f pulse, whichever happens first. erased. Address bits A19–A12 uniquely select any sector. in bypass mode, or is being erased.

1. See Tables1 through 3 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A19–A11 are don’t cares.
3. No unlock or command cycles required when bank is in read
4. The Reset command is required to return to reading array data

high (while the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The data is 80h for factory locked and 00h for not factory locked.
2. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

28 DS42514

Table 13 shows the outputs for RY/BY#. complete, DQ6 stops toggling. Table 13 shows the outputs for Toggle Bit I on DQ6. subsection on DQ2: Toggle Bit II. Figure 6. Toggle Bit Algorithm

30 DS42514

Table 13. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further
2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

32 DS42514

Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC , VCC = VCC max ±1.0 µA ILIT RESET# Input Load Current V CC = VCC max ; RESET# = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC , VCC = VCC max ±1.0 µA ILIA ACC Input Leakage Current VCC = VCC max , WP#/ACC = V ACC max 35 µA ICC1 f Flash VCC Active Read Current (Notes 1, 2) CE#f = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

1 MHz 2 4

CE#f = VIL, OE# = VIH, Word Mode ICC2 f Flash VCC Active Write Current (Notes 2, 3) CE#f = VIL, OE# = VIH, WE# = VIL 15 30 mA ICC3 fF l a s h VCC Standby Current (Note 2)VCC f = VCC max , CE#f, RESET#, WP#/ACC = V CC f ± 0.3 V 0.2 5 µA ICC4 fF l a s h VCC Reset Current (Note 2)VCC f = VCC max , RESET# = VSS ± 0.3 V, WP#/ACC = VCC f ± 0.3 V 0.2 5 µA ICC5 f Flash VCC Current Automatic Sleep Mode (Notes 2, 4) VCC f = VCC max , VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 f Flash VCC Active Read-While-Program Current (Notes 1, 2) CE#f = V IL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7 f Flash VCC Active Read-While-Erase Current (Notes 1, 2) CE#f = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8 f Flash VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE#f = VIL, OE#f = VIH 17 35 mA IACC ACC Accelerated Program Current, Word or Byte CE#f = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA ICC1 sS R A M V CC Active Current VCC s = VCC max , CE1#s = VIL, CE2s = VIH

10 MHz 45 mA

ICC2 sS R A M V CC Active Current CE1#s = 0.2 V, CE2s = VCC s – 0.2V

10 MHz 45

1 MHz 5

ICC3 sS R A M V CC Standby Current 1) CE1#s = VIH, CE2s = VIH 2) CE2s = VIL 0.3 mA ICC4 sS R A M V CC Standby Current CE1#s ≥ VCC s – 0.2V, CE2s ≥ VCC s – 0.2V 12 µA ICC5 sS R A M V CC Standby Current CE2s ≤ 0.2V 12 µA VIL Input Low Voltage –0.2 0.8 V VIH Input High Voltage 2.4 V CC + 0.2 V

Notes: 1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum ICC specifications are tested with VCC = VCC max. 3. ICC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. VHH Voltage for WP#/ACC Program Acceleration and Sector Protection/Unprotection 8.5 9.5 V VID Voltage for Sector Protection, Autoselect and Temporary Sector Unprotect 8.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC f = VCC s = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC f = VCC s = VCC min 0.85 x VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC –0.4 VLKO Flash Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V SRAM DC AND OPERATING CHARACTERISTICS Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Leakage Current V IN = VSS to VCC –1.0 1.0 µA ILO Output Leakage Current CE1#s = VIH, CE2s = VIL or OE# = VIH or WE# = VIL, VIO= VSS to VCC –1.0 1.0 µA ICC Operating Power Supply Current IIO = 0 mA, CE1#s = VIL, CE2s = WE# = VIH, VIN = VIH or VIL 3m A ICC1 s Average Operating Current Cycle time = 1 µs, 100% duty, IIO = 0 mA, CE1#s ≤ 0.2 V, CE2 ≥ VCC – 0.2 V, VIN ≤ 0.2 V or VIN ≥ VCC – 0.2 V 5m A ICC2 s Average Operating Current Cycle time = Min., IIO = 0 mA, 100% duty, CE1#s = VIL, CE2s = VIH, VIN = VIL = or VIH 45 mA VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = –1.0 mA 2.4 V ISB Standby Current (TTL) CE1#s = VIH, CE2 = VIL, Other inputs = VIH or VIL 0.3 mA ISB1 Standby Current (CMOS) CE1#s ≥ VCC – 0.2 V, CE2 ≥ VCC –

0.2 V (CE1#s controlled) or CE2 ≤

0.2 V (CE2s controlled), CIOs =

VSS or VCC , Other input = 0 ~ VCC 12 µA DC CHARACTERISTICS (Continued) CMOS Compatible Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit

34 DS42514

Figure 9. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical ICC1 vs. Frequency

36 DS42514

SRAM CE#s Timing Figure 13. Timing Diagram for Alternating Between SRAM to Flash

Description

— tCCR CE#s Recover Time — Min 0 ns E#f tCCR tCCR E1#s E2s tCCR tCCR

Flash Read-Only Operations Notes: 1. Not 100% tested. 2. See Figure 11 and Table 14 for test specifications. Parameter tAVAV tRC Read Cycle Time (Note 1) 85 ns tAVQV tACC Address to Output Delay CE#f, OE# = V IL 85 ns tELQV tCE Chip Enable to Output Delay OE# = V IL 85 ns tGLQV tOE Output Enable to Output Delay 35 ns tEHQZ tDF Chip Enable to Output High Z (Note 1) 16 ns tGHQZ tDF Output Enable to Output High Z (Note 1) 16 ns tAXQX tOH Output Hold Time From Addresses, CE#f or OE#, Whichever Occurs First 0n s tOEH Output Enable Hold Time (Note 1) Read 0 ns Toggle and Data# Polling 10 ns tOH tCE Outputs WE# Addresses CE#f OE# HIGH Z Output Valid HIGH Z Addresses Stable tRC tACC tOEH tRH tOE tRH

0 VRY/BY#

RESET# tDF Figure 14. Read Operation Timings

38 DS42514

Figure 15. Reset Timings

40 DS42514

Flash Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter 85 ns Speed Unit JEDEC Std Description Min Typ Max tAVAV tWC Write Cycle Time (Note 1) 85 ns tAVWL tAS Address Setup Time (WE# to Address) 0 ns tASO Address Setup Time to OE# or CE#f low during toggle bit polling 15 ns tWLAX tAH Address Hold Time (WE# to Address) 45 ns tAHT Address Hold Time From CE#f or OE# high during toggle bit polling 0n s tDVWH tDS Data Setup Time 35 ns tWHDX tDH Data Hold Time 0 ns tOEH OE# Hold Time Read 0 ns Toggle and Data# Polling 10 ns tOEPH Output Enable High during toggle bit polling 20 20 20 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to CE#f Low) 0 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) 0 ns tWLEL tWS WE# Setup Time (CE#f to WE#) 0 ns tELWL tCS CE#f Setup Time (WE# to CE#f) 0 ns tEHWH tWH WE# Hold Time (CE#f to WE#) 0 ns tWHEH tCH CE#f Hold Time (CE#f to WE#) 0 ns tWLWH tWP Write Pulse Width 35 ns tELEH tCP CE#f Pulse Width 35 ns tWHDL tWPH Write Pulse Width High 30 ns tSR/W Latency Between Read and Write Operations 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte 5 µs Word 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) 4µ s tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec tVCS VCC f Setup Time (Note 1) 50 µs tRB Write Recovery Time from RY/BY# 0 ns tBUSY Program/Erase Valid to RY/BY# Delay 90 ns

42 DS42514

. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”). . These waveforms are for the word mode. Figure 20. Chip/Sector Erase Operation Timings

44 DS42514

Figure 23. Toggle Bit Timings (During Embedded Algorithms) Figure 24. DQ2 vs. DQ6

Figure 25. Temporary Sector/Sector Block Unprotect Timing Diagram

46 DS42514

Figure 26. Sector/Sector Block Protect and Unprotect Timing Diagram

Alternate CE#f Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Flash Erase And Programming Performance” section for more information. Parameter 85 ns Speed JEDEC Std Description Min Typ Max Unit tAVAV tWC Write Cycle Time (Note 1) 85 ns tAVWL tAS Address Setup Time (WE# to Address) 0 ns tASO Address Setup Time to CE#f Low During Toggle Bit Polling 15 ns tELAX tAH Address Hold Time 45 ns tAHT Address Hold time from CE#f or OE# High During Toggle Bit Polling 0n s tDVEH tDS Data Setup Time 35 ns tEHDX tDH Data Hold Time 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) 0n s tWLEL tWS WE# Setup Time 0 ns tEHWH tWH WE# Hold Time 0 ns tELEH tCP CE#f Pulse Width 35 ns tEHEL tCPH CE#f Pulse Width High 35 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte 5 µs Word 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) 4µ s tWHWH2 tWHWH2 Sector Erase Operation (Note 2) 0.7 sec

48 DS42514

1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Operation Timings

Figure 28. SRAM Read Cycle— Address Controlled

50 DS42514

Figure 29. SRAM Read Cycle

1. WE# = VIH, if CIOs is low, ignore UB#s/LB#s timing.
2. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output
3. At any given temperature and voltage condition, tHZ (Max.) is less than tLZ (Min.) both for a given device and from device to device

1. WE# controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 30. SRAM Write Cycle— WE# Control

52 DS42514

1. CE1#s controlled, if CIOs is low, ignore UB#s and LB#s timing.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 31. SRAM Write Cycle— CE1#s Control

1. UB#s and LB#s controlled, CIOs must be high.
2. tCW is measured from CE1#s going low to the end of write.
3. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CE1#s or WE# going high.
4. tAS is measured from the address valid to the beginning of write.
5. A write occurs during the overlap (tWP ) of low CE#1 and low WE#. A write begins when CE1#s goes low and WE# goes low when

Figure 32. SRAM Write Cycle— UB#s and LB#s Control

54 DS42514

FLASH ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC , 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12 for further information on command definitions. 6. The device has a minimum erase and program cycle endurance of 1,000,000 cycles. FLASH LATCHUP CHARACTERISTICS Note:Includes all pins except VCC . Test conditions: VCC = 3.0 V, one pin at a time. PACKAGE PIN CAPACITANCE Note: 7.Test conditions TA = 25°C, f = 1.0 MHz. FLASH DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 27 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Word Program Time 7 210 µs Accelerated Byte/Word Program Time 4 120 µs Chip Program Time (Note 3) Byte Mode 9 27 sec Word Mode 6 18 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including OE# and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Description Test Setup Typ Max Unit C IN Input Capacitance V IN = 0 11 14 pF C OUT Output Capacitance V OUT = 0 12 16 pF C IN2 Control Pin Capacitance V IN = 0 14 16 pF C IN3 WP#/ACC Pin Capacitance V IN = 0 17 20 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

56 DS42514

FLA069 — 69-Ball Fine-Pitch Grid Array 8 x 11 mm

8.00 BSC

1.40 (max) 0.20 (min) ABCDEFGHJK 0.80

7.20 BSC

0.80 (69x) Pin A1 Corner Index Mark

11.00 BSC

0.08

0.15 M B

0.40 DATUM A DATUM B B A 0.08 0.97 1.07 C 0.20 C 0.15 C (2x) 0.15 C (2x) C 0.40 0.25 0.35

Revision A (July 10, 2000) Initial release as Preliminary Draft. Revision B (December 13, 2000) Global Deleted Preliminary status from document. Added table of contents. Command Definitions Table 12, Command Definitions: The SecSi Sector In- dicator Bit values have changed from 80h and 00h to 81h and 01h, respectively. AC Characteristics— Alternate CE#f Controlled Erase and Program Operations t WHWH1 Programming Operation: Corrected typical byte value of 9 µs to 5 µs and the typical word value of 11 µs to 7 µs. t WHWH1 Accelerated Programming Operation: Cor- rected typical value of 7 µs to 4 µs. Revision B+1 (March 7, 2001) Sector/Sector Block Protection/Unprotection Added to second paragraph: “Note that the sector un- protect algorithm unprotects all sectors in parallel. All previously protected sectors must be individually re-protected. To change data in protected sectors effi- ciently, the temporary sector unprotect function is available. See “Temporary Sector/Sector Block Unprotect”.” Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory Added to end of first paragraph: “Note that the acceler- ated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector.” Common Flash Memory Interface (CFI) Added to second paragraph: “The CFI Query mode is not accessible when the device is executing an Em- bedded Program or embedded erase algorithm.” Revision B+2 (March 15, 2001) Added “Am29DL163D Bottom Boot” to the product de- scription on the top portion of the first page. Trademarks Copyright © 2001 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.