AM29DL800B_06 AMD | Alldatasheet

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Publication Number 21519 Revision C Amendment 4 Issue Date December 4, 2006 The following document contains information on Spansion memory products. Although the document is marked with the name of the company that orig inally developed the specification, Spansion will continue to offer these products to existing customers. Continuity of Specifications There is no change to this data sheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal data sheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers Spansion continues to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local sales office for additional information about Spansion memory solutions. Am29DL800B Data Sheet Publication Number 21519 Revision C Amendment 4 Issue Date December 4, 2006

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Publication# 21519 Rev: C Amendment: 4 Issue Date: December 4, 2006 DATA SHEET Am29DL800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS ■ Simultaneous Read/Write operations — Host system can program or erase in one bank, then immediately and simultaneously read from the other bank — Zero latency between read and write operations — Read-while-erase — Read-while-program ■ Single power supply operation — Full voltage range: 2.7 to 3.6 volt read and write operations for battery-powered applications ■ Manufactured on 0.35 µm process technology — Compatible with 0.5 µm Am29DL800 device ■ High performance — Access times as fast as 70 ns ■ Low current consumption (typical values at 5 MHz) — 7 mA active read current — 21 mA active read-while-program or read-while- erase current — 17 mA active program-while-erase-suspended current — 200 nA in standby mode — 200 nA in automatic sleep mode — Standard t CE chip enable access time applies to transition from automatic sleep mode to active mode ■ Flexible sector architecture — Two 16 Kword, two 8 Kword, four 4 Kword, and fourteen 32 Kword sectors in word mode — Two 32 Kbyte, two 16 Kbyte, four 8 Kbyte, and fourteen 64 Kbyte sectors in byte mode — Any combination of sectors can be erased — Supports full chip erase ■ Unlock Bypass Program Command — Reduces overall programming time when issuing multiple program command sequences ■ Sector protection — Hardware method of locking a sector to prevent any program or erase operation within that sector — Sectors can be locke d in-system or via programming equipment — Temporary Sector Unprotect feature allows code changes in previously locked sectors ■ Top or bottom boot block configurations available ■ Embedded Algorithms — Embedded Erase algorithm automatically pre-programs and erases sectors or entire chip — Embedded Program algorithm automatically programs and verifies data at specified address ■ Minimum 1,000,000 program/erase cycles guaranteed per sector ■ Package options — 44-pin SO — 48-pin TSOP — 48-ball FBGA ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard — Superior inadvertent write protection ■ Data# Polling and Toggle Bits — Provides a software method of detecting program or erase cycle completion ■ Ready/Busy# output (RY/BY#) — Hardware method for detecting program or erase cycle completion ■ Erase Suspend/Erase Resume — Suspends or resumes erasing sectors to allow reading and programming in other sectors — No need to suspend if sector is in the other bank ■ Hardware reset pin (RESET#) — Hardware method of resetting the device to reading array data

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The Am29DL800B is an 8 Mbit, 3.0 volt-only flash memory device, organized as 524,288 words or 1,048,576 bytes. The device is offered in 44-pin SO, 48-pin TSOP , and 48-ball FBGA packages. The word- wide (x16) data appears on DQ0–DQ15; the byte-wide (x8) data appears on DQ0–DQ7. This device requires only a single 3.0 volt V CC supply to perform read, pro - gram, and erase operations. A standard EPROM programmer can also be used to program and erase the device. This device is manufactured using AMD’s 0.35 µm pro- cess technology, and offers all the features and benefits of the Am29DL800, which was manufactured using a 0.5 µm technology. The standard device offers access times of 70, 90, and 120 ns, allowing high-speed microprocessors to oper ate without wait states. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides si- multaneous operation by dividing the memory space into two banks. Bank 1 contains eight boot/parameter sectors, and Bank 2 consists of fourteen larger, code sectors of uniform size. The device can improve overall system performance by allowing a host system to pro gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. Am29DL800B Features The device offers complete compatibility with the JEDEC single-power-supply Flash command set standard. Commands are written to the command reg ister using standard microprocessor write timings. Register contents serve as input to an internal state machine that controls the erase and programming cir - cuitry. Write cycles also internally latch addresses and data needed for the programming and erase opera - tions. Reading data out of the device is similar to reading from other Flash or EPROM devices. Device programming occurs by executing the program command sequence. This initiates the Embedded Program algorithm—an internal algorithm that auto matically times the program pulse widths and verifies proper cell margin. The Unlock Bypass mode facili - tates faster programming times by requiring only two write cycles to program data instead of four. Device erasure occurs by executing the erase com - mand sequence. This initiates the Embedded Erase algorithm—an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the DQ7 (Data# Polling) and DQ6 (toggle) status bits. After a program or erase cycle has been completed, the device automatically returns to reading array data. The sector erase architecture allows memory sectors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. The hardware sector protec tion feature disables both program and erase operations in any combination of the sectors of memory. This can be achieved in-system or via programming equipment. The Erase Suspend feature enables the user to put erase on hold for any period of time to read data from, or program data to, any sector within that bank that is not selected for erasure. True background erase can thus be achieved. There is no need to suspend the erase operation if the read data is in the other bank. The hardware RESET# pin terminates any operation in progress and resets the internal state machine to reading array data. The RESET# pin may be tied to the system reset circuitry. A sys tem reset would thus also reset the device to reading array data, enabling the sys tem microprocessor to read the boot-up firmware from the Flash memory. The device offers two power-saving features. When ad- dresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode. Power consumption is greatly reduced in both these modes. AMD’s Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The device electrically erases all bits within a sector simultaneously via Fowler-Nordheim tunneling. The bytes are programmed one byte or word at a time using hot electron injection.

4 Am29DL800B 21519C4 December 4, 2006

Note: See “AC Characteristics” for full specifications. BLOCK DIAGRAM Family Part Number Am29DL800B Speed Option Full Voltage Range: VCC = 2.7 – 3.6 V 70 90 120 Max Access Time (ns) 70 90 120 CE# Access (ns) 70 90 120 OE# Access (ns) 30 35 50 VCC VSS Upper Bank AddressA0–A18 RESET# WE# CE# BYTE# DQ0–DQ15 STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ0–DQ15 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address Status Control A0–A18 A0–A18 A0–A18A0–A18 DQ0–DQ15 DQ0–DQ15 OE# BYTE#

December 4, 2006 21519C4 Am29DL800B 5 DATA SHEET CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 NC NC WE# RESET# NC NC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 Standard TSOP

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Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compro - mised if the package body is exposed to temperatures above 150°C for prolonged periods of time. A1 B1 C1 D1 E1 F1 G1 H1 A2 B2 C2 D2 E2 F2 G2 H2 A3 B3 C3 D3 E3 F3 G3 H3 A4 B4 C4 D4 E4 F4 G4 H4 A5 B5 C5 D5 E5 F5 G5 H5 A6 B6 C6 D6 E6 F6 G6 H6 DQ15/A-1 V SSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5NCNCRESET#WE# DQ11 DQ3DQ10DQ2NCA18NCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# V SSCE#A0A1A2A4A3 RY/BY# A18 A17 CE# V SS OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 RESET# WE# A10 A11 A12 A13 A14 A15 A16 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 V CC 48-Ball FBGA Top View, Balls Facing Down SO

December 4, 2006 21519C4 Am29DL800B 7 DATA SHEET PIN DESCRIPTION A0-A18 = 19 Addresses DQ0-DQ14 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable BYTE# = Selects 8-bit or 16-bit mode RESET# = Hardware Reset Pin, Active Low RY/BY# = Ready/Busy Output VCC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) VSS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A18 CE# OE# WE# RESET# BYTE# RY/BY#

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ORDERING INFORMATION

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi - nation) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be sup - ported in volume for this device. Consult the local AMD sales office to confirm availability of specific valid combinations and to check on newly released combinations. Am29DL800B T 70 E I TEMPERATURE RANGE C = Commercial (0°C to +70°C) D = Commercial (0°C to +70°C) with Pb-Free package I = Industrial (–40 °C to +85°C) F = Industrial (–40 °C to +85°C) with Pb-Free package E = Extended (–55 °C to +125°C) K = Extended (–55 °C to +125°C) with Pb-Free package PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) S = 44-Pin Small Outline Package (SO 044) WB = 48-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 6 x 9 mm package (FBB048) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29DL800B

8 Megabit (1 M x 8-Bit/512 K x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP and SO Packages AM29DL800BT70, AM29DL800BB70 EC, EI, ED, EF SC, SI, SD, SF AM29DL800BT90, AM29DL800BB90 EC, EI, EE, ED, EF , EK SC, SI, SE, SD, SF , SK AM29DL800BT120, AM29DL800BB120 Valid Combinations for FBGA Packages Order Number Package Marking AM29DL800BT70, AM29DL800BB70 WBC, WBI, WBD, WBF D800BT70V, D800BB70V C, I, D, F AM29DL800BT90, AM29DL800BB90 WBC, WBI, WBE, WBD, WBF , WBK D800BT90V, D800BB90V C, I, E, D, F, KAM29DL800BT120, AM29DL800BB120 D800BT12V, D800BB12V

register serve as inputs to the internal state machine. these operations in further detail. Table 1. Am29DL800B Device Bus Operations

  1. Addresses are A18:A0 in word mode (BYTE# = V IH), A18:A-1 in byte mode (BYTE# = VIL).
  2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector

Protection/Unprotection” section. an input for the LSB (A-1) address function. device outputs array data in words or bytes. current specification for reading array data.

0.3 V X X VCC ±

0.3 V X High-Z High-Z High-Z

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sectors of memory), the system must drive WE# and CE# to VIL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re - quired to program a word or byte, instead of four. The “Byte/Word Program Command Sequence” section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 2 and 3 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con - tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad - dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. If the system writes the autoselect command se - quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autoselect Command Sequence sections for more information. ICC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification ta- bles and timing diagrams for write operations. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 19 shows how read and write cycles may be ini- tiated for simultaneous operation with zero latency. I CC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-program and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the device, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, inde pendent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device requires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program - ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC + 30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. I CC4 in the DC Characteristics table represents the automatic sleep mode current specification.

December 4, 2006 21519C4 Am29DL800B 11 DATA SHEET RESET#: Hardware Reset Pin The RESET# pin provides a hardware method of reset- ting the device to reading array data. When the RESET# pin is driven low for at least a period of tRP, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/ write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. The operation that was interrupted should be reinitiated once the device is ready to accept another command sequence, to ensure data integrity. Current is reduced for the duration of the RESET# pulse. When RESET# is held at VSS±0.3 V, the device draws CMOS standby current (ICC4). If RESET# is held at VIL but not within VSS±0.3 V, the standby current will be greater. The RESET# pin may be tied to the system reset cir - cuitry. A system reset would thus also reset the Flash memory, enabling the system to read the boot-up firm- ware from the Flash memory. If RESET# is asserted during a program or erase oper- ation, the RY/BY# pin remains a “0” (busy) until the internal reset operation is complete, which requires a time of t READY (during Embedded Algorithms). The system can thus monitor RY/BY# to determine whether the reset operation is complete. If RESET# is asserted when a program or erase operation is not executing (RY/BY# pin is “1”), the reset operation is completed within a time of t READY (not during Embedded Algo - rithms). The system can read data t RH after the RESET# pin returns to VIH. Refer to the AC Characteristics tables for RESET# pa- rameters and to Figure 14 for the timing diagram. Output Disable Mode When the OE# input is at VIH, output from the device is disabled. The output pins are placed in the high imped- ance state.

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Table 2. Am29DL800BT Top Boot Sector Architecture Note: The address range is A18:A-1 if in byte mode (BYTE# = VIL). The address range is A18:A0 if in word mode (BYTE# = VIH).

Table 3. Am29DL800BB Bottom Boot Sector Architecture Note: The address range is A18:A-1 if in byte mode (BYTE# = VIL). The address range is A18:A0 if in word mode (BYTE# = VIH). through the command register. Table 4. In addition, when verifying sector protection, 4 shows the remaining address bits that are don’t care. sponding identifier code on DQ7-DQ0. Table 5. This method Sequence section for more information.

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Table 4. Am29DL800B Autoselect Codes (High Voltage Method) Note: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care. ID on address pin A9 and OE#. an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD representative for details. Figure 1. Temporary Sector Unprotect Operation

  1. All protected sectors unprotected.
  2. All previously protected sectors are protected once

Figure 2. In-System Sector Protect/Unprotect Algorithms

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The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 5 for com - mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not ac - cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to reading array data. Subsequent writes are ignored until V CC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to reading array data on power-up. COMMAND DEFINITIONS Writing specific address and data commands or se - quences into the command re gister initiates device operations. Table 5 defines the valid register command sequences. Writing incorrect address and data val - ues or writing them in the improper sequence resets the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the appropriate timing diagrams in the AC Characteristics section. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-suspend- read mode, after which the system can read data from any non-erase-suspended sector within the same bank. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase operation, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se - quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys tem was writing to reading array data. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the reading array data. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se - quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to reading array data. If a bank en tered the autoselect mode while in the Erase Suspend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to reading array data (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and devices codes,

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Note: See Table 5 for program command sequence. Figure 3. Program Operation information on these status bits. data, to ensure data integrity. Figure 18 section for timing diagrams. ings during these operations. quence and any additional addresses and commands.

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Table 5. Am29DL800B Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. PA = Address of the memory location to be programmed. rising edge of WE# or CE# pulse, whichever happens first. erased. Address bits A18–A12 uniquely select any sector.

  1. See Table 1 for description of bus operations.
  2. All values are in hexadecimal.
  3. Except when reading array or aut oselect data, all bus cycles
  4. Data bits DQ15–DQ8 are don’t cares for unlock and command
  5. Address bits A18–A11 are don’ t cares for unlock and command

cycles, unless bank address (BA) is required.

  1. No unlock or command cycles required when bank is in read
  2. The Reset command is required to return to reading array data

goes high (while the bank is providing status information).

  1. The fourth cycle of the autos elect command sequence is a read

manufacturer or device ID information.

  1. The data is 00h for an unprotected sector and 01h for a

section for more information.

  1. The Unlock Bypass command is required prior to the Unlock
  2. The Unlock Bypass Reset command is required to return to

reading array data when the bank is in the unlock bypass mode.

  1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. erase operation, and requires the bank address.

  1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

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RY/BY#: Ready/Busy# The RY/BY# is a dedicated, open-drain output pin that indicates whether an Embedded Algorithm is in progress or complete. The RY/BY# status is valid after the rising edge of the final WE# pulse in the command sequence. Since RY/BY# is an open-drain output, sev eral RY/BY# pins can be tied together in parallel with a pull-up resistor to V CC. If the output is low (Busy), the device is actively erasing or programming. (This includes programming in the Erase Suspend mode.) If the output is high (Ready), the device is ready to read array data, is in the standby mode, or one of the banks is in the erase-suspend-read mode. Table 6 shows the outputs for RY/BY#. DQ6: Toggle Bit I Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address within the programming or erasing bank, and is valid after the rising edge of the final WE# pulse in the command se quence (prior to the program or erase operation), and during the sector erase time-out. During an Embedded Program or Erase algorithm op - eration, successive read cycles to any address within the programming or erasing bank cause DQ6 to toggle. The system may use either OE# or CE# to control the read cycles. When the operation is complete, DQ6 stops toggling. After an erase command sequence is written, if all sec- tors selected for erasing are protected, DQ6 toggles for approximately 100 µs, then returns to reading array data. If not all selected sectors are protected, the Em bedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. The system can use DQ6 and DQ2 together to deter - mine whether a sector is acti vely erasing or is erase- suspended. When a bank is actively erasing (that is, the Embedded Erase algorithm is in progress), DQ6 toggles. When that bank enters the Erase Suspend mode, DQ6 stops toggling. However, the system must also use DQ2 to determine which sectors are erasing or erase-suspended. Alternatively, the system can use DQ7 (see the subsection on DQ7: Data# Polling). If a program address falls within a protected sector, DQ6 toggles for approximately 1 µs after the program command sequence is written, then returns to reading array data. DQ6 also toggles during the erase-suspend-program mode, and stops toggling once the Embedded Pro - gram algorithm is complete. Table 6 shows the outputs for Toggle Bit I on DQ6. Fig- ure 6 shows the toggle bit algorithm. Figure 21 in the “AC Characteristics” section shows the toggle bit timing diagrams. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. See also the subsec - tion on DQ2: Toggle Bit II. DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era - sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus - pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era - sure. Thus, both status bits are required for sector and mode information. Refer to Table 6 to compare outputs for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 21 shows the toggle bit timing diagram. Figure 22 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When - ever the system initially be gins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has com pleted the program or erase operation. The system can read array data on DQ7–DQ0 on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys - tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation su ccessfully, and the system must write the reset command to return to reading array data.

termine the status of the operation (top of Figure 6). Figure 6. Toggle Bit Algorithm exceeded, DQ5 produces a “1”. the erase-suspend-program mode). device will accept additional sector erase commands. and following each subsequent sector erase command. mand might not have been accepted.

24 Am29DL800B 21519C4 December 4, 2006

Table 6. Write Operation Status

  1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

  1. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.
  2. When reading write operation status bits, the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

26 Am29DL800B 21519C4 December 4, 2006

Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for t ACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 7 12

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode (Notes 2, 3) CE# = VIL, OE# = VIH, WE# = VIL 15 30 mA ICC3 VCC Standby Current (Note 2) OE# = VIL; CE#, RESET# = VCC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = VSS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While- Program Current (Notes 1, 2, 5) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2, 5) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8 VCC Active Program-While- Erase-Suspended Current (Notes 2, 5) CE# = VIL, OE# = VIH 17 35 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x VCC VCC + 0.3 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V VOH2 IOH = –100 µA, VCC = VCC min VCC–0.4 V VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

28 Am29DL800B 21519C4 December 4, 2006

Table 7. Test Specifications Figure 11. Test Setup Figure 12. Input Waveforms and Measurement Levels

  1. See Figure 11 and Table 7 for test specifications.

0 VRY/BY#

Figure 13. Read Operation Timings

30 Am29DL800B 21519C4 December 4, 2006

Figure 14. Reset Timings

32 Am29DL800B 21519C4 December 4, 2006

Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter 70 90 120JEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 45 45 50 ns tWLAX tAH Address Hold Time Min 45 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 20 25 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Zero Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

34 Am29DL800B 21519C4 December 4, 2006

Figure 19. Back-to-Back Read/Write Cycle Timings Figure 20. Data# Polling Timings (During Embedded Algorithms)

36 Am29DL800B 21519C4 December 4, 2006

0 V or 3 V

Figure 23. Temporary Sector Unprotect Timing Diagram Figure 24. Sector Protect/Unprotect Timing Diagram

December 4, 2006 21519C4 Am29DL800B 37 DATA SHEET AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Notes: 1. Not 100% tested. 2. See the “Erase and Programming Performance” section for more information. Parameter 70 90 120JEDEC Std Description Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 50 ns tDVEH tDS Data Setup Time Min 35 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 35 35 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 9 µs Word Typ 11 tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

38 Am29DL800B 21519C4 December 4, 2006

  1. Figure indicates last two bus cycles of a program or erase operation.
  2. PA = program address, SA = sector address, PD = program data, DQ7# = complement of the data written to the device,

DOUT = data written to the device.

  1. Waveforms are for the word mode.

Figure 25. Alternate CE# Controlled Erase/Program Operation Timings

December 4, 2006 21519C4 Am29DL800B 39 DATA SHEET ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, V CC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 5 for further information on command definitions. 6. The device has a guaranteed minimum erase and program cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 14 sec Byte Program Time 9 300 µs Excludes system level overhead (Note 5) Word Program Time 11 360 µs Chip Program Time (Note 3) Byte Mode 9 27 sec Word Mode 5.8 17 Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance VIN = 0 6 7.5 pF COUT Output Capacitance VOUT = 0 8.5 12 pF CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF Parameter Description Test Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Ye a r s 125°C 20 Ye a r s

40 Am29DL800B 21519C4 December 4, 2006

TS 048—48-Pin Standard TSOP * For reference only. BSC is an ANSI standard for Basic Space Centering Dwg rev AA; 10/99

December 4, 2006 21519C4 Am29DL800B 41 DATA SHEET PHYSICAL DIMENSIONS (continued) FBB048 —48-Ball Fine-Pitch Ball Grid Array (FBGA), 6 x 9 mm package Dwg rev AF; 10/99

42 Am29DL800B 21519C4 December 4, 2006

PHYSICAL DIMENSIONS (continued) SO 044—44-Pin Small Outline Dwg rev AC; 10/99

44 Am29DL800B 21519C4 December 4, 2006

Revision C+2 (June 7, 2000) Added Pb-Free OPNs. Revision C+3 (January 5, 2006) Global Removed TSR048 48-pin Reverse TSOP option. Revision C4 (December 4, 2006) Erase and Program Operations table Changed tBUSY to a maximum specification. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products Trademarks Copyright ©2002-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trade- marks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies. Copyright © 2006 Spansion Inc. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, HD-SIM, and combinations thereof are trademarks of Spansion Inc. Other names are for informational purposes only and may be trademarks of their respective owners.