D640D12VE

AM29DL640D_05 AMD | Alldatasheet

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Publication Number 23695 Revision C Amendment 3 Issue Date December 13, 2005 Am29DL640D Data Sheet July 2003 The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that originally developed the specification, these produc ts will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropri- ate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing pa rt numbers beginning wi th "Am" and "MBM". To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion mem- ory solutions. This product has been retired and is not available for designs. For new and current designs involving TSOP packages, S29JL064H supersedes Am29DL640D and is the factory- recommended migration path. Please refer to the S29JL064H datasheet for specifications and ordering informa- tion. For new and current designs involving Fine-pitch BG A (FBGA) packages, S29PL064J supersedes Am29DL640D and is the factory-recommended migration path. Please refer to the S29PL064J Datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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Publication# 23695 Rev: C Amendment/3 Issue Date: December 13, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. Am29DL640D

64 Megabit (8 M x 8-Bit/4 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES „ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in another bank. — Zero latency between read and write operations „ Flexible BankTM architecture — Read may occur in any of the three banks not being written or erased. — Four banks may be grouped by customer to achieve desired bank divisions. „ Boot Sectors — Top and bottom boot sect ors in the same device — Any combination of sectors can be erased „ Manufactured on 0.23 µm process technology „ Secured Silicon Sector: Extra 256 Byte sector — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read or programmed just like other sectors. Once locked, data cannot be changed „ Zero Power Operation — Sophisticated power mana gement circuits reduce power consumed during inactive periods to nearly zero. „ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PACKAGE OPTIONS „ 63-ball Fine Pitch BGA ■ 48-pin TSOP PERFORMANCE CHARACTERISTICS „ High performance — Access time as fast as 90 ns — Program time: 4 µs/word typical utilizing Accelerate function „ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode „ Minimum 1 million erase cycles guaranteed per sector „ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES „ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations „ Supports Common Flash Memory Interface (CFI) „ Program/Erase Suspend/Erase Resume — Suspends program/erase operations to allow programming/erasing in same bank „ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles „ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES „ Ready/Busy# output (RY/BY#) — Hardware method for detec ting program or erase cycle completion „ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode „ WP#/ACC input pin — Write protect (WP#) functi on protects sectors 0, 1, 140, and 141, regardless of sector protect status — Acceleration (ACC) function accelerates program timing „ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotec t allows changing data in protected sectors in-system This product has been retired and is not available for designs. For new and current designs involving TSOP packages, S29JL064H supersedes Am29DL640D and is the factory-recommended migration path. Please refer to the S29JL064H datasheet for specifications and ordering information. For new and current designs involving Fine-pitch BGA (FBGA) packages, S29PL064J supersedes Am29DL640D and is the factory-recomm ended migration path. Please refer to the S29PL064J Datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

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The Am29DL640D is a 64 megabit, 3.0 volt-only flash memory device, organized as 4,194,304 words of 16 bits each or 8,388,608 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The device is available with an access time of 90 or 120 ns and is offered in 48-pin TSOP and 63-ball Fine-Pitch BGA. Standard control pins—chip enable (CE#), write enable (WE#), and output enable (OE#)—control normal read and write operations, and avoid bus contention issues. The device requires only a single 3.0 volt power sup- ply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into four banks, two 8 Mb banks with small and large sectors, and two 24 Mb banks of large sectors. Sector addresses are fixed, system software can be used to form user-defined bank groups. During an Erase/Program operation, any of the three non-busy banks may be read from. Note that only two banks can operate simultaneously. The device can im- prove overall system performance by allowing a host system to program or erase in one bank, then immediately and simultaneously read from the other bank, with zero latency. This releases the system from waiting for the completion of program or erase operations. The Am29DL640D can be organized as both a top and bottom boot sector configuration. Am29DL640D Features The Secured Silicon Sector is an extra 256 byte sec- tor capable of being permanently locked by AMD or customers. The Secured Silicon Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, cus- tomer lockable parts can never be used to replace a factory locked part. Factory locked parts provide several options. The Se- cured Silicon Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (programmed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the Se- cured Silicon Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS also allows the system software to be simpli fied, as it performs all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers comple te compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Bank Megabits Sector Sizes Bank 1 8 Mb Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword Bank 2 24 Mb Forty-eight 64 Kbyte/32 Kword Bank 3 24 Mb Forty-eight 64 Kbyte/32 Kword Bank 4 8 Mb Eight 8 Kbyte/4 Kword, Fifteen 64 Kbyte/32 Kword

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Speed Option Standard Voltage Range: V CC = 2.7–3.6 V 90 120 Max Access Time (ns), tACC 90 120 CE# Access (ns), tCE 90 120 OE# Access (ns), tOE 35 50 VCC VSS Bank 1 Address Bank 2 Address A20–A0 RESET# WE# CE# BYTE# DQ0–DQ15 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Bank 1 X-Decoder OE# BYTE# DQ15–DQ0 Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 DQ15–DQ0 Mux Mux Mux Bank 2 X-Decoder Y-gate Bank 3 X-Decoder Bank 4 X-Decoder Y-gate Bank 3 Address Bank 4 Address

December 13, 2005 Am29DL640D 5 CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7A7 B7 A8 B8 A1 B1 E7 F7 G7 H7 J7 K7 L7 NC* NC*NC* NC* NC* NC* NC* NC* NC* NC* NC*NC NC NC NC DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19A21RESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 * Balls are shorted together via the substrate but not connected to the die. 63-Ball Fine-Pitch BGA (FBGA) Top View, Balls Facing Down

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A0–A21 = 22 Addresses DQ0–DQ14 = 15 Data Inputs/Outputs (x16-only devices) DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/ Acceleration Pin RESET# = Hardware Reset Pin, Active Low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy Output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply tolerances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A21 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

December 13, 2005 Am29DL640D 7

ORDERING INFORMATION

AMD standard products are available in several packages and o perating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. Am29DL640D 90 E I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) F = Industrial for Pb-free Package (–40°C to +85°C) K = Extended for Pb-free Package (–55°C to +125°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) WH = 63-Ball Fine-Pitch Ball Grid Array, 0.80 mm pitch, 12 x 11 mm package (FBE063) SPEED OPTION See Product Selector Guide and Valid Combinations DEVICE NUMBER/DESCRIPTION Am29DL640D

64 Megabit (8 M x 8-Bit/4 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages Am29DL640D90 EI, EF Am29DL640D120 EI, EE, EF , EK Valid Combinations for BGA Packages Order Number Package Marking Am29DL640D90 WHF , WHI D640D90V I, F Am29DL640D120 WHI, WHE, WHF , WHK D640D12V I, E, F, K

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each of these operations in further detail. Table 1. Am29DL640D Device Bus Operations

1. Addresses are A21:A0 in word mode (BYTE# = V IH), A21:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the Sector/Sector

Block Protection and Unprotection section.

1. If WP#/ACC = V IL, sectors 0, 1, 140, and 141 remain protected. If WP#/ACC = VIH, protection on sectors 0, 1, 140, and 141

and Unprotection. If WP#/ACC = VHH, all sectors are unprotected. used as an input for the LSB (A-1) address function. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H X High-Z High-Z High-Z

December 13, 2005 Am29DL640D 9 addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. Refer to the AC Read-Only Operations table for timing specifications and to Figure 14 for the timing diagram. I CC1 in the DC Characteristics table represents the ac- tive current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to Word/Byte Configuration for more information. The device features an Unlock Bypass mode to facili- tate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The Byte/Word Program Command Sequence section has details on programming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Table 2 indicates the address space that each sector occupies. The device address space is divided into four banks: Banks 1 and 4 con- tains the boot/parameter sectors, and Banks 2 and 3 contains the larger, code sectors of uniform size. A “bank address” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the ad- dress bits required to uniquely select a sector. The Command Definitions section has details on erasing a sector or the entire chip, or suspending/resuming the erase operation. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that VHH must not be asserted on WP#/ACC for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. See “Write Protect (WP#)” on page 16 for related information. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ15–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 21 shows how read and write cycles may be initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device is in the standby mode, but the standby current is greater. The device requires stan- dard access time (t CE ) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. ICC3 in the DC Characteristics table represents the standby current specification.

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data is latched and always available to the system. automatic sleep mode current specification. rameters and to Figure 15 for the timing diagram. Table 2. Am29DL640D Sector Architecture

Table 2. Am29DL640D Sector Architecture (Continued)

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Note: The address range is A21:A-1 in byte mode (BYTE#=VIL) or A21:A0 in word mode (BYTE#=VIH). Table 3. Bank Address Table 4. Secured Silicon Sector Addresses accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 5. In addition, when verifying sector protection, shows the remaining address bits that are don’t care.

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mand Sequence section for more information. Table 5. Am29DL640D Autoselect Codes, (High Voltage Method) Legend: L = Logic Low = VIL, H = Logic High = VIH, BA = Bank Address, SA = Sector Address, X = Don’t care.

Table 6. Am29DL640D Boot Sector/Sector Block available. See “Temporary Sector Unprotect”.

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equipment requires V ID on address pin A9 and OE#. written for earlier 3.0 volt-only AMD flash devices. The device is shipped with all sectors unprotected. AMD representative for details. one of two provided by the WP#/ACC pin. tor/Sector Block Protection and Unprotection. Table 7. WP#/ACC Modes Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP#/ACC = V IL,

sectors 0, 1, 140, and 141 remain protected).

1. All previously protected sectors are protected once

Figure 2. In-System Sector Protect/Unprotect Algorithms

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The Secured Silicon Sector feature provides a Flash memory region that enables permanent part identifica- tion through an Electronic Serial Number (ESN). The Secured Silicon Sector is 256 bytes in length, and uses a Secured Silicon Sector Indicator Bit (DQ7) to indicate whether or not the Secured Silicon Sector is locked when shipped from the factory. This bit is per- manently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. AMD offers the device with the Secured Silicon Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the Secured Silicon Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the Secured Silicon Sector unprotected, allowing customers to uti- lize the that sector in any manner they choose. The customer-lockable version has the Secured Silicon Sector Indicator Bit permanently set to a “0.” Thus, the Secured Silicon Sector Indicator Bit prevents cus- tomer-lockable devices from being used to replace devices that are factory locked. Note that the ACC function and unlock bypass modes are not available when the Secured Silicon Sector is enabled. The system accesses the Secured Silicon Sector Se- cure through a command sequence (see Enter/Exit Secured Silicon Sector Command Sequence ). After the system has written the Enter Secured Silicon Sec- tor command sequence, it may read the Secured Silicon Sector by using the addresses normally occu- pied by the boot sectors. This mode of operation continues until the system issues the Exit Secured Sil- icon Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to sending com- mands to the first 256 bytes of Sector 0. Note that the ACC function and unlock bypass modes are not avail- able when the Secured Silicon Sector is enabled. Factory Locked: Secured Silicon Sector Programmed and Protected At the Factory In a factory locked device, the Secured Silicon Sector is protected when the device is shipped from the fac- tory. The Secured Silicon Sector cannot be modified in any way. The device is preprogrammed with both a ran- dom number and a secure ESN. The 8-word random number will at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). The se- cure ESN is programmed in the next 8 words at addresses 000008h–00000Fh (or 000010h–000020h in byte mode). The device is available preprogrammed with one of the following: „ A random, secure ESN only „ Customer code through the ExpressFlash service „ Both a random, secure ESN and customer code through the ExpressFlash service. Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the Secured Silicon Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: Secured Silicon Sector NOT Programmed or Protected At the Factory If the security feature is not required, the Secured Sili- con Sector can be treated as an additional Flash memory space. The Secured Silicon Sector can be read any number of times, but can be programmed and locked only once. Note that the accelerated pro- gramming (ACC) and unlock bypass functions are not available when programming the Secured Silicon Sector. The Secured Silicon Sector area can be protected using one of the following procedures: „ Write the three-cycle Enter Secured Silicon Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, except that RESET# may be at either V IH or VID. This allows in-system protection of the Se- cured Silicon Sector Region without raising any de- vice pin to a high voltage. Note that this method is only applicable to the Secured Silicon Sector. „ To verify the protect/unprotect status of the Secured Silicon Sector, follow the algorithm shown in Figure 3. Once the Secured Silicon Sector is locked and veri- fied, the system must write the Exit Secured Silicon Sector Region command sequence to return to read- ing and writing the remainder of the array. The Secured Silicon Sector lock must be used with caution since, once locked, there is no procedure available for unlocking the Secured Silicon Sector area and none of the bits in the Secured Silicon Sector memory space can be modified in any way.

Figure 3. Secured Silicon Sector Protect Verify and power-down transitions, or from system noise. or WE# do not initiate a write cycle. cally reset to the read mode on power-up. interfaces for long-term compatibility. device to reading array data.

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Table 8. CFI Query Identification String Table 9. System Interface String

Table 10. Device Geometry Definition

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Table 11. Primary Vendor-Specific Extended Query Note: The number of sectors in Bank 2 is device dependent.

December 13, 2005 Am29DL640D 23 COMMAND DEFINITIONS Writing specific address and data commands or se- quences into the command register initiates device operations. Table 12 defines the valid register com- mand sequences. Writing incorrect address and data values or writing them in the improper se- quence may place the device in an unknown state. A reset command is then required to return the device to reading array data. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. Refer to the AC Characteristics section for timing diagrams. Reading Array Data The device is automatically set to reading array data after device power-up. No commands are required to retrieve data. Each bank is ready to read array data after completing an Embedded Program or Embedded Erase algorithm. After the device accepts an Erase Suspend command, the corresponding bank enters the erase-sus- pend-read mode, after which the system can read data from any non-erase-suspended sector within the same bank. The system can read array data using the standard read timing, except that if it reads at an ad- dress within erase-suspended sectors, the device outputs status data. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same excep- tion. See the Erase Suspend/Erase Resume Commands section for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 14 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read any number of autoselect codes without reinitiating the command sequence. Table 12 shows the address and data requirements. To determine sector protection information, the system must write to the appropriate bank address (BA) and sector address (SA). Table 2 shows the address range and bank number associated with each sector. The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter/Exit Secured Silicon Sector Command Sequence The Secured Silicon Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the Se- cured Silicon Sector region by issuing the three-cycle

24 Am29DL640D December 13, 2005

Enter Secured Silicon Sector command sequence. The device continues to access the Secured Silicon Sector region until the system issues the four-cycle Exit Secured Silicon Sector command sequence. The Exit Secured Silicon Sector command sequence re- turns the device to normal operation. The Secured Silicon Sector is not accessible when the device is ex- ecuting an Embedded Program or embedded Erase algorithm. Table 12 shows the address and data re- quirements for both command sequences. See also Secured Silicon Sector Flash Memory Region for fur- ther information. Note that the ACC function and unlock bypass modes are not available when the Se- cured Silicon Sector is enabled. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algo- rithm. The system is not required to provide further controls or timings. The device automatically provides internally generated program pulses and verifies the programmed cell margin. Table 12 shows the address and data requirements for the byte program command sequence. Note that the Secured Silicon Sector, au- toselect, and CFI functions are unavailable when a program operation in is progress. When the Embedded Program algorithm is complete, that bank then returns to the read mode and ad- dresses are no longer latched. The system can determine the status of the program operation by using DQ7, DQ6, or RY/BY#. Refer to the Write Oper- ation Status section for information on these status bits. Any commands written to the device during the Em- bedded Program Algorithm are ignored. Note that a hardware reset immediately terminates the program operation. The program command sequence should be reinitiated once that bank has returned to the read mode, to ensure data integrity. Programming is allowed in any sequence and across sector boundaries. A bit cannot be programmed from “0” back to a “1.” Attempting to do so may cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate the operation was success- ful. However, a succeeding read shows that the data is still “0.” Only erase operations can convert a “0” to a “1.” Unlock Bypass Command Sequence The unlock bypass feature allows the system to pro- gram bytes or words to a bank faster than using the standard program command sequence. The unlock bypass command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle containing the unlock bypass command, 20h. That bank then enters the unlock bypass mode. A two-cycle unlock bypass program command sequence is all that is required to program in this mode. The first cycle in this sequence contains the unlock bypass pro- gram command, A0h; the second cycle contains the program address and data. Additional data is pro- grammed in the same manner. This mode dispenses with the initial two unlock cycles required in the stan- dard program command sequence, resulting in faster total programming time. Table 12 shows the require- ments for the command sequence. During the unlock bypass mode, only the Unlock By- pass Program and Unlock Bypass Reset commands are valid. To exit the unlock bypass mode, the system must issue the two-cycle unlock bypass reset com- mand sequence. (See Table 12). The device offers accelerated program operations through the WP#/ACC pin. When the system asserts V HH on the WP#/ACC pin, the device automatically en- ters the Unlock Bypass mode. The system may then write the two-cycle Unlock Bypass program command sequence. The device uses the higher voltage on the WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not be at V HH any operation other than accelerated programming, or device dam- age may result. In addition, the WP#/ACC pin must not be left floating or unconnected; inconsistent behavior of the device may result. Figure 4 illustrates the algorithm for the program oper- ation. Refer to the Erase and Program Operations table in the AC Characteristics section for parameters, and Figure 18 for timing diagrams.

26 Am29DL640D December 13, 2005

reading array data, to ensure data integrity. ters, and Figure 20 section for timing diagrams. period during the sector erase command sequence. imum of 20 µs to suspend the erase operation. if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard Byte Program operation. Command Sequence sections for details. pended bank is required when writing this command. Further writes of the Resume command are ignored. the chip has resumed erasing. Figure 5. Erase Operation

1. See Table 12 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 12. Am29DL640D Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. device. Refer to Table 2 for information on sector addresses. in bypass mode, or is being erased.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A21–A11 (x16-only devices)

unlock and command cycles, unless SA or PA is required.

1. No unlock or command cycles required when bank is reading
2. The Reset command is required to return to the read mode (or to

the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The device ID must be read across the fourth, fifth, and sixth
2. The data is 80h for factory locked and 00h for not factory locked.
3. The data is 00h for an unprotected sector/sector block and 01h for

a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

28 Am29DL640D December 13, 2005

progress or has been completed. WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 13 shows the outputs for Data# Polling on DQ7. Figure 6. Data# Polling Algorithm

1. VA = Valid address for prog ramming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

30 Am29DL640D December 13, 2005

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 13 to compare out- puts for DQ2 and DQ6. Figure 7 shows the toggle bit algorithm in flowchart form, and the section DQ2: Toggle Bit II explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 23 shows the toggle bit timing diagram. Figure 24 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 7 for the following discussion. When- ever the system initially begins reading toggle bit status, it must read DQ15–DQ0 (or DQ7–DQ0 for x8-only device) at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the toggle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the following read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it re- turns to determine the status of the operation (top of Figure 7). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device accepts additional sector erase commands. To ensure the command has been accepted, the system software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3 is high on the second status check, the last com- mand might not have been accepted. Table 13 shows the status of DQ3 relative to the other status bits.

Table 13. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status info rmation. Refer to the appropriate subsection for further
2. When reading write operation status bits , the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

32 Am29DL640D December 13, 2005

1. Minimum DC voltage on input or I/O pins is –0.5 V.

overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V.

1. Minimum DC input voltage on pins A9, OE#, RESET#,

overshoot to +12.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. Figure 8. Maximum Negative Figure 9. Maximum Positive Overshoot Waveform functionality of the device is guaranteed.

December 13, 2005 Am29DL640D 33 DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description (Notes) Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode ICC2 VCC Active Write Current (2, 3)C E # = V IL, OE# = VIH, WE# = VIL 15 30 mA ICC3 VCC Standby Current (2) CE#, RESET# = V CC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (2) RESET# = V SS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7 VCC Active Read-While-Erase Current (1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8 VCC Active Program-While-Erase-Suspended Current (2, 5) CE# = VIL, OE# = VIH 17 35 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 11.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC –0 . 4 VLKO Low VCC Lock-Out Voltage (5)2 . 3 2 . 5 V

34 Am29DL640D December 13, 2005

Figure 10. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 11. Typical I CC1 vs. Frequency

36 Am29DL640D December 13, 2005

1. See Figure 12 and Table 14 for test specifications
2. Measurements performed by placing a 50 Ω termination on the data pin with a bias of VCC/2. The time from OE# high to the

0 VRY/BY#

Figure 14. Read Operation Timings

Figure 15. Reset Timings

38 Am29DL640D December 13, 2005

Figure 16. BYTE# Timings for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 17. BYTE# Timings for Write Operations

December 13, 2005 Am29DL640D 39 AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the Erase And Programming Performance section for more information. Parameter Description (Notes) Speed Options JEDEC Std 90 120 Unit tAVAV tWC Write Cycle Time (1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 ns tWLAX tAH Address Hold Time Min 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (2) Byte Typ 8.6 µs Word Typ 12.6 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (2)T y p 4 µ s tWHWH2 tWHWH2 Sector Erase Operation (2)T y p 0 . 7 s e c tVCS VCC Setup Time (1)M i n 5 0 µ s tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Max 90 ns

40 Am29DL640D December 13, 2005

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 18. Program Operation Timings Figure 19. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see Write Operation Status.)
2. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

42 Am29DL640D December 13, 2005

Figure 21. Back-to-back Read/Write Cycle Timings Figure 22. Data# Polling Timings (During Embedded Algorithms)

44 Am29DL640D December 13, 2005

Figure 25. Temporary Sector Unprotect Timing Diagram

Figure 26. Sector/Sector Block Protect and

46 Am29DL640D December 13, 2005

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the Erase And Programming Performance section for more information. Parameter Description (Notes) Speed Options JEDEC Std 90 120 Unit tAVAV tWC Write Cycle Time (1) Min 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 50 ns tDVEH tDS Data Setup Time Min 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (2) Byte Typ 8.6 µs Word Typ 12.6 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (2)T y p 4 µ s tWHWH2 tWHWH2 Sector Erase Operation (2) Typ 0.7 sec

1. Figure indicates last two bus cycl es of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

48 Am29DL640D December 13, 2005

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 12 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 100 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 4 120 µs Word Program Time 7 210 µs Chip Program Time (Note 3) Byte Mode 42 126 sec Word Mode 28 84 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance V OUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C1 0 Y e a r s 125°C2 0 Y e a r s

December 13, 2005 Am29DL640D 49 PHYSICAL DIMENSIONS FBE063—63-Ball Fine-Pitch Ball Grid Array (FBGA) 12 x 11 mm package xFBE 063 Dwg rev AF; 10/99

50 Am29DL640D December 13, 2005

TS 048—48-Pin Standard TSOP Dwg rev AA; 10/99

December 13, 2005 Am29DL640D 51 REVISION SUMMARY Revision A (March 5, 2001) Initial release. Revision A+1 (March 9, 2001) Corrected FBGA package marking to include “V” des- ignation. Deleted “0” from 120 ns package marking. Revision B (August 10, 2001) Global Replaced the phrase “outermost 8 Kb sectors” with the actual sector names (sectors 0, 1, 140, and 141) for greater clarity. Changed data sheet status from “Ad- vance Information” to “Preliminary”. Block Diagram Corrected address bus callout from A20 to A21. Factory Locked: SecSi Sector Programmed and Protected At the Factory Deleted references to top and bottom boot devices. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory Deleted reference to 64 Kbyte SecSi Sector. Table 4, SecSi™ Sector Addresses Added table. Table 5, Am29DL640D Autoselect Codes, (High Voltage Method) Deleted rows for byte mode. Table 7, WP#/ACC Modes Added table for clarity. Revision B+1 (August 30, 2001) Autoselect Command Sequence Deleted explanatory bullets and included references to the appropriate tables for autoselect functions. Table 12, Am29DL640D Command Definitions Added second and third read cycle information for the autoselect device ID command sequence. AC Characteristics: Erase and Program Operations Changed t BUSY specification from minimum to maximum. Revision B+2 (October 11, 2001) Connection Diagrams, Ordering Information, Physical Dimensions Added 64-ball Fortified BGA package information. Revision B+3 (November 5, 2001) Global Removed Preliminary designation from document. Corrected BGA part numbers and markings. Distinctive Characteristics Corrected accelerated programming specification. Device Bus Operations Added Table 3, Bank Address. Table 10, Device Geometry Definition Added definition for address 4Fh. Revision B+4 (April 15, 2002) Added P designator to package marking for Fortified BGA package. Revision B+5 (August 19, 2002) Distinctive Characteristics Corrected erase cycles.b Connection Diagram Changed all references to RFU to NC. Modified the last sentence in the first paragraph.

52 Am29DL640D December 13, 2005

Revision C (January 10, 2003) Package Options Removed the 64-ball Fortified BGA package and pinout. Sector/Sector Block Protection and Unprotection Change wording of first sentence of third paragraph. Customer Lockable: SecSi Sector NOT Programmed or Protected at the factory. Added second bullet, SecSi sector-protect verify text and figure 3. SecSi Sector Flash Memory Region, and Enter SecSi Sector/Exit SecSi Sector Command Sequence Noted that the ACC function and unlock bypass modes are not available when the SecSi sector is enabled. Byte/Word Program Command Sequence, Sector Erase Command Sequence, and Chip Erase Com- mand Sequence Noted that the SecSi Sector, autoselect, and CFI functions are unavailable when a program or erase operation is in progress. Common Flash Memory Interface (CFI) Changed CFI website address. Revision C+1 (October 7, 2004) Cover Sheet and Title Page Added notation to superseding documents. Revision C+2 (January 11, 2005) Ordering Information and Valid Combinations Added Pb-free package options. Updated cross-references. Changed SecSi™ to Selected Silicon Removed Sales Office Listing Revision C+3 (December 13, 2005) This product has been retired and is not available for designs. Availability of this document is retained for reference and historical purposes only. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2001 – 2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.