D324DB12VE

AM29DL322D_05 AMD | Alldatasheet

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The following document specifies Spansion memory products that are now offered by both Advanced Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig- inally developed the specification, these products will be offered to customers of both AMD and Fujitsu. Continuity of Specifications There is no change to this datasheet as a result of offering the device as a Spansion product. Any changes that have been made are the result of normal datasheet improvement and are noted in the document revision summary, where supported. Future routine revisions will occur when appropriate, and changes will be noted in a revision summary. Continuity of Ordering Part Numbers AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order these products, please use only the Ordering Part Numbers listed in this document. For More Information Please contact your local AMD or Fujitsu sales office for additional information about Spansion memory solutions. Am29DL322D/323D/324D Data Sheet Publication Number 21534 Revision D Amendment +8 Issue Date December 13, 2005 This product has been retired and is not available for designs. For new and current designs involving TSOP pack- ages, S29JL032H supersedes Am29DL32xD and is the factory-recommended migration path. Please refer to the S29JL032H Datasheet for specifications and ordering information. For new and current designs involving Fine-pitch BG A (FBGA) packages, S29PL032J supersedes Am29DL32xD and is the factory-recommended migration path. Please refer to the S29PL032J Datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

Publication# 21534 Rev: D Amendment/+8 Issue Date: December 13, 2005 Refer to AMD’s Website (www.amd.com) for the latest information. Am29DL322D/323D/324D

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Operation Flash Memory DISTINCTIVE CHARACTERISTICS ARCHITECTURAL ADVANTAGES ■ Simultaneous Read/Write operations — Data can be continuously read from one bank while executing erase/program functions in other bank. — Zero latency between read and write operations ■ Multiple bank architectures — Three devices available with different bank sizes (refer to Table 3) ■ SecSiTM (Secured Silicon) Sector — Current version of device has 64 Kbytes; future versions will have 256 bytes — Factory locked and identifiable: 16 bytes available for secure, random factory Electronic Serial Number; verifiable as factory locked through autoselect function. ExpressFlash option allows entire sector to be available for factory-secured data — Customer lockable: Can be read, programmed, or erased just like other sectors. Once locked, data cannot be changed ■ Zero Power Operation — Sophisticated power mana gement circuits reduce power consumed during inactive periods to nearly zero. ■ Package options —6 3 - b a l l F B G A — 48-pin TSOP ■ Top or bottom boot block ■ Manufactured on 0.23 µm process technology ■ Compatible with JEDEC standards — Pinout and software compatible with single-power-supply flash standard PERFORMANCE CHARACTERISTICS ■ High performance — Access time as fast 70 ns — Program time: 7 µs/word typical utilizing Accelerate function ■ Ultra low power consumption (typical values) — 2 mA active read current at 1 MHz — 10 mA active read current at 5 MHz — 200 nA in standby or automatic sleep mode ■ Minimum 1 million write cycles guaranteed per sector ■ 20 year data retention at 125°C — Reliable operation for the life of the system SOFTWARE FEATURES ■ Data Management Software (DMS) — AMD-supplied software manages data programming, enabling EEPROM emulation — Eases historical sector erase flash limitations ■ Supports Common Flash Memory Interface (CFI) ■ Erase Suspend/Erase Resume — Suspends erase operations to allow programming in same bank ■ Data# Polling and Toggle Bits — Provides a software method of detecting the status of program or erase cycles ■ Unlock Bypass Program command — Reduces overall programming time when issuing multiple program command sequences HARDWARE FEATURES ■ Any combination of sectors can be erased ■ Ready/Busy# output (RY/BY#) — Hardware method for detec ting program or erase cycle completion ■ Hardware reset pin (RESET#) — Hardware method of resetting the internal state machine to the read mode ■ WP#/ACC input pin — Write protect (WP#) function allows protection of two outermost boot sectors, regardless of sector protect status — Acceleration (ACC) function accelerates program timing ■ Sector protection — Hardware method of locking a sector, either in-system or using programming equipment, to prevent any program or erase operation within that sector — Temporary Sector Unprotec t allows changing data in protected sectors in-system This product has been retired and is not available for designs. For new and current designs involving TSOP packages, S29JL032H supersedes Am29DL32xD and is the factory-recom- mended migration path. Please refer to the S29JL032H Datasheet for specifications and ordering information. For new and current designs involving Fine-pitch BGA (FBGA) pa ckages, S29PL032J supersedes Am29DL32xD and is the factory-recomm ended migration path. Please refer to the S29PL032J Datasheet for specifications and ordering information. Availability of this document is retained for reference and historical purposes only.

2 Am29DL322D/323D/324D December 13, 2005

The Am29DL322D/323D/324D family consists of 32 megabit, 3.0 volt-only flash memory devices, orga- nized as 2,097,152 words of 16 bits each or 4,194,304 bytes of 8 bits each. Word mode data appears on DQ0–DQ15; byte mode data appears on DQ0–DQ7. The device is designed to be programmed in-system with the standard 3.0 volt V CC supply, and can also be programmed in standard EPROM programmers. The devices are available with an access time of 70, 90 or 120 ns. The devices are offered in 48-pin TSOP and 63-ball FBGA packages. Standard control pins—chip enable (CE#), write enable (WE#), and out- put enable (OE#)—control normal read and write operations, and avoid bus contention issues. The devices requires only a single 3.0 volt power supply for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. Simultaneous Read/Write Operations with Zero Latency The Simultaneous Read/Write architecture provides simultaneous operation by dividing the memory space into two banks. The device can improve overall system performance by allowing a host system to pro- gram or erase in one bank, then immediately and simultaneously read from the other bank, with zero la- tency. This releases the system from waiting for the completion of program or erase operations. The Am29DL32xD device family uses multiple bank architectures to provide flexibility for different applica- tions. Three devices are available with the following bank sizes: Am29DL322D/323D/324D Features The SecSiTM (Secured Silicon) Sector is an extra sector capable of being permanently locked by AMD or cus- tomers. The SecSi Indicator Bit (DQ7) is permanently set to a 1 if the part is factory locked, and set to a 0 if customer lockable . This way, cus- tomer lockable parts can never be used to replace a factory locked part. Current version of device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. Factory locked parts provide several options. The SecSi Sector may store a secure, random 16 byte ESN (Electronic Serial Number), customer code (pro- grammed through AMD’s ExpressFlash service), or both. Customer Lockable parts may utilize the SecSi Sector as bonus space, reading and writing like any other flash sector, or may permanently lock their own code there. DMS (Data Management Software) allows systems to easily take advantage of the advanced architecture of the simultaneous read/write product line by allowing removal of EEPROM devices. DMS will also allow the system software to be simplifie d, as it will perform all functions necessary to modify data in file structures, as opposed to single-byte modifications. To write or update a particular piece of data (a phone number or configuration data, for example), the user only needs to state which piece of data is to be updated, and where the updated data is located in the system. This is an advantage compared to systems where user-written software must keep track of the old data location, status, logical to physical translation of the data onto the Flash memory device (or memory de- vices), and more. Using DMS, user-written software does not need to interface with the Flash memory di- rectly. Instead, the user's software accesses the Flash memory by calling one of only six functions. AMD pro- vides this software to simplify system design and software integration efforts. The device offers comple te compatibility with the JEDEC single-power-supply Flash command set standard . Commands are written to the command register using standard microprocessor write timings. Reading data out of the device is similar to reading from other Flash or EPROM devices. The host system can detect whether a program or erase operation is complete by using the device sta- tus bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2 (toggle bits). After a program or erase cycle has been completed, the device automatically returns to the read mode. The sector erase architecture allows memory sec- tors to be erased and reprogrammed without affecting the data contents of other sectors. The device is fully erased when shipped from the factory. Hardware data protection measures include a low V CC detector that automatically inhibits write opera- tions during power transitions. The hardware sector protection feature disables both program and erase operations in any combination of the sectors of mem- ory. This can be achieved in-system or via programming equipment. The device offers two power-saving features. When addresses have been stable for a specified amount of time, the device enters the automatic sleep mode . The system can also place the device into the standby mode . Power consumption is greatly re- duced in both modes. Device Bank 1 Bank 2 DL322 4 28 DL323 8 24 DL324 16 16

4 Am29DL322D/323D/324D December 13, 2005

Part Number Am29DL322D/323D/324D Speed Option Regulated Voltage Range: VCC = 3.0–3.6 V 70R Standard Voltage Range: VCC = 2.7–3.6 V 90 120 Max Access Time (ns) 70 90 120 CE# Access (ns) 70 90 120 OE# Access (ns) 30 40 50 VCC VSS Upper Bank AddressA20–A0 RESET# WE# CE# BYTE# DQ15–DQ0 WP#/ACC STATE CONTROL COMMAND REGISTER RY/BY# Upper Bank X-Decoder Y-Decoder Latches and Control Logic OE# BYTE# DQ15–DQ0 Lower Bank Y-Decoder X-Decoder Latches and Control Logic Lower Bank Address OE# BYTE# Status Control A20–A0 A20–A0 A20–A0A20–A0 DQ15–DQ0 DQ15–DQ0

December 13, 2005 Am29DL322D/323D/324D 5 CONNECTION DIAGRAMS A15 A18 A14 A13 A12 A11 A10 A19 A20 WE# RESET# NC WP#/ACC RY/BY# A17 A16 DQ2 BYTE# V SS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 48-Pin Standard TSOP C2 D2 E2 F2 G2 H2 J2 K2 C3 D3 E3 F3 G3 H3 J3 K3 C4 D4 E4 F4 G4 H4 J4 K4 C5 D5 E5 F5 G5 H5 J5 K5 C6 D6 E6 F6 G6 H6 J6 K6 C7 D7A7 B7 A8 B8 A1 B1 E7 F7 G7 H7 J7 K7 L7 NC* NC*NC* NC* NC* NC* NC* NC* NC* NC* NC*NC NC NC NC DQ15/A-1 VSSBYTE#A16A15A14A12A13 DQ13 DQ6DQ14DQ7A11A10A8A9 VCC DQ4DQ12DQ5A19NCRESET#WE# DQ11 DQ3DQ10DQ2A20A18WP#/ACCRY/BY# DQ9 DQ1DQ8DQ0A5A6A17A7 OE# VSSCE#A0A1A2A4A3 * Balls are shorted together via the substrate but not connected to the die. 63-Ball FBGA Top View, Balls Facing Down

6 Am29DL322D/323D/324D December 13, 2005

Special Handling Instructions for FBGA Package Special handling is required for Flash Memory products in FBGA packages. Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The package and/or data integrity may be compromised if the package body is exposed to temperatures above 150°C for prolonged periods of time. PIN DESCRIPTION A0–A20 = 21 Addresses DQ0–DQ14 = 15 Data Inputs/Outputs DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB Address Input, byte mode) CE# = Chip Enable OE# = Output Enable WE# = Write Enable WP#/ACC = Hardware Write Protect/ Acceleration Pin RESET# = Hardware Reset Pin, Active Low BYTE# = Selects 8-bit or 16-bit mode RY/BY# = Ready/Busy Output V CC = 3.0 volt-only single power supply (see Product Selector Guide for speed options and voltage supply toler- ances) V SS = Device Ground NC = Pin Not Connected Internally LOGIC SYMBOL 16 or 8 DQ0–DQ15 (A-1) A0–A20 CE# OE# WE# RESET# BYTE# RY/BY# WP#/ACC

December 13, 2005 Am29DL322D/323D/324D 7

ORDERING INFORMATION

AMD standard products are available in several packages and o perating ranges. The order number (Valid Combination) is formed by a combination of the following: Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local AMD sales office to con- firm availability of specific valid combinations and to check on newly released combinations. Am29DL322D/323D/324D T 70R E I OPTIONAL PROCESSING Blank = Standard Processing N = 16-byte ESN devices (Contact an AMD representative for more information) TEMPERATURE RANGE I = Industrial (–40°C to +85°C) E = Extended (–55°C to +125°C) PACKAGE TYPE E = 48-Pin Thin Small Outline Package (TSOP) Standard Pinout (TS 048) WD = 63-Ball Fine-Pitch Ball Grid Array (FBGA) 0.80 mm pitch, 8 x 14 mm package (FBD063) SPEED OPTION See Product Selector Guide and Valid Combinations BOOT CODE SECTOR ARCHITECTURE T = Top sector B = Bottom sector DEVICE NUMBER/DESCRIPTION Am29DL322D/323D/324D

32 Megabit (4 M x 8-Bit/2 M x 16-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program, and Erase

Valid Combinations for TSOP Packages AM29DL322DT70R, AM29DL322DB70R EI, EIN AM29DL323DT70R, AM29DL323DB70R AM29DL324DT70R, AM29DL324DB70R AM29DL322DT90, AM29DL322DB90 AM29DL323DT90, AM29DL323DB90 AM29DL324DT90, AM29DL324DB90 AM29DL322DT120, AM29DL322DB120 EI, EIN, EE, EENAM29DL323DT120, AM29DL323DB120 AM29DL324DT120, AM29DL324DB120 Valid Combinations for FBGA Packages Order Number Package Marking AM29DL322DT70R, AM29DL322DB70R WDI, WDIN D322DT70R, D322DB70R I AM29DL323DT70R, AM29DL323DB70R D323DT70R, D323DB70R AM29DL324DT70R, AM29DL324DB70R D324DT70R, D324DB70R AM29DL322DT90, AM29DL322DB90 D322DT90V, D322DB90V AM29DL323DT90, AM29DL323DB90 D323DT90V, D323DB90V AM29DL324DT90, AM29DL324DB90 D324DT90V, D324DB90V AM29DL322DT120, AM29DL322DB120 WDI, WDIN, WDE, WDEN D322DT12V, D322DB12V I, EAM29DL323DT120, AM29DL323DB120 D323DT12V, D323DB12V AM29DL324DT120, AM29DL324DB120 D324DT12V, D324DB12V

8 Am29DL322D/323D/324D December 13, 2005

each of these operations in further detail. Table 1. Device Bus Operations

1. Addresses are A20:A0 in word mode (BYTE# = V IH), A20:A-1 in byte mode (BYTE# = VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector/Sector

Block Protection and Unprotection” section.

1. If WP#/ACC = V IL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, the two outermost boot sector

Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected. used as an input for the LSB (A-1) address function. mand is necessary in this mode to obtain array data.

0.3 V XX VCC ±

0.3 V H X High-Z High-Z High-Z

December 13, 2005 Am29DL322D/323D/324D 9 addresses on the device address inputs produce valid data on the device data outputs. Each bank remains enabled for read access until the command register contents are altered. See “Requirements for Reading Array Data” for more information. Refer to the AC Read-Only Operations table for timing specifications and to Figure 13 for the timing diagram. I CC1 in the DC Characteristics table represents the active current specification for reading array data. Writing Commands/Command Sequences To write a command or command sequence (which in- cludes programming data to the device and erasing sectors of memory), the system must drive WE# and CE# to V IL, and OE# to VIH. For program operations, the BYTE# pin determines whether the device accepts program data in bytes or words. Refer to “Word/Byte Configuration” for more information. The device features an Unlock Bypass mode to facil- itate faster programming. Once a bank enters the Unlock Bypass mode, only two write cycles are re- quired to program a word or byte, instead of four. The “Word/Byte Configuration” section has details on pro- gramming data to the device using both standard and Unlock Bypass command sequences. An erase operation can erase one sector, multiple sec- tors, or the entire device. Tables 3–6 indicate the address space that each sector occupies. The device address space is divided into two banks: Bank 1 con- tains the boot/parameter sectors, and Bank 2 contains the larger, code sectors of uniform size. A “bank ad- dress” is the address bits required to uniquely select a bank. Similarly, a “sector address” is the address bits required to uniquely select a sector. I CC2 in the DC Characteristics table represents the ac- tive current specification for the write mode. The AC Characteristics section contains timing specification tables and timing diagrams for write operations. Accelerated Program Operation The device offers accelerated program operations through the ACC function. This is one of two functions provided by the WP#/ACC pin. This function is prima- rily intended to allow faster manufacturing throughput at the factory. If the system asserts V HH on this pin, the device auto- matically enters the aforementioned Unlock Bypass mode, temporarily unprotects any protected sectors, and uses the higher voltage on the pin to reduce the time required for program operations. The system would use a two-cycle program command sequence as required by the Unlock Bypass mode. Removing V HH from the WP#/ACC pin returns the device to nor- mal operation. Note that the WP#/ACC pin must not be at V HH for operations other than accelerated pro- gramming, or device damage may result. In addition, the WP#/ACC pin must not be left floating or uncon- nected; inconsistent behavior of the device may result. Autoselect Functions If the system writes the autoselect command se- quence, the device enters the autoselect mode. The system can then read autoselect codes from the inter- nal register (which is separate from the memory array) on DQ7–DQ0. Standard read cycle timings apply in this mode. Refer to the Autoselect Mode and Autose- lect Command Sequence sections for more information. Simultaneous Read/Write Operations with Zero Latency This device is capable of reading data from one bank of memory while programming or erasing in the other bank of memory. An erase operation may also be sus- pended to read from or program to another location within the same bank (except the sector being erased). Figure 20 shows how read and write cycles may be initiated for simultaneous operation with zero latency. I CC6 and I CC7 in the DC Characteristics table represent the current specifications for read-while-pro- gram and read-while-erase, respectively. Standby Mode When the system is not reading or writing to the de- vice, it can place the device in the standby mode. In this mode, current consumption is greatly reduced, and the outputs are placed in the high impedance state, independent of the OE# input. The device enters the CMOS standby mode when the CE# and RESET# pins are both held at V CC ± 0.3 V. (Note that this is a more restricted voltage range than V IH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device will be in the standby mode, but the standby current will be greater. The device re- quires standard access time (t CE) for read access when the device is in either of these standby modes, before it is ready to read data. If the device is deselected during erasure or program- ming, the device draws active current until the operation is completed. I CC3 in the DC Characteristics table represents the standby current specification. Automatic Sleep Mode The automatic sleep mode minimizes Flash device en- ergy consumption. The device automatically enables this mode when addresses remain stable for t ACC +

10 Am29DL322D/323D/324D December 13, 2005

data is latched and always available to the system. automatic sleep mode current specification. the RESET# pin returns to VIH. Table 2. Device Bank Divisions

64 Kbyte/32 Kword

Table 3. Top Boot Sector Addresses

12 Am29DL322D/323D/324D December 13, 2005

Am29DL322DT, A20 and A19 for Am29DL323DT, and A20 for Am29DL324DT. Table 4. Top Boot SecSi TM Sector Addresses Table 3. Top Boot Sector Addresses (Continued)

December 13, 2005 Am29DL322D/323D/324D 13

14 Am29DL322D/323D/324D December 13, 2005

Table 5. Bottom Boot Sector Addresses

are A20–A18 for Am29DL322DB, A20 and A19 for Am29DL323DB, and A20 for Am29DL324DB. Table 6. Bottom Boot SecSi TM Sector Addresses Table 5. Bottom Boot Sector Addresses (Continued)

16 Am29DL322D/323D/324D December 13, 2005

accessed in-system through the command register. ID (8.5 V to 12.5 V) on address pin A9. Table 7. In addition, when verifying sector protection, shows the remaining address bits that are don’t care. sponding identifier code on DQ7–DQ0. mand Sequence section for more information. Table 7. Autoselect Codes, (High Voltage Method)

Table 8. Top Boot Sector/Sector Block Addresses Table 9. Bottom Boot Sector/Sector Block

18 Am29DL322D/323D/324D December 13, 2005

equipment requires V ID on address pin A9 and OE#. written for earlier 3.0 volt-only AMD flash devices. contact an AMD representative to request a copy. The device is shipped with all sectors unprotected. AMD representative for details. a top-boot-configured device. in “Sector/Sector Block Protection and Unprotection”. Figure 1. Temporary Sector Unprotect Operation

1. All protected sectors unprotected (If WP#/ACC = V IL,

outermost boot sectors will remain protected).

1. All previously protected sectors are protected once

Figure 2. In-System Sector Protection/

20 Am29DL322D/323D/324D December 13, 2005

SecSiTM (Secured Silicon) Sector Flash Memory Region The SecSi (Secured Silicon) Sector feature provides a Flash memory region that enables permanent part identification through an Electronic Serial Number (ESN). The SecSi Sector uses a SecSi Sector Indica- tor Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from the factory. This bit is permanently set at the factory and cannot be changed, which prevents cloning of a factory locked part. This ensures the security of the ESN once the product is shipped to the field. Current version of de- vice has 64 Kbytes; future versions will have only 256 bytes. This should be considered during sys- tem design. AMD offers the device with the SecSi Sector either factory locked or customer lockable. The fac- tory-locked version is always protected when shipped from the factory, and has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “1.” The cus- tomer-lockable version is shipped with the SecSi Sector unprotected, allowing customers to utilize the that sector in any manner they choose. The cus- tomer-lockable version has the SecSi (Secured Silicon) Sector Indicator Bit permanently set to a “0.” Thus, the SecSi Sector Indicator Bit prevents cus- tomer-lockable devices from being used to replace devices that are factory locked. The system accesses the SecSi Sector through a command sequence (see “Enter SecSi TM Sector/Exit SecSi Sector Command Sequence”). After the system has written the Enter SecSi Sector command se- quence, it may read the SecSi Sector by using the addresses normally occupied by the boot sectors. This mode of operation continues until the system issues the Exit SecSi Sector command sequence, or until power is removed from the device. On power-up, or following a hardware reset, the device reverts to send- ing commands to the boot sectors. Factory Locked: SecSi Sector Programmed and Protected At the Factory In a factory locked device, the SecSi Sector is pro- tected when the device is shipped from the factory. The SecSi Sector cannot be modified in any way. The device is available preprogrammed with one of the following: ■ A random, secure ESN only ■ Customer code through the ExpressFlash service ■ Both a random, secure ESN and customer code through the ExpressFlash service. In devices that have an ESN, a Bottom Boot device will have the 16-byte ESN at addresses 000000h–000007h in word mode (or 000000h–00000Fh in byte mode). In the Top Boot de- vice the ESN will be at addresses 1F8000h–1F8007h in word mode (or addresses 3F0000h–3F000Fh in byte mode). Note that in upcoming top boot versions of this device, the ESN will be located at addresses 1FF000h–1FF007h in word mode (or addresses 3FE000h–3FE00Fh in byte mode). Customers may opt to have their code programmed by AMD through the AMD ExpressFlash service. AMD programs the customer’s code, with or without the ran- dom ESN. The devices are then shipped from AMD’s factory with the SecSi Sector permanently locked. Contact an AMD representative for details on using AMD’s ExpressFlash service. Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory If the security feature is not required, the SecSi Sector can be treated as an additional Flash memory space, expanding the size of the available Flash array. Cur- rent version of device has 64 Kbytes; future versions will have only 256 bytes. This should be considered during system design. Additionally, note the change in the location of the ESN in up- coming top boot factory locked devices. The SecSi Sector can be read, programmed, and erased as often as required. ( Note that in upcoming versions of this device, the SecSi Sector erase function will not be available. ) Note that the accelerated programming (ACC) and unlock bypass functions are not available when programming the SecSi Sector. The SecSi Sector area can be protected using one of the following procedures: ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then follow the in-system sector protect algorithm as shown in Figure 2, ex- cept that RESET# may be at either V IH or VID. This allows in-system protection of the SecSi Sector without raising any device pin to a high voltage. Note that this method is only applicable to the SecSi Sector ■ Write the three-cycle Enter SecSi Sector Region command sequence, and then use the alternate method of sector protection described in the “Sec- tor/Sector Block Protection and Unprotection” sec- tion. Once the SecSi Sector is locked and verified, the sys- tem must write the Exit SecSi Sector Region command sequence to return to reading and writing the remainder of the array. The SecSi Sector protection must be used with cau- tion since, once protected, there is no procedure available for unprotecting the SecSi Sector area and none of the bits in the SecSi Sector memory space can be modified in any way.

December 13, 2005 Am29DL322D/323D/324D 21 Hardware Data Protection The command sequence requirement of unlock cycles for programming or erasing provides data protection against inadvertent writes (refer to Table 14 for com- mand definitions). In addition, the following hardware data protection measures prevent accidental erasure or programming, which might otherwise be caused by spurious system level signals during V CC power-up and power-down transitions, or from system noise. Low VCC Write Inhibit When VCC is less than V LKO, the device does not ac- cept any write cycles. This protects data during V CC power-up and power-down. The command register and all internal program/erase circuits are disabled, and the device resets to the read mode. Subsequent writes are ignored until V CC is greater than V LKO. The system must provide the proper signals to the control pins to prevent unintentional writes when V CC is greater than VLKO. Write Pulse “Glitch” Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by holding any one of OE# = VIL, CE# = V IH or WE# = V IH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = V IL and OE# = V IH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automati- cally reset to the read mode on power-up. COMMON FLASH MEMORY INTERFACE (CFI) The Common Flash Interface (CFI) specification out- lines device and host system software interrogation handshake, which allows specific vendor-specified software algorithms to be used for entire families of devices. Software support can then be device-inde- pendent, JEDEC ID-independent, and forward- and backward-compatible for the specified flash device families. Flash vendors can standardize their existing interfaces for long-term compatibility. This device enters the CFI Query mode when the sys- tem writes the CFI Query command, 98h, to address 55h in word mode (or address AAh in byte mode), any time the device is ready to read array data. The system can read CFI information at the addresses given in Tables 10–13. To terminate reading CFI data, the system must write the reset command. The CFI Query mode is not accessible when the device is exe- cuting an Embedded Program or Embedded Erase algorithm. The system can also write the CFI query command when the device is in the autoselect mode. The device enters the CFI query mode, and the system can read CFI data at the addresses given in Tables 10–13. The system must write the reset command to return the device to the autoselect mode. For further information, please refer to the CFI Specifi- cation and CFI Publication 100, available via the World Wide Web at http://www.amd.com/prod- ucts/nvd/overview/cfi.html. Alternatively, contact an AMD representative for copies of these documents.

22 Am29DL322D/323D/324D December 13, 2005

Table 10. CFI Query Identification String Table 11. System Interface String Table 12. Device Geometry Definition

December 13, 2005 Am29DL322D/323D/324D 23 31h 32h 33h 34h 62h 64h 66h 68h 003Eh 0000h 0000h 0001h Erase Block Region 2 Information 35h 36h 37h 38h 6Ah 6Ch 6Eh 70h 0000h 0000h 0000h 0000h Erase Block Region 3 Information 39h 3Ah 3Bh 3Ch 72h 74h 76h 78h 0000h 0000h 0000h 0000h Erase Block Region 4 Information

24 Am29DL322D/323D/324D December 13, 2005

Table 13. Primary Vendor-Specific Extended Query The number of sectors in Bank 2 is device dependent. quence resets the device to reading array data.

December 13, 2005 Am29DL322D/323D/324D 25 again read array data with the same exception. See the Erase Suspend/Erase Resume Commands sec- tion for more information. The system must issue the reset command to return a bank to the read (or erase-suspend-read) mode if DQ5 goes high during an active program or erase opera- tion, or if the bank is in the autoselect mode. See the next section, Reset Command, for more information. See also Requirements for Reading Array Data in the Device Bus Operations section for more information. The Read-Only Operations table provides the read pa- rameters, and Figure 13 shows the timing diagram. Reset Command Writing the reset command resets the banks to the read or erase-suspend-read mode. Address bits are don’t cares for this command. The reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. This resets the bank to which the sys- tem was writing to the read mode. Once erasure begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the sequence cycles in a program command sequence before programming begins. This resets the bank to which the system was writing to the read mode. If the program command sequence is written to a bank that is in the Erase Suspend mode, writing the reset command returns that bank to the erase-sus- pend-read mode. Once programming begins, however, the device ignores reset commands until the operation is complete. The reset command may be written between the se- quence cycles in an autoselect command sequence. Once in the autoselect mode, the reset command must be written to return to the read mode. If a bank entered the autoselect mode while in the Erase Sus- pend mode, writing the reset command returns that bank to the erase-suspend-read mode. If DQ5 goes high during a program or erase operation, writing the reset command returns the banks to the read mode (or erase-suspend-read mode if that bank was in Erase Suspend). Autoselect Command Sequence The autoselect command sequence allows the host system to access the manufacturer and device codes, and determine whether or not a sector is protected. Table 14 shows the address and data requirements. This method is an alternative to that shown in Table 7, which is intended for PROM programmers and re- quires V ID on address pin A9. The autoselect command sequence may be written to an address within a bank that is either in the read or erase-suspend-read mode. The autoselect command may not be written while the device is actively pro- gramming or erasing in the other bank. The autoselect command sequence is initiated by first writing two unlock cycles. This is followed by a third write cycle that contains the bank address and the au- toselect command. The bank then enters the autoselect mode. The system may read at any ad- dress within the same bank any number of times without initiating another autoselect command sequence: ■ A read cycle at address (BA)XX00h (where BA is the bank address) returns the manufacturer code. ■ A read cycle at address (BA)XX01h in word mode (or (BA)XX02h in byte mode) returns the device code. ■ A read cycle to an address containing a sector ad- dress (SA) within the same bank, and the address 02h on A7–A0 in word mode (or the address 04h on A6–A-1 in byte mode) returns 01h if the sector is protected, or 00h if it is unprotected. (Refer to Ta- bles 3–6 for valid sector addresses). The system must write the reset command to return to the read mode (or erase-suspend-read mode if the bank was previously in Erase Suspend). Enter SecSiTM Sector/Exit SecSi Sector Command Sequence The SecSi Sector region provides a secured data area containing a random, sixteen-byte electronic serial number (ESN). The system can access the SecSi Sector region by issuing the three-cycle Enter SecSi Sector command sequence. The device continues to access the SecSi Sector region until the system is- sues the four-cycle Exit SecSi Sector command sequence. The Exit SecSi Sector command sequence returns the device to normal operation. The SecSi Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algo- rithm. Table 14 shows the address and data requirements for both command sequences. See also “SecSi TM (Secured Silicon) Sector Flash Memory Region” for further information. Byte/Word Program Command Sequence The system may program the device by word or byte, depending on the state of the BYTE# pin. Program- ming is a four-bus-cycle operation. The program command sequence is initiated by writing two unlock write cycles, followed by the program set-up com- mand. The program address and data are written next, which in turn initiate the Embedded Program algo- rithm. The system is not required to provide further controls or timings. The device automatically provides

26 Am29DL322D/323D/324D December 13, 2005

mode, to ensure data integrity. cycle containing the unlock bypass command, 20h. ments for the command sequence. and Figure 17 for timing diagrams. Figure 3. Program Operation Note: See Table 14 for program command sequence.

28 Am29DL322D/323D/324D December 13, 2005

if a sector is actively erasing or is erase-suspended. mation on these status bits. just as in the standard Byte Program operation. Figure 4. Erase Operation

1. See Table 14 for erase command sequence.
2. See the section on DQ3 for information on the sector

Table 14. Command Definitions RA = Address of the memory location to be read. RD = Data read from location RA during read operation. edge of WE# or CE# pulse, whichever happens first. erased. Address bits A20–A12 uniquely select any sector. in bypass mode, or is being erased.

1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselect

command sequence, all bus cycles are write cycles.

1. Data bits DQ15–DQ8 are don’t care in command sequences,
2. Unless otherwise noted, address bits A20–A11 are don’t cares.
3. No unlock or command cycles required when bank is reading
4. The Reset command is required to return to the read mode (or to

the bank is providing status information).

1. The fourth cycle of the autoselect command sequence is a read

Autoselect Command Sequence section for more information.

1. The data is 81h for factory locked and 01h for not factory locked.
2. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

1. The Unlock Bypass command is required prior to the Unlock
2. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

1. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode. operation, and requires the bank address.

1. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

1. Command is valid when device is ready to read array data or when

device is in autoselect mode.

30 Am29DL322D/323D/324D December 13, 2005

progress or has been completed. WE# pulse in the command sequence. Suspend mode, Data# Polling produces a “1” on DQ7. sector, the status may not be valid. Table 15 shows the outputs for Data# Polling on DQ7. Figure 5. Data# Polling Algorithm

1. VA = Valid address for prog ramming. During a sector

valid address is any non-protected sector address.

1. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

32 Am29DL322D/323D/324D December 13, 2005

DQ2: Toggle Bit II The “Toggle Bit II” on DQ2, when used with DQ6, indi- cates whether a particular sector is actively erasing (that is, the Embedded Erase algorithm is in progress), or whether that sector is erase-suspended. Toggle Bit II is valid after the rising edge of the final WE# pulse in the command sequence. DQ2 toggles when the system reads at addresses within those sectors that have been selected for era- sure. (The system may use either OE# or CE# to control the read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or is erase-sus- pended. DQ6, by comparison, indicates whether the device is actively erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected for era- sure. Thus, both status bits are required for sector and mode information. Refer to Table 15 to compare out- puts for DQ2 and DQ6. Figure 6 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. Figure 22 shows the toggle bit timing diagram. Figure 23 shows the differences between DQ2 and DQ6 in graphical form. Reading Toggle Bits DQ6/DQ2 Refer to Figure 6 for the following discussion. When- ever the system initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice in a row to determine whether a toggle bit is toggling. Typically, the system would note and store the value of the tog- gle bit after the first read. After the second read, the system would compare the new value of the toggle bit with the first. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7–DQ0 on the fol- lowing read cycle. However, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of DQ5 is high (see the section on DQ5). If it is, the system should then determine again whether the toggle bit is tog- gling, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the de- vice did not completed the operation successfully, and the system must write the reset command to return to reading array data. The remaining scenario is that the system initially de- termines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cy- cles, determining the status as described in the previous paragraph. Alternatively, it may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm when it re- turns to determine the status of the operation (top of Figure 6). DQ5: Exceeded Timing Limits DQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. Under these conditions DQ5 produces a “1,” indicating that the program or erase cycle was not successfully completed. The device may output a “1” on DQ5 if the system tries to program a “1” to a location that was previously pro- grammed to “0.” Only an erase operation can change a “0” back to a “1.” Under this condition, the device halts the operation, and when the timing limit has been exceeded, DQ5 produces a “1.” Under both these conditions, the system must write the reset command to return to the read mode (or to the erase-suspend-read mode if a bank was previ- ously in the erase-suspend-program mode). DQ3: Sector Erase Timer After writing a sector erase command sequence, the system may read DQ3 to determine whether or not erasure has begun. (The sector erase timer does not apply to the chip erase command.) If additional sectors are selected for erasure, the entire time-out also applies after each additional sector erase com- mand. When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the time between addi- tional sector erase commands from the system can be assumed to be less than 50 µs, the system need not monitor DQ3. See also the Sector Erase Command Sequence section. After the sector erase command is written, the system should read the status of DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase algorithm has begun; all fur- ther commands (except Erase Suspend) are ignored until the erase operation is complete. If DQ3 is “0,” the device will accept additional sector erase commands. To ensure the command has been accepted, the sys- tem software should check the status of DQ3 prior to and following each subsequent sector erase com- mand. If DQ3 is high on the second status check, the last command might not have been accepted. Table 15 shows the status of DQ3 relative to the other status bits.

Table 15. Write Operation Status

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

Refer to the section on DQ5 for more information.

1. DQ7 and DQ2 require a valid address when reading status info rmation. Refer to the appropriate subsection for further
2. When reading write operation status bits , the system must always provide the bank address where the Embedded Algorithm

is in progress. The device outputs array data if the system addresses a non-busy bank.

34 Am29DL322D/323D/324D December 13, 2005

1. Minimum DC voltage on input or I/O pins is –0.5 V.

overshoot V SS to –2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is V CC +0.5 V.

1. Minimum DC input voltage on pins A9, OE#, RESET#,

overshoot to +12.0 V for periods up to 20 ns.

1. No more than one output may be shorted to ground at a

operational sections of this data sheet is not implied. conditions for extended periods may affect device reliability. Figure 7. Maximum Negative Figure 8. Maximum Positive functionality of the device is guaranteed.

December 13, 2005 Am29DL322D/323D/324D 35 DC CHARACTERISTICS CMOS Compatible Notes: 1. The I CC current listed is typically less than 2 mA/MHz, with OE# at VIH. 2. Maximum I CC specifications are tested with VCC = VCCmax. 3. I CC active while Embedded Erase or Embedded Program is in progress. 4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode current is 200 nA. 5. Not 100% tested. Parameter Symbol Parameter Description Test Conditions Min Typ Max Unit ILI Input Load Current VIN = VSS to VCC, VCC = VCC max ±1.0 µA ILIT A9 Input Load Current V CC = VCC max; A9 = 12.5 V 35 µA ILO Output Leakage Current VOUT = VSS to VCC, VCC = VCC max ±1.0 µA ICC1 VCC Active Read Current (Notes 1, 2) CE# = VIL, OE# = VIH, Byte Mode

5 MHz 10 16

1 MHz 2 4

CE# = VIL, OE# = VIH, Word Mode ICC2 VCC Active Write Current (Notes 2, 3) CE# = V IL, OE# = VIH, WE# = VIL 15 30 mA ICC3 VCC Standby Current (Note 2) CE#, RESET# = V CC ± 0.3 V 0.2 5 µA ICC4 VCC Reset Current (Note 2) RESET# = V SS ± 0.3 V 0.2 5 µA ICC5 Automatic Sleep Mode (Notes 2, 4) VIH = VCC ± 0.3 V; VIL = VSS ± 0.3 V 0.2 5 µA ICC6 VCC Active Read-While-Program Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC7 VCC Active Read-While-Erase Current (Notes 1, 2) CE# = VIL, OE# = VIH Byte 21 45 mA Word 21 45 ICC8 VCC Active Program-While-Erase-Suspended Current (Notes 2, 5) CE# = V IL, OE# = VIH 17 35 mA IACC ACC Accelerated Program Current, Word or Byte CE# = VIL, OE# = VIH ACC pin 5 10 mA VCC pin 15 30 mA VIL Input Low Voltage –0.5 0.8 V VIH Input High Voltage 0.7 x V CC VCC + 0.3 V VHH Voltage for WP#/ACC Sector Protect/Unprotect and Program Acceleration V CC = 3.0 V ± 10% 8.5 9.5 V VID Voltage for Autoselect and Temporary Sector Unprotect VCC = 3.0 V ± 10% 8.5 12.5 V VOL Output Low Voltage I OL = 4.0 mA, VCC = VCC min 0.45 V VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 V CC V VOH2 IOH = –100 µA, VCC = VCC min V CC–0.4 VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V

36 Am29DL322D/323D/324D December 13, 2005

Figure 9. I CC1 Current vs. Time (Showing Active and Automatic Sleep Currents) Figure 10. Typical I CC1 vs. Frequency

38 Am29DL322D/323D/324D December 13, 2005

1. See Figure 11 and Table 16 for test specifications.

0 VRY/BY#

Figure 13. Read Operation Timings

Figure 14. Reset Timings

40 Am29DL322D/323D/324D December 13, 2005

Figure 15. BYTE# Timings for Read Operations Note: Refer to the Erase/Program Operations table for tAS and tAH specifications. Figure 16. BYTE# Timings for Write Operations

December 13, 2005 Am29DL322D/323D/324D 41 AC CHARACTERISTICS Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 70R 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tASO Address Setup Time to OE# low during toggle bit polling Min 15 15 ns tWLAX tAH Address Hold Time Min 45 45 50 ns tAHT Address Hold Time From CE# or OE# high during toggle bit polling Min 0 ns tDVWH tDS Data Setup Time Min 35 45 50 ns tWHDX tDH Data Hold Time Min 0 ns tOEPH Output Enable High during toggle bit polling Min 20 ns tGHWL tGHWL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tELWL tCS CE# Setup Time Min 0 ns tWHEH tCH CE# Hold Time Min 0 ns tWLWH tWP Write Pulse Width Min 30 35 50 ns tWHDL tWPH Write Pulse Width High Min 30 ns tSR/W Latency Between Read and Write Operations Min 0 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec tVCS VCC Setup Time (Note 1) Min 50 µs tRB Write Recovery Time from RY/BY# Min 0 ns tBUSY Program/Erase Valid to RY/BY# Delay Min 90 ns

42 Am29DL322D/323D/324D December 13, 2005

1. PA = program address, PD = program data, D OUT is the true data at the program address.
2. Illustration shows device in word mode.

Figure 17. Program Operation Timings Figure 18. Accelerated Program Timing Diagram

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.
2. These waveforms are for the word mode.

Figure 19. Chip/Sector Erase Operation Timings

44 Am29DL322D/323D/324D December 13, 2005

Figure 20. Back-to-back Read/Write Cycle Timings Figure 21. Data# Polling Timings (During Embedded Algorithms)

46 Am29DL322D/323D/324D December 13, 2005

Figure 24. Temporary Sector Unprotect Timing Diagram

Figure 25. Sector/Sector Block Protect and Unprotect Timing Diagram

48 Am29DL322D/323D/324D December 13, 2005

Alternate CE# Controlled Erase and Program Operations Notes: 1. Not 100% tested. 2. See the “Erase And Programming Performance” section for more information. Parameter Speed Options JEDEC Std Description 70R 90 120 Unit tAVAV tWC Write Cycle Time (Note 1) Min 70 90 120 ns tAVWL tAS Address Setup Time Min 0 ns tELAX tAH Address Hold Time Min 45 45 50 ns tDVEH tDS Data Setup Time Min 45 45 50 ns tEHDX tDH Data Hold Time Min 0 ns tGHEL tGHEL Read Recovery Time Before Write (OE# High to WE# Low) Min 0 ns tWLEL tWS WE# Setup Time Min 0 ns tEHWH tWH WE# Hold Time Min 0 ns tELEH tCP CE# Pulse Width Min 45 45 50 ns tEHEL tCPH CE# Pulse Width High Min 30 ns tWHWH1 tWHWH1 Programming Operation (Note 2) Byte Typ 5 µs Word Typ 7 tWHWH1 tWHWH1 Accelerated Programming Operation, Word or Byte (Note 2) Typ 4 µs tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

1. Figure indicates last two bus cycl es of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.

Figure 26. Alternate CE# Controlled Write (Erase/Program) Operation Timings

50 Am29DL322D/323D/324D December 13, 2005

ERASE AND PROGRAMMING PERFORMANCE Notes: 1. Typical program and erase times assume the following conditions: 25 °C, 3.0 V VCC, 1,000,000 cycles. Additionally, programming typicals assume checkerboard pattern. 2. Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for regulated devices), 1,000,000 cycles. 3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes program faster than the maximum program times listed. 4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure. 5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Table 14 for further information on command definitions. 6. The device has a minimum erase and pr ogram cycle endurance of 1,000,000 cycles. LATCHUP CHARACTERISTICS Note: Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time. TSOP AND SO PIN CAPACITANCE Notes: 1. Sampled, not 100% tested. 2. Test conditions T A = 25°C, f = 1.0 MHz. DATA RETENTION Parameter Typ (Note 1) Max (Note 2) Unit Comments Sector Erase Time 0.7 15 sec Excludes 00h programming prior to erasure (Note 4)Chip Erase Time 49 sec Byte Program Time 5 150 µs Excludes system level overhead (Note 5) Accelerated Byte/Word Program Time 4 120 µs Word Program Time 7 210 µs Chip Program Time (Note 3) Byte Mode 21 63 sec Word Mode 14 42 Description Min Max Input voltage with respect to VSS on all pins except I/O pins (including A9, OE#, and RESET#) –1.0 V 12.5 V Input voltage with respect to VSS on all I/O pins –1.0 V V CC + 1.0 V VCC Current –100 mA +100 mA Parameter Symbol Parameter Description Test Setup Typ Max Unit CIN Input Capacitance V IN = 0 6 7.5 pF COUT Output Capacitance V OUT = 0 8.5 12 pF CIN2 Control Pin Capacitance V IN = 0 7.5 9 pF Parameter Description T est Conditions Min Unit Minimum Pattern Data Retention Time 150°C 10 Y ears 125°C 20 Y ears

December 13, 2005 Am29DL322D/323D/324D 51 PHYSICAL DIMENSIONS FBD063—63-ball Fine-Pitch Ball Grid Array (FBGA) 8 x 14 mm Dwg rev AF; 10/99

52 Am29DL322D/323D/324D December 13, 2005

TS 048—48-Pin Standard TSOP Dwg rev AA; 10/99

December 13, 2005 Am29DL322D/323D/324D 53 REVISION SUMMARY Revision B (October 1998) Global Deleted the 90R and 120R speed options. Expanded the full voltage range to 2.7–3.6 V. Distinctive Characteristics Added 125°C to 20-year data retention bullet. Connection Diagrams Changed the FBGA diagram from bottom view to top view. Changed the FBGA ordering nomenclature to “YD.” The package designation is now FBD063. Device Bus Operations Accelerated Program Operation and Write Protect (WP#) sections: Added note to indicate that the WP#/ACC must not be left floating or unconnected. Command Definitions Unlock Bypass Command Sequence: Added note to indicate that the WP#/ACC must not be left floating or unconnected. DC Characteristics Changed maximum I LI current to ±3.0 µA. Erase and Programming Performance Replaced TBDs in table with actual values. Physical Dimensions Updated the FBGA drawing, table, and notes. The package designation is now FBD063. Deleted 40-pin TSOP drawing. Revision B+1 (October 1998) Valid Combinations table: Changed combinations to indicate YD for the FBGA package, but reverted to WD in revision C. Sector Address table Corrected bank divisions for both sector address tables. Command Definitions table Added the term “sector block” to the notes where appropriate. DC Characteristics Changed maximum I LI current to ±1.0 µA. AC Characteristics Temporary Sector Unprotect: Moved the accelerated program timing diagram to follow the program opera- tions timings. Added the term “sector block” where appropriate elsewhere on the page. Revision C (January 1999) Global Changed data sheet title. Product Selector Guide Replaced “Full Voltage Range: V CC = 2.7–3.6 V” with “Standard Voltage Range: VCC = 2.7–3.3 V.” Removed 70R speed option. Reverted FBGA designator to WD. Secured Silicon (SecSi) Sector Flash Memory Region Factory Locked: SecSi Sector Programmed and Pro- tected at the Factory: Corrected the address range of the ESN and distinguished between word and byte modes. Operating Ranges VCC Supply Voltages: Replaced full voltage range with standard voltage range. Revision C+1 (January 1999) Sector/Sector Block Protection and Unprotection Tables Changed the sector address range to A20—A12. Revision C+2 (March 17, 1999) Device Bus Operations All references to SecureSector have been changed to SecSi Sector. Connection Diagrams Modified FBGA drawing to show how outrigger balls are shorted. Revision C+3 (June 14, 1999) Global Changed data sheet status to Preliminary. Deleted all references to the 56-pin TSOP package.

54 Am29DL322D/323D/324D December 13, 2005

Revision C+4 (July 2, 1999) Device Bus Operations Sector Address Tables: In the note below the tables, corrected the bank address bit range for Am29DL323. Revision C+5 (September 27, 1999) Device Bus Operations Sector Address tables: Corrected the bank address bits specified. Revision D (December 17, 1999) Global Changed Am29DL322C/323C to Am29DL322D/323D to reflect new 0.23 µm process technology. Added 70 ns speed option. AC Characteristics Figure 17, Program Operations Timing; Figure 19, Chip/Sector Erase Operations: Deleted t GHWL and changed OE# waveform to start at high. Erase and Program Operations table; Alternate CE# Controlled Erase and Program Operations table: Changed the typical and maximum specifications for programming time. Erase and Programming Performance In the table, changed the typical and maximum specifi- cations for programming time. Physical Dimensions Replaced figures with more detailed illustrations. Revision D+1 (June 21, 2000) Global Added information on the Am29DL324 device. Device Bus Operations Table 7, Autoselect Codes: The SecSi Sector Indicator Bit values have changed from 80h and 00h to 81h and 01h, respectively. Command Definitions Table 14, Command Definitions: The SecSi Sector In- dicator Bit values have changed from 80h and 00h to 81h and 01h, respectively. Revision D+2 (August 3, 2000) Block Diagram Corrected “A0–A19” to “A0–A20”. Table 3. Sector Addresses for Top Boot Sector Table 5. Sector Addresses for Bottom Boot Sector Added OE# and BYTE# inputs to lower bank section. Deleted burn-in option. Changed 70 ns speed option from standard voltage range to regulated voltage range. Table 8, Top Boot Sector/Sector Block Addresses for Protection/Unprotection Corrected SA3 address range to 000011XXX. RESET#: Hardware Reset Pin Corrected reference to I CC current in DC Characteris- tics table. Revision D+4 (April 27, 2001) Distinctive Characteristics, General Description, SecSiTM (Secured Silicon) Sector Flash Memory Region Clarified that current version of device has 64 Kbyte SecSi Sector; future versions will have 256 bytes. Added valid combinations for “N” designator. Common Flash Memory Interface (CFI) Modified first paragraph to indicate that the CFI Query is not accessible when the device is executing an Em- bedded Algorithm. SecSi TM (Secured Silicon) Sector Flash Memory Region Added note indicating that ACC and unlock bypass are not available when programming the SecSi Sector. Enter SecSiTM Sector/Exit SecSi Sector Command Sequence Added statement that SecSi Sector is not accessible when the device is executing an Embedded Program or Embedded Erase algorithm.

December 13, 2005 Am29DL322D/323D/324D 55 AC Characteristics Read-only Operations: Changed tDF specification to 16 ns. Word/Byte Configuration: Changed tFLQZ specification to 16 ns. Revision D+5 (May 8, 2001) Global Removed Preliminary status from data sheet. SecSiTM (Secured Silicon) Sector Flash Memory Region Noted changes for upcoming versions of these de- vices: reduced SecSi Sector size, different ESN location for top boot devices, and deletion of SecSi Sector erase functionality. Current versions of these devices remain unaffected. Revision D+6 (June 10, 2003) Unlock Bypass Command Sequence; Command Definitions table Text and table now state that addresses are don’t care for the unlock bypass command sequence (that is, a bank address is not required as previously stated). Revision D+7 (October 7, 2004) Cover sheet and title page Added notation to superseding documents. Revision D+8 (December 13, 2005) Clarified product availability in notation to superseding documents. Colophon The products described in this document are designed, developed and manufactured as contemplated for general use, including without limita- tion, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as con- templated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor de- vices have an inherent chance of failure. Y ou must protect against injury, damage or loss from such failures by incorporating safety design mea- sures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the US Export Administration Regulations or the applicable laws of any other country, the prior au- thorization by the respective government entity will be required for export of those products. Trademarks Copyright © 2004-2005 Advanced Micro Devices, Inc. All rights reserved. AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc. ExpressFlash is a trademark of Advanced Micro Devices, Inc. Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.